On Tue, Feb 28, 2023 at 10:28 PM Marek Vasut
wrote:
> Use CONFIG_RCAR_64 to make the driver available on both
> R-Car Gen3 and R-Car Gen4.
>
> Signed-off-by: Marek Vasut
LGTM, so
Reviewed-by: Geert Uytterhoeven
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -381,7 +381,7 @@ confi
From: Dhruva Gole
This should have been op->data.buswidth instead as we check for octal
bus width for the data related ops
Also add explanation for why there is checks for 8D even data bytes
Cc: Pratyush Yadav
Reviewed-by: Pratyush Yadav
Tested-by: Nikhil M Jain
Signed-off-by: Dhruva Gole
--
From: Dhruva Gole
in spi_mem_dtr_supports_op we have a check for allowing only even number
of bytes to be r/w. Odd bytes writing can be a concern while writing
data to a flash for example because 8 DTR mode doesn't support it.
However, reading ODD Bytes even though may not be physically possible
From: Dhruva Gole
Currently if one tries to read an odd filesize from a flash in OSPI DTR
Mode then the transaction just straightaway returns failure without even
attempting a read.
Base on comments from a series a while back:
https://lore.kernel.org/u-boot/20221025062036.383460-1-d-g...@ti.com/
Hi Pali,
On 2/28/23 23:41, Pali Rohár wrote:
So my question is, why are less patches in your github branch? Or did
you try to re-send with this smaller amount of patches and this did not
work because of the crashing mail server?
I cannot understand how it is possible. There should be 59 pat
Hello Marek,
On 28.02.23 22:25, Marek Vasut wrote:
> From: Hai Pham
>
> Add support for R-Car Gen4 SoCs into the driver.
>
> While I2C on R-Car Gen4 does support some extra features (Slave Clock
> Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
> which let us share the sam
Hello Marek,
On 28.02.23 00:03, Marek Vasut wrote:
> Sort the list of "depends" symbols in ascending order.
> No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Heiko Schocher
> ---
> drivers/i2c/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Heiko
Hello Marek,
On 28.02.23 00:03, Marek Vasut wrote:
> Sort the list of "depends" symbols in ascending order.
> No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Heiko Schocher
> ---
> drivers/i2c/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Heiko
[ Felipe: Ported from Linux kernel commit
f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]
According to Synopsys Databook, we shouldn't be
relying on GCTL.CORESOFTRESET bit as that's only for
debugging purposes. Instead, let's use DCTL.CSFTRST
if we're OTG or PERIPHERAL mode.
Update the script to run VPL tests as well as the others.
Signed-off-by: Simon Glass
---
test/run | 5 +
1 file changed, 5 insertions(+)
diff --git a/test/run b/test/run
index c4ab046ce8f..9e94ae23fb7 100755
--- a/test/run
+++ b/test/run
@@ -56,6 +56,11 @@ echo "${prompt}"
run_test "sandb
This is actually skipped at present due to the condition in the file.
Fix this by running all vpl tests.
Signed-off-by: Simon Glass
---
.azure-pipelines.yml | 2 +-
.gitlab-ci.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.azure-pipelines.yml b/.azure-pipeline
At present this inadvertently relies on having a symlink to the correct
file from the current directory. Use the correct path to fix this.
Signed-off-by: Simon Glass
---
test/py/tests/test_vbe_vpl.py | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/test/py/tests/test_vb
It was reported that one of the VPL tests does not work. The problem
turned out to be a leftover symlink that I had which made things work
locally. This was not noticed in CI since the tests did not run there
either.
This little series fixes these problems.
Simon Glass (3):
vbe: Use the correc
Hi Pali,
On Tue, Feb 28, 2023 at 2:19 PM Pali Rohár wrote:
>
> On Tuesday 28 February 2023 13:51:24 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár wrote:
> > >
> > > On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > > > On Monday 27 February 2023 17:17
> -Original Message-
> From: Pali Rohár
> Sent: Tuesday, February 28, 2023 9:32 AM
> To: Leo Li
> Cc: Fabio Estevam ; Priyanka Jain
> ; Fabio Estevam ;
> ka...@kernel.org; u-boot@lists.denx.de
> Subject: Re: [PATCH] README.mpc85xx-sd-spi-boot: Suggest the NXP boot
> format github repo
On 2/28/2023 6:08 AM, Tom Rini wrote:
With clang-15, it is now reported that cont_img_count is unused. This is
true as the code will increment / reset this counter, but never
functionally use it. Remove it.
Signed-off-by: Tom Rini
Reviewed-by: Peng Fan
---
Cc: Peng Fan
Cc: Mikhail Ilin
Hi Ioana,
Thanks for working on this.
On 3/1/2023 12:32 AM, Ioana Ciornei wrote:
This patch set converts the LS208xA based boards to DM_SERIAL.
Since we don't want to introduce even more differences between the
U-Boot's and Linux's device trees the first 4 patches make the necessary
updates so
+ Haibo
On 2/27/2023 8:55 PM, Luca Ellero wrote:
Add ADC support for NXP iMX93
Changes for v2:
- add "static" to functions
- enable ADC in iMX93 EVK
Changes for v3:
- split in 3 commits
- keep dts file in sync with Linux devicetree
- add comments to commits
Luca Ellero (3):
dm: adc: add iM
tags/u-boot-rockchip-20230228
for you to fetch changes up to a6e85a35b50ade7df5f32092c1cc05ade303a22a:
board: rock5b-rk3588: add memory gaps into kernel's DTB (2023-02-28 18:07:29
+0800)
Akash Gajjar (2):
arm64: dts: roc
On Tuesday 28 February 2023 11:16:03 Stefan Roese wrote:
> Hi Pali,
>
> On 2/28/23 11:10, Pali Rohár wrote:
> > On Tuesday 28 February 2023 11:01:55 Stefan Roese wrote:
> > > Hi Pali,
> > >
> > > On 2/28/23 10:54, Pali Rohár wrote:
> > > > On Tuesday 28 February 2023 08:03:47 Stefan Roese wrote:
On Tuesday 28 February 2023 13:51:24 Tony Dinh wrote:
> Hi Pali,
>
> On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár wrote:
> >
> > On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > > On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > > > Hi Pali,
> > > >
> > > > On Mon, Feb 27, 2023 a
On Tue, Feb 28, 2023 at 10:01:46PM +0100, Angelo Dureghello wrote:
> Hi Tom,
>
> On 28/02/23 9:34 PM, Tom Rini wrote:
> > On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:
> >
> > > The following changes since commit
> > > e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
> > >
> > >
Hi Pali,
On Tue, Feb 28, 2023 at 10:52 AM Pali Rohár wrote:
>
> On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> > On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > > Hi Pali,
> > >
> > > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh wrote:
> > > >
> > > > Hi Pali,
> > > >
> > > > On
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.
Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT op
From: Hai Pham
Add board code for R8A779G0 V4H White Hawk board.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
S
From: Phong Hoang
Add initial DT support for R8A779G0 (R-Car V4H). Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Phong Hoang
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Sync with
From: Hai Pham
Add Kconfig entry and PRR ID to support R8A779G0 V4H SoC.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update commit message]
---
arch/arm/mach-rmobile/Kconfig.rcar4 | 6 ++
arch/arm/mach-rmobile/cpu_info.c | 1 +
From: Tho Vu
Add DTs for R8A779G0 V4H White Hawk CPU and BreakOut boards.
Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Tho Vu
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[M
From: Hai Pham
Add R8A779G0 V4H DT extras for U-Boot.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update compatible string to match latest upstream]
---
arch/arm/dts/r8a779g0-u-boot.dtsi | 28
1 file changed, 28 insertions(
From: Hai Pham
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
From: Tho Vu
Add all Clock Pulse Generator Core Clock Outputs for the
Renesas R-Car V4H (R8A779G0) SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Tho Vu
Signed-off-by: Hai Pham
Signed-off-by: Marek Vas
From: Tho Vu
Add power domain indices for R-Car V4H (R8A779G0) from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Tho Vu
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update to linux next 2023
From: LUU HOAI
Add pinctrl tables for R8A779F0 S4 SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: LUU HOAI
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[
From: Hai Pham
Add board code for R8A779F0 S4 Spider board.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Synchronize configuration symbols which are now switched to Kconfig
Mallocate gd->bd->bi_boot_params, i.e. drop the assignment
Sort h
From: Hai Pham
Add Kconfig entry and PRR ID to support R8A779F0 S4 SoC.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update commit message]
---
arch/arm/mach-rmobile/Kconfig.rcar4 | 6 ++
arch/arm/mach-rmobile/cpu_info.c | 1 +
From: Hai Pham
Add DTs for R8A779F0 S4 Spider CPU boards and Breakout boards.
Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Sync with
From: Hai Pham
Add initial DT for R8A779F0 S4 SoC. Based on Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Sync with Linux next 20230228, update commit message]
---
From: Hai Pham
Add R8A779F0 S4 DT extras for U-Boot.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update compatible string to match latest upstream]
---
arch/arm/dts/r8a779f0-u-boot.dtsi | 28
1 file changed, 28 insertions(+
From: Hai Pham
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family [1]. Hence reflect this in related files, select appropriate
configuration options and split DT build into its own GEN4 entry.
[1]
https://www.renesas.com/us/en/products/automotive-products/automotive-system
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset
From: Hai Pham
Add clock tables for R8A779F0 S4 SoC
Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Revi
From: Tho Vu
Add power domain indices for R-Car S4 (R8A779F0) from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Tho Vu
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update to linux next 2023
From: Tho Vu
Add definitions for R8A779F0 S4 CPG Core Clock headers from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut
Signed-off-by: Tho Vu
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Update to linux nex
From: Hai Pham
Provide the basic HSCIF support for R-Car SoC.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Fill in HSSRR offset for Gen2 and SCBRR calculation for Gen2 and Gen3]
---
Cc: Simon Glass
---
doc/device-tree-bindings/serial/sh.txt | 2 +-
dr
From: Hai Pham
Add R-Car Gen4 family support. The basic function is as same as previous
R-Car Generation.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
[Marek: Swap RZ/A1 and Gen4 to keep the GenN sequence, use RCAR_64]
---
Cc: Simon Glass
---
drivers/serial/se
Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.
Signed-off-by: Marek Vasut
---
Cc: Geert Uytterhoeven
Cc: Jagan Teki
Cc: Simon Glass
Cc: Tom Rini
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig
From: Hai Pham
Add support for R-Car Gen4 SoCs into the driver.
While I2C on R-Car Gen4 does support some extra features (Slave Clock
Stretch Select), for now it is treated the same as I2C on R-Car Gen3,
which let us share the same driver.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Sign
From: Hai Pham
Support R-Car Gen4 family. The default quirk is similar to previous
generation.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut # Use RCAR_64
Kconfig
---
drivers/mmc/renesas-sdhi.c | 1 +
drivers/mmc/tmio-common.c | 2 +-
2 files changed, 2 insert
From: Hai Pham
Add support for the GPIO controller block in the R-Car Gen4 family.
It has a General Input Enable Register (INEN), whose reset state is to
have all inputs disabled.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/gpio/gpio-rcar.c | 1 +
The DT specification supports CPUs with both 32-bit and 64-bit addressing
capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled
by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions
with a 64-bit reg property. These partitions synced from Linux end up with
th
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.
Signed-off-by: Johan Jonker
---
arch/arm/mach-stm32mp
From: Hai Pham
This adds R-Car Generation 4 (Gen4) support as Renesas ARM64 SoC.
In this version, reusing R-Car Gen3 lowlevel initialize routine [1]
and R-Car Gen3 memory map tables [2] .
[1] arch/arm/mach-rmobile/lowlevel_init_gen3.S
[2] arch/arm/mach-rmobile/memmap-gen3.c
Reviewed-by: Marek
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker
---
Changed V5:
new patch
---
arch/arm/mach-mvebu/cpu.c | 2 +-
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
---
Change
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.
Signed-off-by: Joh
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
---
Changed V2
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
Rev
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes.
Signed-off-by: Johan
Add dev_read_addr_index_ptr function with the same
functionality as dev_read_addr_index, but instead
a return pointer is given.
Signed-off-by: Johan Jonker
---
Changed V5:
new patch
---
drivers/core/read.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/core/read.c b/driver
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.
Suggested-by: Michael Nazzareno Trimarchi
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V5:
fix spelling
use tabs
---
driv
Make the indent of these macro elements consistent with the
rest of this table. No functional change.
Signed-off-by: Marek Vasut
---
drivers/serial/serial_sh.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
inde
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to phys_addr_t in files
that use this function. Also correct struct syscon_base_plat
depending on CONFIG_PHYS_64BIT setting and fix ARRAY_
The 64bit limitation check is compiled and optimized out on 32bit
platforms, but generates a type width warning:
drivers/mmc/tmio-common.c: In function ‘tmio_sd_addr_is_dmaable’:
drivers/mmc/tmio-common.c:376:26: warning: right shift count >= width of type
[-Wshift-count-overflow]
376 |
When fdt_addr_t and phys_addr_t are split it turns out that
the header don't match the functions, so fix the headers.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
include/dm/ofnode.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
dif
Instead of #if and #ifdef, use IS_ENABLED and CONFIG_IS_ENABLED macros.
This improves build test coverage. The CONFIG_SPL_BUILD must remain an
ifdef, as CONFIG_SPL_STACK may not always be defined, e.g. in U-Boot
proper build. No functional change.
Signed-off-by: Marek Vasut
---
Cc: Jaehoon Chung
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert dev_read_addr output to phys_addr_t in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
drivers/timer/dw-apb-timer.c | 4 ++--
1 fi
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
drivers/adc/rockchip-saradc.c | 4 ++--
1 file changed, 2 inse
Add support for debug output very early during boot using the DEBUG_UART
mechanism. This uses a static fixed UART port configuration selected via
Kconfig options and dedicated print functions from debug_uart.h. This is
useful e.g. when debugging problems so early during boot, that not even
the DM i
Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a
matching Kconfig entry because they are internal to the SCIF driver.
Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI,
to reflect that and avoid interferring with Kconfig symbols. Since
neither of those options are
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
drivers/mtd/nand/raw/nand_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/nan
The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 p
Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Reviewed-by: Michael Trimarchi
---
drivers/mtd/nand/raw/rockchip_nfc.c | 1 +
1 file changed, 1 insertion(+)
di
The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.
Ensure the reset framework is also always ena
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker
Reviewed-
The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Re
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
drivers/mtd/nand/raw/rockchip_nfc.c | 6 +++---
1 file cha
This serie contains fixes for the Rockchip NFC driver,
which was ported to U-boot and merged with little review
and testing it seems.
Part 1 aims at passing the probe function without errors.
Extended with tree wide function cleanup needed for 64bit DT parsing.
Fixed are:
64bit FDT parsing
com
Hi Tom,
On 28/02/23 9:34 PM, Tom Rini wrote:
On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:
The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)
are available in the Git repository at:
git://g
On 2023-02-28 10:19, Jagan Teki wrote:
> On Sun, 26 Feb 2023 at 00:31, Jonas Karlman wrote:
>>
>> Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
>> back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
>> jumps to U-Boot SPL to continue the normal boot flow
On Tue, Feb 28, 2023 at 09:21:23PM +0100, Angelo Dureghello wrote:
> The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
>
> Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-coldfire.git master
Enable use of the python-azurepipelines package which provides automatic
formatting and uploading of the pytest output.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index f6609bb
The default pytest cache directory is in a read-only directory in Azure,
which results in a warning on the build page. Use the pytest command
line option to set the cache dir to somewhere writable.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletio
The following changes since commit e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8:
Prepare v2023.04-rc3 (2023-02-27 17:18:36 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-coldfire.git master
for you to fetch changes up to 4c885f9f64cd85471614c75027620e3bcf3046bd:
m68
On Tuesday 28 February 2023 10:48:24 Pali Rohár wrote:
> On Monday 27 February 2023 17:17:31 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Mon, Feb 27, 2023 at 4:42 PM Tony Dinh wrote:
> > >
> > > Hi Pali,
> > >
> > > On Mon, Feb 27, 2023 at 3:41 PM Tony Dinh wrote:
> > > >
> > > > Hi Pali,
> > > > I
On Tue, Feb 28, 2023 at 11:28:24AM +0200, Ilias Apalodimas wrote:
> Hi Tom,
>
> The following changes since commit 5b197eee334bdf75cc9e9148161299679a5251ea:
>
> Merge tag 'v2023.04-rc3' into next (2023-02-27 17:28:21 -0500)
>
> are available in the Git repository at:
>
> https://source.den
On Mon, Feb 27, 2023 at 05:52:29PM +0100, Dario Binacchi wrote:
> Hi Tom,
>
> The following changes since commit 0024e7f72b689f8c2df731a69e20f47b6f8dc5a7:
>
> Merge branch 'master' of
> https://source.denx.de/u-boot/custodians/u-boot-tegra (2023-02-23
> 17:40:18 -0500)
>
> are available in th
From: chao zeng
Add support for the M.2 board based on the iot2050 advanced board.
The board has two m.2 connectors, one is B-keyed, the other E-keyed.
The B-key slot can connect 5G/SSD devices, and E-key can be used for
WIFI/BT devices.
This variant is covered by PG2 firmware image.
Signed-off
From: Jan Kiszka
The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
wri
From: Jan Kiszka
This feature is desired on the platform.
Signed-off-by: Jan Kiszka
---
configs/iot2050_pg1_defconfig | 1 +
configs/iot2050_pg2_defconfig | 5 +
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_pg1_defconfig
ind
From: Jan Kiszka
This is enabled by default, thus should be described as well.
Signed-off-by: Jan Kiszka
---
doc/board/siemens/iot2050.rst | 4
1 file changed, 4 insertions(+)
diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index cb49a0e36bf..efe94a448a9 100644
From: Jan Kiszka
Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.
From: Jan Kiszka
Allows to create a public key device tree dtsi for inclusion into U-Boot
SPL and proper during first build already. This can be achieved via
CONFIG_DEVICE_TREE_INCLUDES.
Signed-off-by: Jan Kiszka
---
tools/key2dtsi.py | 64 +++
1 fil
From: Jan Kiszka
There are many ways to get a signed firmware for the IOT2050 devices,
namely for the parts under user-control. This script documents one way
of doing it, given a signing key. Augment the board documentation with
the required procedure around it.
Signed-off-by: Jan Kiszka
---
d
From: chao zeng
User-button is controlled by the mcu domain gpio number 25.
But main0 main1 mcu domain all have gpio number 25.
To identify where the gpio is from, Using gpio controll base as the prefix
to indicate the gpio resource.
Signed-off-by: chao zeng
---
board/siemens/iot2050/board.c
Flushing our upstream queue for the IOT2050 device, this mostly
brings board-specific changes such as:
- updated build process and firmware layout for PG1 vs. PG2 devices
- more watchdog preparations
- preparations for verified boot on IOT2050 Advanced devices
- support for M.2 variant
Change
From: Jan Kiszka
Will be needed when CONFIG_ENV_WRITEABLE_LIST is enabled. The listed
variables shall remain writable, for informational purposes - they have
to be considered untrusted because the persistent U-Boot env is not
protected.
Signed-off-by: Jan Kiszka
---
include/configs/iot2050.h |
From: Su Baocheng
Refactor according to the entry `fit: Entry containing a FIT` of
document tools/binman/README.entries.
As the generator uses the device tree name for the config description,
board_fit_config_name_match requires a small adjustment as well.
Signed-off-by: Su Baocheng
[Jan: re-a
From: Su Baocheng
Due to different signature keys, the PG1 and the PG2 boards can no
longer use the same FSBL (tiboot3). This makes it impossible anyway to
maintaine a single flash.bin for both variants, so we can also split the
build.
A new target is added to indicates the build is for PG1 vs.
From: Jan Kiszka
The latest version of the binary-only firmware parts come in a combined
form of FSBL and sysfw containers. This implies some layout changes to
the generated firmware image but also makes handling of artifacts much
simpler (4 files less). The env locations will not change, just th
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