: 0x40605060
EDIS: 0x
ECNTRL: 0x1000
Im using u-boot-2009-11
Any help is welcome,
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zero.
- If I use chip select from CPM (SPISEL, dedicated pin), instead a
simple GPIO, I got a Multiple Master Error, as if it was reading the
pin.
Any help is welcome, thanks!
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On Mon, Oct 12, 2009 at 4:24 AM, Jens Gehrlein se...@tqs.de wrote:
Hi Alemao,
Alemao schrieb:
Hi all,
I have used UPM in a MPC83xx with LBC running at 64MHz.
Now I have a MPC85xx, with LBC at 41MHz.
It only works if I put a delay in drivers/mtd/nand/fsl_upm.c :
nand_write_buf
in board/tqc/tqm85xx/nand.c that the driver use an UPM
configuration for each frequency.
Can some one tell me what signals I have to change or just some hint
about what could be causing this behavior?
Im using UPM waveform editor and u-boot-2009-03.
Thanks in advance,
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Alemao
is first executed in
the last 4K page(0xf000-0x) in flash/rom.
So I think there's nothing in 0xfffc, using u-boot.bin from
u-boot-2009.03, cause it only has 516kB.
Do I have to set TEXT_BASE with the exact u-boot.bin size?
Or am I missing something?
Cheers,
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Alemao
that another variable is limiting the size to 512kB.
Cheers,
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address. Is it not needed?
In almost all boards thats use ethernet FCC, I saw the flag FCC_PSMR_LPB seted:
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Why loopback is seted by default?
Cheers,
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-03.
Cheers,
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On Tue, Jul 7, 2009 at 7:41 PM, Kim Phillipskim.phill...@freescale.com wrote:
On Tue, 7 Jul 2009 15:01:05 -0300
Alemao xcarand...@gmail.com wrote:
On Mon, Jul 6, 2009 at 7:07 PM, Alemaoxcarand...@gmail.com wrote:
On Mon, Jul 6, 2009 at 3:45 PM, Scott Woodscottw...@freescale.com wrote:
I
On Mon, Jul 6, 2009 at 7:07 PM, Alemaoxcarand...@gmail.com wrote:
On Mon, Jul 6, 2009 at 3:45 PM, Scott Woodscottw...@freescale.com wrote:
On Mon, Jul 06, 2009 at 02:39:26PM -0300, Alemao wrote:
Hi all,
I've made ports of u-boot for two powerpc processors, MPC8343 and
MPC8541.
The boards
: memories get ddr_clk / 2
Make sense?
Is this cause MPC85xx family has L2 cache?
Or cause ddr_clk? Or my port has problems in DDR configuration?
Im using Micron DDR2 memory, MT47H32M16HR-3:F, with CL = 3 for both ports.
Thanks in advance,
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Alemao
On Mon, Jul 6, 2009 at 3:45 PM, Scott Woodscottw...@freescale.com wrote:
On Mon, Jul 06, 2009 at 02:39:26PM -0300, Alemao wrote:
Hi all,
I've made ports of u-boot for two powerpc processors, MPC8343 and
MPC8541.
The boards has 128MB of DDR2. So I enabled CFG_DRAM_TEST in 127MB
of those
?
My board has 128 MB of DDR SDRAM, I think space is not a problem, so
is there a place that I can set for exemple max values for
allocations?
Im using U-boot-1.2.0.
Cheers,
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On Fri, Jan 16, 2009 at 8:46 PM, Anton Vorontsov
avoront...@ru.mvista.com wrote:
On Fri, Jan 16, 2009 at 02:02:26PM -0200, Alemao wrote:
I'm guessing that 1.2.0 was a BSP u-boot, that was not upstream. I don't
think upstream 1.2.0 had UPM NAND support.
You are right, there were no UPM
On Tue, Jan 20, 2009 at 8:56 AM, Alemao xcarand...@gmail.com wrote:
On Fri, Jan 16, 2009 at 8:46 PM, Anton Vorontsov
avoront...@ru.mvista.com wrote:
On Fri, Jan 16, 2009 at 02:02:26PM -0200, Alemao wrote:
I'm guessing that 1.2.0 was a BSP u-boot, that was not upstream. I don't
think
I'm guessing that 1.2.0 was a BSP u-boot, that was not upstream. I don't
think upstream 1.2.0 had UPM NAND support.
You are right, there were no UPM support on U-boot-1.2.0.
I used patches sended by Anton from here:
.
Is there any other configuration in u-boot that I have to do?
Is there a problem using a loop in FPGA? Or a real PHY do some more
things to the signal when we put it in loop?
PS: FPGA doesnt reply to any mdio commands, so u-boot thinks its a
generic phy.
Cheers,
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Alemao
00 00 00 00 00 00 00 00 00 00 00 00 00 X...
Thanks in advance,
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is at linux/drivers/mtd/chips
The UPM driver is at linux/drivers/mtd/nand
So, how can I load the UPM driver before physmap?
Thanks in advance,
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) ?
Thanks in advance
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that an
out_8(), for example, should start at offset 24 (write data) in upm.
My question is: how u-boot knows it? Can I change this?
Cheers,
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-RDK, but I found one difference:
MPC8360E-RDK is running at 667 Mhz and mine is at 500 Mhz (CSB: 333 MHz)
Could this influence local bus timming?
Cheers,
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Alemao
On Thu, Aug 14, 2008 at 2:22 PM, Alemao [EMAIL PROTECTED] wrote:
Dont know if can be a hardware problem, cause NAND is found
thing i notice: when reseting the board without turning off
power, NAND is not found.
Cheers,
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Alemao
On Tue, Aug 12, 2008 at 2:57 PM, Scott Wood [EMAIL PROTECTED] wrote:
Alemao wrote:
Hi all,
Im trying to use my NAND flash at MPC8360E-RDK based board.
But it seems that the whole chip
did not fit into device, due to bad blocks
1 bytes written: ERROR
=
Any help/suggestions welcome.
Im using U-Boot-1.1.4 with NAND and FSL_UPM drivers from U-Boot-1.3.3
Cheers,
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