Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment.
It enables PCIe reset to fix link width 2x - 4x.
Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
include/configs/T208xQDS.h |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/include/c
For some special reset times for longer pcie devices, the pcie device
may on polling compliance state, the RC considers the pcie device is
link up, but the pcie device is not link up, only the L0 state is link
up state.
Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
arch/powerpc/i
Adjust the code structure, detail the function module function,
remove the redundancy code.
Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
arch/powerpc/include/asm/fsl_pci.h | 1 +
drivers/pci/fsl_pci_init.c | 150 -
2 files chang
Fix the whitespace of PCI_LTSSM_L0 in fsl_pci.h
Signed-off-by: Bao Xiaowei <xiaowei@nxp.com>
---
arch/powerpc/include/asm/fsl_pci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h
b/arch/powerpc/include/asm/fsl_pci.h
index cad3
-by: Bao Xiaowei <xiaowei@nxp.com>
---
v2:
- Detailed function module
- Adjust the code structure
arch/powerpc/include/asm/fsl_pci.h | 3 +
drivers/pci/fsl_pci_init.c | 151 -
2 files changed, 86 insertions(+), 68 deletions(-)
diff --git
-by: Bao Xiaowei <xiaowei@nxp.com>
---
drivers/pci/pcie_layerscape.c | 25 +
drivers/pci/pcie_layerscape.h | 3 +++
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 78cde21..4db95c5
modifiy the ls_pcie_link_up function, add the following three judging
mechanisms:
detect state: return link down status;
L0 state: return link up status;
other state: delay about 100ms retrieve Status Returns the corresponding link
status;
Signed-off-by: Bao Xiaowei <xiaowei@nxp.
ot;
mtd20: 0010 0004 "nand_uboot_env"
mtd21: 0020 0004 "nand_ppa"
mtd22: 0030 0004 "nand_secure_boot"
mtd23: 0060 0004 "nand_dppa_qe"
mtd24: 0010 0004 "nand_dtb"
mtd25: 0100 0004 "nand_kernel&quo
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