Dear Tom,
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing:
1. Add option to reprogram FPGA every reboot, enable this as default in
chameleonv3 defconfig.
2. Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG, so
the driver can be built when
> -Original Message-
> From: U-Boot On Behalf Of "Michal
> Barnas"
> Sent: Wednesday, March 20, 2024 2:18 AM
> To: u-boot@lists.denx.de
> Cc: "Michał Barnaś" ; "Marcel Ziswiler"
> ; "Martyn Welch"
> ; "Paweł Anikiel" ;
> "Simon Glass" ; "Svyatoslav Ryhel"
> ; "Tom Rini"
> Subject:
> -Original Message-
> From: Michał Barnaś
> Sent: Wednesday, March 20, 2024 2:18 AM
> To: u-boot@lists.denx.de
> Cc: Michał Barnaś ; Dinh Nguyen
> ; Marek Vasut ; Simon Glass
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Tom Rini
> Subject: [PATCH v3 1
> -Original Message-
> From: Lau, Wan Yee
> Sent: Thursday, March 28, 2024 2:24 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Chong, Teik Heng
> ; Marek ; Hea, Kok Kiang
>
> Subject: [PATCH v1 1/1] [U-Boot] drivers: misc: Fixes: Rename
>
> -Original Message-
> From: Tom Rini
> Sent: Monday, March 18, 2024 8:29 PM
> To: Chee, Tien Fong
> Cc: u-boot@lists.denx.de; Vasut, Marek ; Hea, Kok Kiang
> ; Lim, Jit Loon ; Lau, Wan
> Yee
> Subject: Re: Pull Request: SoCFPGA changes for efi-2024-04-rc5
&
Dear Tom,
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing:
1. A new driver in the misc to register setting from device tree. This also
provides user a clean interface and all register
settings are centralized in one place, device tree.
1. Enable Agilex5 platform
Dear Tom,
Please pull the SoCFPGA changes for master from u-boot-socfpga, thanks.
Best regards,
Tien Fong
The following changes since commit 86fd291a7990af84e96808f48eff2219dd4ef496:
Merge tag 'efi-2024-04-rc5' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2024-03-13 20:39:46
Hi,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, March 12, 2024 10:01 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
>
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Monday, March 11, 2024 9:52 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
>
Hi Jit loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Thursday, March 7, 2024 12:42 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
>
Hi,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Thursday, March 7, 2024 12:42 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
>
> -Original Message-
> From: Michał Barnaś
> Sent: Thursday, February 22, 2024 11:21 PM
> To: u-boot@lists.denx.de
> Cc: Michał Barnaś ; Dinh Nguyen
> ; Marek Vasut ; Simon Glass
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Tom Rini
> Subject: [PATCH 1
> -Original Message-
> From: Michał Barnaś
> Sent: Thursday, February 29, 2024 9:49 PM
> To: Dinh Nguyen
> Cc: u-boot@lists.denx.de; Marcel Ziswiler ;
> Marek Vasut ; Martyn Welch
> ; Paweł Anikiel ; Simon
> Glass ; Simon Goldschmidt
> ; Svyatoslav Ryhe
Hi,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, February 20, 2024 10:36 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Marek ;
> Simon ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
>
> -Original Message-
> From: Lau, Wan Yee
> Sent: Monday, February 5, 2024 11:47 AM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Chong, Teik Heng
> Subject: [PATCH v2 1/1] drivers: misc: Add socfpga_dtreg driver for I
> -Original Message-
> From: U-Boot On Behalf Of "Alexander
> Daum"
> Sent: Wednesday, January 4, 2023 5:11 AM
> To: u-boot@lists.denx.de
> Cc: "Alexander Daum"
> Subject: [PATCH 1/1] socfpga_de1_soc: Specify Uart clock in dts
>
> UART output was broken since commit c402e8170245
Hi Tom,
> -Original Message-
> From: Tom Rini
> Sent: Monday, January 22, 2024 10:47 PM
> To: Chee, Tien Fong
> Cc: u-boot@lists.denx.de; Vasut, Marek ; Maniyam,
> Dinesh ; Hea, Kok Kiang
>
> Subject: Re: Pull request: SoCFPGA changes for commit 3c9bb8fbdc77f
&
Hi Tom,
Please pull the SoCFPGA changes as shown in below.
Best regards,
Tien Fong
The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78:
Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 11:39:13
-0500)
are available in the Git repository at:
Hi,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Thursday, December 7, 2023 3:46 PM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Maniyam, Dinesh ;
> Ng, Boon Khai ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Hen
Hi,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Friday, December 15, 2023 3:15 PM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Lukasz Majewski ; Sean Anderson ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yusla
Hi,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Friday, December 15, 2023 3:22 PM
> To: u-boot@lists.denx.de
> Cc: Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yuslaimi, Alif Zakuan ; Chong, Teik Hen
cio ;
> Marek Vasut ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH v1 1/1] drivers: misc: Ad
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 21 June, 2023 11:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
>
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 21 June, 2023 11:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
>
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 21 June, 2023 11:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
>
Hi,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 31 August, 2022 2:46 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R
> ; Vasut, Marek ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lim, Elly Siew Chin ; Kho, Sin Hui
>
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, 30 August, 2022 11:52 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Lim, Elly Siew Chin ;
> Kho, Sin Hui ; Lokanathan, Raaj
> -Original Message-
> From: Lim, Jit Loon
> Sent: Wednesday, 31 August, 2022 1:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Lim, Elly Siew Chin ;
> Kho, Sin Hui ; Lokanatha
Hi Jit Loon,
> -Original Message-
> From: Lim, Jit Loon
> Sent: Tuesday, 2 August, 2022 9:55 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Vasut, Marek ; Simon ;
> Chaplin, Kris ; Chee, Tien Fong
> ; Hea, Kok Kiang ; Lim,
> Elly Siew Chin ;
Hi Tom,
Please pull the SoCFPGA changes as shown in below.
Thanks.
Best regards,
Tien Fong
The following changes since commit 05dcb5be507a0580a0fc57dd363c632ac4a6b3c4:
mtd: mxs_nand_spl: fix nand_command protocol violation (2022-06-29 09:26:44
-0400)
are available in the Git repository
> -Original Message-
> From: Chong, Teik Heng
> Sent: Wednesday, 29 June, 2022 1:52 PM
> To: u-boot@lists.denx.de
> Cc: Lukasz ; Sean ; Simon
> ; Chaplin, Kris ;
> Hea, Kok Kiang ; Chee, Tien Fong
> ; Lim, Elly Siew Chin
> ; Kho, Sin Hui ;
> Lokanathan,
> -Original Message-
> From: Paweł Anikiel
> Sent: Tuesday, 21 June, 2022 12:00 AM
> To: Chee, Tien Fong
> Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org;
> feste...@denx.de; ja...
> -Original Message-
> From: Paweł Anikiel
> Sent: Monday, 20 June, 2022 8:14 PM
> To: Chee, Tien Fong
> Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org;
> feste...@denx.de; ja...@amarulasolutio
Hi,
> -Original Message-
> From: Paweł Anikiel
> Sent: Friday, 17 June, 2022 6:47 PM
> To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> Chee, Tien Fong ; michal.si...@xilinx.com
> Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> ja...
Hi Tom,
Please pull the SoCFPGA changes as shown in below.
Thanks.
Best regards,
Tien Fong
The following changes since commit c18e5fb055ab789f58434e3cb432582adee0134c:
dtoc: Update test_src_scan.py for new tegra compatibles (2022-06-14 13:59:23
-0400)
are available in the Git repository
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Wednesday, 1 June, 2022 6:49 PM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Lim, Elly Siew Chin
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokana
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Wednesday, 1 June, 2022 3:57 PM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Mani
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Wednesday, 1 June, 2022 3:55 PM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> M
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 4:15 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Hea, Kok Kiang
> ; Gan, Yau Wai ; Kho,
> Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh
>
> Subject: [PATCH] arm: dts:
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 4:06 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong ; Hea, Kok Kiang
> ; Gan, Yau Wai ; Kho,
> Sin Hui ; Lokanathan, Raaj
> ; Maniyam, Dinesh
>
> Subject: [PATCH] arm: dt
Hi Pawel,
> -Original Message-
> From: Paweł Anikiel
> Sent: Thursday, 26 May, 2022 10:37 PM
> To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> Chee, Tien Fong ; michal.si...@xilinx.com
> Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> ja...
Ying-Chun
> Liu ; Christian Hewitt ;
> adrian.fiergol...@fastree3d.com; Marek Behún ; Denk,
> Wolfgang ; Lim, Elly Siew Chin ;
> Chee, Tien Fong ; Michal Simek
> ; Vasut, Marek ; Marcin Wojtas
>
> Subject: Re: [PATCH v2 00/11] Add Chameleon v3 support
>
> On Thu, May 26, 20
> -Original Message-
> From: Marek Vasut
> Sent: Saturday, 11 June, 2022 6:08 PM
> To: Chee, Tien Fong ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Chaplin, Kris
> ; Hea, Kok Kiang ; Kho, Sin
> Hui ; Lokanathan, Raaj ;
> Maniyam, Dinesh
> Subject:
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Friday, 13 May, 2022 10:15 AM
> To: u-boot@lists.denx.de
> Cc: Vasut, Marek ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam,
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Tuesday, 31 May, 2022 3:51 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh
> Subject: [PAT
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Monday, 9 May, 2022 3:43 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ley Foon Tan
> -Original Message-
> From: Gan, Yau Wai
> Sent: Tuesday, 24 May, 2022 3:02 PM
> To: u-boot@lists.denx.de
> Cc: Gan, Yau Wai ; Chee, Tien Fong
>
> Subject: [PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
>
> From: Yau Wai Gan
>
>
Hi,
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 21 December, 2021 5:58 AM
> To: u-boot@lists.denx.de
> Cc: tr...@konsulko.com; Vasut, Marek ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH] arm: socfpga: vinin
Hi Tom,
Please pull the SoCFPGA changes for clk-2022.01-rc3.
Regards
Tien Fong
The following changes since commit 5b20efeafec0ebe0ee5742c611e4f2153346797a:
Merge tag 'clk-2022.01-rc3' of
https://source.denx.de/u-boot/custodians/u-boot-clk (2021-12-15 14:51:44 -0500)
are available in the Git
> -Original Message-
> From: Kho, Sin Hui
> Sent: Sunday, 7 November, 2021 11:09 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; Chee, Tien Fong ; Hea, Kok
> Kiang ; Westergreen, Dalon
> ; Cozart, Sue ; Kho,
> Sin Hui
> Sub
> -Original Message-
> From: Kho, Sin Hui
> Sent: Sunday, 7 November, 2021 11:09 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; Chee, Tien Fong ; Hea, Kok
> Kiang ; Westergreen, Dalon
> ; Cozart, Sue ; Kho,
> Sin Hui
> Sub
> -Original Message-
> From: Kho, Sin Hui
> Sent: Sunday, 7 November, 2021 11:09 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; Chee, Tien Fong ; Hea, Kok
> Kiang ; Westergreen, Dalon
> ; Cozart, Sue ; Kho, Sin
> Hui
> Sub
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 8/8] arm: socfpga: vining: Let DWMAC
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 7/8] arm: socfpga: vining: Enable DW I2C dri
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 5/8] arm: socfpga: vining: Un-dis
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 4/8] arm: socfpga: vining: Set default S
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 3/8] arm: socfpga: vining: Set USB gadge
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 2/8] arm: socfpga: vining: Increase env
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:25 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH 1/8] arm: socfpga: vining: Drop meaningle
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, 14 September, 2021 11:20 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Lim, Elly Siew Chin
> ; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: [PATCH] ddr: altera: use KBUILD_B
Hi Tom
Please pull the SoCFPGA changes for efi-2021-10-rc3.
Regards
Tien Fong
The following changes since commit 4865db07169126ca0205f1a6265adf01bd69b3df:
Merge tag 'efi-2021-10-rc3' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2021-08-23 12:44:12 -0400)
are available in the Git
Hi,
> -Original Message-
> From: Tom Rini
> Sent: Wednesday, 11 August, 2021 4:57 AM
> To: Marek Vasut
> Cc: u-boot@lists.denx.de; Simon Goldschmidt
> ; Chee, Tien Fong
>
> Subject: Re: [PATCH 1/1] arm: socfpga: Migrate CONFIG_HPS namespace to HPS
>
>
Hi Simon,
> -Original Message-
> From: Simon Glass
> Sent: Tuesday, 22 June, 2021 9:32 PM
> To: Chee, Tien Fong
> Cc: Ley Foon Tan ; Lim, Elly Siew Chin
> ; ZY - u-boot ; Marek
> Vasut ; Tan, Ley Foon ; See, Chin
> Liang ; Simon Goldschmidt
> ; Westergr
Hi Ley Foon,
> -Original Message-
> From: Ley Foon Tan
> Sent: Friday, 14 May, 2021 5:13 PM
> To: Lim, Elly Siew Chin
> Cc: ZY - u-boot ; Marek Vasut ;
> Tan, Ley Foon ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
>
> -Original Message-
> From: Tan, Ley Foon
> Sent: Wednesday, 14 April, 2021 6:30 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Ga
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Friday, 9 April, 2021 1:54 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Friday, 9 April, 2021 2:08 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Monday, 5 April, 2021 3:17 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass
On Fri, 2019-10-04 at 15:30 -0700, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> Add a script to process hps handoff data and generate a header
> for inclusion in u-boot specific devicetree addons. The header
> should be included in the top level u-boot.dtsi.
>
> Signed-off-by: Dalon
On Thu, 2019-08-22 at 09:54 +0200, Marek Vasut wrote:
> On 8/22/19 9:40 AM, Chee, Tien Fong wrote:
> >
> > On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote:
> > >
> > > From: Tien Fong Chee
> > >
> > > Different SPI
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Adding UBI support for SPI flash.
>
> Signed-off-by: Tien Fong Chee
> ---
> common/spl/spl_ubi.c| 11 ++-
> drivers/mtd/spi/sf-uclass.c | 30 ++
>
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Different SPI flash has different block erase size configuration, it
> can
> be configured as block erase size or sub-block erase size, so
> SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent
On Fri, 2019-05-24 at 14:00 +0200, Simon Goldschmidt wrote:
> On Fri, May 24, 2019 at 1:57 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
> > >
> > > On Fri, May 24
On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
> On Fri, May 24, 2019 at 1:44 PM Marek Vasut wrote:
> >
> >
> > On 5/24/19 1:40 PM, tien.fong.c...@intel.com wrote:
> > >
> > > From: Tien Fong Chee
> > >
> > > Current implementation almost release all peripherals out of
> > >
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> Introduce a framework that allows loading the System Firmware (SYSFW)
> binary as well as the associated configuration data from an image
> tree
> blob named "sysfw.itb" from an FS-based boot media using the FS
> loader
> framework.
>
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> From: Lokesh Vutla
>
> In order to load the sysfw.itb from an MMC device, clocks should be
> hard
> coded to the same value as ROM configured frequency. Clock updates
> cannot
> happen at this point as SYSFW is not yet available. So
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> To give us more flexibility using the FS loader eliminate the need of
> always having to use the ENV to configure the block device but rather
> allow the respective block device and partition to be setup through
> platform data.
>
>
On Thu, 2019-05-16 at 15:54 -0500, Andreas Dannenberg wrote:
> Introduce a framework that allows loading the System Firmware (SYSFW)
> binary as well as the associated configuration data from an image
> tree
> blob named "sysfw.itb" from an FS-based boot media using the FS
> loader
> framework.
>
On Sat, 2019-04-27 at 10:43 -0400, Tom Rini wrote:
> On Fri, Apr 26, 2019 at 06:12:40AM +0000, Chee, Tien Fong wrote:
> >
> > On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> > >
> > > On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.
On Wed, 2019-05-08 at 13:43 -0500, dannenb...@ti.com wrote:
> Hi TF,
> thanks for chiming in. Comments inlined...
>
> On Wed, May 08, 2019 at 04:31:35AM +, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
> > >
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> > >
> > > On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> > > >
> > > >
>
On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> > > >
> > > >
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
>
> On 07.05.19 19:25, Andreas Dannenberg wrote:
> >
[...]
> >
> > While I also have a working solution based on the existing FS
> > loader
> > framework this has its own challenges, namely by its very nature
> > only
> > addressing a
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is
On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 20
On Fri, 2019-05-03 at 13:54 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:56 AM Chee, Tien Fong com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 20
On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.c
On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.c
On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Increasing Malloc pool size up to 0x15000 is required to support
> > FAT in SPL
> > . The result of calculation is come from after applying
On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is
On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.c...@intel.com
> wrote:
>
> >
> > From: Tien Fong Chee
> >
> > This would print out all the FPGA node names setting to fpga
> > property.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> >
On Tue, 2019-03-19 at 16:50 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This version mainly resolved comments from Dinh in [v11].
>
> This series is working on top of u-boot.git http://git.denx.de/u-boot
> .git
>
> These patches are required before applying this series of
On Wed, 2019-03-27 at 09:40 -0400, Tom Rini wrote:
> On Wed, Mar 27, 2019 at 07:00:19AM +0100, Stefan Roese wrote:
> >
> > Hi Marek,
> >
> > On 26.03.19 17:43, Marek Vasut wrote:
> > >
> > > I would like to nominate Simon Goldschmidt as a co-custodian for
> > > the
> > > SoCFPGA platform to
On Tue, 2019-03-19 at 17:29 +0100, Simon Goldschmidt wrote:
> Am 19.03.2019 um 17:19 schrieb Chee, Tien Fong:
> >
> > On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote:
> > >
> > > Instead of fixing the SPL stack to 64 KiB in the bo
On Fri, 2019-03-15 at 21:13 +0100, Simon Goldschmidt wrote:
> Instead of fixing the SPL stack to 64 KiB in the board config header
> via
> CONFIG_SYS_SPL_MALLOC_SIZE, let's just use
> CONFIG_SPL_SYS_MALLOC_F_LEN
> in the defconfig.
>
> This also has the advandage that it removes sub-mach specific
On Tue, 2019-03-19 at 09:22 +0800, Simon Glass wrote:
> Hi Tien Fong,
>
> On Mon, 11 Mar 2019 at 12:28, Chee, Tien Fong om> wrote:
> >
> >
> > On Sun, 2019-03-10 at 15:51 -0600, Simon Glass wrote:
> > >
> > > Hi Tien Fong,
> > >
>
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