From: Conor Dooley
A given AMP configuration for a board may make either one, or neither
of, the ethernet ports available to U-Boot. The Icicle's init code will
fail if mac1 is not present, so move it to the optional approach taken
for mac0.
Signed-off-by: Conor Dooley
---
board/microchip
From: Conor Dooley
Node offsets returned by libfdt can contain negative error numbers, so
the variable type should be "int". As things stand, if the ethernet
nodes are not found in the early init callback, the if (node < 0) tests
pass and the code errors out while trying to set
From: Conor Dooley
Two fixes for issues that I spotted today while looking into passing a
minimal dtb to U-Boot from the first bootloader stage. This minimal dtb
had no ethernet nodes, and the code in this patches fell over :\
Cheers,
Conor.
---
CC: Padmarao Begari
CC: Cyril Jean
CC: Tom Rini
On Tue, Apr 23, 2024 at 09:52:06AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 4/23/24 09:41, Conor Dooley wrote:
> > On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote:
> > > On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote
On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote:
> On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:
> > [EXTERNAL MAIL]
> >
> > Hi,
> >
> > In QEMU we have a 'max' type CPU that implements (almost) all extensions
> > that QEMU
> > is able to emulate. Recently,
From: Conor Dooley
A new property has been added, with an extensive rationale at [1], that
can be used in place of "riscv,isa" to indicate what extensions are
supported by a given platform that is a list of strings rather than a
single string. There are some differences between the ne
From: Conor Dooley
cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get
the description, but it is no longer a required property and cannot be
assummed to always be present, as the new "riscv,isa-extensions" and
"riscv,isa-base" properties may
From: Conor Dooley
This would have just been a single patch (the second one), but as I
reported a while back there's a problem with extension detection when
the ISA string exceeds 32 characters:
https://lore.kernel.org/u-boot/20240221-daycare-reliably-8ec86f95fe71@spud/
The first patch here
On Tue, Mar 12, 2024 at 05:59:44PM +0800, Leo Liang wrote:
> On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote:
> > Add ethernet node for cv1800b SoC
> >
> > Signed-off-by: Kongyang Liu
> > ---
> >
> > arch/riscv/dts/cv18xx.dtsi | 6 ++
> > 1 file changed, 6 insertions(+)
>
>
On Fri, Mar 01, 2024 at 01:54:13PM -0500, Tom Rini wrote:
> On Fri, Mar 01, 2024 at 01:32:53PM +0000, Conor Dooley wrote:
> > > > > > > > > On Wed, 28 Feb 2024 at 18:40, Tom Rini
> > > > > > > > > wrote:
> > > > > > &
; Fixes: dfe08374943c ("risc-v: implement DBCN based debug console")
> Signed-off-by: Heinrich Schuchardt
This also appears to fix the inconsistent boot issues that I've been
seeing since I reported:
https://lore.kernel.org/u-boot/20240122-finicky-ancient-797ba048f927@spud/
Tested-by: Con
ot the implementation ID.
>
> * Show the correct number
> * Use a hexadecimal output format
> * Add a missing line feed
>
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Conor Dooley
Thanks,
Conor.
> cmd/riscv/sbi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
sion because of space
constraints mostly. Since the bug prevents using some forms of suspend,
we moved to a custom implementation ID so that there could be
differentiation.
Reviewed-by: Conor Dooley
Cheers,
Conor.
> ---
> cmd/riscv/sbi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> dif
On Tue, Mar 05, 2024 at 09:10:59AM +0100, Heinrich Schuchardt wrote:
> On 3/5/24 08:54, Conor Dooley wrote:
> > On Tue, Mar 05, 2024 at 08:34:20AM +0100, Heinrich Schuchardt wrote:
> > > On 3/5/24 00:28, Conor Dooley wrote:
> > > > From: Conor Dooley
> > >
On Tue, Mar 05, 2024 at 08:34:20AM +0100, Heinrich Schuchardt wrote:
> On 3/5/24 00:28, Conor Dooley wrote:
> > From: Conor Dooley
> According to
> https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc the
> ISA string is case insensitive. Why can we assume her
From: Conor Dooley
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi
Apologies for the delay replying here.
On Thu, Feb 22, 2024 at 01:36:41PM +0100, Heinrich Schuchardt wrote:
> On 21.02.24 18:59, Conor Dooley wrote:
> > I mentioned this last night to Heinrich on IRC, supports_extension() is
> > broken for ISA strings longer than 32 characters
Hey,
Replying here because this is only version of this in my inbox atm.
On Fri, Mar 01, 2024 at 10:17:35AM +0100, Sébastien Szymanski wrote:
> On 3/1/24 07:02, Sumit Garg wrote:
> > On Thu, 29 Feb 2024 at 19:31, Tom Rini wrote:
> > > On Thu, Feb 29, 2024 at 08:42:42AM -0500, Tom Rini wrote:
>
Yo,
I mentioned this last night to Heinrich on IRC, supports_extension() is
broken for ISA strings longer than 32 characters. M-Mode U-Boot doesn't
parse a devicetree, so this doesn't apply there, but for S-mode
supports_extension() looks like:
static inline bool supports_extension(char ext)
{
On Tue, Jan 23, 2024 at 01:03:00PM -0500, Tom Rini wrote:
> On Tue, Jan 23, 2024 at 11:27:57AM +0000, Conor Dooley wrote:
> > On Mon, Jan 22, 2024 at 06:55:01PM +0000, Conor Dooley wrote:
> > > On Mon, Jan 22, 2024 at 01:47:17PM -0500, Tom Rini wrote:
> > > > On M
On Mon, Jan 22, 2024 at 06:55:01PM +, Conor Dooley wrote:
> On Mon, Jan 22, 2024 at 01:47:17PM -0500, Tom Rini wrote:
> > On Mon, Jan 22, 2024 at 06:36:31PM +0000, Conor Dooley wrote:
> > > Hey,
> > >
> > > On Tue, Jan 16, 2024 at 01:48:06PM +
On Mon, Jan 22, 2024 at 01:47:17PM -0500, Tom Rini wrote:
> On Mon, Jan 22, 2024 at 06:36:31PM +0000, Conor Dooley wrote:
> > Hey,
> >
> > On Tue, Jan 16, 2024 at 01:48:06PM +, Conor Dooley wrote:
> > > Yo,
> > >
> > > On Wed, Jan
Hey,
On Tue, Jan 16, 2024 at 01:48:06PM +, Conor Dooley wrote:
> Yo,
>
> On Wed, Jan 03, 2024 at 06:49:19PM -0700, Simon Glass wrote:
> > Standard passage provides for a bloblist to be passed from one firmware
> > phase to the next. That can be used to pass the dev
Yo,
On Wed, Jan 03, 2024 at 06:49:19PM -0700, Simon Glass wrote:
> Standard passage provides for a bloblist to be passed from one firmware
> phase to the next. That can be used to pass the devicetree along as well.
> Add an option to support this.
>
> Tests for this will be added as part of the
On Fri, Dec 22, 2023 at 04:38:01PM +0100, Krzysztof Kozlowski wrote:
> On 22/12/2023 14:43, Sumit Garg wrote:
> > On Fri, 22 Dec 2023 at 13:48, Krzysztof Kozlowski
> > wrote:
> >>
> >> On 22/12/2023 07:12, Sumit Garg wrote:
> >>> Changes in v2:
> >>> --
> >>> - Patch #1: excluded
On Fri, Dec 15, 2023 at 08:37:43AM -0500, Tom Rini wrote:
> On Fri, Dec 15, 2023 at 08:50:51AM +0100, Krzysztof Kozlowski wrote:
> > On 14/12/2023 20:48, Rob Herring wrote:
> > >>
> > >> I think some of the important questions to ask are, how often / likely
> > >> are the breakages to occur? It
On Fri, Dec 08, 2023 at 09:39:27AM +, ff wrote:
>
>
> Le 7 déc. 2023 à 21:31, Conor Dooley a écrit :
>
> What on earth has happened here with quoting? Please fix your mail
> client man, this mail is a mess to read.
>
> Conor: Hopefully I have now fixed MacOS Mail
What on earth has happened here with quoting? Please fix your mail
client man, this mail is a mess to read.
On Thu, Dec 07, 2023 at 08:24:01PM +, ff wrote:
>
>
> Le 7 déc. 2023 à 19:51, Rob Herring a écrit :
>
> On Thu, Dec 7, 2023 at 2:08 AM ff wrote:
>
>
>
> Le 6 déc. 2023 à 21:42,
On Tue, Nov 07, 2023 at 06:23:05PM -0500, Tom Rini wrote:
> On Tue, Nov 07, 2023 at 11:12:16PM +0000, Conor Dooley wrote:
> > +CC Palmer
> >
> > On Tue, Nov 07, 2023 at 05:38:37PM -0500, Tom Rini wrote:
> > > On Tue, Nov 07, 2023 at 10:27:50PM +, Conor Dooley
+CC Palmer
On Tue, Nov 07, 2023 at 05:38:37PM -0500, Tom Rini wrote:
> On Tue, Nov 07, 2023 at 10:27:50PM +0000, Conor Dooley wrote:
> > On Tue, Nov 07, 2023 at 05:10:23PM -0500, Tom Rini wrote:
> >
> >
> > > further clarify or not
> > > the RISC-V IS
On Tue, Nov 07, 2023 at 05:10:23PM -0500, Tom Rini wrote:
> further clarify or not
> the RISC-V ISA thing that's elsewhere in this thread (and part of the
> kernel, not a U-Boot thing).
TBH, this a bit fragmented across threads, and as someone that hasn't
been following it it's a bit difficult
Yo,
Since you sent it to me, I may as well comment...
On Fri, Nov 03, 2023 at 05:03:25PM +0100, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> The patch contains initial wiring and
Hey Heinrich,
On Fri, Jul 28, 2023 at 05:48:31PM +0200, Heinrich Schuchardt wrote:
> Add more detail to the description of U-Boot boot phases:
>
> * describe which steps are optional
> * mentions alternative boot flows
>
> Signed-off-by: Heinrich Schuchardt
> ---
> doc/develop/spl.rst | 13
From: Conor Dooley
intro
=
When the RISC-V dt-bindings were accepted upstream in Linux, the base
ISA etc had yet to be ratified. By the ratification of the base ISA,
incompatible changes had snuck into the specifications - for example the
Zicsr and Zifencei extensions were spun out
On Sat, Jul 01, 2023 at 01:01:40PM +0200, Andrew Jones wrote:
> On Fri, Jun 30, 2023 at 07:04:04PM +0100, Conor Dooley wrote:
> > From: Conor Dooley
> ...
> > +oneOf:
> > + - required:
> > + - riscv,isa
> > + - required:
> > + - riscv,isa-ba
From: Conor Dooley
intro
=
When the RISC-V dt-bindings were accepted upstream in Linux, the base
ISA etc had yet to be ratified. By the ratification of the base ISA,
incompatible changes had snuck into the specifications - for example the
Zicsr and Zifencei extensions were spun out
Been implementing feedback, so going back through this
On Tue, Jun 27, 2023 at 12:30:25PM +0100, Conor Dooley wrote:
> On Mon, Jun 26, 2023 at 11:35:10PM -0700, Atish Patra wrote:
> > On Mon, Jun 26, 2023 at 5:40 PM Stefan O'Rear wrote:
> > > On Mon, Jun 26, 2023, at 6:10 AM,
Hey Atish, Stefan,
On Mon, Jun 26, 2023 at 11:35:10PM -0700, Atish Patra wrote:
> On Mon, Jun 26, 2023 at 5:40 PM Stefan O'Rear wrote:
> > On Mon, Jun 26, 2023, at 6:10 AM, Conor Dooley wrote:
> > > Off-list, some of the RVI folks have committed to shoring up the wording
>
On Mon, Jun 26, 2023 at 11:08:43PM +0530, Anup Patel wrote:
> On Mon, Jun 26, 2023 at 3:42 PM Conor Dooley
> wrote:
> > acpi
> >
> >
> > The current ACPI ECR is based on having a single ISA string unfortunately,
> > but ideally ACPI will move to anot
CC: Rick Chen
CC: Leo
CC: Oleksii
CC: linux-ri...@lists.infradead.org
CC: qemu-ri...@nongnu.org
CC: u-boot@lists.denx.de
CC: devicet...@vger.kernel.org
CC: linux-ker...@vger.kernel.org
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Signed-off-by: Conor Dooley
---
Changes in v3:
- Per Rob's sugg
On Thu, Jun 22, 2023 at 11:25:35AM -0700, Palmer Dabbelt wrote:
> Reviewed-by: Palmer Dabbelt
> Acked-by: Palmer Dabbelt
>
> I'm not wed to any particular encoding for the properties, IMO that's more
> of a decision for the DT folks. IMO the important bit is to just get away
> from ISA
f the icicle's default configuration
is removed.
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi| 71 +++
arch/riscv/dts/mpfs-icicle-kit.dts| 190 +---
arch/riscv/dts/mpfs.dtsi
Begari
Signed-off-by: Conor Dooley
---
board/microchip/mpfs_icicle/mpfs_icicle.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index e74c9fb03c..0f5f82924e 100644
The original names picked for the DT doesn't match Linux's naming scheme
and it was renamed there a while ago. Rename it in U-Boot to allow
easily syncing dts between the two projects.
Reviewed-by: Rick Chen
Reviewed-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/Makefile
address setting code as it'll be needed to support another board.
Cheers,
Conor.
Changes in v2:
- Fix address in error print in 3/3
Conor Dooley (3):
riscv: dts: drop microchip from dts filenames
riscv: dts: sync mpfs-icicle devicetree with linux
board: microchip: set mac address for e
On Tue, Jun 13, 2023 at 05:35:58AM +, padmarao.beg...@microchip.com wrote:
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> > @@ -123,6 +123,15 @@ int board_late_init(void)
> >
> > mac_addr[5] = device_serial_number[0] + 1;
> >
> > + n
On Tue, Jun 13, 2023 at 07:28:34AM -0600, Rob Herring wrote:
> On Mon, Jun 12, 2023 at 3:23 PM Conor Dooley wrote:
> > On Thu, Jun 08, 2023 at 08:30:28PM +0100, Conor Dooley wrote:
> > > On Thu, Jun 08, 2023 at 01:15:37PM -0600, Rob Herring wrote:
> > > > On Tue, Ma
Rob,
Before I press on with more versions...
On Thu, Jun 08, 2023 at 08:30:28PM +0100, Conor Dooley wrote:
> On Thu, Jun 08, 2023 at 01:15:37PM -0600, Rob Herring wrote:
> > On Tue, May 30, 2023 at 03:12:12PM +0100, Conor Dooley wrote:
> > > On Thu, May 18, 2023 at 10:42:34PM +
On Fri, Jun 09, 2023 at 08:03:44AM -0600, Rob Herring wrote:
> Nope, vendor prefixes don't go in node names. That's not explicit
> anywhere, but goes against using generic node names.
Yeah, that makes sense.
> Also, note that looking at the DT spec, there's already prior art here
> with PPC.
On Thu, Jun 08, 2023 at 01:15:37PM -0600, Rob Herring wrote:
> On Tue, May 30, 2023 at 03:12:12PM +0100, Conor Dooley wrote:
> > On Thu, May 18, 2023 at 10:42:34PM +0100, Conor Dooley wrote:
> > > On Thu, May 18, 2023 at 02:30:53PM -0400, Sean Anderson wrote:
> >
>
On Thu, Jun 08, 2023 at 11:49:08AM -0600, Rob Herring wrote:
> On Thu, 08 Jun 2023 17:54:05 +0100, Conor Dooley wrote:
> > As a result of implementing Sean's suggestion, I believe I need to add
> > riscv,isa-extensions as an exception to the rules preventing vendor
> > prope
From: Conor Dooley
intro
=
When the RISC-V dt-bindings were accepted upstream in Linux, the base
ISA etc had yet to be ratified. By the ratification of the base ISA,
incompatible changes had snuck into the specifications - for example the
Zicsr and Zifencei extensions were spun out
The dts sync from Linux leaves mac0/ethernet1 enabled on icicle, but
U-Boot does not currently set a mac address for it. Expand on the code
which currently sets the mac for mac1/ethernet0 to optionally set the
mac address for the second ethernet.
Signed-off-by: Conor Dooley
---
board/microchip
f the icicle's default configuration
is removed.
Signed-off-by: Conor Dooley
---
arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi| 71 +++
arch/riscv/dts/mpfs-icicle-kit.dts| 190 +---
arch/riscv/dts/mpfs.dtsi | 442 --
.../dt-bindings/clock/
The original names picked for the DT doesn't match Linux's naming scheme
and it was renamed there a while ago. Rename it in U-Boot to allow
easily syncing dts between the two projects.
Signed-off-by: Conor Dooley
---
arch/riscv/dts/Makefile | 2 +-
...s
address setting code as it'll be needed to support another board.
Cheers,
Conor.
Conor Dooley (3):
riscv: dts: drop microchip from dts filenames
riscv: dts: sync mpfs-icicle devicetree with linux
board: microchip: set mac address for ethernet1 on icicle
arch/riscv/dts/
On Thu, May 18, 2023 at 10:42:34PM +0100, Conor Dooley wrote:
> On Thu, May 18, 2023 at 02:30:53PM -0400, Sean Anderson wrote:
> >
> > Why not just have something like
> >
> > mycpu {
> > ...
> > riscv,isa {
> > i;
> >
On Fri, May 26, 2023 at 09:34:32AM +0200, Torsten Duwe wrote:
> On Wed, 24 May 2023 11:19:48 +0100
> Conor Dooley wrote:
>
> > On Wed, May 24, 2023 at 05:00:02PM +0800, Xingyu Wu wrote:
> > > On 2023/5/23 19:28, Conor Dooley wrote:
> > > > On Tue, May 23, 20
On Wed, May 24, 2023 at 05:00:02PM +0800, Xingyu Wu wrote:
> On 2023/5/23 19:28, Conor Dooley wrote:
> > On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote:
> >> On Tue, 23 May 2023 09:28:39 +0100
> >> Conor Dooley wrote:
> >>
> >> > On
On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote:
> On Tue, 23 May 2023 09:28:39 +0100
> Conor Dooley wrote:
>
> > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote:
> > > On 2023/5/19 22:16, Conor Dooley wrote:
> > > > On Fri, May 19, 20
On Thu, May 18, 2023 at 02:30:53PM -0400, Sean Anderson wrote:
> On 5/18/23 10:06, Conor Dooley wrote:
> > On Thu, May 18, 2023 at 07:13:15PM +0530, Anup Patel wrote:
> >> On Thu, May 18, 2023 at 4:02 PM Andrew Jones
> >> wrote:
> >> > On Thu, May 18, 2023
On Thu, May 18, 2023 at 07:41:17AM -0700, Palmer Dabbelt wrote:
> On Thu, 18 May 2023 07:06:17 PDT (-0700), Conor Dooley wrote:
> > On Thu, May 18, 2023 at 07:13:15PM +0530, Anup Patel wrote:
> > > On Thu, May 18, 2023 at 4:02 PM Andrew Jones
> > > wrote:
> >
On Thu, May 18, 2023 at 07:13:15PM +0530, Anup Patel wrote:
> On Thu, May 18, 2023 at 4:02 PM Andrew Jones wrote:
> > On Thu, May 18, 2023 at 09:58:30AM +0100, Conor Dooley wrote:
> > > - riscv,isa:
> > > -description:
> > > - Identifies the specific
On Thu, May 18, 2023 at 12:31:51PM +0200, Andrew Jones wrote:
> > + # Additional Standard Extensions, sorted by category then alphabetically
>
> Can we just do pure alphabetically? And the single-letter extensions above
> don't have a "sorted by" comment above them. I guess they need one, or
>
Hey Drew,
On Thu, May 18, 2023 at 12:31:51PM +0200, Andrew Jones wrote:
> On Thu, May 18, 2023 at 09:58:30AM +0100, Conor Dooley wrote:
> > - riscv,isa:
> > -description:
> > - Identifies the specific RISC-V instruction set architecture
> > -
-boot@lists.denx.de
CC: devicet...@vger.kernel.org
CC: linux-ker...@vger.kernel.org
Signed-off-by: Conor Dooley
---
I've tried to CC a few folks here that would care about this, but I am
sure there are more. I'll go cross-post it to sw-dev, if it allows me to
post there...
---
.../devicetree/binding
ng a fair hackier & probably should have
already sent something by now :/ What you have here is either the
same as what we have, or an improvement:
Reviewed-by: Conor Dooley
Thanks for doing this.
signature.asc
Description: PGP signature
On Thu, Mar 16, 2023 at 10:53:29AM +0800, Yanhong Wang wrote:
> Add initial device tree for the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> Tested-by: Conor Dooley
> + S7_0: cpu@0 {
> + compatible = "sifive,s7", "riscv&q
On 22 March 2023 01:37:53 GMT, yanhong wang
wrote:
>
>
>On 2023/3/21 5:25, Conor Dooley wrote:
>> On Thu, Mar 16, 2023 at 10:53:31AM +0800, Yanhong Wang wrote:
>>> Add initial device tree for StarFive VisionFive v2 board.
>>>
>>> Signed-off-by:
On Thu, Mar 16, 2023 at 10:53:31AM +0800, Yanhong Wang wrote:
> Add initial device tree for StarFive VisionFive v2 board.
>
> Signed-off-by: Yanhong Wang
> Tested-by: Conor Dooley
btw, are you running some sort of cc suppression argument to
send-email? There's not much rea
On Tue, Mar 07, 2023 at 06:30:19AM +, Conor Dooley wrote:
>
>
> On 7 March 2023 01:59:31 GMT, yanhong wang
> wrote:
> >
> >
> >On 2023/3/4 5:16, Conor Dooley wrote:
> >> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
> >>>
On 7 March 2023 01:59:31 GMT, yanhong wang
wrote:
>
>
>On 2023/3/4 5:16, Conor Dooley wrote:
>> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
>>> Add initial device tree for the JH7110 RISC-V SoC.
>>>
>>> Signed-off-by: Yanhong Wan
Hey Yanhong,
In the future, if you forget to send a patch as part of the series
itself, please make sure to send it as a reply to the original series.
Since you have the message-id's from your previous invocation of git
send-email, or can trivially find them in your mail client (or somewhere
On Fri, Mar 03, 2023 at 11:24:31AM +0800, Yanhong Wang wrote:
> Add initial device tree for StarFive VisionFive v2 board.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/riscv/dts/Makefile | 3 +-
> ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 85 ++
>
On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
> Add initial device tree for the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/riscv/dts/jh7110.dtsi | 582 +
> 1 file changed, 582 insertions(+)
> create mode 100644
Hey Yanhong,
On Fri, Mar 03, 2023 at 11:24:15AM +0800, Yanhong Wang wrote:
> This series of patches base on the latest branch/master, and add support
> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for
> this to be achieved, the respective DT nodes have been added, and the
On Fri, Mar 03, 2023 at 11:24:17AM +0800, Yanhong Wang wrote:
> This adds support for the StarFive JH7110 SoC which also
> feature this SiFive cache controller.
>
> Signed-off-by: Yanhong Wang
> ---
> drivers/cache/cache-sifive-ccache.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
Hey Jan,
On 2 March 2023 10:04:06 GMT, Jan Reinhard wrote:
>Hello,
>
>
>I am working on the PolarFire RISC-V icicle kit and use u-boot to start my
>application.
>I configured the firmware to start u-boot on all harts (cores) and found out
>that u-boot uses a "HART lottery system" to decide
On 23 February 2023 01:21:01 GMT, "Bernard, Philip"
wrote:
>Hi,
>
>Is it possible to boot from a DRAM memory address beyond the 32-bit boundary?
>I'm trying to configure a new RISC-V board which has 2GB of DRAM starting at
>offset 0x40__. I started from the settings for an existing
On Sun, Jan 22, 2023 at 06:42:04PM +, Conor Dooley wrote:
> On Sat, Jan 21, 2023 at 10:05:47PM +0000, Conor Dooley wrote:
> > > > Apologies if I have missed it somewhere - but where is patch 12?
> > > > I don't see it on lore.kernel.org nor in my inbox :(
> >
On Sat, Jan 21, 2023 at 10:05:47PM +, Conor Dooley wrote:
> > > Apologies if I have missed it somewhere - but where is patch 12?
> > > I don't see it on lore.kernel.org nor in my inbox :(
>
> > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfi
> > Apologies if I have missed it somewhere - but where is patch 12?
> > I don't see it on lore.kernel.org nor in my inbox :(
> https://lore.kernel.org/all/20230118082907.31629-1-yanhong.w...@starfivetech.com/
Oh, thanks! Hopefully I can provide a tested-by so...
> Not sure why it isn't with
On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote:
> This series of patches base on the latest branch/master, and add support
> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for
> this to be achieved, the respective DT nodes have been added, and the
> required
On Thu, Jan 19, 2023 at 02:16:51PM -0500, Sean Anderson wrote:
> On 1/19/23 13:30, Conor Dooley wrote:
> > Hey Seán, David,
> >
> > On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
> >> On 1/19/23 01:18, David Abdurachmanov wrote:
> >> > On
Hey Seán, David,
On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
> On 1/19/23 01:18, David Abdurachmanov wrote:
> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
> > wrote:
> > > + U74_4: cpu@4 {
> > > + compatible = "sifive,u74-mc", "riscv";
>
On Tue, Nov 08, 2022 at 09:23:19AM -0500, Sean Anderson wrote:
> On 11/8/22 09:16, Conor Dooley wrote:
> > > +CONFIG_SYSRESET_SBI=y
> >
> > I took a look at the config option, but something seemed odd to me. It
> > says "depends on SBI_V02" but the help te
oot to match.
Reviewed-by: Conor Dooley
One minor & mostly unrelated question below.
> Signed-off-by: Heinrich Schuchardt
> ---
> configs/microchip_mpfs_icicle_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/configs/microchip_mpfs_icic
On Wed, Nov 02, 2022 at 01:20:33PM +, padmarao.beg...@microchip.com wrote:
> Hi Conor,
>
> > On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> > Currently the clock driver for PolarFire SoC takes a very naive
> > approach
> > to the relationship between
should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.
Reported-by: Andreas Buerkler
Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
Signed-
ravan Chippa
Signed-off-by: Conor Dooley
---
drivers/i2c/i2c-microchip.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c
index 12f65d0af7..3a27459386 100644
--- a/drivers/i2c/i2c-microchip.c
+++ b/dri
Hey all,
Pair of fixes here for some of the logic in the microchip i2c driver.
Both were reported against the Linux driver, which formed the basis for
the U-Boot driver & the issues are present here too.
Thanks,
Conor.
Conor Dooley (2):
i2c: microchip: fix ack sending logic
i2c: micro
Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Co
t;periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.
Signed-off-by: Conor Dooley
---
drivers/clk/microchip/Makefile | 2 +-
drivers/clk/microchip/m
representation of the msspll out for the actual
reference clock.
Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4
arch/riscv/dts/microchip-mpfs.dtsi | 14 ++-
new driver for
it, based on the one in Linux.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley
---
drivers/clk/microchip/mpfs_clk.c| 23 -
drivers/clk/microchip/mpfs_clk.h| 8 ++
drivers/clk/microchip/mpfs_clk_ms
When this binding header was initally upstreamed, the PLL clocking the
microprocessor subsystem (MSS) and the RTC reference clocks were
omitted. Add them now, matching the IDs used in Linux.
Signed-off-by: Conor Dooley
---
include/dt-bindings/clock/microchip-mpfs-clock.h | 3 +++
1 file changed
tead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley
---
drivers/clk/microchip/mpfs_clk.c| 4 +-
drivers/clk/microchip/mpfs_clk.h| 4 +-
drivers/clk/microchip/mpfs_clk_periph.c | 72 +
3 f
p series. I've omitted these fixes here to
do just what is needed to unblock the dt sync.
Thanks,
Conor.
Conor Dooley (6):
dt-bindings: clk: add missing clk ids for microchip mpfs
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
clk: microchip: mpfs: fix reference clock
dulo the required interrupt and
clocking changes for U-Boot.
Reviewed-by: Conor Dooley
Thanks,
Conor.
> chosen {
> @@ -113,3 +114,17 @@
> ti,fifo-depth = <0x1>;
> };
> };
> +
> + {
> + status = "okay";
> + num-cs = <1>;
Convention suggests a blank line before children, right?
Other than that, LGTM..
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