Re: [U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.

2014-07-04 Thread Diana Craciun
On 07/04/2014 04:43 AM, Xiubo Li-B47053 wrote: Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting. On 07/03/2014 12:51 PM, Xiubo Li wrote: For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Can you give an example? In LS1021A-QDS/TWR, the

Re: [U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7

2014-07-04 Thread Diana Craciun
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote: diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define

Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.

2014-07-04 Thread Diana Craciun
On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled

Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.

2014-07-03 Thread Diana Craciun
On 07/03/2014 12:51 PM, Xiubo Li wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence

Re: [U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.

2014-07-03 Thread Diana Craciun
On 07/03/2014 12:51 PM, Xiubo Li wrote: For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Can you give an example? Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here. Signed-off-by: Xiubo Li

Re: [U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7

2014-07-03 Thread Diana Craciun
On 07/03/2014 12:51 PM, Xiubo Li wrote: To enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address

Re: [U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region

2014-07-03 Thread Diana Craciun
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Re: [U-Boot] [PATCH 1/9] arm: ls102xa: Add Freescale LS102xA SoC support

2014-06-03 Thread Diana Craciun
On 05/30/2014 10:22 AM, Alison Wang wrote: The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that