+Zhang Hongbo.
>
> Hi Scott,
>
> Thanks for your review.
>
> > On Tue, 2016-01-19 at 06:28 +, Dongsheng Wang wrote:
> > > Hi Scott,
> > >
> > > > On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > > > > From:
Hi all,
+Zhang Hongbo, Hongbo will take over this patchset.
Thanks.
Regards,
-Dongsheng
> From: Wang Dongsheng
>
> Support PSCI v1.0 for u-boot.
>
> Wang Dongsheng (9):
> ARM: PSCI: Change function ID base value
> ARM: PSCI: Change PSCI related macro definition
Hi Scott,
Thanks for your review.
> On Tue, 2016-01-19 at 06:28 +0000, Dongsheng Wang wrote:
> > Hi Scott,
> >
> > > On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > > > From: Wang Dongsheng <dongsheng.w...@nxp.com>
> > > >
>
Hi Scott,
Thanks for your review.
> On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > +
> > +#ifdef CONFIG_ARMV7_PSCI_GTE_1_0
> > + tmp = fdt_psci_gte_1_0_fixup(fdt, nodeoff);
> > if (tmp)
> > return tmp;
> > - tmp =
Hi Scott,
> On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > From: Wang Dongsheng <dongsheng.w...@nxp.com>
> >
> > Based on PSCI v1.0, implement interface for ls102xa SoC:
> > psci_version,
> > psci_features,
> > psci_cpu_suspend,
Hi Scott,
>
> On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > From: Wang Dongsheng <dongsheng.w...@nxp.com>
> >
> > Add validation code to make sure target cpu ID is valid.
> >
> > Signed-off-by: Wang Dongsheng <dongsheng.w...@nxp.com>
From: Wang Dongsheng
LS1021 support two secure OCRAM block for trustzone. So move
all of secure text section into OCRAM, and not need to use
memory anymore.
Signed-off-by: Wang Dongsheng
---
arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
From: Wang Dongsheng
Following PSCI v1.0 spec and Linux kernel bindings:
U-Boot's choice of base value is arbitrary for v0.1, because it's
described in the device tree, so we're choosing to make things easier
by using 0x8400 for all PSCI versions.
Signed-off-by:
From: Wang Dongsheng
Support PSCI v1.0 for u-boot.
Wang Dongsheng (9):
ARM: PSCI: Change function ID base value
ARM: PSCI: Change PSCI related macro definition style
ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared
ARM: ARMv7: PSCI: Factor
From: Wang Dongsheng
Move save target PC codes to a common function.
Signed-off-by: Wang Dongsheng
---
arch/arm/cpu/armv7/ls102xa/psci.S | 20 --
arch/arm/cpu/armv7/mx7/psci.S | 3 ---
arch/arm/cpu/armv7/psci.S
From: Wang Dongsheng
To follow PSCI, we need to save a "Context ID" in CPU_ON,
and pass it to a CPU when it first enters the OS.
Signed-off-by: Wang Dongsheng
---
arch/arm/cpu/armv7/nonsec_virt.S | 4
arch/arm/cpu/armv7/psci.S| 28
From: Wang Dongsheng
All of cpu share the same targetPC space that is unsafe. So move
target PC save space into CPU stack.
Signed-off-by: Wang Dongsheng
---
arch/arm/cpu/armv7/ls102xa/psci.S | 4 +--
arch/arm/cpu/armv7/mx7/psci.S |
From: Wang Dongsheng
Add the PSCI v1.0 API to U-Boot:
PSCI_VERSION,
AFFINITY_INFO,
MIGRATE_INFO_TYPE,
MIGRATE_INFO_UP_CPU,
SYSTEM_OFF,
SYSTEM_RESET,
PSCI_FEATURES,
SYSTEM_SUSPEND.
In order to be compatible with PSCI v0.1 version, introduce
From: Wang Dongsheng
Based on PSCI v1.0, implement interface for ls102xa SoC:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng
From: Wang Dongsheng
The macro style changes just to keep the style of the macro concise
and consistent, and style mimicking linux.
Signed-off-by: Wang Dongsheng
---
arch/arm/cpu/armv7/ls102xa/psci.S | 2 +-
arch/arm/cpu/armv7/psci.S
From: Wang Dongsheng
Add validation code to make sure target cpu ID is valid.
Signed-off-by: Wang Dongsheng
---
arch/arm/cpu/armv7/ls102xa/psci.S | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git
From: Wang Dongsheng
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140
Hi Tom,
Thanks for your review.
I will update this patch.
Regards,
-Dongsheng
> On Mon, Jan 11, 2016 at 02:51:39AM +0000, Dongsheng Wang wrote:
> > Hi Tom,
> >
> > Sorry for my late reply, and thanks for your reply.
> >
> > How about the following comments, f
address.
*
* So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
*/
/DISCARD/ : { *(.rel._secure*) }
#endif
Regards,
-Dongsheng
>
> On Fri, Dec 11, 2015 at 03:30:24PM +0000, Dongsheng Wang wrote:
> > Hi Tom,
> >
> > > On Fri, Dec 11, 2015 at 10:15:03AM +000
Hi Tom,
Thanks for your review.
> On Thu, Dec 10, 2015 at 10:49:01AM +0800, Dongsheng Wang wrote:
>
> > From: Wang Dongsheng <dongsheng.w...@nxp.com>
> >
> > Fix PSCI hang up without CONFIG_ARMV7_SECURE_BASE define.
> > "DISCARD" will remove
Hi Tom,
> On Fri, Dec 11, 2015 at 10:15:03AM +0000, Dongsheng Wang wrote:
> > Hi Tom,
> >
> > Thanks for your review.
> >
> > > On Thu, Dec 10, 2015 at 10:49:01AM +0800, Dongsheng Wang wrote:
> > >
> > > > From: Wang Dongsheng <dong
From: Wang Dongsheng
Fix PSCI hang up without CONFIG_ARMV7_SECURE_BASE define.
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr:
From: Wang Dongsheng
Base on PSCI services, implement CPU_SUSPEND for ls102xa platform.
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..1bc7e45 100644
From: Wang Dongsheng dongsheng.w...@freescale.com
low power boot means u-boot will put non-boot cpus into a low power
status. Non-boot cpus don't need any more spin wait. e500, e500v2 will
going to DOZE status. e500mc, e5500, e6500 will going to PW10 state.
e500/e500v2 will be kicked up by
From: Wang Dongsheng dongsheng.w...@freescale.com
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang
From: Wang Dongsheng dongsheng.w...@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git
From: Wang Dongsheng dongsheng.w...@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git
From: Wang Dongsheng dongsheng.w...@freescale.com
timer_wait is moved from sunxi/psci.S, and it can be converted completely
into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch depend on Jan Kiszka
From: Wang Dongsheng dongsheng.w...@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch depend on
From: Wang Dongsheng dongsheng.w...@freescale.com
Base on CPLD changes, so DIU switch channel also need to fix.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch depends on T1042D4RDB platform code patches.
Priyanka Jain has send T1042D4RDB patches to upstrem, but I
From: Wang Dongsheng dongsheng.w...@freescale.com
T1042D4RDB CPLD SFPCSR register defined has changed to 0:1 QE_MUX.
There have two bits to control DVI, DFP, PROFIBUS, TMD MUX select.
So we need to update a macro define value to switch to DIU channel.
Signed-off-by: Wang Dongsheng
From: Wang Dongsheng dongsheng.w...@freescale.com
low power boot means u-boot will put non-boot cpus into a low power
status. Non-boot cpus don't need any more spin wait. e500, e500v2 will
going to DOZE status. e500mc, e5500, e6500rev1 will going to PW10 state.
e6500rev2 will going to PW20 state.
From: Wang Dongsheng dongsheng.w...@freescale.com
We should remove this support.
First, there is not any documents to say we need to support this
feature, and kernel also not support this feature.
Second, Kerneal not support this on T1040QDS, so if we open it in
u-boot, FPGA will be changed and
From: Wang Dongsheng dongsheng.w...@freescale.com
The ch7301 encoder not only used in t1040qds platform, so we split
it for t1042rdb and LSx platform.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index
From: Jason Jin jason@freescale.com
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
From: Jason Jin jason@freescale.com
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This
From: Wang Dongsheng dongsheng.w...@freescale.com
The ch7301 encoder not only used in t1040qds platform, so we split
it for t1042rdb and LSx platform.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
V2: No Change
diff --git a/board/freescale/common/Makefile
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