在 2023-07-12星期三的 14:13 +0100，Maciej W. Rozycki写道：
> On Wed, 28 Jun 2023, Icenowy Zheng wrote:
>
> > When building the package `rustc` for AOSC OS on HiFive Unmatched,
> > random SIGSEGV prevents the package from getting correctly built.
> > Downclocking the CPU PLL cl
-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b384..6b80cab588 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv
在 2023-06-05星期一的 15:03 -0600，Sam Edwards写道：
> Hey hey Icenowy,
>
> On 10/13/22 21:05, Icenowy Zheng wrote:
> > This patchset tries to extend SPI-based boot code in sunxi SPL to
> > support SPI NAND, following the same principle with current SPI NOR
> > code
> >
在 2022-10-14星期五的 11:05 +0800，Icenowy Zheng写道：
> Signed-off-by: Icenowy Zheng
By the way should we have some better way to handle the placement of
environments?
> ---
> board/sunxi/board.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/board/sunxi/board.c b/b
于 2023年1月15日 GMT+08:00 上午3:56:08, Samuel Holland 写到:
>On 10/13/22 22:05, Icenowy Zheng wrote:
>> As we're going to add support for SPI NAND to this code, add code that
>> allows multiple boot attempts with different load offsets and functions.
>>
>> To keep com
在 2023-01-03星期二的 17:38 +，Andre Przywara写道：
> On Tue, 06 Dec 2022 13:55:02 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> > > This adds the basic SoC .dtsi devicetree stub for the Allwinner
> >
在 2023-01-03星期二的 01:17 +，Andre Przywara写道：
> The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use
> the
> same DRAM initialisation code.
> Make use of prior art here and lift some code from awboot[1], which
> carried init code based on earlier decompilation efforts, but with a
在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
>
> Include the existing D1
在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> Allwinner seems to typically stick to a common MMIO memory map for
> several SoCs, but from time to time does some breaking changes, which
> also introduce new generations of some peripherals. The last time
> this
> happened with the H6, which apart
---
configs/popstick_defconfig | 35 +++
1 file changed, 35 insertions(+)
create mode 100644 configs/popstick_defconfig
diff --git a/configs/popstick_defconfig b/configs/popstick_defconfig
new file mode 100644
index 00..6dc21695b7
--- /dev/null
+++
Signed-off-by: Icenowy Zheng
---
board/sunxi/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21a2407e06..f4138573d4 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,6 +133,7 @@ void i2c_init_board(void)
*/
enum
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 +++
arch/arm/dts/suniv-f1c100s.dtsi | 26 +
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 +++
4 files changed, 145
As we added support for SPI NAND to the existing SPL SPI codepath, route
the boot code to it when it detects the BROM loads SPL from SPI NAND, as
for SoCs with both SPI NAND and boot media indicator support, the boot
media indicator is the same for SPI NOR and NAND.
Signed-off-by: Icenowy Zheng
This commit adds support for booting from SPI NAND to SPL SPI code by
mimicing the behavior of boot ROM (use fixed page size and sequentially
try SPI NOR and NAND).
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 16 +++
arch/arm/mach-sunxi/spl_spi_sunxi.c | 74
.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 58 +++--
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 88c15a3ee9..21be33a23f 100644
--- a/arch/arm
, this makes it not compatible with usual 3 byte address.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index
To support SPI NAND flashes, more commands than Read (03h) are needed.
Extract the code for doing SPI transfer from the reading code for code
reuse.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 105
1 file changed, 59 insertions(+), 46
of PopStick, U-Boot main part is assumed to be
with 0x800 page size (which is the real situation of the W25N01 flash
used by PopStick).
Icenowy Zheng (8):
sunxi: SPL SPI: extract code for doing SPI transfer
sunxi: SPL SPI: add support for read command with 2 byte address
sunxi: SPL SPI: allow
As the compile error when D-Cache is enabled is gone, we can have
D-Cache enabled now.
Signed-off-by: Icenowy Zheng
---
configs/licheepi_nano_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
index a9776bbcac
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.
Only provide our implementation of enable_caches() for V7A CPUs.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/board.c | 2
Currently D$ support of SUNIV is broken because of duplicated definition
of the D$ enabling function.
Mask the one in mach-sunxi to fix the build error when D$ is enabled,
and enable the D$ on Lichee Pi Nano.
Icenowy Zheng (2):
sunxi: fix SUNIV build when enabling D-Cache
configs: sunxi
I am against using "f1c100" in commit message, because there is a chip
called F1C100 that is part of legacy sun3i instead of suniv.
Using "suniv" or "f1c100s" is better.
在 2022-10-12星期三的 17:34 +0100，Andre Przywara写道：
> So far we stated the lack of a lowlevel() init function for the
> F1C100s
>
在 2022-08-30星期二的 03:26 +，Leo Liang写道：
> Hi Icenowy,
> On Thu, Aug 25, 2022 at 04:11:18PM +0800, Icenowy Zheng wrote:
> > This commit sychornizes the header file for FU740 PRCI clocks with
> > the
> > one from Linux 5.19.
> >
> > The constant values
These DT files are synchornized from Linux 5.19.
Signed-off-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000.dtsi | 67 +
arch/riscv/dts/hifive-unmatched-a00.dts | 95 +++--
2 files changed, 73 insertions(+), 89 deletions(-)
diff --git a/arch/riscv
This commit sychornizes the header file for FU740 PRCI clocks with the
one from Linux 5.19.
The constant values are the same, but all constant names are changed
(most are just prefixed with FU740_).
Signed-off-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 16
This patchset tries to sync FU740 related DT from Linux 5.19.
The first patch fetches the DT binding header from Linux, and the second
one fetches the main DT files.
Icenowy Zheng (2):
dt-bindings: clock: sifive: sync FU740 PRCI clock binding header
riscv: dts: sifive: Synchornize FU740
在 2022-07-14星期四的 07:38 +0200，Michael Nazzareno Trimarchi写道：
> Hi Samuel
>
> On Thu, Jul 14, 2022 at 5:15 AM Samuel Holland
> wrote:
> >
> > This series converts the sunxi NAND driver to get its resources
> > (clocks,
> > resets, pins) from the devicetree, and probe using the driver
> > model.
>
在 2022-07-11星期一的 00:03 +0100，Andre Przywara写道：
> On Tue, 28 Jun 2022 14:49:24 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > The current detection of RX FIFO depth seems to be not reliable,
> > and
> > XCH will self-clear when a transfer is done.
>
&g
The current detection of RX FIFO depth seems to be not reliable, and
XCH will self-clear when a transfer is done.
Check XCH bit when polling for transfer finish.
Signed-off-by: Icenowy Zheng
---
drivers/spi/spi-sunxi.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff
在 2022-03-05星期六的 21:33 +，Andre Przywara写道：
> On Sat, 5 Mar 2022 00:06:01 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > Currently CONFIG_UART0_PORT_F will forbid the build of sunxi-mmc
> > driver,
> > which leads calls to it in board/sunxi/
Currently CONFIG_UART0_PORT_F will forbid the build of sunxi-mmc driver,
which leads calls to it in board/sunxi/board.c a undefined reference.
Guard that code in #ifndef to fix build.
Signed-off-by: Icenowy Zheng
---
board/sunxi/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
,
> and if so how should I do so.
As you are keeping my SoB and adding yours, it's totally okay.
Thanks for cleaning up these patches! ;-)
>
> Icenowy Zheng (11):
> arm: arm926ej-s: start.S: port save_boot_params support from armv7
> code
> arm: arm926ej-s: add sunxi
he symbol to match what's defined in Kconfig and
> what
> the defconfig files actually use.
>
> Fixes: 03510bf62149 ("sunxi: only include alias for eMMC when mmc2
> used")
> Signed-off-by: Andre Przywara
> Reported-by: 5...@5kft.org
LGTM. I am just too careless.
Re
在 2021-10-29星期五的 10:41 -0400，Tom Rini写道：
> On Fri, Oct 29, 2021 at 10:20:32PM +0800, Icenowy Zheng wrote:
> > 在 2021-10-29星期五的 11:53 +0100，Andre Przywara写道：
> > > On Mon, 25 Oct 2021 14:29:10 -0400
> > > Tom Rini wrote:
> > >
> > > Hi Tom,
> >
在 2021-10-29星期五的 11:53 +0100，Andre Przywara写道：
> On Mon, 25 Oct 2021 14:29:10 -0400
> Tom Rini wrote:
>
> Hi Tom,
>
> > On Mon, Oct 25, 2021 at 03:06:58PM +0100, Andre Przywara wrote:
> >
> > > Hi Tom,
> > >
> > > please pull the second sunxi PR for the 2021.10 merge window.
> > > I decided
在 2021-10-23星期六的 13:23 -0400，Siva Mahadevan写道：
> Icenowy Zheng wrote:
> > The OHCI and EHCI controllers are both bound to the same PHY. They
> > will
> > both do init and power_on operations when the controller is brought
> > up
> > and both do power_off and ex
在 2021-07-25星期日的 19:16 -0400，Yifan Gu写道：
> We renumber mmc2 to mmc1 for sunxi devices, but if mmc2 does not exist
> dts will not build.
>
> This patch prevents that by checking CONFIG_MMC_SUNXI_SLOT_EXTRA.
I have a similar patch at
Maix IIA is a SoM by Sipeed, and a official baseboard is sold with it.
Add support for this official baseboard with Maix IIA attached.
Signed-off-by: Icenowy Zheng
---
board/sunxi/MAINTAINERS| 5 +
configs/sipeed_maix_iia_dock_defconfig | 8
2 files changed, 13
R329 SoC has similar MMC controllers with previous Allwinner SoCs.
Add support for it by adding its compatible string.
Signed-off-by: Icenowy Zheng
---
drivers/mmc/sunxi_mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6b809c001f
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun50i-r329-maix-iia-dock.dts | 36
arch/arm/dts/sun50i-r329-maix-iia.dtsi | 45 +
arch/arm/dts/sun50i-r329.dtsi | 225 +
4 files changed, 308
Signed-off-by: Icenowy Zheng
---
include/dt-bindings/clock/sun50i-r329-ccu.h | 73 +++
include/dt-bindings/clock/sun50i-r329-r-ccu.h | 32
include/dt-bindings/reset/sun50i-r329-ccu.h | 45
include/dt-bindings/reset/sun50i-r329-r-ccu.h | 23 ++
4
Currently only a subset of clocks/resets (similar to other SoCs) are
supported.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/Kconfig| 7 +++
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_r329.c | 94
3 files changed, 102 insertions
As most code are ready for basic R329 support, let's add a Kconfig
option for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig| 14 +-
arch/arm/mach-sunxi/cpu_info.c | 2 ++
common/spl/Kconfig | 1 +
3 files changed, 16 insertions(+), 1 deletion
CCU one.
Add support for basical R329 clock initialization.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 49 ---
1 file changed, 44 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
b/arch/arm/mach-sunxi
Allwinner R329 SoC is the first known Allwinner SoC that has two
possible pinmux setups for MMC0 controller.
Support configuration of both setups of MMC0 and UART0 at PB4/5.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/Kconfig
Allwinner R329 has no MMC2.
Only include the code of MMC2 if the base address of it is defined.
Signed-off-by: Icenowy Zheng
---
drivers/mmc/sunxi_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 178b8cf106..6b809c001f 100644
Allwinner R329 SoC has a different memory map with previous post-H6
SoCs.
Add the memory map to a dedicated header file, fill everywhere that
uses a hardcoded MMIO address and specify the SPL/ATF load address.
Signed-off-by: Icenowy Zheng
---
arch/arm/cpu/armv8/fel_utils.S| 2
There are more Allwinner SoCs that do not have a SCP now.
When there's no SCP_ADDR macro defined, we can assume there's no SCP
available.
Drop the scp part of FIT description when SCP_ADDR does not exist.
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++--
1 file changed
,
routines with socid parameter are added, although not checked now.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
.../include/asm/arch-sunxi/dram_sun50i_r329.h | 232 +++
arch/arm/mach-sunxi/Kconfig
Some Allwinner SoCs (e.g. R329) doesn't have a MMC2 controller at all,
and on boards that we do not utilize MMC2, the alias for it is just
useless.
Only include the alias when we specify CONFIG_MMC_SUNXI_EXTRA_SLOT to 2.
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sunxi-u-boot.dtsi | 2 ++
1
changes.
Finally it comes the defconfig file for a R329 board, Sipeed Maix IIA
Dock.
This patchset is RFC mainly because of the DT-related part, as no DT
binding is mainlined in Linux now (it's still WIP). All other patches
are ready for being reviewed and, if proper, merged.
Icenowy Zheng (13
在 2021-06-27星期日的 13:32 -0600，Simon Glass写道：
> Hi Icenowy,
>
> On Sat, 26 Jun 2021 at 17:57, Icenowy Zheng wrote:
> >
> > 在 2021-06-26星期六的 12:31 -0600，Simon Glass写道：
> > > Hi Icenowy,
> > >
> > > On Sat, 19 Jun 2021 at 03:19, Icenowy Zheng
> &
在 2021-06-26星期六的 12:31 -0600，Simon Glass写道：
> Hi Icenowy,
>
> On Sat, 19 Jun 2021 at 03:19, Icenowy Zheng wrote:
> >
> > The sunxi_egon type used to take no -A argument (because we assume
> > sunxi
> > targets are all ARM). However, as Allwinner D1 appears as
As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.
Signed-off-by: Icenowy Zheng
---
No changes in v2.
scripts/Makefile.spl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Makefile.spl b
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Removed changes that should belong to the previous patch in v1.
tools/sunxi_egon.c | 23 +++
1 file changed, 23
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Signed-off-by: Icenowy Zheng
-by: Icenowy Zheng
---
Changes in v2:
- Added Tom Rini's Review tag.
tools/imagetool.h | 1 +
tools/mkimage.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/tools/imagetool.h b/tools/imagetool.h
index e229a34ffc..5dc28312c2 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -51,6
This patchset tries to make mkimage -T sunxi_egon to be able to generate
an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1).
In addition, to keep the compatibility, it will still consider the
architecture to be ARM when no architecture is specified.
Icenowy Zheng (4):
mkimage: add a flag
As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.
Signed-off-by: Icenowy Zheng
---
scripts/Makefile.spl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Signed-off-by: Icenowy Zheng
---
tools/sunxi_egon.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/tools/sunxi_egon.c b/tools
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Signed-off-by: Icenowy Zheng
compatibility with command line without -A.
As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.
Signed-off-by: Icenowy Zheng
whether the change to
mkimage common code is proper (maybe we should just change default value
to IH_ARCH_INVALID?).
Icenowy Zheng (4):
mkimage: add a flag to describe whether -A is specified
mkimage: sunxi_egon: refactor for multi-architecture support
mkimage: sunxi_egon: add support
在 2021-06-16星期三的 15:06 +0100，Peter Robinson写道：
> On Wed, Jun 16, 2021 at 1:20 PM Icenowy Zheng
> wrote:
> >
> > 在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> > > Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> > > :
> > > > Sometimes
在 2021-06-16星期三的 15:20 +0200，Heinrich Schuchardt写道：
> Am 16. Juni 2021 14:19:41 MESZ schrieb Icenowy Zheng
> :
> > 在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> > > Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> > > :
> > > > Someti
在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> :
> > Sometimes EFI GOP support may be not wanted (e.g. because the
> > operating
> > system cannot operate well with it) even if video support in U-Boot
> >
Sometimes EFI GOP support may be not wanted (e.g. because the operating
system cannot operate well with it) even if video support in U-Boot is
needed.
Allow to disable EFI GOP support with a Kconfig option.
Signed-off-by: Icenowy Zheng
---
lib/efi_loader/Kconfig | 8
lib
于 2021年5月20日 GMT+08:00 上午5:44:30, Andre Przywara 写到:
>On Wed, 19 May 2021 21:42:07 +0200
>Andreas Rehn wrote:
>
>Hi,
>
>> h3 and v3s have internal phys and can share the same driver.
>> Furthermore sun8i-v3s-emac is not available, use sun8i-h3-emac
>instead
>> - add emac pins
>> - enable emac
于 2021年5月20日 GMT+08:00 上午5:44:07, Andre Przywara 写到:
>On Wed, 19 May 2021 21:42:06 +0200
>Andreas Rehn wrote:
>
>Hi,
>
>> Driver uses pinmux instead of emac type.
>> Add v3s pinmux to support SoC.
>
>So if I understand this correctly, then the v3s does NOT expose the MAC
>pins
ACH_SUN50I_H5) += \
>> sun50i-h5-bananapi-m2-plus.dtb \
>> sun50i-h5-emlid-neutis-n5-devboard.dtb \
>> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
>> index 76eba2ad20..e956087b76 100644
>> --- a/board/sunxi/MAINTAINERS
>> +++ b/board/
于 2021年4月7日 GMT+08:00 下午3:28:53, Frank Wang 写到:
>Hi,
>
>
>On 2021/4/7 14:43, Icenowy Zheng wrote:
>>
>> 于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang
> 写到:
>>> Hi Icenowy Zheng,
>>>
>>> In my view, it is better to implement this mechanism
于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang 写到:
>Hi Icenowy Zheng,
>
>In my view, it is better to implement this mechanism in phy-uclass
>which
>resemble Linux Kernel have implemented that can avoid do duplication of
>
>work in each SoC's PHY driver.
I'm afraid of brea
controllers (manually or before booting
a kernel) will work.
Signed-off-by: Icenowy Zheng
Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/phy/ro
于 2021年3月8日 GMT+08:00 上午8:12:24, Andre Przywara 写到:
>On Sun, 7 Mar 2021 13:53:56 +0100
>Nicolas Boulenguez wrote:
>
>Hi,
>
>> From: Arnaud Ferraris
>>
>> The PineTab device-tree is already in u-boot, this commit adds the
>corresponding
>> defconfig, based on pinephone_defconfig.
>>
>>
在 2021-03-02星期二的 15:19 +，Andre Przywara写道：
> On Tue, 02 Mar 2021 21:50:49 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara <
> > andre.przyw...@arm.com> 写到:
> > > On Fri, 26 Feb 2021
在 2021-03-02星期二的 15:19 +，Andre Przywara写道：
> On Tue, 02 Mar 2021 21:50:49 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara <
> > andre.przyw...@arm.com> 写到:
> > > On Fri, 26 Feb 2021
于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara 写到:
>On Fri, 26 Feb 2021 00:13:25 +0800
>Icenowy Zheng wrote:
>
>> Previously we do not have proper dual rank memory detection on R40
>> (because we omitted PIR_QSGATE, which does not work on R40 with our
>> configura
on R40.
Similar routine can be used to detect half DQ width (which is also
detected by PIR_QSGATE on other SoCs), but it's left unimplemented
because there's no known R40 board with half DQ width now.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/dram_sunxi_dw.c | 55
detection is broken on R40 now, we cannot really use it on R40
currently.
Signed-off-by: Icenowy Zheng
---
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 ++-
arch/arm/mach-sunxi/dram_sunxi_dw.c | 94 +++
2 files changed, 82 insertions(+), 23 deletions(-)
diff --git
, and
then tries to access rank 1 and then check for error. It's placed at 2nd
patch because it depends on the function that calculates rank 0 size
(and rank 1 base address) introduced in PATCH 1.
Icenowy Zheng (2):
sunxi: support asymmetric dual rank DRAM on A64/R40
sunxi: enable dual rank memory on R40
urning into FEL mode, so that other payloads can be
> transferred via FEL as well.
>
> Tested on A64, H5 and H6.
>
> Signed-off-by: Andre Przywara
Tested-by: Icenowy Zheng
> ---
> arch/arm/cpu/armv8/Makefile | 2 +
> arch/arm/cpu/armv8/fel_utils.S | 78
&
MAINTAINER item and provide a defconfig.
Signed-off-by: Icenowy Zheng
---
Changes since v2:
- Add Makefile reference to DT.
Changes since v1:
- Dropped LDO3 quirk.
arch/arm/dts/Makefile | 1 +
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 15 +++
3 files
.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Removed LDO3 hack in U-Boot because LDO3 is kept disabled in U-Boot.
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 15 +++
2 files changed, 20 insertions(+)
create mode 100644 configs/pinecube_defconfig
diff
于 2020年10月27日 GMT+08:00 上午2:32:30, Maxime Ripard 写到:
>On Mon, Oct 26, 2020 at 10:21:00PM +0800, Icenowy Zheng wrote:
>> PineCube is an IP camera development kit released by Pine64.
>>
>> It comes with the following compoents:
>>
>> - A mainboard with S
.
Signed-off-by: Icenowy Zheng
---
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 17 +
2 files changed, 22 insertions(+)
create mode 100644 configs/pinecube_defconfig
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 1180b86db3
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sun8i-s3-lichee-zero-plus.dts| 53 +++
arch/arm/dts/sun8i-s3-pinecube.dts| 235 +
The reference design of Allwinner V3 series uses an
AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the
first community-available V3s board, Lichee Pi Zero, omitted it.
Allow to introduce support for the PMIC on boards with it.
Signed-off-by: Icenowy Zheng
---
arch/arm
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.
Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/clk_v3s.c | 2 ++
1
A new compatible string is introduced for V3 GPIO, because it has more
pins available than V3s.
Add the compatible string to the GPIO driver.
Signed-off-by: Icenowy Zheng
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio
-Boot.
Finally the device tree is synchorized from Linux v5.10-rc1 (which
contains the PineCube DT) and PineCube defconfig is added.
Icenowy Zheng (6):
sunxi: add V3/S3 support
sunxi: gpio: introduce compatible string for V3 GPIO
clk: sunxi: add compatible string for V3
sunxi: allow to use
-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index be0822bfb7..31339ac2a1 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -253,7 +253,7
these information from it and tweak some other magic
bits.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/mach-sunxi/dram_sunxi_dw.c | 91 +--
2 files changed, 87 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch
to export
PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core
ARMv7 SoCs.
Signed-off-by: Icenowy Zheng
---
arch/arm/cpu/armv7/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 8eee801dce..60bb0a9e1e
于 2020年6月24日 GMT+08:00 上午8:28:39, "André Przywara" 写到:
>On 19/06/2020 13:16, Icenowy Zheng wrote:
>
>Hi Icenowy,
>
>> Previously we have known that R40 has a configuration register for
>its
>> rank 1, which allows different configuration than rank 0. Rev
allow R40 dual rank memory setup to work too.
Signed-off-by: Icenowy Zheng
---
Testing on R40 boards and A64 single rank boards (e.g. the original Pine
A64+) is welcomed. I have these boards, but I get too lazy to take them
out and test them.
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11
long sunxi_dram_init(void)
> (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
> struct dram_para para = {
> .clk = CONFIG_DRAM_CLK,
>+#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
> .type = SUNXI_DRAM_TYPE_LPDDR3,
>
于 2019年5月16日 GMT+08:00 上午9:26:29, Andre Przywara 写到:
>The Allwinner H6 pin controller is not really special, at least not
>when
>it comes to normal GPIO operation.
>
>Add the H6 compatible strings to the list of recognised strings, to
>make
>GPIOs work for H6 boards.
>
>Signed-off-by: Andre
在 2019-04-24三的 13:44 +0800，Icenowy Zheng写道：
> The Allwinner H6 SoC has a register to set the PIO banks' voltage.
> When
> it mismatches the real voltage supplied to the VCC to the PIO supply,
> the PIO will work improperly.
>
> The PIO controller also has a register that c
definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/board.c
uot;
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)
Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.
config and .dtsi file are adapted from pinebook files.
Tested-by: Jonas Smedegaard
Signed-off-by: Jonas Smedegaard
Signed-off-by: Icenowy Zheng
---
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