Hi Heinrich
> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> Sent: Tuesday, August 04, 2020 7:10 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
> Subject: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V
>
> The command 'exception' can be used
: remove redundant logical constraint.
>
> After
>
> if (ret) return ret;
>
> we know that ret is zero. Don't check it again.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/lib/andes_plic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
n
>
> We should not initialize a variable if the value is overwritten before being
> read.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/cpu/fu540/cache.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
;
> Define the variable ret as __maybe_unused.
>
> Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot
> SPL")
> Fixes: 8c59f2023cc8 ("riscv: add SPL support")
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/lib/spl.c | 2 +-
> 1
eng
>
> Use the generic board_init_f() provided by the RISC-V library codes.
>
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> board/sifive/fu540/spl.c | 19 +--
> 1 file changed, 1 insertion(+), 18 deletions(-)
>
> diff --git a/boa
eng
>
> The generic SPL version of board_init_f() should give a call to board
> specific codes to initialize board in the SPL phase.
>
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> arch/riscv/include/asm/spl.h | 7 +++
> arch/riscv/lib/spl.c
regs->s2, regs->s3);
> + printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n",
> + regs->s4, regs->s5, regs->s6);
> + printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n",
> + regs->s7, regs->s8, regs->s9);
> + printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n",
> + regs->s10, regs->s11, regs->t3);
> + printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n",
> + regs->t4, regs->t5, regs->t6);
> #endif
> }
>
> @@ -69,8 +76,14 @@ static void _exit_trap(ulong code, ulong epc, ulong tval,
> struct pt_regs *regs)
> else
> printf("Unhandled exception code: %ld\n", code);
>
> - printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval);
> + printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
> + epc, regs->ra, tval);
> + if (gd->flags & GD_FLG_RELOC)
> + printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n",
> + epc - gd->reloc_off, regs->ra - gd->reloc_off);
> +
> show_regs(regs);
> + show_efi_loaded_images(epc);
> hang();
> }
>
> --
Reviewed-by: Rick Chen
於 2020年8月3日 週一 上午11:05寫道：
>
>
>
> -Original Message-
> From: Sagar Kadam [mailto:sagar.ka...@sifive.com]
> Sent: Friday, July 31, 2020 9:15 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Paul Walmsley ( Sifive); pal...@dabbelt.com;
> anup.pa...@wdc.com; atish.pa...@wdc.com;
Hi Sagar
> From: Sagar Kadam [mailto:sagar.ka...@sifive.com]
> Sent: Tuesday, July 28, 2020 11:19 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Paul Walmsley ( Sifive); pal...@dabbelt.com;
> anup.pa...@wdc.com; atish.pa...@wdc.com; lu...@denx.de; Pragnesh Patel;
>
Hi Sean
> The riscv-timer driver currently serves as a shim for several riscv timer
> drivers. This is not too desirable because it bypasses the usual timer
> selection via the driver model. There is no easy way to specify an
> alternate timing driver, or have the tick rate depend on the cpu's
>
: Add #address-cells and #size-cells in nor node
Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.
With this patch, there is unnecessary to re-declaration address-cells
and size-cells in nor node indeed.
Tested-by: Rick Chen
Thanks,
Rick
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Friday, July 24, 2020 11:26 AM
> To: Leo Yu-Chi Liang(梁育齊); Rick Jian-Zhi Chen(陳建志)
> Cc: U-Boot Mailing List
> Subject: Re: [PATCH v4] riscv: Make SiFive HiFive Unleashed board boot again
>
> Hi Rick,
>
> On Tue, Jul 21, 2020 at 4:30 PM
Hi Sagar
> From: Sagar Shrikant Kadam [mailto:sagar.ka...@sifive.com]
> Sent: Friday, July 10, 2020 4:38 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); paul.walms...@sifive.com; pal...@dabbelt.com;
> anup.pa...@wdc.com; atish.pa...@wdc.com; lu...@denx.de;
>
Hi Jagan
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Tuesday, July 21, 2020 2:26 PM
> To: Rick Jian-Zhi Chen(陳建志); Atish Patra; Palmer Dabbelt; Bin Meng; Paul
> Walmsley; Anup Patel; Sagar Kadam
> Cc: U-Boot-Denx; linux-amarula
> Subject: Re: [PATCH v5 0/6] riscv:
Hi Pragnesh
> Hi Rick,
>
> Any comments on this patch ?
Applied to u-boot-riscv/master !
Thanks,
Rick
> >From: U-Boot On Behalf Of Pragnesh Patel
> >Sent: 24 June 2020 13:14
> >To: Bin Meng ; Rick Chen
> >Cc: U-Boot Mailing List ; Atish Patra
> >;
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, July 20, 2020 11:52 AM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Tom Rini; Bin Meng
> Subject: [PATCH v3] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> From: Bin Meng
>
> Change to use OpenSBI
Hi Bin
> Hi Rick,
>
> On Mon, Jul 20, 2020 at 11:16 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Monday, July 20, 2020 10:41 AM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
>
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, July 20, 2020 10:41 AM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Tom Rini; Bin Meng
> Subject: Re: [PATCH v2] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> Hi Rick,
>
> On Thu, Jul 16, 2020
> offset and mask property
>
> Hi Rick,
>
> On Fri, Jun 26, 2020 at 1:53 PM Pragnesh Patel
> wrote:
> >
> > >-Original Message-
> > >From: Bin Meng
> > >Sent: 23 June 2020 11:00
> > >To: Rick Chen ; Simon Glass ;
> > >P
Hi Bin
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Tom Rini
> Sent: Tuesday, July 07, 2020 10:13 PM
> To: Bin Meng
> Cc: U-Boot Mailing List; Bin Meng
> Subject: Re: [PATCH] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> On Sat, Jun 27, 2020 at
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursday, July 16, 2020 9:36 AM
> To: Sean Anderson
> Cc: Rick Jian-Zhi Chen(陳建志); Tom Rini; U-Boot Mailing List; Bin Meng
> Subject: Re: [PATCH 1/2] Revert "riscv: Allow use of reset drivers"
>
> Hi Rick,
>
> On Wed, Jul 8, 2020 at 3:04
Hi Jagan
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Thursday, July 02, 2020 4:03 PM
> To: Rick Jian-Zhi Chen(陳建志); Atish Patra; Palmer Dabbelt; Bin Meng; Paul
> Walmsley; Anup Patel; Sagar Kadam
> Cc: u-boot@lists.denx.de; linux-amar...@amarulasolutions.com; Jagan Teki; Bin
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Thursday, July 02, 2020 9:53 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Thu, Jul 02, 2020 at 10:51:48AM +0800, ub...@andestech.com
ch Schuchardt
> ---
> arch/riscv/lib/fdt_fixup.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Rick Chen
This patch conflicts with Atish's [PATCH v3 0/2] Assorted fixes
related to reserved memory
Can you rebase it and send again ?
Thanks,
Rick
> diff
v/Kconfig | 3 +++
> configs/sifive_fu540_defconfig | 1 -
> 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d9854f5..ff8a9f8
> 100644
> --- a/arch/riscv/Kconfig
> +++ b
>
> The FDT blob might not have sufficient space to hold a copy of reserved
> memory node. Expand it before the copy.
>
> Reported-by: Rick Chen
> Signed-off-by: Bin Meng
> Reviewed-by: Atish Patra
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Extend
Hi Jagan
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, June 22, 2020 9:53 PM
> To: Jagan Teki
> Cc: Rick Jian-Zhi Chen(陳建志); Atish Patra; Palmer Dabbelt; Paul Walmsley; Anup
> Patel; Sagar Kadam; U-Boot Mailing List; linux-amarula
> Subject: Re: [PATCH v3 2/6] sifive: fu540: Add
Hi Bin
> Hi Rick,
>
> On Wed, Jun 24, 2020 at 1:24 PM Pragnesh Patel
> wrote:
> >
> > Hi Rick,
> >
> > >-----Original Message-
> > >From: Rick Chen
> > >Sent: 24 June 2020 10:44
> > >To: Pragnesh Patel
> > >Cc:
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-----
> >From: Rick Chen
> >Sent: 24 June 2020 06:30
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; palmerdabb...@google.com; Bin Meng
> >; Paul Walmsley ( Sifive)
> >; A
Hi Tom
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, June 24, 2020 10:58 AM
> To: Open Source Project uboot
> Cc: Tom Rini; U-Boot Mailing List; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> Hi Rick,
>
> On Wed, Jun 24, 2020 at 10:41 AM
Hi Bin
> Hi Rick,
>
> On Wed, Jun 24, 2020 at 9:36 AM Rick Chen wrote:
> >
> > Hi Sagar
> >
> > >
> > > Hello Rick,
> > >
> > > > -Original Message-
> > > > From: Rick Chen
> > > > Sent: Monda
Hi Sagar
>
> Hello Rick,
>
> > -Original Message-
> > From: Rick Chen
> > Sent: Monday, June 22, 2020 7:24 AM
> > To: Sagar Kadam
> > Cc: U-Boot Mailing List ; Lukasz Majewski
> > ; Bin Meng ; Jagan Teki
> > ; Pragnesh Patel
> &
Hi Sean
Tom Rini 於 2020年6月23日 週二 上午8:45寫道：
>
> On Mon, Jun 22, 2020 at 02:03:52PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > From: Tom Rini [mailto:tr...@konsulko.com]
> > > Sent: Monday, May 25, 2020 11:40 PM
> > > To: Open Source Project uboot
Hi Pragnesh
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Friday, May 29, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Jian-Zhi
Hi Tom,
> On Mon, Jun 22, 2020 at 02:03:52PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > From: Tom Rini [mailto:tr...@konsulko.com]
> > > Sent: Monday, May 25, 2020 11:40 PM
> > > To: Open Source Project uboot
> > > Cc: u-boot@lists.denx.de;
Hi Tom
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, May 25, 2020 11:40 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Mon, May 25, 2020 at 04:01:08PM +0800, ub...@andestech.com
Hi Sagar,
> From: Sagar Shrikant Kadam [mailto:sagar.ka...@sifive.com]
> Sent: Sunday, June 21, 2020 9:10 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); lu...@denx.de; bmeng...@gmail.com;
> ja...@amarulasolutions.com; pragnesh.pa...@sifive.com; anup.pa...@wdc.com;
>
Hi Sagar
> From: Sagar Shrikant Kadam [mailto:sagar.ka...@sifive.com]
> Sent: Thursday, June 04, 2020 6:45 PM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志); lu...@denx.de
> Cc: bmeng...@gmail.com; ja...@amarulasolutions.com;
> pragnesh.pa...@sifive.com; anup.pa...@wdc.com;
Hi Jagan
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Wednesday, June 03, 2020 2:57 AM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: U-Boot-Denx; Atish Patra; Palmer Dabbelt; Bin Meng; Paul Walmsley; Anup
> Patel; Sagar Kadam; Pragnesh Patel
> Subject: Re: [PATCH v13 00/19] RISC-V SiFive
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午5:39寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 5:13 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月1日 週一 下午5:06寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Jun 1, 2020 at
Hi Atish
Atish Patra 於 2020年6月3日 週三 上午2:32寫道：
>
> On Mon, Jun 1, 2020 at 2:09 AM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Mon, Jun 1, 2020 at 5:08 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > > From: Bin Meng
Hi Atish
Atish Patra 於 2020年6月3日 週三 上午2:22寫道：
>
> On Mon, Jun 1, 2020 at 11:51 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月2日 週二 下午2:33寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Jun 2, 2020 at 2:16 PM Rick Che
Hi Bin
Bin Meng 於 2020年6月1日 週一 下午5:06寫道：
>
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 4:14 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > To: Rick Jian
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午2:33寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 2:16 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月2日 週二 下午2:13寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Jun 2, 2020 at 2:
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午2:13寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 2:04 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Mon, Jun 1, 2020 at 3:36 PM Rick Chen wrote:
> > > >
> > >
Hi Bin
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 3:36 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> &g
Hi Bin
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 3:40 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> > > >
> > > > Hi Rick,
> > >
ONFIG_SBI_V01
> >
> > From: Bin Meng
> >
> > sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
> >
> > Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
> > Signed-off-by: Bin Meng
> > ---
&
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 27, 2020 5:05 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Atish Patra; Bin Meng
> Subject: [PATCH 1/2] riscv: sbi: Remove sbi_spec_version
>
> From: Bin Meng
>
> U-Boot defaults to use SBI v0.2. Howerver
>
> sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
>
> Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> arch/riscv/lib/sbi.c | 37 +++--
Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > From: Bin Meng [mailto:bmeng...@gmail.com]
Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 20, 2020 3:40 PM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing Li
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 20, 2020 3:40 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Bin Meng
> Subject: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by default
>
> From: Bin Meng
>
> Starting from OpenSBI v0.7, the SBI firmware
: Bin Meng
>
> The copy of reserved memory node from source dtb to destination dtb can be
> avoided if they point to the same place. This is useful when OF_PRIOR_STAGE
> is used.
>
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> arch/riscv/lib/fdt_fixup.c | 12
Hi Tom
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, May 25, 2020 11:40 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Mon, May 25, 2020 at 04:01:08PM +0800, ub...@andestech.com
Hi Sean
>
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor
t_dm. In SPL, it is
> called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
> should be called.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Rick Chen
> ---
>
> Changes in v11:
> - Initialize IPI when used by SPL
> Changes in v9:
> - Fix typ
Hi Bin
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, May 19, 2020 4:44 PM
> To: Pragnesh Patel; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>
> Hi Rick,
>
> On Tue, May 19, 2020 at 3:04 PM Pragnesh Patel
>
Hi Sean
> On 5/5/20 1:02 PM, Sean Anderson wrote:
> > On 5/5/20 5:01 AM, Rick Chen wrote:
> >> Hi Sean
> >>
> >>> This patch adds documentation for the Sipeed Maix bit, and more generally
> >>> for the Kendryte K210
Hi Sean
> This patch adds documentation for the Sipeed Maix bit, and more generally
> for the Kendryte K210 processor.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v9:
> - Mark dts code block as "none" explicitly
> Changes in v7:
> - Split off into its own patch
> - Fix size of clint
>
t_dm. Before this
> point, no riscv_*_ipi functions should be called.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Rick Chen
> ---
>
> Changes in v9:
> - Fix type of ret variable in riscv_ipi_init
> Changes in v7:
> - Split IPI clearing off into its own patch
h has none of its own info to show. Move it over to use the generic
> do_bdinfo().
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> cmd/bdinfo.c | 15 +--
> 1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/cmd/bdinfo.c b/
t; This arch has none of its own info to show. Move it over to use the generic
> do_bdinfo().
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> cmd/bdinfo.c | 14 +-
> 1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/cmd/bdin
s own private bd_info struct. Move it over to
> use the generic one like other archs.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> arch/riscv/include/asm/u-boot.h | 19 ++-
> 1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff -
nds32 still uses its own private bd_info struct. Move it over to
> use the generic one like other archs.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> arch/nds32/include/asm/u-boot.h | 20 ++--
> 1 file changed, 2 insertions(+), 18 deletions
ive: fu540: Enable spi-nor flash support
>
> HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and
> add test result log for future reference.
>
> Tested on SiFive FU540 board.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Bin Meng
Acked-by: Ri
; slaves.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Bin Meng
Acked-by: Rick Chen
> ---
> Changes for v4:
> - update licence
>
> arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/
five/fu540: Enable SPI-NOR support
>
> On Fri, Apr 24, 2020 at 11:48 PM Sagar Kadam wrote:
> >
> > Hello Jagan,
> >
> > > -Original Message-
> > > From: Jagan Teki
> > > Sent: Thursday, April 23, 2020 10:31 PM
> > > To: u-boot@l
Hi Sean
> On Wed, Apr 22, 2020 at 10:03:41PM -0400, Sean Anderson wrote:
> > On 4/22/20 9:51 PM, Rick Chen wrote:
> > > Hi Sean
> > >
> > >> Hi Sean
> > >>
> > >>> This patch series adds support for Sipeed Maix boards an
Hi Sean
>
> Hi Sean
>
> > On 4/22/20 9:51 PM, Rick Chen wrote:
> > > Hi Sean
> > >
> > >> Hi Sean
> > >>
> > >>> This patch series adds support for Sipeed Maix boards and the Kendryte
> > >>> K210 CPU. C
Hi Sean
> On 4/22/20 9:51 PM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> This patch series adds support for Sipeed Maix boards and the Kendryte
> >>> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
>
Hi Sean
> Hi Sean
>
> > This patch series adds support for Sipeed Maix boards and the Kendryte
> > K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> > models are similar.
> >
> > Known Bugs/Limitations:
> > - Accessing the AI ram hangs, limiting available ram to 6M
> > -
Hi Sean
> This patch series adds support for Sipeed Maix boards and the Kendryte
> K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
> models are similar.
>
> Known Bugs/Limitations:
> - Accessing the AI ram hangs, limiting available ram to 6M
> - Trying to boot an image
Hi Atish
> On Mon, Apr 20, 2020 at 1:41 AM Rick Chen wrote:
> >
> > Hi Atish
> >
> > > From: Atish Patra [mailto:atish.pa...@wdc.com]
> > > Sent: Sunday, April 19, 2020 3:32 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Bin Men
Hi Atish
> From: Atish Patra [mailto:atish.pa...@wdc.com]
> Sent: Sunday, April 19, 2020 3:32 AM
> To: u-boot@lists.denx.de
> Cc: Atish Patra; Bin Meng; Anup Patel; Lukas Auer; Heinrich Schuchardt;
> ag...@csgraf.de; ard.biesheu...@linaro.org; Marcus Comstedt; Paul Walmsley;
> Rick Jian-Zhi
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Saturday, April 18, 2020 10:44 PM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; Paul
> Walmsley; Simon Glass; Trevor Woerner
> Subject: RE: [PATCH v2]
Hi Bin
> Hi Rick,
>
> On Fri, Apr 17, 2020 at 8:51 AM Rick Chen wrote:
> >
> > 於 2020年4月17日 週五 上午8:39寫道：
> > >
> > >
> > >
> > > -Original Message-
> > > From: Atish Patra [mailto:ati...@atishpatra.org]
> > &g
於 2020年4月17日 週五 上午8:39寫道：
>
>
>
> -Original Message-
> From: Atish Patra [mailto:ati...@atishpatra.org]
> Sent: Wednesday, April 15, 2020 7:18 AM
> To: Bin Meng
> Cc: Ard Biesheuvel; Heinrich Schuchardt; U-Boot Mailing List; Anup Patel;
> Lukas Auer; Alexander Graf; Rick Jian-Zhi
Hi Sean
> From: Sean Anderson [mailto:sean...@gmail.com]
> Sent: Wednesday, April 08, 2020 10:21 PM
> To: Bin Meng; Rick Jian-Zhi Chen(陳建志); Lukas Auer; Anup Patel; Atish Patra;
> Pragnesh Patel; U-Boot Mailing List
> Subject: Re: [PATCH 4/7] riscv: Add SMP Kconfig option dependency for U-Boot
during arch_cpu_init_dm. Before this
> > point, no riscv_*_ipi functions should be called.
> >
> > Signed-off-by: Sean Anderson
>
> Reviewed-by: Rick Chen
conflict with u-boot/master, please rebase
Thanks
Rick
Applying: riscv: Clean up IPI initialization code
error: patc
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
Hi Peng and Lukasz
> This patch adds alternate versions of the clk_*_register functions for use
> with statically-allocated struct clks. This allows drivers to define clocks
> at compile-time and register them at run-time without malloc-ing. This
> increases the size of the binary, but should not
Hi Jagan
> clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
> predicate instead of the index. Other clk_get_by_* functions got the clock
> correctly, but passed a predicate instead of the index to clk_get_by_tail.
> This could lead to confusing error messages.
>
>
ing some of our cases of
> adding different bit/endian linker flags via ldflags-y
>
> Cc: Rick Chen
> Signed-off-by: Tom Rini
> ---
> arch/riscv/config.mk | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Rick Chen
.
em, ensuring
> that only one hart modifies shared memory at once.
>
> Signed-off-by: Sean Anderson
> ---
Reviewed-by: Rick Chen
t_dm. Before this
> point, no riscv_*_ipi functions should be called.
>
> Signed-off-by: Sean Anderson
Reviewed-by: Rick Chen
esh Patel ; U-Boot Mailing List >b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt
> >; Paul Walmsley ;
> >Jagan Teki ; Troy Benjegerdes
> >; Anup Patel ; Sagar
> >Kadam ; Rick Chen ; Palmer
> >Dabbelt
> >Subject: Re: [PATCH v5 12/14] riscv: sifive: fu540: e
have Kconfig entries that set SPL_LDSCRIPT to what is the
> default value anyways. Drop these.
>
> Cc: Michal Simek
> Cc: Rick Chen
> Cc: Philippe Reynes
> Cc: Eric Jarrige
> Signed-off-by: Tom Rini
> ---
> arch/microblaze/Kconfig | 3 ---
> arch/risc
Hi Sean
> On 3/10/20 2:51 AM, Rick Chen wrote:
> > Hi Sean
> >
> >>> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> >>> just enable them as normal. The enable count is local to the struct clk,
> >>> but this will neve
Hi Sean
> On 3/10/20 5:04 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The Sipeed Maix series is a collection of boards built around the RISC-V
> >> Kendryte K210 processor. This processor contains several peripherals to
> >> accelerate neural network proc
Hi Sean
> On 3/10/20 5:08 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Where possible, I have tried to find compatible drivers based on the layout
> >> of registers. However, many devices remain untested. All untested devices
> >> have been le
Hi Sean
> On 3/10/20 4:20 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The IPI code could have race conditions in several places.
> >> * Several harts could race on the value of gd->arch->clint/plic
> >> * Non-boot harts could race with the main hart o
Hi Sean
> Where possible, I have tried to find compatible drivers based on the layout
> of registers. However, many devices remain untested. All untested devices
> have been left disabled, but some tentative properties (such as compatible
> strings, and clocks, interrupts, and resets properties)
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
Hi Sean
> The IPI code could have race conditions in several places.
> * Several harts could race on the value of gd->arch->clint/plic
> * Non-boot harts could race with the main hart on the DM subsystem In
> addition, if an IPI was pending when U-Boot started, it would cause the
> IPI
Hi Sean
> This patch adds alternate versions of the clk_*_register functions for use
> with statically-allocated struct clks. This allows drivers to define clocks
> at compile-time and register them at run-time without malloc-ing. This
> increases the size of the binary, but should not affect ram
Hi Sean
> > For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> > just enable them as normal. The enable count is local to the struct clk,
> > but this will never result in the actual en-/dis-able op being called
> > (unless the same struct clk is enabled twice).
> >
> >
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, March 10, 2020 9:54 AM
> To: Lukas Auer; Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Subject: Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}
>
> Hi Rick,
>
> On Fri, Mar 6, 2020 at 4:44 PM Bin Meng wrote:
> >
> >
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in
Hi Sean
> Hi Sean
>
> > On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote:
> >
> > > On 3/2/20 4:08 AM, Rick Chen wrote:
> > > > Hi Sean
> > > >
> > > > > The IPI code could have race conditions in several places.
> &g
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