The patch populates the slave data which will be used by flash driver to
set the flash quad enable bit.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/ti_qspi.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index c5d2245
ever called in the
non-XIP full U-Boot case.
Signed-off-by: Tom Rini tr...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu
a different CONFIG_SYS_TEXT_BASE than normal).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 --
arch/arm/cpu/armv7/am33xx/emif4.c |3 ++-
board/ti/am43xx/Makefile |2 +-
board/ti/am43xx/board.c
. In s_init, we do a i2c_init for which we access
a gd-cur_bus_num, but since gd is not
initilaised, so I get a data abort here.
Sourav Poddar (2):
am43xx_evm: Add qspi and qspiboot targets
ti: qspi: Notify core to use quad command.
Tom Rini (1):
am33xx: Rework #ifdef's around s_init for clarity
Currently, flash quad bit is set in spi_flash_validate_params and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in spi_flash_probe_slave
Signed-off-by: Sourav Poddar
On Monday 07 April 2014 10:51 PM, Tom Rini wrote:
On Thu, Apr 03, 2014 at 08:45:42PM +0530, Jagan Teki wrote:
On Thu, Apr 3, 2014 at 5:22 PM, Tom Rinitr...@ti.com wrote:
From: Poddar, Souravsourav.pod...@ti.com
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add
On Thursday 03 April 2014 11:30 AM, Jagan Teki wrote:
Hi Sourav,
On Wednesday 02 April 2014 04:06 PM, Sourav Poddar wrote:
Bulk erase is not happening properly on dra7 due to erase timing
constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar
On Thursday 03 April 2014 11:59 AM, Jagan Teki wrote:
On Wed, Apr 2, 2014 at 4:06 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Add MTD partition info for qspi on dra7 evm
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
include/configs/dra7xx_evm.h | 46
Add support to enable boot from qspi in qspi4 pin mode.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/include/asm/arch-omap5/spl.h |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index
These add a qspi boot config for dra7 board.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
boards.cfg |2 ++
1 file changed, 2 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 69c8936..d6d5bb3 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -356,6 +356,8 @@ Active arm
any key to stop autoboot: 0
Sourav Poddar (5):
board.cfg: am43xx: Add QSPI boot config.
qspi: add support for qspi4 device
configs: dra7-evm: Add mtd parts info for qspi.
configs: dra7-evm: change uboot offset
spi: ti_qspi: Add delay for successful bulk erase.
arch/arm/include/asm
Change uboot offset in accordance with the partition formed.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/configs/dra7xx_evm.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 68496dc
Add MTD partition info for qspi on dra7 evm
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/configs/dra7xx_evm.h | 46 ++
1 file changed, 46 insertions(+)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Tested-by: Yebio Mesfin ymes...@ti.com
---
drivers/spi/ti_qspi.c |3 +++
1 file changed, 3 insertions
On Monday 06 January 2014 01:06 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:10 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu
On Monday 06 January 2014 01:10 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 12:39 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
On Monday 06 January 2014 04:00 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 04 January
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu Tekijagannadha.sutradharudu-t...@xilinx.com
From: Poddar, Souravsourav.pod...@ti.com
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
This a suffix series for
http://u-boot.10912.n7.nabble.com/PATCH-v4-00-36-sf-Add-common-probe-and-extended-quad-read-write-cmds-support-td163949.html
for adding extended read and quad read/write commands support.
Concept:
On Friday 20 December 2013 11:56 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/20/2013 01:18 PM, Jagan Teki wrote:
Hi Sourav,
On Fri, Dec 20, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com wrote:
The patch series add support for enabling qspi
on AM43xx at
November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for MX25L51235F
Sourav Poddar
12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash
12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar
12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31
.
This patches are developed and tested on top of the following tree:
git://git.denx.de/u-boot-ti.git
branch: master
Sourav Poddar (5):
am43xx: add qspi support
am437x_epos_evm: add SPL API, QSPI, and serial flash support
qspi/spi: Add AM43xx specifics changes
am43xx: add delay before xfer
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions
8100 0xdededede 0x4
U-Boot# sf write 8100 0 0x4
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 8200 0 0x4
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x8200
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
- updated commit log with error message.
- Add a FIXME
This shows the log obtained while testing qspi on AM437x board.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
doc/SPI/README.ti_qspi_am43x_test | 76 +
1 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 doc/SPI
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers
On Thursday 19 December 2013 12:21 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com wrote:
From: Jagannadha Sutradharudu Tekijagannadha.sutradharudu-t...@xilinx.com
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
Signed-off-by: Sourav
On Thursday 19 December 2013 12:17 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav
Jagan,
On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series adds:
Add BAR config in dra7 config file.
Set spi controller device control registers before
doing a memory mapped read.
Patches
On Thursday 19 December 2013 11:22 AM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:33 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:21 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Jagannadha Sutradharudu
On Thursday 19 December 2013 11:24 AM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:35 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:17 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Without this delay,
On Thursday 19 December 2013 11:41 AM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:36 AM, Sourav Poddarsourav.pod...@ti.com wrote:
Jagan,
On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series
November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series adds:
Add BAR config in dra7 config file.
Set spi controller device control registers before
doing a memory mapped read.
Patches available here:
git://gitorious.org
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done
November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for MX25L51235F
Sourav Poddar
Hi Jagan,
On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series adds:
Add BAR config in dra7 config file.
Set spi controller device control registers before
doing a memory mapped read.
Patches
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support
debug_dra_qspi
Tested on dra7 evm with qspi boot.
Sourav Poddar (2):
config: dra7_evm: Add Bank Address Register(BAR) config
driver: mtd: sf_ops: claim bus while doing memcpy
drivers/mtd/spi/sf_ops.c |6 ++
include/configs/dra7xx_evm.h |1 +
2 files changed, 7 insertions(+), 0
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Tested-by: Yebio Mesfin ymes...@ti.com
---
drivers/mtd/spi/sf_ops.c |6 ++
1 files changed, 6 insertions(+), 0
Add config to support bank address register.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Tested-by: Yebio Mesfin ymes...@ti.com
---
include/configs/dra7xx_evm.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/configs/dra7xx_evm.h b/include/configs
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Hi Jagan,
This patch seems to be necessary for read/write.
I tested by changing few timing variables, but it did
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for MX25L51235F
Sourav Poddar (4):
am43xx: add qspi support
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support
On Monday 07 October 2013 12:33 PM, Jagannadha Sutradharudu Teki wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
supports only 16MB access.
Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Jagannadha Sutradharudu Teki
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c
to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v5-v6:
Add
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
doc/SPI/README.ti_qspi_dra_test | 48 +++
doc/SPI/README.ti_qspi_flash| 47 ++
2 files
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v5-v6:
change MMAP name to amore
2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav
Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing
regression
after 4k bytes, as a result doing a page by page read. Its
happening,
because
ti qpsi
):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
sf: Add memory mapped read support
README: qspi usecase and testing documentation.
arch/arm/cpu/armv7/omap5
On Thursday 03 October 2013 09:19 PM, Jagan Teki wrote:
Hi Sourav,
Can you test this macronix part w.r.t latest code base on
u-boot-spi.git with master-probe branch.
Please let me know about any issues/concerns.
Regarding the number of blocks, it should be 1024 only.
I will do other testing
On Sunday 06 October 2013 03:03 PM, Gerhard Sittig wrote:
On Fri, Oct 04, 2013 at 20:21 +0530, Sourav Poddar wrote:
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..bee4128 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave-cmd = 0;
+ qslave-cmd |= QSPI_WLEN(8);
+ qslave-cmd |= QSPI_EN_CS(slave-cs);
+ if (flags SPI_3WIRE)
+
On Sunday 06 October 2013 09:00 PM, Jagan Teki wrote:
On Sun, Oct 6, 2013 at 3:44 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c
supports only 16MB access.
Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v5
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3
to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v4-v5:
- Make
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/dra7xx/mux_data.h | 10
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
v4-v5:
- use tabs wherever required.
- remove
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v4-v5:
- Move the doc to doc/SPI
- testing details formatted to actual testing logs done on the
board.
doc/SPI/README.ti_qspi_dra_test | 48
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Matt
On Saturday 05 October 2013 01:44 AM, Jagan Teki wrote:
May be your are missing my comments in previous post.
- Please place these these readme files in doc/SPI/*
- Please use the doc/SPI/status.txt as an example format for writing
new readme files.
ok.
On Sat, Oct 5, 2013 at 1:15 AM, Sourav
On Saturday 05 October 2013 01:36 AM, Jagan Teki wrote:
Please use the commit msg head as sf: ..
Ok.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 12:27
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 01:43
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v4
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
doc/README.ti_qspi_dra_test | 38 ++
doc/README.ti_qspi_flash| 47 +++
2 files changed, 85
to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/dra7xx/mux_data.h | 10
On Saturday 05 October 2013 12:08 AM, Jagan Teki wrote:
Hi Sourav,
Please place these these readme files in doc/SPI/*
All these patches tested on top of u-boot-spi.git master-probe?
Yes, this are tested on the above branch.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav
On Thursday 03 October 2013 11:19 PM, Jagan Teki wrote:
Hi Sourav,
Please try to code the driver as specified in below thread!
http://lists.denx.de/pipermail/u-boot/2013-August/160472.html
Ok.
On Fri, Sep 20, 2013 at 8:21 AM, Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
Hi,
the code logically.
3. Remove a page read hack.
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Ravikumar Kattekola (1):
drivers: mtd: :spi: Add quad read support
Sourav Poddar (3):
armv7: hw_data: change
Hi Jagan,
If you see the mcspi defconfig(CONFIG_OMAP3_SPI), it is moved to
common file include/configs/ti_armv7_common.h . But with this, now after
adding qspi the build breaks like this..
ti_qspi.o: In function `spi_cs_is_valid':
/home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:108: multiple
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c
Kattekola (1):
drivers: mtd: :spi: Add quad read support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.
arch/arm/cpu/armv7/omap5/hw_data.c | 10 +-
arch/arm/cpu/armv7/omap5
to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi
a
SPI_QUAD flag. This need to be done because quad read should
only happen when quad command is sent. For reading status register
and other configuration register normal transfers should happen.
Signed-off-by: Ravikumar Kattekola r...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
doc/README.ti_qspi_dra_test | 38 ++
doc/README.ti_qspi_flash| 47 +++
2 files changed, 85
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