Hi Jonas,
On 2023-10-01 21:17, Jonas Karlman wrote:
> Add rk_gmac_ops and other special handling that is needed for GMAC to
> work on RK3588.
>
> rk_gmac_ops was ported from linux commits:
> 2f2b60a0ec28 ("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588")
> 88619e77b33d ("net:
Hi Ivan,
On 2023-12-18 22:03, Ivan T. Ivanov wrote:
> Hi,
>
> These patches are adding basic support for RPi5.
> They are based on v2 series from Dmitry Malkin[1].
>
> With them I am able to _start_ current openSUSE
> Tumbleweed without modification. They are still
> a lot of things to be added
On 2023-07-06 07:08, Jonas Karlman wrote:
> On 2023-07-06 01:27, Stefan Agner wrote:
>> On 2023-07-02 22:47, Jonas Karlman wrote:
>>> Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
>>> a slightly modified version of the RK3568 SoC.
>>>
&g
ve also tested it on an ODORID-M1 with 8GB of memory, it
boots fine from SD card.
Reviewed-by: Stefan Agner
Tested-by: Stefan Agner
One thing I've noticed is that USB isn't working when I use the stock
SPL (2017.09) running from the SPI RAM and upstream U-Boot (by writing
u-boot.itb to a raw
On 2023-07-05 18:24, Jonas Karlman wrote:
> Hi Stefan,
> On 2023-07-05 18:16, Stefan Agner wrote:
>> Add ODROID-M1 board support. Board device tree rk3568-odroid-m1.dts
>> from v6.4.
>
> I sent out a series that add support for ODROID-M1 a few days ago.
> Please see h
Add ODROID-M1 board support. Board device tree rk3568-odroid-m1.dts
from v6.4.
Signed-off-by: Stefan Agner
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 29 +
arch/arm/dts/rk3568-odroid-m1.dts | 744 ++
configs
Hi Andrew,
On 2022-03-29 18:58, Andrew Scull wrote:
> When parsing the `ranges` DT node, check that both extremes of the
> regions are addressable without overflow. This assumption can then be
> safely made when processing the regions.
I've bisected this patch to break USB support on 32-bit
If the CROS device class is not compiled in, uclass returns not
supported. Ignore this case as well.
This avoids boot failures on ODROID-XU4 without CONFIG_CROS_EC
ending with:
cros-ec communications failure -96
Please reset with Power+Refresh
Cannot init cros-ec device
Signed-off-by: Stefan
Hi Bin,
On 2022-01-05 02:21, Bin Meng wrote:
> Hi Stefan,
>
> On Wed, Jan 5, 2022 at 3:48 AM Stefan Agner wrote:
>>
>> Bin Meng,
>>
>> On 2021-09-27 17:14, Marek Vasut wrote:
>> > On 9/27/21 2:42 PM, Stefan Agner wrote:
>> >> There are devic
Bin Meng,
On 2021-09-27 17:14, Marek Vasut wrote:
> On 9/27/21 2:42 PM, Stefan Agner wrote:
>> There are devices which cause a USB stall when trying to read strings.
>> Specifically Arduino Mega R3 stalls when trying to read the product
>> string.
>>
>> The
dev_err seems to be moved to different header file. Include
dm/device_compat.h file to compile properly.
Fixes: 69dae8902b16 ("linux/compat.h: Remove redefinition of dev_xxx macros")
Signed-off-by: Stefan Agner
---
Changes in v2:
- Correctly place include
drivers/usb/host/xhci-brcm.
dev_err seems to be moved to different header file. Include
dm/device_compat.h file to compile properly.
Fixes: 69dae8902b16 ("linux/compat.h: Remove redefinition of dev_xxx macros")
Signed-off-by: Stefan Agner
---
drivers/usb/host/xhci-brcm.c | 1 +
1 file changed, 1 insertion(+)
e DMA buffers")
Reviewed-by: Andre Przywara
Signed-off-by: Stefan Agner
---
Changes in v2:
- Use uintptr_t to avoid casts
drivers/nvme/nvme.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index f6465ea7f4..3c529a2
On 2021-09-30 18:09, Andre Przywara wrote:
> On Tue, 28 Sep 2021 10:01:40 +0200
> Stefan Agner wrote:
>
>> The current code invalidates the range after the read buffer since the
>> buffer pointer gets incremented in the read loop. Use a temporary
>> pointer to m
e DMA buffers")
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index f6465ea7f4..354513ad30 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -743,6 +743,7
a
TRB_RESET_EP command.
Introduce reset_ep() which issues a TRB_RESET_EP followed by setting the
transfer ring dequeue pointer via TRB_SET_DEQ. This allows to properly
recover from a USB stall error and continue communicating with the USB
device.
Signed-off-by: Stefan Agner
---
This has been
oot? Setting the FUA bit will make certain that
data land on non-volatile storage in any case. So:
Reviewed-by: Stefan Agner
Out of curiosity, has this been a problem in a real world situation?
--
Stefan
>
> Signed-off-by: Jon Lin
> ---
>
> drivers/nvme/nvme.c | 3 +++
>
On 2021-09-24 01:20, Stefan Agner wrote:
> So far we've been content with passing physical/CPU addresses when
> configuring memory addresses into NVMe controllers, but not all
> platforms have buses with transparent mappings. Specifically the
> Raspberry Pi 4 might introduce an offs
Pass buffers which use CPU addressing as void pointers. This aligns with
DMA APIs which use void pointers as argument. It will avoid unnecessary
type casts when adding support bus address translations.
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.c | 50
;xhci: translate virtual addresses into the bus's
address space").
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.c | 32 ++--
drivers/nvme/nvme.h | 15 +++
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/n
List pointer if there is more
than a single memory page of data to be transferred."
For the purpose of calculating the number of pages required for PRP
lists we should always assume that the last entry is required for
the next PRP list.
Signed-off-by: Stefan Agner
Cc: Wesley Sheng
---
dr
Improve readability by introducing consts, reuse consts where
appropriate and adding variables with discriptive name.
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
Home Assistant:
https://github.com/home-assistant/operating-system/issues/1490
It does seem that it depends on the binary size (since USB enumeration
worked with 2021.04 at one point, but after enabling more configurations
it caused issues).
So:
Tested-by: Stefan Agner
I've seen that this did not ma
rt the new bindings in the PHY node.
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-b
rt the new bindings in the PHY node.
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-gxbb-odroidc2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts
b/arc
On 2021-04-07 16:29, Neil Armstrong wrote:
> On 07/04/2021 16:21, Stefan Agner wrote:
>> On 2021-04-07 15:31, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 06/04/2021 19:47, Stefan Agner wrote:
>>>> The sync of the device tree and dt-bindings from
On 2021-04-07 15:31, Neil Armstrong wrote:
> Hi,
>
> On 06/04/2021 19:47, Stefan Agner wrote:
>> The sync of the device tree and dt-bindings from Linux v5.6-rc2
>> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
>> ODROID-C2.
>>
>>
ream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
deassert timing requirements").
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
arch/arm/dts/meson-gxbb-nanop
uot;).
Cc: Sylwester Nawrocki
Cc: Nicolas Saenz Julienne
Cc: Matthias Brugger
Reviewed-by: Stefan Roese
Reviewed-by: Bin Meng
Signed-off-by: Stefan Agner
---
Changes in v2:
- Fix subject and message to reflect NVMe change
drivers/nvme/nvme.h | 8
1 file changed, 8 deletions(-)
On 2020-12-30 02:36, Bin Meng wrote:
> Hi Stefan,
>
> On Wed, Dec 30, 2020 at 3:37 AM Stefan Agner wrote:
>
> The tag is wrong. Should be nvme:
Thanks for pointing out. Will send a v2.
FWIW, the send to amlogic ML was accidentially.
--
Stefan
>
>>
>> There mi
ly
32-bit accesses in xhci_writeq/xhci_readq").
Cc: Sylwester Nawrocki
Cc: Zhikang Zhang
Cc: Nicolas Saenz Julienne
Cc: Matthias Brugger
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nv
On 2020-12-15 06:19, Jaehoon Chung wrote:
> Hi,
>
> On 12/15/20 3:58 AM, Neil Armstrong wrote:
>> Hi,
>>
>> On 07/12/2020 18:15, Stefan Agner wrote:
>>> Amlogic AGX SoCs seem to have issue communicating with some eMMC
>>> devices (in particu
is set to 270° it is detected with 8-bit bus width and is
working fine accross all temperatures.
Signed-off-by: Stefan Agner
---
Hi Neil,
I debugged this issue today on an ODROID N2+ not booting reliably. I am
not sure if we can safely switch to 270° for all SoCs with
amlogic,meson-axg-mmc, but I
From: Pascal Vizeli
Add SoC revision to environment. This can be useful to select the
correct device tree at runtime (N2/N2+).
Signed-off-by: Pascal Vizeli
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-meson/boot.h | 4
arch/arm/mach-meson/board-info.c | 12
Move loading of socinfo into a separate function so the value can be
reused later.
Signed-off-by: Stefan Agner
---
arch/arm/mach-meson/board-info.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board
Hi,
When trying to boot rpi_4_32b_defconfig of U-Boot 2020.10 (or master)
using a USB flash drive, U-Boot hangs early at:
U-Boot 2020.10 (Nov 20 2020 - 10:25:26 +0100)
DRAM: 3.9 GiB
The weird thing is that at this point U-Boot does not access USB/SD card
at all, still it matters if it got
On 2020-11-04 15:05, Stefan Agner wrote:
> On 2020-10-16 03:28, Ricardo Salveti wrote:
>> On Tue, Oct 13, 2020 at 11:04 AM Peter Robinson wrote:
>>>
>>> > >> Hello Matthias,
>>> > >>
>>> > >> I have upgraded the Raspberry
On 2020-10-16 03:28, Ricardo Salveti wrote:
> On Tue, Oct 13, 2020 at 11:04 AM Peter Robinson wrote:
>>
>> > >> Hello Matthias,
>> > >>
>> > >> I have upgraded the Raspberry 3 firmware from raspi3-firmware
>> > >> (1.20190215-1+deb10u4) to raspi-firmware (1.20200601-3)
>> > >>
On 2020-09-20 21:01, Stefan Agner wrote:
> A JMicron JMS583 based NVMe to USB 3.1 enclosure connected to a Raspberry
> Pi 4 fails to enumerate as a USB Mass Storage device on first try:
>
> ...
> startig USB...
> Bus xhci_pci: Register 5000420 NbrPorts 5
> Starting t
retry count typically works.
Increase retries to 20 for a startup time of up to 2s.
Signed-off-by: Stefan Agner
---
common/usb_storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb_storage.c b/common/usb_storage.c
index ff25441995..04910de21f 100644
--- a/common
On 2020-09-19 23:20, Sean Anderson wrote:
> On 9/19/20 7:55 AM, Stefan Agner wrote:
>> On 2020-09-14 10:15, Matthias Brugger wrote:
>>> On 10/09/2020 23:12, Stefan Agner wrote:
>>>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>>>> Any thoughts
On 2020-09-14 10:15, Matthias Brugger wrote:
> On 10/09/2020 23:12, Stefan Agner wrote:
>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>> Any thoughts on this issue?
>>>
>>> Any reason why you're using 2020.01 and not at least 2020.07, or at
>>>
On 2020-09-14 10:15, Matthias Brugger wrote:
> On 10/09/2020 23:12, Stefan Agner wrote:
>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>> Any thoughts on this issue?
>>>
>>> Any reason why you're using 2020.01 and not at least 2020.07, or at
>>>
>
>> I still think there is something wrong with caching. From what I
>> understand caches are enabled by the RPi (4) firmware. Is it safe to run
>> 32-bit ARM U-Boot with enabled caches?
>>
>> --
>> Stefan
>>
>> On 2020-08-23 19:06, Stefan Agner wrote:
>
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
Cc: Jonas Karlman
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++
arch/arm/dts/rk3288-tinker.dts | 7
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm
2020 - 22:02:31 +)
DRAM: 3.9 GiB
I still think there is something wrong with caching. From what I
understand caches are enabled by the RPi (4) firmware. Is it safe to run
32-bit ARM U-Boot with enabled caches?
--
Stefan
On 2020-08-23 19:06, Stefan Agner wrote:
> Hi,
>
> I notice
Hi,
I noticed a quite common freeze when running 32-bit U-Boot 2020.01
(rpi_4_32b_defconfig) on a 2GB RPi4 model:
U-Boot 2020.01 (Aug 07 2020 - 13:00:23 +)
DRAM: 1.9 GiB
This happens fairly often, I would say 4 out of 5 boot tries. However,
if it boots, everything seems to run fine.
The
On 2020-07-19 12:06, Nicolas Saenz Julienne wrote:
> Hi Stefan,
>
> On Sun, 2020-07-19 at 02:37 +0200, Stefan Agner wrote:
>> Hi Nicolas,
>>
>> On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
>> > Newer revisions of the RPi4 need their xHCI chip, VL805,
for the noise! And thanks for all your work!
--
Stefan
On 2020-07-19 02:37, Stefan Agner wrote:
> Hi Nicolas,
>
> On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
>> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
>> loaded explicitly. Earlier
Hi Nicolas,
On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> loaded explicitly. Earlier versions didn't need that as they where using
> an EEPROM for that purpose. This series takes care of setting up the
> relevant
On 2019-11-04 12:56, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Take over maintainership for colibri_imx6/imx6ull/t30/vf modules.
>
> Signed-off-by: Igor Opaniuk
Acked-by: Stefan Agner
Thanks for looking after those boards!
--
Stefan
> ---
>
> board
On 2019-07-03 15:50, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> NXP downstream kernel uses legacy method to enable other cores,
> which requires kernel to run in a security mode (althought upstream kernel
> uses PSCI for this).
>
> As we're using NXP kernel in our BSPs, lets enable this by
On 2019-07-23 15:29, Tobias Junghans wrote:
> Hi Igor,
>
> thanks for your comments! Is there any solution, patch or workaround I can
> try
> to power on the 2nd CPU core in secure mode with mainline kernel?
I am afraid that is not possible since without PSCI mainline simply
lacks the code how
On 11.06.2019 14:29, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Enable CONFIG_ARMV7_BOOT_SEC_DEFAULT by default to avoid a kernel
> crash when booting NXP linux kernels in non-secure world,
> when job ring device allocation is done by CAAM hw accelerator driver:
I rather prefer if mainline
On 27.05.2019 07:21, Igor Opaniuk wrote:
> Hi everyone,
>
> I've finally started looking into the cfb_console.c driver and it's
> conversion to DM_VIDEO after our initial discussion [1].
> Unfortunately I've a bit underestimated the amount of effort that
> should be done, as mxsfb.c in the Linux
Hi Igor,
On 13.05.2019 12:46, Igor Opaniuk wrote:
> cpu_imx_get_temp() definition is wrapped with a ifdef macro,
> therefore all function references should be also wrapped the same way
> instead IS_ENABLED() usage.
>
> Fix warning:
> arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’:
On 26.04.19 20:53, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> Drop Toradex ARM Support from maintainer email
> list as this just clogs our support ticketing system.
Acked-by: Stefan Agner
--
Stefan
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
>
On 03.02.2019 00:02, Lukasz Majewski wrote:
> Provide function to enable I2C clocks for vf610 - in the generic code.
> This function overrides the default weak function implementation (which
> only returns 1).
>
> Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Ag
Hi Tim,
On 02.02.19 03:32, Tim Harvey wrote:
> Stefan,
>
> I'm trying to track down an IMX6 SPL NAND boot regression that started
> in v2018.07 with your patch series to mxs_nand.
I am sorry about that. Unfortunately I did not had a design at hand where I was
able to test the NAND driver in
On 01.02.2019 15:19, Lukasz Majewski wrote:
> Hi Stefan,
>
>> On 20.01.2019 14:34, Lukasz Majewski wrote:
>> > Provide function to enable I2C2 clock for vf610 (BK4) - in the
>> > generic code.
>>
>> Can you split this in two commits, one adding enable_i2c_clk and the
>> second removing board
On 21.01.2019 15:22, Lukasz Majewski wrote:
> On Mon, 21 Jan 2019 09:33:23 +0100
> Lukasz Majewski wrote:
>
>> Hi Stefan,
>>
>> > This patch series converts PCM052 and BK4 to use Driver Model and
>> > Device Tree.
>> >
>> > Some notable changes:
>> > - The way how MAC address is read from fuses
On 20.01.2019 14:34, Lukasz Majewski wrote:
> Provide function to enable I2C2 clock for vf610 (BK4) - in the
> generic code.
Can you split this in two commits, one adding enable_i2c_clk and the
second removing board specific clock enable?
Also our module seems to use I2C0, could you add that
On 20.01.2019 14:34, Lukasz Majewski wrote:
> This patch allows moving vf610 based boards to a device tree and model.
> Ported from Linux kernel - v4.20 (tag)
>
> Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner
--
Stefan
> ---
>
> Changes in v2: None
>
>
On 20.01.2019 14:34, Lukasz Majewski wrote:
> This patch provides definitions necessary for VF610 DDR pad configurations.
>
> Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner
--
Stefan
> ---
>
> Changes in v2: None
>
> arch/arm/
On 20.01.2019 14:34, Lukasz Majewski wrote:
> Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner
--
Stefan
> ---
>
> Changes in v2: None
>
> drivers/net/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/Kconfig b/
On 20.01.2019 14:34, Lukasz Majewski wrote:
> The NXP's FEC driver can be reused on vf610 device (with DM).
>
> Signed-off-by: Lukasz Majewski
Reviewed-by: Stefan Agner
--
Stefan
> ---
>
> Changes in v2: None
>
> drivers/net/fec_mxc.c | 1 +
> 1 file change
From: Stefan Agner
Access to CAAM in non-secure mode must be enabled by the boot
loader first. The U-Boot CAAM driver enables access to CAAM in
non-secure mode by default. Hence enable the CAAM driver to
allow Linux accessing CAAM directly. This prevents error
messages like the following
From: Stefan Agner
Drop legacy pinmux/usdhc board configuration.
Signed-off-by: Stefan Agner
Acked-by: Marcel Ziswiler
---
Changes in v2: None
board/toradex/colibri_imx7/colibri_imx7.c | 97 ---
1 file changed, 97 deletions(-)
diff --git a/board/toradex/colibri_imx7
From: Stefan Agner
Now that device tree is in place use DM_MMC for Colibri iMX7
devices.
Signed-off-by: Stefan Agner
Acked-by: Marcel Ziswiler
---
Changes in v2: None
configs/colibri_imx7_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs
From: Stefan Agner
Add a default configuration for Colibri iMX7D 1GB (with eMMC
NAND flash).
Signed-off-by: Stefan Agner
---
Changes in v2:
- Add CONFIG_FIT/DFU/CRC32_VERIFY/CMD_GPT/DFU_MMC and FAT_WRITE
configs/colibri_imx7_emmc_defconfig | 66 +
1 file changed
From: Stefan Agner
The defconfig already use most features implied by distro defaults.
Make sure we enable all features required by distro boot by making
use of CONFIG_DISTRO_DEFAULTS.
Signed-off-by: Stefan Agner
---
Changes in v2:
- New patch
configs/colibri_imx7_defconfig | 13
From: Stefan Agner
The colibri_imx7_defconfig is for Colibri iMX7 raw NAND devices.
Hence DFU for NAND is more useful then for MMC devices.
Signed-off-by: Stefan Agner
---
Changes in v2:
- New patch
configs/colibri_imx7_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Stefan Agner
In preparation of adding CONFIG_DM_MMC support use separate device
trees for raw NAND and eMMC devices.
Signed-off-by: Stefan Agner
Acked-by: Marcel Ziswiler
---
Changes in v2:
- Remove imx7-colibri.dtb from Makefile
arch/arm/dts/Makefile | 3
From: Stefan Agner
Use OF_SEPARATE as suggested by the build system.
Signed-off-by: Stefan Agner
Acked-by: Marcel Ziswiler
---
Changes in v2: None
configs/colibri_imx7_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/colibri_imx7_defconfig b/configs
From: Stefan Agner
Add usdhci peripherals to device tree. This allows to use DM_MMC
for Colibri iMX7 devices.
Signed-off-by: Stefan Agner
---
Changes in v2:
- Remove unnecessary properties
arch/arm/dts/imx7-colibri-emmc.dts | 31 ++
arch/arm/dts/imx7-colibri.dtsi
From: Stefan Agner
Use DM and device trees for raw NAND devices by default. This
fixes -74 NAND read errors since it makes sure the ECC settings
are the same as used in Linux and our downstream U-Boot.
Signed-off-by: Stefan Agner
---
Changes in v2: None
configs/colibri_imx7_defconfig | 3
From: Stefan Agner
Fix mixed up boot commands between raw NAND and eMMC variant. Also
make sure that the boot_file is defined for the eMMC boot command.
Fixes: a62c60610f51 ("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module
support")
Signed-off-by: Stefan Agner
Acked-by: Marce
From: Stefan Agner
This patchset fixes some small issues with Colibri iMX7 and
converts the board to use DM_MMC. It also adds the so far
missing configuration for the eMMC variant.
This patchset gets rid of all but one deprecation warning.
The remaining warning is due to CONFIG_USB still being
On 07.01.2019 00:49, Marcel Ziswiler wrote:
> On Sun, 2019-01-06 at 22:00 +0100, Stefan Agner wrote:
>> From: Stefan Agner
>>
>> Add a default configuration for Colibri iMX7D 1GB (with eMMC
>> NAND flash).
>
> Finally (;-p).
>
>> Signed-o
On 07.01.2019 00:25, Marcel Ziswiler wrote:
> On Sun, 2019-01-06 at 22:00 +0100, Stefan Agner wrote:
>> From: Stefan Agner
>>
>> Use DM and device trees for raw NAND devices by default. This
>> fixes -74 NAND read errors since it makes sure the ECC settings
>&
On 07.01.2019 00:18, Marcel Ziswiler wrote:
> On Sun, 2019-01-06 at 22:00 +0100, Stefan Agner wrote:
>> From: Stefan Agner
>>
>> In preparation of adding CONFIG_DM_MMC support use separate device
>> trees for raw NAND and eMMC devices.
>>
>> Signed-off-by: S
From: Stefan Agner
Access to CAAM in non-secure mode must be enabled by the boot
loader first. The U-Boot CAAM driver enables access to CAAM in
non-secure mode by default. Hence enable the CAAM driver to
allow Linux accessing CAAM directly. This prevents error
messages like the following
From: Stefan Agner
Add usdhci peripherals to device tree. This allows to use DM_MMC
for Colibri iMX7 devices.
Signed-off-by: Stefan Agner
---
arch/arm/dts/imx7-colibri-emmc.dts| 69 +++
arch/arm/dts/imx7-colibri-rawnand.dts | 4 ++
arch/arm/dts/imx7-colibri.dtsi
From: Stefan Agner
Now that device tree is in place use DM_MMC for Colibri iMX7
devices.
Signed-off-by: Stefan Agner
---
configs/colibri_imx7_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index
From: Stefan Agner
Use OF_SEPARATE as suggested by the build system.
Signed-off-by: Stefan Agner
---
configs/colibri_imx7_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 3aaf1a417d..0c9467e136 100644
From: Stefan Agner
Drop legacy pinmux/usdhc board configuration.
Signed-off-by: Stefan Agner
---
board/toradex/colibri_imx7/colibri_imx7.c | 97 ---
1 file changed, 97 deletions(-)
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c
b/board/toradex/colibri_imx7
From: Stefan Agner
Add a default configuration for Colibri iMX7D 1GB (with eMMC
NAND flash).
Signed-off-by: Stefan Agner
---
configs/colibri_imx7_emmc_defconfig | 65 +
1 file changed, 65 insertions(+)
create mode 100644 configs/colibri_imx7_emmc_defconfig
diff
From: Stefan Agner
Use DM and device trees for raw NAND devices by default. This
fixes -74 NAND read errors since it makes sure the ECC settings
are the same as used in Linux and our downstream U-Boot.
Signed-off-by: Stefan Agner
---
configs/colibri_imx7_defconfig | 3 +++
1 file changed, 3
From: Stefan Agner
In preparation of adding CONFIG_DM_MMC support use separate device
trees for raw NAND and eMMC devices.
Signed-off-by: Stefan Agner
---
arch/arm/dts/imx7-colibri-emmc.dts| 16 +++
arch/arm/dts/imx7-colibri-rawnand.dts | 46
From: Stefan Agner
Fix mixed up boot commands between raw NAND and eMMC variant. Also
make sure that the boot_file is defined for the eMMC boot command.
Fixes: a62c60610f51 ("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module
support")
Signed-off-by: Stefan Agner
---
inclu
From: Stefan Agner
This patchset fixes some small issues with Colibri iMX7 and
converts the board to use DM_MMC. It also adds the so far
missing configuration for the eMMC variant.
This patchset gets rid of all but one deprecation warning.
The remaining warning is due to CONFIG_USB still being
Hi Stefano,
On 14.12.2018 14:40, Stefano Babic wrote:
> On 14/12/18 14:30, Tom Rini wrote:
>> On Fri, Dec 14, 2018 at 02:26:22PM +0100, Stefan Agner wrote:
>>> On 14.12.2018 14:20, Tom Rini wrote:
>>>> On Fri, Dec 14, 2018 at 02:13:46PM +0100, St
[this time using reply to all]
On 03.01.19 03:36, Adam Ford wrote:
> The LogicPD board uses a Micron Flash with ECC. To boot this from
> SPL, the ECC needs to be correctly configured or the BCH engine
> times out.
>
> Signed-off-by: Adam Ford
Looks good to me,
Acked-b
-off-by: Adam Ford
Seems sensible
Acked-by: Stefan Agner
>
> diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c
> b/drivers/mtd/nand/raw/mxs_nand_spl.c
> index 2d7bbe83cc..c628f3adec 100644
> --- a/drivers/mtd/nand/raw/mxs_nand_spl.c
> +++ b/drivers/mtd/nand/raw/mxs_nand_sp
and if every other boot option fails. I
> plan to use SDP as official flashing/recovery procedure in OpenWrt for
> Apalis imx6 boards.
>
> I've copy almost everything from the `f086812a mx6sxsabresd: Use
> PARTUUID to specify the rootfs location` commit, so credits for the rest
From: Stefan Agner
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.
Signed-off-by: Stefan
On 14.12.2018 14:20, Tom Rini wrote:
> On Fri, Dec 14, 2018 at 02:13:46PM +0100, Stefan Agner wrote:
>> Hi Tom,
>>
>> On 08.12.2018 17:48, Lukasz Majewski wrote:
>> > Hi Stefan,
>> >
>> >> From: Stefan Agner
>> >>
>>
Lukasz, Stefano,
On 04.12.2018 12:20, Stefan Agner wrote:
> On 04.12.2018 11:59, Lukasz Majewski wrote:
>> Hi Stefan,
>>
>>> From: Stefan Agner
>>>
>>> The CR80 register has multiple interrupt bits, the code is supposed
>>> to check
Hi Tom,
On 08.12.2018 17:48, Lukasz Majewski wrote:
> Hi Stefan,
>
>> From: Stefan Agner
>>
>> The current bitmap is a bit larger than necessary, it has a black
>> border around the Toradex logo. Crop the logo slightly which safes
>> some space, useful es
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