From: Thierry Reding tred...@nvidia.com
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code
From: Thierry Reding tred...@nvidia.com
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/armv8/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
From: Thierry Reding tred...@nvidia.com
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier marc.zyng...@arm.com
Suggested-by: Mark Rutland mark.rutl
From: Thierry Reding tred...@nvidia.com
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
Signed
From: Thierry Reding tred...@nvidia.com
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Thierry Reding tred
On Wed, Aug 19, 2015 at 11:41:09AM -0600, Stephen Warren wrote:
On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants
From: Thierry Reding tred...@nvidia.com
GCC 5.1 starts warning for comparisons such as !a 0, assuming that the
negation was meant to apply to the whole expression rather than just the
left operand.
Indeed the comparison in the FIT loadable code is confusingly written,
though it does end up
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants for PMIC I2C and register addresses.
---
arch/arm/dts/Makefile | 1 +
On Fri, Aug 14, 2015 at 04:44:28PM +0800, Bin Meng wrote:
Hi Thierry,
On Fri, Aug 14, 2015 at 4:32 PM, Thierry Reding tred...@nvidia.com wrote:
On Fri, Aug 14, 2015 at 04:10:32PM +0800, Bin Meng wrote:
Hi,
On Sun, Aug 9, 2015 at 11:08 PM, Simon Glass s...@chromium.org wrote:
Hi
On Fri, Aug 14, 2015 at 04:10:32PM +0800, Bin Meng wrote:
Hi,
On Sun, Aug 9, 2015 at 11:08 PM, Simon Glass s...@chromium.org wrote:
Hi Stephen,
On 6 August 2015 at 13:03, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/05/2015 05:45 PM, Simon Glass wrote:
Hi Stephen,
On 5
On Sun, Aug 02, 2015 at 03:27:53PM -0600, Simon Glass wrote:
Hi,
On 27 July 2015 at 11:13, Simon Glass s...@chromium.org wrote:
Hi,
On 23 July 2015 at 10:51, Stephen Warren swar...@wwwdotorg.org wrote:
From: Thierry Reding tred...@nvidia.com
Signed-off-by: Thierry Reding tred
On Sun, Aug 02, 2015 at 06:13:50PM -0600, Simon Glass wrote:
This reverts commit 5b34436035fc862b5e8d0d2c3eab74ba36f1a7f4.
This function has a few problems. It calls fdt_parent_offset() which as
mentioned in code review is very slow.
https://patchwork.ozlabs.org/patch/499482/
On Tue, Aug 04, 2015 at 09:23:27AM -0600, Stephen Warren wrote:
On 08/04/2015 08:26 AM, Thierry Reding wrote:
... [ discussion of new fdtdec_get_addr_size() implementation]
So what this does is really fix parsing of address and size cells in the
general case, though it would still fail
On Thu, Jul 30, 2015 at 12:13:06PM -0600, Stephen Warren wrote:
On 07/29/2015 05:02 PM, Simon Glass wrote:
Hi Stephen,
On 29 July 2015 at 13:48, Stephen Warren swar...@wwwdotorg.org wrote:
Commit message?
I guess I can add one, but there really much useful additional information I
On Wed, Jul 29, 2015 at 10:09:57AM -0600, Stephen Warren wrote:
On 07/29/2015 05:07 AM, Thierry Reding wrote:
On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote:
On 07/24/2015 04:01 PM, Tom Warren wrote:
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table
On Wed, Jul 29, 2015 at 01:47:58PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at
On Tue, Jul 28, 2015 at 01:27:07PM -0600, Stephen Warren wrote:
On 07/24/2015 04:01 PM, Tom Warren wrote:
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with
From: Thierry Reding tred...@nvidia.com
ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include/configs/tegra-common.h | 3 +++
1 file changed, 3
From: Thierry Reding tred...@nvidia.com
A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay
On Wed, Jul 22, 2015 at 04:56:10PM -0600, Stephen Warren wrote:
From: Thierry Reding tred...@nvidia.com
Some SoCs come with a custom timer interface, so allow them to use that
instead.
swarren notes: I did consider reworking this patch so the Makefile only
compiles generic_timer.c ifndef
On Mon, Jul 20, 2015 at 01:41:00PM +0200, Mirza Krak wrote:
From: Mirza Krak mirza.k...@hostmobility.com
Add the device tree node for the SPI controllers found on Tegra20 SOCs.
Signed-off-by: Mirza Krak mirza.k...@hostmobility.com
---
arch/arm/dts/tegra20.dtsi | 44
On Wed, Jul 15, 2015 at 01:35:26PM +0200, Albert ARIBAUD wrote:
Hello Thierry,
On Wed, 15 Jul 2015 13:17:18 +0200, Thierry Reding
thierry.red...@gmail.com wrote:
On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
+Scott, Masahiro
Hi Thierry,
On 25 March 2015 at 17
On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
+Scott, Masahiro
Hi Thierry,
On 25 March 2015 at 17:23, Simon Glass s...@chromium.org wrote:
Hi Thierry,
On 8 September 2014 at 09:02, Simon Glass s...@chromium.org wrote:
Applied to u-boot-fdt/next, thanks!
Did you
-by: Michal Simek michal.si...@xilinx.com
---
include/net.h | 14 +++---
net/bootp.c | 18 +-
net/bootp.h | 2 +-
3 files changed, 17 insertions(+), 17 deletions(-)
Looks reasonable to me:
Reviewed-by: Thierry Reding tred...@nvidia.com
pgpOQfwEm0gNi.pgp
On Tue, Mar 24, 2015 at 04:42:04PM +0100, Marek Vasut wrote:
On Tuesday, March 24, 2015 at 12:36:55 AM, Rob Herring wrote:
On Fri, Mar 20, 2015 at 8:19 AM, Marek Vasut ma...@denx.de wrote:
On Tuesday, March 17, 2015 at 09:46:37 PM, Rob Herring wrote:
Change addresses to unsigned long to
From: Thierry Reding tred...@nvidia.com
This fixes some build errors and warnings caused by inline assembly and
pointer to integer cast size mismatches. The inline assembly build error
in config_cache() is easy to fix because the code isn't meaningful on 64
bit ARM. For the assembly-level
From: Thierry Reding tred...@nvidia.com
Explicitly cast the result of a pointer arithmetic to unsigned int so
that it matches the corresponding printf format string. While at it, use
%p to print a buffer address rather than %x and an explicit cast (which
causes a warning in this case because it's
From: Thierry Reding tred...@nvidia.com
Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.
Cc: Joe Hershberger
From: Thierry Reding tred...@nvidia.com
Fix a couple of pointer to integer size mismatch warnings by casting
pointers to unsigned long rather than unsigned int.
Cc: Heiko Schocher h...@denx.de
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/i2c/tegra_i2c.c | 4 ++--
1 file changed
From: Thierry Reding tred...@nvidia.com
Fix an pointer to integer cast size mismatch warning by casting to
unsigned long instead of unsigned int and fix up the corresponding
printf format string to use %lx instead of %x.
Also remove a pointless cast producing a size mismatch warning.
Cc: Simon
From: Thierry Reding tred...@nvidia.com
Fix a couple of pointer to integer size mismatch warnings by casting
pointers to unsigned long rather than unsigned int.
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
Cc: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
From: Thierry Reding tred...@nvidia.com
Fix a type mismatch in a printf format string.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/usb/eth/asix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/eth/asix.c b/drivers
From: Thierry Reding tred...@nvidia.com
Implement early malloc() support in a similar way as on 32-bit ARM. This
is required for 64-bit Tegra SoCs that initialize from the device tree
just like the earlier 32-bit SoCs.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng
From: Thierry Reding tred...@nvidia.com
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
While at it, fix the values for the shareability attribute field to
match the documentation.
Cc: Albert Aribaud
From: Thierry Reding tred...@nvidia.com
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix
From: Thierry Reding tred...@nvidia.com
This is mostly useful for debugging the early boot process. Often boards
can provide some low-level code that outputs a character on some debug
port prior to passing the early setup code. Allow boards to implement an
early_putc() function that will be used
From: Thierry Reding tred...@nvidia.com
Use the physical address of the debug serial port from the configuration
to provide an early_putc() implementation that can be used with the new
early console support.
Cc: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
From: Thierry Reding tred...@nvidia.com
Fix a slew of pointer to integer cast size mismatch warnings caused by
this driver explicitly casting pointers to 32-bit integers. While it is
true that the hardware can only deal with 32-bit addresses, truncating
using a cast isn't the right solution
From: Thierry Reding tred...@nvidia.com
Cast pointers to unsigned long instead of a sized 32-bit type to avoid
pointer to integer cast size mismatch warnings.
Cc: Tom Warren twar...@nvidia.com
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/usb/host
From: Thierry Reding tred...@nvidia.com
Fix a slew of pointer to integer cast size mismatch warnings caused by
this driver explicitly casting pointers to 32-bit integers. While it is
true that the hardware can only deal with 32-bit addresses, truncating
using a cast isn't the right solution
From: Thierry Reding tred...@nvidia.com
Use the %lx printf specifier to print unsigned long variables to avoid a
build warning on 64-bit.
Cc: Simon Glass s...@chromium.org
Signed-off-by: Thierry Reding tred...@nvidia.com
---
lib/fdtdec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Thierry Reding tred...@nvidia.com
Use the %pa specifier to print physical addresses rather than %x. The
latter causes build warnings on 64-bit.
Cc: Tom Warren twar...@nvidia.com
Cc: Tom Rini tr...@konsulko.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/pci/pci_tegra.c
From: Thierry Reding tred...@nvidia.com
Fix a printf format mismatch warning seen on 64-bit builds.
Cc: Łukasz Majewski l.majew...@samsung.com
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/usb/gadget/f_mass_storage.c | 2 +-
1 file changed, 1
From: Thierry Reding tred...@nvidia.com
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier marc.zyng...@arm.com
Suggested-by: Mark Rutland mark.rutl
From: Thierry Reding tred...@nvidia.com
Some SoCs come with a custom timer interface, so allow them to use that
instead.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/armv8/generic_timer.c | 2
From: Thierry Reding tred...@nvidia.com
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
Signed
From: Thierry Reding tred...@nvidia.com
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Cc: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
From: Thierry Reding tred...@nvidia.com
Move various selects from the TEGRA symbol to the symbols for 32-bit
Tegra boards. This is necessary because these settings do not extend
to U-Boot for 64-bit Tegra SoCs. Also tie the private libgcc build
to SPL, it isn't needed on 64-bit Tegra.
Cc: Tom
From: Thierry Reding tred...@nvidia.com
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Cc: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/mach-tegra/board.c | 2 +-
1 file
From: Thierry Reding tred...@nvidia.com
This header file uses type definitions (u8, u32) from linux/types.h but
doesn't include it. If includes aren't carefully ordered this can cause
build failures.
Cc: Tom Warren twar...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm
From: Thierry Reding tred...@nvidia.com
U-Boot inspects the initrd_high and fdt_high environment variables and
skips relocation of the initial ramdisk and FDT, respectively, if these
variables are set to all-ones. The Tegra configuration sets these
variables to in the default environment
From: Thierry Reding tred...@nvidia.com
Most peripherals on Tegra can do DMA only to the lower 32-bit address
space, even on 64-bit SoCs. This limitation is typically overcome by the
use of an IOMMU. Since the IOMMU is not entirely trivial to set up and
serves no other purpose (I/O protection
From: Thierry Reding tred...@nvidia.com
The current implementation of fdtdec_get_addr_size() assumes that the
sizes of fdt_addr_t and fdt_size_t match the number of cells specified
by the #address-cells and #size-cells properties. However, there is no
reason why that needs to be the case, so
From: Thierry Reding tred...@nvidia.com
Drivers that need to parse addresses from the device tree will want to
reuse this function rather than duplicating it.
Cc: Simon Glass s...@chromium.org
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include/fdtdec.h | 8
lib/fdtdec.c
From: Thierry Reding tred...@nvidia.com
The fdtdec_get_pci_addr() implementation uses fdt_addr_to_cpu() to read
cells from an FDT blob. That is wrong because cells are always 32 bits
wide, irrespective of the architecture's address bus width, which does
not apply to fdt_addr_t.
Besides reading
From: Thierry Reding tred...@nvidia.com
The source command uses an unsigned long to iterate over the 32-bit
lengths array contained in the legacy image format. On architectures
where unsigned long is 64-bit this fails to find the correct entry
point of a script.
Cc: Tom Rini tr...@konsulko.com
From: Thierry Reding tred...@nvidia.com
The bootz command doesn't work with Linux kernel images on 64-bit ARM.
The replacement command with the same interface and functionality is
booti.
Cc: Dennis Gilmore den...@ausil.us
Cc: Tom Rini tr...@konsulko.com
Signed-off-by: Thierry Reding tred
From: Thierry Reding tred...@nvidia.com
Reuse the 32-bit ARM client architecture and identify ARMv8 specifically
by setting the BOOTP VCI string.
Cc: Dennis Gilmore den...@ausil.us
Cc: Tom Rini tr...@konsulko.com
Signed-off-by: Thierry Reding tred...@nvidia.com
---
include
On Thu, Mar 19, 2015 at 07:43:35AM -0600, Simon Glass wrote:
Hi Hanna,
On 18 March 2015 at 11:17, Hanna Hawa han...@marvell.com wrote:
Hi Simon,
My name is Hanna, I’m working in Software team in Marvell with Yehuda.
I’m trying to run U-Boot with FDT in 64Bit.
I’ve issue
| 5 ++
20 files changed, 428 insertions(+), 98 deletions(-)
create mode 100644 arch/arm/mach-tegra/psci.S
create mode 100644 arch/arm/mach-tegra/tegra124/ap.c
For the series:
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
On Wed, Mar 11, 2015 at 11:12:25AM -0400, Tom Rini wrote:
* PGP Signed by an unknown key
On Mon, Mar 09, 2015 at 08:00:18AM +0100, Jan Kiszka wrote:
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
+ENTRY(psci_cpu_off)
+ bl psci_cpu_off_common
+
+ mrc p15, 0, r1, c0, c0, 5 @ MPIDR
+ and r1, r1, #7 @ number of CPUs in cluster
+
+ get_csr_reg r1, r2, r3
+
+ ldr
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
diff --git a/arch/arm/cpu/armv7/tegra124/ap.c
b/arch/arm/cpu/armv7/tegra124/ap.c
[...]
+void ap_pm_init(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ struct pmc_ctlr *pmc = (struct
On Tue, Feb 24, 2015 at 08:23:55AM +0100, Jan Kiszka wrote:
On 2015-02-20 10:36, Jan Kiszka wrote:
On 2015-02-19 10:14, Thierry Reding wrote:
On Wed, Feb 18, 2015 at 09:34:53AM -0700, Stephen Warren wrote:
On 02/17/2015 11:13 PM, Jan Kiszka wrote:
On 2015-02-17 22:03, Stephen Warren wrote
support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help
On Mon, Feb 16, 2015 at 01:54:46PM +0100, Jan Kiszka wrote:
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Thierry Reding
One more thing...
On Mon, Feb 16, 2015 at 01:54:46PM +0100, Jan Kiszka wrote:
diff --git a/arch/arm/cpu/armv7/tegra-common/psci.S
b/arch/arm/cpu/armv7/tegra-common/psci.S
[...]
+ENTRY(psci_arch_init)
+ mov r6, lr
+
+ mrc p15, 0, r5, c1, c1, 0 @ Read SCR
+ bic r5,
On Thu, Feb 19, 2015 at 10:25:56AM +0100, Jan Kiszka wrote:
On 2015-02-19 10:19, Ian Campbell wrote:
On Thu, 2015-02-19 at 09:28 +0100, Thierry Reding wrote:
On Tue, Feb 17, 2015 at 11:55:24AM +, Mark Rutland wrote:
[...]
This is getting invasive:
If I add carveouts via
On Tue, Feb 17, 2015 at 09:09:57AM +0100, Jan Kiszka wrote:
On 2015-02-16 16:38, Jan Kiszka wrote:
On 2015-02-16 15:56, Mark Rutland wrote:
On Mon, Feb 16, 2015 at 02:31:21PM +, Jan Kiszka wrote:
On 2015-02-16 15:25, Mark Rutland wrote:
On Mon, Feb 16, 2015 at 01:51:37PM +, Jan
On Tue, Feb 17, 2015 at 11:55:24AM +, Mark Rutland wrote:
[...]
This is getting invasive:
If I add carveouts via adjusting memory banks, I need to account for the
case that an existing bank is split into two halves, creating additional
banks this way. But then current
On Thu, Feb 05, 2015 at 12:37:39PM +, Mark Rutland wrote:
On Thu, Feb 05, 2015 at 11:44:25AM +, Thierry Reding wrote:
On Fri, Jan 23, 2015 at 12:37:20PM +, Mark Rutland wrote:
On Fri, Jan 23, 2015 at 10:10:45AM +, Thierry Reding wrote:
On Thu, Jan 22, 2015 at 07:20:15PM
On Fri, Jan 23, 2015 at 12:37:20PM +, Mark Rutland wrote:
On Fri, Jan 23, 2015 at 10:10:45AM +, Thierry Reding wrote:
On Thu, Jan 22, 2015 at 07:20:15PM +, Mark Rutland wrote:
On Fri, Jan 16, 2015 at 09:12:59AM +, Thierry Reding wrote:
On Thu, Jan 15, 2015 at 07:19:37PM
On Fri, Jan 23, 2015 at 12:37:20PM +, Mark Rutland wrote:
On Fri, Jan 23, 2015 at 10:10:45AM +, Thierry Reding wrote:
On Thu, Jan 22, 2015 at 07:20:15PM +, Mark Rutland wrote:
On Fri, Jan 16, 2015 at 09:12:59AM +, Thierry Reding wrote:
On Thu, Jan 15, 2015 at 07:19:37PM
On Sat, Jan 24, 2015 at 12:19:56PM +0800, Bin Meng wrote:
Hi Thierry,
On Fri, Jan 23, 2015 at 6:19 PM, Thierry Reding tred...@nvidia.com wrote:
On Thu, Jan 22, 2015 at 12:04:06AM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 5:40 PM, Thierry Reding tred...@nvidia.com wrote
On Thu, Jan 22, 2015 at 07:20:15PM +, Mark Rutland wrote:
On Fri, Jan 16, 2015 at 09:12:59AM +, Thierry Reding wrote:
On Thu, Jan 15, 2015 at 07:19:37PM +, Mark Rutland wrote:
On Wed, Jan 14, 2015 at 07:57:25AM +, Thierry Reding wrote:
On Tue, Jan 13, 2015 at 07:44:50PM
On Thu, Jan 22, 2015 at 12:04:06AM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 5:40 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 05:15:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:24 PM, Thierry Reding tred...@nvidia.com wrote
.
So this patch:
Tested-by: Thierry Reding tred...@nvidia.com
Acked-by: Thierry Reding tred...@nvidia.com
pgpdFr1HlEzwz.pgp
Description: PGP signature
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On Wed, Jan 21, 2015 at 10:00:39AM +0800, Bin Meng wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 10:31 PM, Simon Glass s...@chromium.org wrote:
+Thierry
Hi Bin,
On 20 January 2015 at 05:59, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 11:19 AM, Simon Glass
On Tue, Jan 20, 2015 at 12:05:40PM -0700, Simon Glass wrote:
Hi Sjoerd,
On 20 January 2015 at 10:06, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root
On Wed, Jan 21, 2015 at 04:46:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:05 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 10:00:39AM +0800, Bin Meng wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 10:31 PM, Simon Glass s...@chromium.org wrote
On Wed, Jan 21, 2015 at 05:15:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:24 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 10:37:07AM +0800, Bin Meng wrote:
Hi,
On Wed, Jan 21, 2015 at 3:05 AM, Simon Glass s...@chromium.org wrote:
Hi
On Wed, Jan 21, 2015 at 10:37:07AM +0800, Bin Meng wrote:
Hi,
On Wed, Jan 21, 2015 at 3:05 AM, Simon Glass s...@chromium.org wrote:
Hi Sjoerd,
On 20 January 2015 at 10:06, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
commit a62e84d7b1824a202dd incorrectly changed the tegra pci
On Fri, Jan 16, 2015 at 04:11:19PM +, Ian Campbell wrote:
On Fri, 2015-01-16 at 17:03 +0100, Thierry Reding wrote:
On Fri, Jan 16, 2015 at 10:24:03AM +, Ian Campbell wrote:
On Fri, 2015-01-16 at 11:05 +0100, Thierry Reding wrote:
On Fri, Jan 16, 2015 at 09:43:22AM +, Ian
On Thu, Jan 15, 2015 at 04:59:12PM -0700, Stephen Warren wrote:
On 01/13/2015 12:45 PM, Ian Campbell wrote:
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next
On Thu, Jan 15, 2015 at 07:19:37PM +, Mark Rutland wrote:
On Wed, Jan 14, 2015 at 07:57:25AM +, Thierry Reding wrote:
On Tue, Jan 13, 2015 at 07:44:50PM +, Ian Campbell wrote:
Hi Thierry,
I needed to boot my Jetson in NS mode (in order to boot Xen) and was
investigating
On Fri, Jan 16, 2015 at 09:43:22AM +, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:55 +0100, Thierry Reding wrote:
On Wed, Jan 14, 2015 at 08:58:41AM +, Ian Campbell wrote:
On Wed, 2015-01-14 at 08:57 +0100, Thierry Reding wrote:
I also pushed my tree to gitorious
On Fri, Jan 16, 2015 at 10:24:03AM +, Ian Campbell wrote:
On Fri, 2015-01-16 at 11:05 +0100, Thierry Reding wrote:
On Fri, Jan 16, 2015 at 09:43:22AM +, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:55 +0100, Thierry Reding wrote:
On Wed, Jan 14, 2015 at 08:58:41AM +, Ian
On Wed, Jan 14, 2015 at 08:58:41AM +, Ian Campbell wrote:
On Wed, 2015-01-14 at 08:57 +0100, Thierry Reding wrote:
I also pushed my tree to gitorious:
https://gitorious.org/ijc/u-boot jetson-psci-v1
I would Ack your patch, but I don't think you've posted it and it has
On Tue, Jan 13, 2015 at 07:44:50PM +, Ian Campbell wrote:
Hi Thierry,
I needed to boot my Jetson in NS mode (in order to boot Xen) and was
investigating the possibility of PSCI support when I discovered that you
had already started on it[0]. Hurrah!
I cherry-picked the relevant commit
On Wed, Nov 12, 2014 at 06:26:51PM -0700, Simon Glass wrote:
[...]
diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c
[...]
+int as3722_init(struct udevice **devp)
+{
+ struct udevice *pmic;
+ u8 id, revision;
+ int bus = 0;
+ int address = 0x40;
Is there a reason
On Wed, Nov 12, 2014 at 06:27:16PM -0700, Simon Glass wrote:
From: Thierry Reding tred...@nvidia.com
This network interface card in found on the NVIDIA Jetson TK1.
Self-correct: s/in found/is found/
Thierry
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On Wed, Nov 12, 2014 at 06:27:15PM -0700, Simon Glass wrote:
[...]
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index fc8c31e..cd26c36 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -41,6 +41,7 @@
* Modified to use le32_to_cpu and cpu_to_le32 properly
*/
Hi Simon,
Thanks for taking this over. Besides the three small nitpicks (which
aren't really blockers, so feel free to ignore) this looks like what I
would've done had I respun the series.
Thierry
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___
On Wed, Oct 22, 2014 at 09:07:40PM -0600, Simon Glass wrote:
Hi,
On 11 September 2014 10:00, Albert ARIBAUD albert.u.b...@aribaud.net wrote:
Hi Thierry,
On Tue, 26 Aug 2014 17:33:48 +0200, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
On Fri, Oct 03, 2014 at 10:41:09AM -0700, Tom Warren wrote:
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org swar...@wwwdotorg.org
]
Sent: Friday, October 03, 2014 8:56 AM
To: Marcel Ziswiler
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren
On Sun, Sep 28, 2014 at 04:48:47PM -0600, Simon Glass wrote:
Hi Thierry,
On 26 August 2014 09:33, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size
is
mostly due
On Wed, Aug 27, 2014 at 11:41:55AM -0600, Stephen Warren wrote:
On 08/27/2014 01:01 AM, Thierry Reding wrote:
On Tue, Aug 26, 2014 at 11:04:56AM -0600, Stephen Warren wrote:
On 08/26/2014 09:33 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Provide a new modifier
On Wed, Aug 27, 2014 at 07:21:51AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 26.08.2014 17:34, schrieb Thierry Reding:
From: Thierry Redingtred...@nvidia.com
This API operates on I2C adapters or I2C clients (a new type of object
which is a bad idea ...
that refers
On Wed, Aug 27, 2014 at 07:26:12AM +0200, Heiko Schocher wrote:
Hello Thierry,
Am 26.08.2014 17:34, schrieb Thierry Reding:
[...]
+int as3722_init(struct as3722 **pmicp, const void *fdt)
+{
+struct as3722 *pmic =as3722_pmic;
+int count, nodes[1], i;
+int err;
+
+count
On Tue, Aug 26, 2014 at 11:04:56AM -0600, Stephen Warren wrote:
On 08/26/2014 09:33 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Provide a new modifier to vsprintf() to print phys_addr_t variables to
avoid having to cast or #ifdef when printing them out. The %pa modifier
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