On 12/11/19 6:47 PM, Simon Glass wrote:
- * void relocate_code (addr_moni)
+ * void relocate_code(addr_moni)
Is this really necessary? I think you're bloating your patch with these
comment changes. Your patch would be half the size without these
changes, so I don't think this really
On 05/02/2018 06:12 PM, Fabio Estevam wrote:
ti...@freescale.com is not a valid email for quite some time, so change
it to Timur's updated email.
Signed-off-by: Fabio Estevam<fabio.este...@nxp.com>
Acked-by: Timur Tabi <ti...@tabi.org>
__
On 5/1/18 1:54 PM, Fabio Estevam wrote:
Timur, would you like to keep maintaining p1022ds?
If so, then please send an email switching your address toti...@tabi.org.
Ok.
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Bin Meng wrote:
>I believe that ACPI systems generally expect EFI runtime services to
>be present as well. I know ours does.
This is not true. ACPI does not require any EFI runtime services.
Please re-read my sentence. I said "generally expect".
If you guys want to spend the man-years
On Wed, Oct 5, 2016 at 8:58 PM, Tom Rini wrote:
>
> I think that takes too narrow of a view. If silicon is sold, someone
> will put it somewhere. And if there's firmware that works, and the
> buyer can modify to suit their design, they'll use it.
I believe that ACPI systems
Tom Rini wrote:
Well, I wouldn't phrase it quite like that. I would ask, do we want to
go down this path? How far down would we want to go, if so?
ACPI is pretty complicated, more so than DT. UEFI is also open source.
I think you need to find a very compelling reason to reinvent the
On Wed, Oct 5, 2016 at 9:46 AM, Simon Glass wrote:
>> Is there any activity to bring ACPI to other than x86 arch? If not, do
>> we have a plan to do so?
>
> Not that I know of, sorry.
Note that ACPI for ARM exists on Linux already, and as far as I know,
all ARM ACPI systems
Mario Six wrote:
On Tue, May 10, 2016 at 2:30 PM, Timur Tabi <ti...@tabi.org
<mailto:ti...@tabi.org>> wrote:
Mario Six wrote:
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
dev->of_offset,
+
Mario Six wrote:
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", 0, );
Why can't you use platform_get_resource()?
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Mario Six wrote:
The problem is that in 36-bit mode the physical addresses are 64-bit, which
means that you get 64-bit integers when you read something from the
device tree
with fdtdec_get_addr. But the device tree addresses themselves seem to be
32-bit, because if I read a property like 'reg =
On Mon, May 2, 2016 at 6:43 AM, Mario Six wrote:
> Regarding the address width discrepancy: The system I'm working on is a
> P1022 Qoriq, which has 36 bit width, which implies that phys_addr_t needs
> to be 64 bit. But the everything else (including the GPIO controller) uses
>
On Fri, May 22, 2015 at 9:55 PM, Kushwaha Prabhakar
prabha...@freescale.com wrote:
It is not getting catch during GCC build. But during static analysis using
Klockwork, this is shown as error.
Then Klockwork is wrong.
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On Fri, Apr 18, 2014 at 4:32 AM, dongsheng.w...@freescale.com
dongsheng.w...@freescale.com wrote:
If we have, why kernel doesn't support DIU on T1040QDS? That I must remove it
reason.
Because no one added that support yet. You should finish the job by
fixing the kernel.
+ string
+ default Timur Tabi ti...@freescale.com
My new email address is now ti...@tabi.org. I don't work for
Freescale any more. You could also assign the board maintainer to
someone else (York?) instead. I don't actually expect to maintain
this board any more
On Mon, Jan 27, 2014 at 2:14 AM, Zhao Qiang b45...@freescale.com wrote:
+#ifndef CONFIG_PPC_T1040
Nack. You need to write this code without all this T1040-specific
#ifdefs everywhere.
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qiang.z...@freescale.com wrote:
T1040QDS has microcode for Fman and another microcode for QE.
The two microcodes is different.
QE microcode is needed.
Then why do you have an #else statement:
+#ifdef CONFIG_PPC_T1040
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
On Fri, Jan 24, 2014 at 7:45 AM, Wolfgang Denk w...@denx.de wrote:
For the test
part, it is probably much easier to add a customized memory test (or
fix just the existing memory test such that it can be built for a 64
bit mode) and use this, then trying to run all of U-Boot in 64 bit
mode.
On Fri, Jan 24, 2014 at 3:05 AM, Zhao Qiang b45...@freescale.com wrote:
+#ifdef CONFIG_PPC_T1040
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
+#else
qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+#endif
It's been a while since I looked at
qiang.z...@freescale.com wrote:
CONFIG_SYS_QE_FMAN_FW_ADDR is used for Fman microcode while
CONFIG_SYS_QE_UCODE_FW_ADDR used
For QE microcode.
No, CONFIG_SYS_QE_FMAN_FW_ADDR is used for both QE and Fman microcode.
That's why it says QE_FMAN in it. This is documented in the README.
qiang.z...@freescale.com wrote:
Other boards have either Fman or QE, So CONFIG_SYS_QE_FMAN_FW_ADDR can
be used either Fman or QE.
But T1040QDS have both Fman and QE.
Does the T1040QDS have microcode for both Fman and QE? Normally, QE
microcode is not needed.
Claudiu Manoil wrote:
I think you're suggesting that virt_to_phys() should be used
to fix that, right?
Yes.
However, virt_to_phys() is equivalent to that
simple cast in most cases as there's no CONFIG_PHYS_64BIT for the
platforms with eTSEC. I'm actually not sure if there's a platform
with
On Fri, Oct 4, 2013 at 11:25 AM, Claudiu Manoil
claudiu.man...@freescale.com wrote:
[v3] declaring the BDs as __iomem to avoid casting submitted:
http://patchwork.ozlabs.org/patch/280664/
+ out_be32(regs-tbase, (u32)txbd[0]);
+ out_be32(regs-rbase, (u32)rxbd[0]);
rxbd[0] is a virtual address.
On Sat, Oct 5, 2013 at 9:31 AM, Timur Tabi ti...@tabi.org wrote:
+ out_be32(regs-tbase, (u32)txbd[0]);
+ out_be32(regs-rbase, (u32)rxbd[0]);
rxbd[0] is a virtual address.
Doesn't rbase require a physical address? You're assuming that virt == phys.
Also:
- out_be32(regs-tbase, (unsigned
On Mon, Sep 30, 2013 at 4:44 AM, Claudiu Manoil
claudiu.man...@freescale.com wrote:
+#define GET_BD_STAT(T, i) be16_to_cpu((__force __be16)T##BD(i).status)
+#define SET_BD_STAT(T, i, v) T##BD(i).status = (__force __u16)cpu_to_be16(v)
+#define GET_BD_BLEN(T, i) be16_to_cpu((__force
On Mon, Sep 30, 2013 at 7:04 PM, York Sun york...@freescale.com wrote:
struct ccsr_ddr __iomem *ddr = (void *) CONFIG_FOO_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *) CONFIG_FOO_ADDR;
You have told me the second format is preferred. I have been using this
format
On Sat, Sep 21, 2013 at 8:31 PM, Po Liu po@freescale.com wrote:
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
(uchar) is wrong.
int i2c_read(uint8_t chip, unsigned int addr, int alen,
On Tue, Sep 17, 2013 at 10:59 AM, York Sun york...@freescale.com wrote:
I am wondering if there is generic
DDR driver used by many ARM platforms, like the one we have for
powerpc/mpc85xx SoCs.
Sadly, no such thing exists. There is no generic DDR controller for
ARM. I'm working on DDR
On Thu, Sep 19, 2013 at 3:57 PM, Tom Rini tr...@ti.com wrote:
Thinking back, as a rule of thumb, PowerPC has SPD I2C data
available, usually. That's not the rule for ARM. One of a few choices
happen:
Even if you do have SPD on your ARM chip, that's still no guarantee
that you can program
On Fri, Sep 6, 2013 at 4:21 AM, Jason Jin jason@freescale.com wrote:
#ifndef CONFIG_FSL_DIU_FB
+#define CONFIG_ATI
#endif
Is this really necessary? If the DIU is disabled, why would someone
use a PCI video controller?
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field to determine if this space is used for
additional MAC addresses.
Which means that you can fill the EEPROM with MAC addresses. If you do
the math, that means 31 addresses.
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On Mon, Jul 6, 2009 at 10:11 AM, Kumar Gala ga...@kernel.crashing.org wrote:
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
/* Is this a valid NXID EEPROM? */
-#define is_valid (*((u32 *)e.id) == (('N' 24) | ('X' 16) | ('I' 8)
| 'D'))
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+
On Fri, Aug 30, 2013 at 5:07 AM, Shengzhou Liu
shengzhou@freescale.com wrote:
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* some boards with non-256-bytes EEPROM have special define */
+/* for MAX_NUM_PORTS in board-specific file */
+#ifndef MAX_NUM_PORTS
#define MAX_NUM_PORTS 23
+#endif
handle v1 and v2.
BTW, your patch breaks EVERY OTHER BOARD. You can't just change the 23
to a 9 for every board. Did you test your patch on other boards?
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On Thu, Aug 8, 2013 at 5:14 AM, Shengzhou Liu
shengzhou@freescale.com wrote:
On some boards, the size of EEPROM is 128 Bytes instead of 256.
so we set default MAX_NUM_PORTS to 9 rather than previous 23 to
avoid the programming failure, we can define MAX_NUM_PORTS in
board-specific header
...@freescale.com
Ack.
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On 07/08/2013 01:19 PM, Wolfgang Denk wrote:
+ uint32_t crc_buf;
+
+ memcpy(crc_buf, buf[24], sizeof(unsigned int));
Well, this is wrong, because it should be sizeof(uint32_t). Or maybe
sizeof(crc_buf).
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;
This should be a uint32_t, because you specifically want only four bytes.
If you fix that,
Acked-by: Timur Tabi ti...@tabi.org
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On Fri, Jun 28, 2013 at 4:47 PM, Andy Fleming aflem...@gmail.com wrote:
Well, he hasn't been at Freescale for years, now, so that's not surprising.
It's not entirely clear to me whether that board is one we actively
support, but I suspect we can get away with maintenance moving over to Kim.
On Tue, Jun 18, 2013 at 5:39 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Support TPL on the P1022DS.
Please define TPL. I have no idea what it is.
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On Tue, Apr 16, 2013 at 4:00 AM, Chunhe Lan chunhe@freescale.com wrote:
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
It's amazing that Freescale is still producing board files that are
missing 57,600 baud.
powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx
- stxssa
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types like this:
i = 0;
j = 0;
k = 2;
if ((i | j | k) == true) ...
Ok, but this is just wrong. i, j, and k are not boolean types, so they
should not be compared with 'true' or 'false'. I don't think you'll find
any disagreement with that.
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Linux kernel
in the past 20 years.
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to copy the
variable's value to the address 0.
Signed-off-by: James Yang james.y...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
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to use this new definition instead of a hand-coded enum.
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Prabhakar Kushwaha wrote:
+#define CONFIG_SYS_AMASK3IFC_AMASK(4*1024)
IFC_AMASK(4 * 1024)
Spaces around binary operators, please.
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Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables. Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.
Signed-off-by: Timur Tabi ti
in
serdes_corenet_t, so we make it a named struct.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 48 +
arch/powerpc/include/asm/config_mpc85xx.h |1 +
arch/powerpc/include/asm/immap_85xx.h |2 +-
3 files changed, 50
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.
This requires adding a few bitfield macros for the BnTTLCRy0 register.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx
in PBI than in U-Boot itself.
It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.
Signed-off-by: Timur Tabi ti
think there is any reasonable objection to my patch. Please
apply it. Without it, we have a broken implementation of the EEPROM
parser, and *that* is not acceptable.
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The P5040DS reference board (a.k.a Superhydra) is an enhanced version of
P3041DS/P5020DS (Hydra) reference board.
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
board/freescale/common/Makefile |2 +
board/freescale/common
. It's a holdover from the SDK.
Signed-off-by: Timur Tabi ti...@freescale.com
---
This patch should be applied before [v4] powerpc/85xx: add support for the
Freescale P5040DS Superhydra reference board
arch/powerpc/include/asm/config_mpc85xx.h |2 +-
1 files changed, 1 insertions(+), 1
Xie Shaohui-B21989 wrote:
Is this still true with Fman v3?
[S.H] No. Fman V3 does not need to set TBIPA on FM1@DTSEC1.
Does this patch break Fman V3?
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The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h. They belong in the board-specific header files.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P3041DS.h|4
include/configs/P4080DS.h|4
include/configs/P5020DS.h
Commit 709389b6 unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/release.S | 24
1 files changed, 12 insertions(+), 12 deletions(-)
diff
From: Laurentiu Tudor laurentiu.tu...@freescale.com
Add a new device tree property named fsl,liodn-offset-list
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a
dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/liodn.c |8
arch/powerpc/include/asm/fsl_liodn.h |4 +++-
2
enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx
The P5040DS reference board (a.k.a Superhydra) is an enhanced version of
P3041DS/P5020DS (Hydra) reference board.
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/cpu/mpc85xx/p5040_ids.c| 66 ++--
board/freescale/common
enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi ti...@freescale.com
---
v4: forgot a couple LIODN updates
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch
Kim Phillips wrote:
need another two DECO entries.
Doh, I merged the change into the wrong commit. Ugh. Thanks for catching
that.
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enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi ti...@freescale.com
---
v5: fixed all the LIODNs, for real this time.
arch/powerpc/cpu/mpc85xx/Makefile
in the p5040 has four DECOs, not two.
I should have the proper LIODN information later today.
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Commit 709389b6 unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/release.S | 24
1 files changed, 12 insertions(+), 12 deletions(-)
diff
From: Laurentiu Tudor laurentiu.tu...@freescale.com
Add a new device tree property named fsl,liodn-offset-list
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a
enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi ti...@freescale.com
---
The LIODNs for the SEC's DECOs are apparently wrong, but the correct
values are not available
dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2
The P5040DS reference board (a.k.a Superhydra) is an enhanced version of
P3041DS/P5020DS (Hydra) reference board.
Signed-off-by: Timur Tabi ti...@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
board/freescale/common/Makefile |2 +
board/freescale/common
The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h. They belong in the board-specific header files.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P3041DS.h|4
include/configs/P4080DS.h|4
include/configs/P5020DS.h
. Unfortunately, not all Freescale developers have gotten
the message.
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software place for test and debug. Maybe I want
to read out RAM contents?
It's a boot loader, not a testing platform.
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Robert Thorhuus wrote:
Still I wonder why the choice was made to have U-Boot relocate in high
memory rather than low memory and also not making it easy to configure
the relocation.
U-Boot relocates in high memory so that you can load your operating system
at address 0.
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Linux
if your extended
testing needs to be a viable option at every boot and that you have
boot time requirements?
You can create U-boot applications that test your hardware, if you want
to test from within U-Boot.
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.
What exactly is the licensing of this code?
It's not GPL-compatible, so linking the code with U-boot and shipping the
binary as one blob is probably a GPL violation. That's why I created the
QE firmware binary format and wrote all that code to treat the firmware
as a separate binary blob.
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.
If you can do it, go ahead. I would approve a patch that adds the ability
to inject a firmware binary into u-boot.bin, provided it's controlled via
a build or CONFIG_SYS_xxx option.
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or rewritten code to
make it smaller. If making U-boot larger were so simple, it would have
been done by now, I think.
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.
3) Don't configure any write-back buffer registers, since we don't use
that mode.
4) The default values for the THRESHOLDS, SYN_POL, and PLUT registers
should be used, so don't touch those registers either.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/video/fsl_diu_fb.c | 21
as wrong). Plus, if I'd had reviewed this, it would have
four DECOs by now.
Ok, I'll just wait until someone tells me what changes to make to this code.
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dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/include/asm/fsl_liodn.h |5 +
arch/powerpc/include/asm/immap_85xx.h |4 +++-
2
enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
arch/powerpc/cpu/mpc85xx
The P5040DS reference board (a.k.a Superhydra) is an enhanced version of
P3041DS/P5020DS (Hydra) reference board.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/Makefile |2 +
board/freescale/corenet_ds/Makefile |2 +
board/freescale
The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h. They belong in the board-specific header files.
Signed-off-by: Timur Tabi ti...@freescale.com
---
include/configs/P3041DS.h|4
include/configs/P4080DS.h|4
include/configs/P5020DS.h
The previous commit unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/release.S | 24
1 files changed, 12 insertions(+), 12 deletions
the kernel code, which I've already done for
my testing.
--
Timur Tabi
Linux kernel developer at Freescale
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enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/init.c
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/init.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/fman.c | 31 +++
board/freescale
code
depends on several device tree aliases to help it find the nodes that
need to be updated.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/eth_p4080.c | 172
1 files changed, 129 insertions(+), 43 deletions(-)
diff --git a/board
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |6 ++
arch/powerpc/include/asm/fsl_serdes.h |1
,
[FM2_10GEC1] = XAUI_FM2,
};
if ((port FM1_DTSEC1) || (port FM2_10GEC1))
return NONE;
else
return srds_table[port];
I'm not sure that's an improvement.
--
Timur Tabi
Linux kernel developer at Freescale
Kim Phillips wrote:
it's ~30% less lines of code, and the maps lie on the same line,
which helps when grepping.
OK.
--
Timur Tabi
Linux kernel developer at Freescale
___
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Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/init.c
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi ti...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |6 ++
arch/powerpc/include/asm/fsl_serdes.h |1
code
depends on several device tree aliases to help it find the nodes that
need to be updated.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds/eth_p4080.c | 172
1 files changed, 129 insertions(+), 43 deletions(-)
diff --git a/board
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi ti...@freescale.com
---
drivers/net/fm/init.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/corenet_ds
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/fman.c | 40
board
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