Hi,
On Wednesday 24 August 2016 03:35 PM, Hannes Schmelzer wrote:
> During probing flashes on the spi bus using the "sf probe" command, a
> maybe existing flash (from fdt) is unbound and removed to force the
> 'spi_flash_probe_bus_cs' really scanning the bus.
>
> Today the bus is probed with spee
On Wednesday 17 August 2016 06:19 PM, Tom Rini wrote:
> On Wed, Aug 17, 2016 at 10:51:52AM +0530, Vignesh R wrote:
>>
>> On Monday 01 August 2016 09:53 PM, Tom Rini wrote:
>>> On Mon, Aug 01, 2016 at 02:41:08PM +0530, Vignesh R wrote:
>>>
>>>> mak
make tags creates a symbolic link called tags to ctags. Remove this file
on make mrproper or make distclean.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index a2f5569b9c14..ac132a926db3
On Monday 01 August 2016 09:53 PM, Tom Rini wrote:
> On Mon, Aug 01, 2016 at 02:41:08PM +0530, Vignesh R wrote:
>
>> make tags creates a symbolic link called tags to ctags. Remove this file
>> on make mrproper or make distclean.
>>
>> Signed-off-by: Vignesh
Some IPs like MMC use PCF GPIO lines as fixed regulator, hence add
support for the same.
Vignesh R (2):
ARM: dts: dra7xx-evm: add evm_3v3_sd regulator
ARM: dra7xx_evm: Enable regulator DM support
arch/arm/dts/dra7-evm.dts | 12 +++-
arch/arm/dts/dra72-evm.dts | 12
Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Vignesh R
---
arch/arm/dts/dra7-evm.dts | 12 +++-
arch/arm/dts
Enable DM based regulator framework and also fixed regulator support as
some IPs like mmc use regulators for there functioning.
Signed-off-by: Vignesh R
---
configs/dra7xx_evm_defconfig| 3 +++
configs/dra7xx_hs_evm_defconfig | 3 +++
2 files changed, 6 insertions(+)
diff --git a/configs
On Wednesday 10 August 2016 01:33 AM, Jagan Teki wrote:
> INFO macro make flash table entries more adjustable like
> adding new flash_info attributes, update ID length bytes
> and so on and more over it will sync to Linux way of defining
> flash_info attributes.
[...]
> diff --git a/drivers/mtd/s
Hi,
On Wednesday 10 August 2016 01:33 AM, Jagan Teki wrote:
> Make rx mode flags as generic to spi, earlier mode_rx is
> maintained separately becuase of some flash specific code.
>
Nit: s/becuase/because
[...]
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index bb72cb0..37dc64
On Friday 29 July 2016 04:50 PM, Vignesh R wrote:
> This series adds support for TI's PCF8575 I2C GPIO expander[1] based on
> Linux Kernel driver for the same. Also adds support for ethernet to use
> new PCF8575 driver to select appropriate cpsw slaves on dra72.
>
> Depen
On DRA7, pcf chip present at address 0x21 on i2c1, is used to
switch between cpsw slave0 and slave1. Hence, enable PCF
driver for the same.
Signed-off-by: Vignesh R
---
v3: Pick up CONFIG_PCF8575_GPIO via Kconfig.
configs/dra7xx_evm_defconfig| 1 +
configs/dra7xx_hs_evm_defconfig | 1 +
2
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v3: No change
arch/arm/dts/dra72
On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Acked-by: Joe Hershberger
---
v3: No
evice documentation for more details[1].
This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.
[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
---
v3: use dm_i2c
PCF8575 does not have any registers hence, offset field needs to be
ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len
with 0 in PCF8575 DT nodes.
Signed-off-by: Vignesh R
---
v3: New patch.
arch/arm/dts/dra7-evm.dts | 1 +
arch/arm/dts/dra72-evm.dts | 2 ++
2 files changed
This series adds support for TI's PCF8575 I2C GPIO expander[1] based on
Linux Kernel driver for the same. Also adds support for ethernet to use
new PCF8575 driver to select appropriate cpsw slaves on dra72.
Tested on DRA72 EVM.
[1]http://www.ti.com/lit/ds/symlink/pcf8575.pdf
Vignesh
make tags creates a symbolic link called tags to ctags. Remove this file
on make mrproper or make distclean.
Signed-off-by: Vignesh R
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 99cc8cf2f701..d1ad6c685442 100644
--- a/Makefile
+++ b
On Monday 01 August 2016 06:31 AM, Simon Glass wrote:
> Hi,
>
> On 25 July 2016 at 07:10, Vignesh R wrote:
>> TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
>> 16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
>> be used a
Hi,
On Monday 01 August 2016 06:31 AM, Simon Glass wrote:
[...]
+/* PCF Support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCF8575_GPIO
+#endif
>>>
>>> We need to invert the logic and undef on SPL, and pick this up normally
>>> via Kconfig.
>>>
>>
>> I tried that initially bu
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v2: no change
arch/arm/dts/dra72
On DRA7, pcf chip present at address 0x21 on i2c1, is used to
switch between cpsw slave0 and slave1. Hence, enable PCF
driver for the same.
Signed-off-by: Vignesh R
---
v2: No change
include/configs/dra7xx_evm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs
evice documentation for more details[1].
This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.
[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v2: Drop GPL license text from driver as
On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v2: Drop extra blank line
drivers
mlink/pcf8575.pdf
[2]https://www.mail-archive.com/u-boot@lists.denx.de/msg218923.html
Vignesh R (4):
gpio: Add driver for TI PCF8575 I2C GPIO expander
ARM: dra7xx_evm: Enable support for TI PCF8575
net: cpsw: Add support to drive gpios for ethernet to be functional
ARM: dts: dra72-evm: Add
On Friday 29 July 2016 02:24 PM, Mugunthan V N wrote:
> On Friday 29 July 2016 12:03 PM, Vignesh R wrote:
>> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
>> board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
>>
>&g
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R
---
v2: Add entries for am57xx_hs_evm_defconfig and am57xx_evm_nodt_defconfig
configs/am57xx_evm_defconfig | 5
This series adds support for QSPI for am571x-idk and am572x-idk. The
flash is same as the one present on DRA74 EVM.
Tested on am572x-idk and am571x-idk.
Vignesh R (2):
ARM: am57xx_evm: Enable QSPI support
ARM: dts: am57xx-idk-common: Enable support for QSPI
arch/arm/dts/am57xx-idk
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R
---
v2: No changes
arch/arm/dts/am57xx-idk-common.dtsi | 49 +
1 file changed, 49
On Friday 29 July 2016 12:03 PM, Vignesh R wrote:
>
>
> This series adds support for QSPI for am571x-idk and am572x-idk. The
> flash is same as the one present on DRA74 EVM.
>
> Tested on am572x-idk and am571x-idk.
>
Please ignore this series, I forgot to add supp
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R
---
arch/arm/dts/am57xx-idk-common.dtsi | 49 +
1 file changed, 49 insertions(+)
diff
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R
---
configs/am57xx_evm_defconfig | 5 +
include/configs/am57xx_evm.h | 36
2 files
This series adds support for QSPI for am571x-idk and am572x-idk. The
flash is same as the one present on DRA74 EVM.
Tested on am572x-idk and am571x-idk.
Vignesh R (2):
ARM: am57xx_evm: Enable QSPI support
ARM: dts: am57xx-idk-common: Enable support for QSPI
arch/arm/dts/am57xx-idk
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
Signed-off-by: Vignesh R
---
configs/am43xx_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
On Tuesday 26 July 2016 11:53 AM, Heiko Schocher wrote:
> Hello Vignesh,
>
> Am 25.07.2016 um 12:56 schrieb Vignesh R:
>> As I2C can be used before DRAM initialization for reading EEPROM,
>> avoid using static variables stored in BSS, since BSS is in DRAM, which
>> ma
On Tuesday 26 July 2016 05:43 PM, Tom Rini wrote:
> On Tue, Jul 26, 2016 at 12:07:26PM +0530, R, Vignesh wrote:
>>
>>
>> On 7/25/2016 7:08 PM, Tom Rini wrote:
>>> On Mon, Jul 25, 2016 at 06:40:22PM +0530, Vignesh R wrote:
>>>
>>>> On DRA72 EVM
On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
> On 25 July 2016 at 15:45, Vignesh R wrote:
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>> the driver to use the same.
>>
>> Signed-off-by: Vignesh R
>> -
On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote:
>
>> By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
>> QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
>> 768.
On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 06:40:21PM +0530, Vignesh R wrote:
>
>> On DRA7, pcf chip present at address 0x21 on i2c1, is used to
>> switch between cpsw slave0 and slave1. Hence, enable PCF
>> driver for the same.
>&g
On Monday 25 July 2016 07:08 PM, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 03:45:47PM +0530, Vignesh R wrote:
>
>> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
>> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
>> DRA72 evm.
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: Vignesh R
---
arch/arm/dts/dra72-evm.dts | 2 +-
1 file changed, 1
On DRA7, pcf chip present at address 0x21 on i2c1, is used to
switch between cpsw slave0 and slave1. Hence, enable PCF
driver for the same.
Signed-off-by: Vignesh R
---
include/configs/dra7xx_evm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/dra7xx_evm.h b/include
On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R
---
drivers/net/cpsw.c | 13 +
1 file changed, 13
evice documentation for more details[1].
This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.
[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf
Signed-off-by: Vignesh R
---
doc/device-tree-bindings/gpio/gpio-pcf857x.txt
mlink/pcf8575.pdf
[2]https://www.mail-archive.com/u-boot@lists.denx.de/msg218923.html
Vignesh R (4):
gpio: Add driver for TI PCF8575 I2C GPIO expander
ARM: dra7xx_evm: Enable support for TI PCF8575
net: cpsw: Add support to drive gpios for ethernet to be functional
ARM: dts: dra72-evm: Add
As I2C can be used before DRAM initialization for reading EEPROM,
avoid using static variables stored in BSS, since BSS is in DRAM, which
may not have been initialised yet. Explicitly mark "static global"
variables as belonging to the .data section.
Signed-off-by: Vignesh R
---
drive
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.
Signed-off-by: Vignesh R
---
arch/arm/dts/dra7-evm.dts | 2 +-
arch/arm/dts/dra72-evm.dts | 2 +-
2 files
Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.
Signed-off-by: Vignesh R
---
include/configs/dra7xx_evm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.
Signed-off-by: Vignesh R
---
drivers/spi/ti_qspi.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index
From: Lokesh Vutla
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R
---
arch/arm/cpu/armv7/omap5/hw_data.c | 2 +-
1 file changed, 1
RA72 Rev B & C EVMs.
Lokesh Vutla (1):
ARM: dra7xx: Change DPLL_PER_HS13 divider value
Vignesh R (3):
spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
configs: dra7xx: Update QSPI speed to 76.8MHz
ARM: dts: dra7xx: Update spi-max-frequency for QSPI
arch/arm/cpu/armv7/omap5/h
uired.
Signed-off-by: Vignesh R
---
v2: no patch
drivers/spi/ti_qspi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 56ae29a3ee7c..fa7ee229878a 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -249,9 +249,6 @@ stati
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: Vignesh R
---
v2: no change
drivers/spi/ti_qspi.c | 4 ++--
1 file changed, 2
d with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: Vignesh R
---
v2: fix up debug print
drivers/spi/ti_qspi.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qsp
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: Vignesh R
---
drivers/spi/ti_qspi.c | 4 ++--
1 file changed, 2 insertions(+), 2
d with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: Vignesh R
---
drivers/spi/ti_qspi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 9a372ad31dae..376
On Saturday 09 July 2016 08:20 PM, Jagan Teki wrote:
> On 7 July 2016 at 04:49, Simon Glass wrote:
>> Hi,
>>
>> On 5 July 2016 at 22:28, Vignesh R wrote:
>>> This API helps to map physical register addresss pace of device to
>>> virtual address
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
arch/arm/dts/dra7-evm.dts | 6
K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
: Vignesh R
Tested-by: Marek Vasut
Acked-by: Marek Vasut
Reviewed-by: Jagan Teki
---
drivers/spi/cadence_qspi.c | 3 ++-
drivers/spi/cadence_qspi.h | 2 +-
drivers/spi/cadence_qspi_apb.c | 10 +-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi
AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R
Tested-by: Marek Vasut
Acked-by: Marek Vasut
Reviewed-by: Jagan Teki
Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also
enable Spansion flash support to access s25fl512s flash present on K2G
QSPI bus.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
configs/k2g_evm_defconfig | 2 ++
include/configs/k2g_evm.h | 6
.html
Rebased on top of v2016.07-rc3
Vignesh R (4):
spi: cadence_qspi_apb: Support 32 bit AHB address
spi: cadence_quadspi: Enable QUAD mode based on DT data
ARM: dts: K2G: Add support for QSPI controller
defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
arch/arm/dts/k2g
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Signed-off-by: Vignesh R
Reviewed-by: Simon Glass
Review
Enable SPI and SPI Flash driver model as K2G SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
configs/k2g_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 8efa58c8c43a
K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Enable SPI and SPI Flash driver model as K2L SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
configs/k2l_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2l_evm_defconfig b/configs
Enable SPI and SPI Flash driver model as K2E SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
configs/k2e_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2e_evm_defconfig b/configs
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
Enable SPI and SPI Flash driver model as K2HK SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
configs/k2hk_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2hk_evm_defconfig b/configs
Convert davinci_spi driver so that it complies with SPI DM framework.
Signed-off-by: Vignesh R
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
---
drivers/spi/davinci_spi.c | 329 +-
1 file changed, 240 insertions(+), 89 deletions(-)
diff --git a
Add aliases for SPI nodes in order for it to be probed by the DM
framework.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
arch/arm/dts/keystone.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
Since Keystone2 devices do not have support DM in SPL, do not define
DM_SPI and DM_SPI_FLASH for SPL build.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
---
include/configs/ti_armv7_keystone2.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs
This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R
Suggested-by: Simon Glass
Reviewed-by: Jagan Teki
Reviewed-by: Simon Glass
---
drivers/core/device.c | 11
This series converts davinci_spi driver to adapt to driver model
framework. And enables the driver on k2l, k2e, k2hk evms. Also,
added support for davinci_spi on k2g evm.
Tested on k2l, k2e, k2hk and k2g evms.
Resend:
Rebased on top of v2016.07-rc3
Vignesh R (12):
dm: core: implement
On Monday 04 July 2016 05:26 AM, Andre Przywara wrote:
> As printf calls may be executed quite early, we should avoid using any
> BSS stored variables, since some boards put BSS in DRAM, which may not
> have been initialised yet.
> Explicitly mark those "static global" variables as belonging to t
On Friday 17 June 2016 03:40 AM, Jagan Teki wrote:
> On Jun 16, 2016 4:12 PM, Vignesh R wrote:
>>
>>
>>
>> On Tuesday 24 May 2016 09:54 AM, Vignesh R wrote:
>>> Convert davinci_spi driver so that it complies with SPI DM framework.
>>>
>>&g
On Tuesday 24 May 2016 09:54 AM, Vignesh R wrote:
> Convert davinci_spi driver so that it complies with SPI DM framework.
>
> Signed-off-by: Vignesh R
> ---
>
> v6: Fix retval on dev_map_physmem() failure.
Gentle ping
>
> drivers
On Tuesday 10 May 2016 11:58 AM, Vignesh R wrote:
> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node. This will make sure that boards
> with multiple SPI/QSPI controllers can be probed at different
> bus frequenc
On 05/04/2016 04:49 PM, Vignesh R wrote:
>
> This series converts davinci_spi driver to adapt to driver model
> framework. And enables the driver on k2l, k2e, k2hk evms. Also,
> added support for davinci_spi on k2g evm.
>
> Tested on k2l, k2e, k2hk and k2g evms.
>
> Re
On 05/20/2016 06:32 PM, Tom Rini wrote:
> On Fri, May 20, 2016 at 04:11:22PM +0530, Vignesh R wrote:
>
>> According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
>> DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
>> MODE-3 is limited to
On 05/20/2016 08:54 PM, Simon Glass wrote:
> Hi Vignesh,
>
> On 19 May 2016 at 23:01, Vignesh R wrote:
>>
>> Convert davinci_spi driver so that it complies with SPI DM framework.
>>
>> Signed-off-by: Vignesh R
>> Reviewed-by: Tom Rini
>> ---
>
Convert davinci_spi driver so that it complies with SPI DM framework.
Signed-off-by: Vignesh R
---
v6: Fix retval on dev_map_physmem() failure.
drivers/spi/davinci_spi.c | 329 +-
1 file changed, 240 insertions(+), 89 deletions(-)
diff --git a
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R
---
arch/arm/dts/dra7-evm.dts | 6 ++
arch/arm/dts
Convert davinci_spi driver so that it complies with SPI DM framework.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v5: correct error message.
v4: Check error returned by dev_map_physmem().
v3: No changes
v2: Add comments to struct davinci_spi_slave members.
Use dev_map_physmem
Hi,
On 05/12/2016 06:14 PM, Martin Hejnfelt wrote:
> Hi,
>
> I am working with a board based off the am335x CPU and I am going to
> use SPI through u-boot. I've therefore been fiddling with u-boot and
> enabling spi0 through devicetree and all, which works fine (at least
> probing and so on). I a
Convert davinci_spi driver so that it complies with SPI DM framework.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v4: Check error returned by dev_map_physmem().
v3: No changes
v2: Add comments to struct davinci_spi_slave members.
Use dev_map_physmem() added by previous patch
On 05/15/2016 01:04 AM, Simon Glass wrote:
> Hi,
>
> On 4 May 2016 at 05:19, Vignesh R wrote:
>> This API helps to map physical register addresss pace of device to
>> virtual address space easily. Its just a wrapper around map_physmem()
>> with MAP_NOCACHE flag.
>
This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R
Suggested-by: Simon Glass
Reviewed-by: Jagan Teki
---
v5: Fix comments by Simon Glass
drivers/core
Hi,
On 05/09/2016 08:04 PM, Jagan Teki wrote:
> On 13 April 2016 at 16:22, Vignesh R wrote:
>>
>> This series adds support for Cadence QSPI controller present on K2G SoC.
>>
>> The first patch extends AHB address to 32 bit as K2G has 32 bit AHB
>> address. Secon
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Signed-off-by: Vignesh R
Reviewed-by: Simon Glass
Review
On 05/09/2016 08:15 PM, Jagan Teki wrote:
> On 13 April 2016 at 15:40, Vignesh R wrote:
>> In case of DT boot, don't read default speed and mode for SPI from
>> CONFIG_*, instead read from DT node. This will make sure that boards
>> with multiple SPI/QSPI controllers
On 05/06/2016 10:00 PM, Jagan Teki wrote:
> On 6 May 2016 at 21:16, R, Vignesh wrote:
>>
>>
>> On 5/6/2016 9:00 PM, Jagan Teki wrote:
>>> On 6 May 2016 at 09:28, Vignesh R wrote:
>>>> This API helps to map physical register addresss pace of device to
&
This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R
Suggested-by: Simon Glass
Reviewed-by: Jagan Teki
---
v4: Reorder include files to avoid build warning on
On 04/25/2016 04:29 PM, Vignesh R wrote:
>
>
> This series converts davinci_spi driver to adapt to driver model
> framework. And enables the driver on k2l, k2e, k2hk evms. Also,
> added support for davinci_spi on k2g evm.
>
> Tested on k2l, k2e, k2hk and k2g evms.
&
K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Enable SPI and SPI Flash driver model as K2L SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
configs/k2l_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 844dd57163f5
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
arch/arm/dts/k2l-e
Enable SPI and SPI Flash driver model as K2G SPI controller driver
supports driver model.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
configs/k2g_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index d0b45ce3f8a5
401 - 500 of 617 matches
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