Acked-by: vikas.mano...@st.com
Rgds,
Vikas
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [P
Thanks Jagan for this patch.
Acked-by: vikas.mano...@st.com
Rgds,
Vikas
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
&g
Thanks Wolfgang,
> -Original Message-
> From: Wolfgang Denk [mailto:w...@denx.de]
> Sent: Thursday, September 24, 2015 3:32 PM
> To: Jagan Teki
> Cc: Vikas MANOCHA; u-boot@lists.denx.de; ma...@denx.de; s...@denx.de;
> grmo...@opensource.altera.com
> Subject: Re: [
Thanks Wolfgang,
> -Original Message-
> From: Wolfgang Denk [mailto:w...@denx.de]
> Sent: Thursday, September 24, 2015 12:22 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
> jt...@openedev.com; ma...@denx.de
> Subject
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Wednesday, September 23, 2015 3:15 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; Stefan Roese; Graham Moore; Marek Vašut
> Subject: Re: [U-Boot] [PATCH v6 4/5] spi: cadence_qs
Thanks Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Wednesday, September 23, 2015 4:00 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; Stefan Roese; Graham Moore; Marek Vašut
> Subject: Re: [U-Boot] [PATCH v6 5/5] spi: cadence_qs
nsfer read/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat->triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: None.
Changes i
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: none
Changes in v6: none
Changes in v5: fixed typ
This macro is not being used anywhere in the code.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: new.
drivers/spi/cadence_qspi_apb.c |3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit m
Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: unused macro moved to separate patch.
Changes in v6: none
Changes in v5: none
Changes in v4: alligned to linux d
plat->ahbbase renamed to plat->flashbase for better clarity.
With ahbbase it was not clear which base address it is, flashbase makes
it clear that it is mapped flash memory base address.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v7: added info for renaming t
ded commit message in patch 1/4
Changes in v2:
- rebased to master.
- removed patch "spi: cadence_qspi: read can be independent of fifo width", it
was implemented in other patchset, in mainline now.
Vikas Manocha (6):
spi: cadence_qspi: move trigger base configuration in init
spi: cad
Reminder... let me know if there is any comment.
Rgds,
Vikas
> -Original Message-
> From: Vikas MANOCHA
> Sent: Friday, September 11, 2015 11:28 AM
> To: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
> jt...@openedev.com; ma...@denx.de
> Cc: Vikas
Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v6: none
Changes in v5: none
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v
nsfer read/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat->triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v6: fixed binding for trigg
plat->ahbbase renamed to plat->flashbase for better clarity.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v6: none
Changes in v5: none
Changes in v4: new
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v6: none
Changes in v5: fixed type cast compilation wa
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v6: None
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit message & rem
dependent of fifo width", it
was implemented in other patchset, in mainline now.
Vikas Manocha (5):
spi: cadence_qspi: move trigger base configuration in init
spi: cadence_qspi: fix indirect read/write start address
spi: cadence_qspi: fix base trigger address & transfer start address
s
Hi Marek,
> -Original Message-
> From: Vikas MANOCHA
> Sent: Thursday, August 27, 2015 9:03 AM
> To: Marek Vasut
> Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
> jt...@openedev.com
> Subject: RE: [PATCH v5 1/5] spi: cadence_qspi: move trigger
Hi,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, August 27, 2015 1:38 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH v5 2/5] spi: cadence_qspi: fix indirect read/write
Hi,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, August 27, 2015 1:40 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH v5 3/5] spi: cadence_qspi: fix base trigger
Hi,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, August 27, 2015 8:52 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH v5 1/5] spi: cadence_qspi: move trigger base
Hi,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, August 27, 2015 1:36 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH v5 1/5] spi: cadence_qspi: move trigger base
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: None.
Changes in v4:
- fifo-width trigger
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit message removed extra bracket.
Changes in v2
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: none
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts
plat-ahbbase renamed to plat-flashbase for better clarity.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: none
Changes in v4: new
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3
which were bypassing the sram level check.
- format string in patch corrected 3/4
- added commit message in patch 1/4
Changes in v2:
- rebased to master.
- removed patch spi: cadence_qspi: read can be independent of fifo width, it
was implemented in other patchset, in mainline now.
Vikas Manocha (5
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- fifo-width trigger address alligned to linux
plat-ahbbase renamed to plat-flashbase for better clarity.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3 files changed, 8 insertions(+), 8 deletions
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: removed extra type casts.
Changes in v3: added commit message removed extra bracket.
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: removed extra type casts.
Changes in v3: none
Changes in v2
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi
.
- format string in patch corrected 3/4
- added commit message in patch 1/4
Changes in v2:
- rebased to master.
- removed patch spi: cadence_qspi: read can be independent of fifo width, it
was implemented in other patchset, in mainline now.
Vikas Manocha (5):
spi: cadence_qspi: move trigger base
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: fix checkpatch CHECK message.
Changes in v3: added commit message removed extra bracket.
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c
plat-ahbbase renamed to plat-flashbase for better clarity.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: new
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3 files changed, 8
- added commit message in patch 1/4
Changes in v2:
- rebased to master.
- removed patch spi: cadence_qspi: read can be independent of fifo width, it
was implemented in other patchset, in mainline now.
Vikas Manocha (5):
spi: cadence_qspi: move trigger base configuration in init
spi
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: fixed CHECKPATCH CHECK message.
Changes in v3: none
Changes in v2
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- fifo-width trigger address alligned to linux
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: added commit message removed extra bracket.
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9 ++---
1 file changed, 2 insertions
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-ahbbase has been renamed to plat-flashbase for clarity.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
the sram level check.
- format string in patch corrected 3/4
- added commit message in patch 1/4
Changes in v2:
- rebased to master.
- removed patch spi: cadence_qspi: read can be independent of fifo width, it
was implemented in other patchset, in mainline now.
Vikas Manocha (4):
spi
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: none
Changes in v2: Rebased to master
drivers/spi
:
On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote:
Hi Marek,
Hi!
On 08/13/2015 09:42 AM, vikasm wrote:
Hi Marek,
On 08/12/2015 07:15 PM, Marek Vasut wrote:
On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote:
This patch is to separate the base trigger from the read/write
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
drivers/spi
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-ahbbase has been renamed to plat-flashbase for clarity.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
for synchronization. For example in case we are
getting SRAM fill level equal to 10 locations but in reality there were 2
another words completed and actual level is 12 but information may not be
synchronized yet because of the synchronization latency on APB domain.
Signed-off-by: Vikas Manocha
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..1ae7edf 100644
Changes in v2:
- rebased to master.
- removed patch spi: cadence_qspi: read can be independent of fifo width, it
was implemented in other patchset, in mainline now.
Vikas Manocha (6):
spi: cadence_qspi: move trigger base configuration in init
spi: cadence_qspi: remove sram polling from flash read
There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c | 61
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |6
Hi Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Monday, July 13, 2015 2:01 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi: cadence_qspi
Hi Stefan,
-Original Message-
From: Vikas MANOCHA
Sent: Wednesday, July 01, 2015 9:25 AM
To: 'Stefan Roese'
Cc: 'u-boot@lists.denx.de'; 'grmo...@opensource.altera.com';
'dingu...@opensource.altera.com'; 'jt...@openedev.com'
Subject: RE: [PATCH RESEND 0/7] spi: cadence_qspi
Vasut; Tom Rini; Albert
Aribaud; Vikas MANOCHA; Pavel Herrmann
Subject: [PATCH 11/20] dm: serial: Update binding for PL01x serial UART
This binding differs from that of Linux. Update it and change existing users.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/stv0991.dts
Hi Graham,
-Original Message-
From: Graham Moore [mailto:grmo...@opensource.altera.com]
Sent: Monday, July 06, 2015 10:57 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; dingu...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- Moved SPI configs in arch/arm/Kconfig
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/Kconfig
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2:
- removed checkpatch.pl error.
arch/arm
error.
Vikas Manocha (10):
stv0991: enable saving enrironment in spi flash
stv0991: move OF_CONTROL config to defconfig
stv0991: remove define CONFIG_OF_SEPARATE from board file
stv0991: configure clock pad muxing for qspi
stv0991: enable cadence qspi controller spi flash
stv0991
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v4: None
Changes in v3: Rebased to spi
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes
This patch adds the device tree binding doc for the cadence qspi controller
also removes the not needed properties from the stv0991 device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: removed changes done in socfpga dts/dtsi
Changes in v3: added new
arch/arm/dts
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- removed not needed properties from stv0991 device tree file for qspi
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/dts
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2: Fixed
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 -
include/configs/stv0991.h |4 +++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/configs
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
include/configs
Hi Graham,
-Original Message-
From: Graham Moore [mailto:grmo...@opensource.altera.com]
Sent: Tuesday, June 23, 2015 7:37 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; dingu...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
Hi Jagan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Thursday, July 02, 2015 3:12 AM
To: Vikas MANOCHA; Jagan Teki
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding
doc
Hi Vikas,
On 01.07.2015 00:57
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Thursday, July 02, 2015 10:49 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de
Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding
doc
On 2 July 2015 at 23:12
Hi Stefan,
-Original Message-
From: Vikas MANOCHA
Sent: Monday, June 22, 2015 4:31 PM
To: 'Stefan Roese'
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: RE: [PATCH RESEND 0/7] spi: cadence_qspi: optimize fix
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, June 29, 2015 11:29 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; Stefan Roese
Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding
doc
On 30 June 2015 at 02:19
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Sunday, June 28, 2015 3:57 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [v2 0/6] stv0991: enable cadence qspi controller spi
flash
On 25 June 2015 at 04:36, Vikas Manocha
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, June 29, 2015 11:15 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [v2 0/6] stv0991: enable cadence qspi controller spi
flash
On 29 June 2015 at 23:14, Vikas MANOCHA
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2:
- removed checkpatch.pl error.
arch/arm/cpu/armv7/stv0991
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 -
include/configs/stv0991.h |4 +++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/configs/stv0991_defconfig b/configs
two patchsets:
1. [v2 0/3] spi: cadence_qspi: sram depth from DT fix for FIFO width
2. [v2 0/6] stv0991: enable cadence qspi controller spi flash
Changes in v2:
- fix the checkpatch error.
Vikas Manocha (10):
stv0991: enable saving enrironment in spi flash
stv0991: move
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig b/configs
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
include/configs/stv0991.h |1 -
1
This patch adds the device tree binding doc for the cadence qspi controller
also removes the not needed properties from the device trees using this
controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: added new
arch/arm/dts/socfpga.dtsi|3
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: Fixed the checkpatch.pl error
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
include/configs/stv0991.h | 18 ++
1 file changed, 18
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/dts/stv0991.dts | 34 ++
1 file changed, 34 insertions
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v3: Rebased to spi-next-dev
Changes
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Wednesday, June 24, 2015 11:54 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; grmo...@opensource.altera.com
Subject: Re: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT
fix
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2:
- removed checkpatch.pl error.
arch/arm/cpu/armv7/stv0991/clock.c |4 +++-
arch
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Wednesday, June 24, 2015 12:00 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; tr...@konsulko.com
Subject: Re: [U-Boot] [PATCH 0/3] stv0991: spi env configs related board
changes
Please test
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h |1 -
1 file changed, 1 deletion(-)
diff --git
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
arch/arm/dts/stv0991.dts | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/stv0991.dts b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index f8ec5db..1d47178 100644
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index d8f51d8..fe5b2fe 100644
--- a/include/configs/stv0991.h
board changes
Changed in v2:
- remove checkpatch.pl error from patch stv0991: configure clock...
- clubbed two patchsets mentioned above.
Vikas Manocha (6):
stv0991: enable saving enrironment in spi flash
stv0991: move OF_CONTROL config to defconfig
stv0991: remove define CONFIG_OF_SEPARATE
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v2: Fixed the checkpatch.pl error
drivers/spi/cadence_qspi_apb.c | 46
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes
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