On 01/05/2018 05:02 AM, Clemens Gruber wrote:
>
> York: Should I send a v3 or a fixup patch ontop of v2.
I have reset my git head. Please send v3 patch.
York
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Tom,
Please abort this PR. More review comments came in last night.
(Somehow I sent to wrong address anyway.)
York
On 01/04/2018 05:19 PM, York Sun wrote:
> Tom,
>
> The following changes since commit ca833ca9579b29c5667ea2fa7a9d3f89f1599a94:
>
> Merge git://git.denx.de/
On 08/30/2017 01:53 AM, Sumit Garg wrote:
> < snip >
>
On 08/29/2017 12:02 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 8k size of
> u-boot-spl.bin image. Following is breif description of changes to
> reduce SPL size:
> 1. Changes in board
On 01/04/2018 01:57 PM, Fabio Estevam wrote:
> From: Clemens Gruber
>
> The blob_encap and blob_decap functions were not flushing the dcache
> before passing data to CAAM/DMA and not invalidating the dcache when
> getting data back.
> Therefore, blob encapsulation and decapsulation failed with er
Tom,
The following changes since commit ca833ca9579b29c5667ea2fa7a9d3f89f1599a94:
Merge git://git.denx.de/u-boot-rockchip (2018-01-03 12:27:12 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
for you to fetch changes up to 2080e50dd38723a50c84715b88c349
On 01/04/2018 09:15 AM, York Sun wrote:
> On 01/04/2018 01:39 AM, Fabio Estevam wrote:
>> Hi York,
>>
>> On Wed, Jan 3, 2018 at 3:26 PM, Tom Rini wrote:
>>> On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
>>>> Hi Tom,
>>>>
On 01/03/2018 06:13 AM, Tom Rini wrote:
> Add a CONFIG_SPL_BUILD guard around the code for the "mux" command so it
> is not included in SPL.
>
> Cc: Qiang Zhao
> Cc: York Sun
> Signed-off-by: Tom Rini
> ---
Reviewed-by: York Sun
___
On 01/04/2018 01:39 AM, Fabio Estevam wrote:
> Hi York,
>
> On Wed, Jan 3, 2018 at 3:26 PM, Tom Rini wrote:
>> On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
>>> Hi Tom,
>>>
>>> On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber
>>> wrote:
The blob_encap and blob_decap function
Either sending 'd' through UART, or save a variable ddr_interactive.
York
Sent from my iPhone
> On Dec 22, 2017, at 08:06, Tom Rini wrote:
>
>> On Fri, Dec 22, 2017 at 04:02:49PM +, York Sun wrote:
>>
>> If SPL is used, the full driver is in SPL. It
Fri, Dec 22, 2017 at 05:29:31AM +0000, York Sun wrote:
>>
>> Why not? I used it before.
>
> In SPL, rather than full U-Boot?
>
> --
> Tom
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er bits of code.
>
> Cc: York Sun
> Signed-off-by: Tom Rini
> ---
> drivers/ddr/fsl/main.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
> index d0a7b3f10763..b9f177f71d10 100644
> --- a/drivers/
On 12/07/2017 02:38 PM, York Sun wrote:
> Update README file to note LS2088A and LS1088A don't support booting
> from NAND flash.
>
> Signed-off-by: York Sun
> ---
>
Applied to fsl-qoriq master.
York
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On 12/12/2017 11:41 AM, York Sun wrote:
> Increase setup, assertion and hold time related to chip-select signal.
> Additional delay is needed for the signal to propogate through FPGA.
> This adjustment slightly increase the read and write cycle but has no
> impact on burst r
On 12/07/2017 02:38 PM, York Sun wrote:
> From: Yuan Yao
>
> Again the image size increases and the length needs to be adjusted.
>
> Signed-off-by: York Sun
> ---
>
Fixed author information.Applied to fsl-qoriq master.
York
__
On 12/07/2017 11:54 PM, Yangbo Lu wrote:
> Add LS1012ARDB RevC/RevC1/RevC2/RevD/RevE information and
> detect it when u-boot starts up.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v4:
> - Added this patch.
Applied to fsl-qoriq master. Thanks.
York
On 12/07/2017 11:54 PM, Yangbo Lu wrote:
> I2C reading for DIP switch setting is not reliable for LS1012ARDB
> RevD and later versions. This patch is to add hwconfig support to
> enable/disable eSDHC1 manually for these boards. Also drop 'status'
> fix-up for eSDHC0 and leave it as it is. It should
On 12/07/2017 11:54 PM, Yangbo Lu wrote:
> This patch is to clean up definitions for I2C IO expanders.
> The value 0x10 of __SW_BOOT_EMU is wrong. It should be 0x2.
> Fixed it in this patch.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v4:
> - Added this patch.
Applied to fsl-qoriq mas
On 12/06/2017 09:40 PM, Yogesh Gaur wrote:
> In fdt_fixup_board_enet() perform fdt fixup, fdt_status_okay, only when
> both MC is applied and DPL is deployed.
> Else returns failure, fdt_status_fail().
>
> This patch add this check for
> - LS2080A/LS2088A boards: in dir ls2080a, ls2080ardb and ls2
On 12/03/2017 08:37 PM, Wenbin song wrote:
> Check LS1043A/LS2080a by device ID without using personality ID to
> determine revision number. This check applies to all various
> personalities of the same SoC family.
>
> Signed-off-by: Wenbin Song
> ---
> Changes for V1:
> None.
> Cha
On 12/03/2017 08:37 PM, Wenbin song wrote:
> Using "cpu_pos_mask()" function to detect the real online cpus,
> and discard the needless cpu nodes on kernel dts.
>
> Signed-off-by: Wenbin Song
> ---
> Changes for v1:
> Remove the config option.
> Use id_to_core() funcat
On 11/30/2017 03:14 AM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by: Bhas
On 11/30/2017 03:14 AM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by: Bhas
On 11/26/2017 11:59 PM, Yangbo Lu wrote:
> The BRDCFG5[SPISDHC] register field of Qixis device is used
> to control SPI and SDHC signal routing.
>
> 10 = Force SDHC Mode
> - SPI_CS[0] is routed to CPLD for SDHC_VS use.
> - SPI_CS[1] is unused.
> - SPI_CS[2:3] are routed to the TDMRiser slot.
information
armv8: ls1012ardb: support hwconfig for eSDHC1 enabling
Yogesh Gaur (1):
board/ls2080a, ls1088a: Add check for mc-dpl applied in fdt
York Sun (3):
armv8: ls2080a: Increase load image len for NAND boot
armv8: ls2085a: Update README file for NAND boot
armv8
On 12/13/2017 09:49 PM, Ahmed Mansour wrote:
> This patch adds changes necessary to move functionality present in
> PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
>
> - Create new board/freescale/common/fsl_portals.c to house shared
> device tree fixups for DPAA1 devices w
On 12/13/2017 09:49 PM, Ahmed Mansour wrote:
> The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
> add device tree fixups that allow deep sleep in Linux. The define was
> placed in header files included by a number of boards, but was not
> explicitly documented in any of the Kconf
On 12/11/2017 03:02 PM, Ahmed Mansour wrote:
> The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
> add device tree fixups that allow deep sleep in Linux. The define was
> placed in header files included by a number of boards, but was not
> explicitly documented in any of the Kconf
On 12/11/2017 03:02 PM, Ahmed Mansour wrote:
> This patch adds changes necessary to move functionality present in
> PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
>
> - Create new board/freescale/common/fsl_portals.c to house shared
> device tree fixups for DPAA1 devices w
Increase setup, assertion and hold time related to chip-select signal.
Additional delay is needed for the signal to propogate through FPGA.
This adjustment slightly increase the read and write cycle but has no
impact on burst read or write.
Signed-off-by: York Sun
---
This patch supersedes http
gned-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Sending as it is
> Changes for v2: Sending as it is
>
Reviewed-by: York Sun
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;ethernet" node in device tree.
>
> Also, enable FDT_SEQ_MACADDR_FROM_ENV to fetch MAC address
> sequentially from environment variables
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Sending as it is
> Changes for v3:
Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Updated description and README
> Changes for v3: sending as it is
>
Reviewed-by: York Sun
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On 11/30/2017 03:14 AM, Rajesh Bhagat wrote:
> --- a/include/configs/ls1012ardb.h
> +++ b/include/configs/ls1012ardb.h
> @@ -60,6 +60,49 @@
> #define CONFIG_SYS_MEMTEST_START 0x8000
> #define CONFIG_SYS_MEMTEST_END 0x9fff
>
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#de
On 12/08/2017 04:46 PM, Ahmed Mansour wrote:
> This patch adds changes necessary to move functionality present in
> PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
>
> - Create new board/freescale/common/fsl_portals.c to house shared
> device tree fixups for DPAA1 devices w
On 12/04/2017 05:39 PM, Andy Tang wrote:
> Hi York,
>
> This patch is to adjust the OOB (out of bound) timing of sata port. It is
> totally hardware timing.
> I was asked to update those timing by hardware/validation team. They
> calculated those values from clock frequency. You can apply it saf
On 11/29/2017 07:02 PM, Wenbin Song wrote:
> Update IFC NOR timings to fix that the NOR flash can not
> be erased with V4 FPGA image on ls1046aqds.
>
> Signed-off-by: Wenbin Song
> ---
> include/configs/ls1046aqds.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/
On 11/29/2017 10:30 PM, Rajesh Bhagat wrote:
> Adds below voltage values supported by LS1088A Soc:
>
> 1.025 V(default), 0.9875V, 0.9750 V, 0.9V, 1.0 V, 1.0125 V, 1.0250 V
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v7:
On 11/29/2017 10:31 PM, Rajesh Bhagat wrote:
> Adds a VID specific API in init_sequence_f and spl code flow
> namely init_func_vid which is required to adjust core voltage.
>
> VID specific code is required in spl, hence moving flag CONFIG_VID
> out of spl flags.
>
> Signed-off-by: Ashish Kumar
On 11/29/2017 10:31 PM, Rajesh Bhagat wrote:
> Restructures common driver to support LTC3882 voltage regulator
> chip.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v7:
>
> None
>
> +stati
On 11/29/2017 10:31 PM, Rajesh Bhagat wrote:
> When VID feature is supported, check the contents of fuse register
> and configure DDR operate at 0.9v.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> board/freescale/ls1088a/ddr.c | 21 +
> 1 file change
On 11/29/2017 10:31 PM, Rajesh Bhagat wrote:
> This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems.
> It reads the fusesr register and changes the VDD accordingly by adjusting
> the voltage via LTC3882 regulator.
>
> This patch also takes care of the special case of 0.9V VDD i
On 11/29/2017 10:30 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v7:
York Sun (1):
powerpc: mpc85xx: Fix static TLB table for SDRAM
board/Arcturus/ucp1020/tlb.c | 2 +-
board/freescale/b4860qds/tlb.c | 2 +-
board/freescale/bsc9131rdb/tlb.c | 2 +-
board/freescale/bsc9132qds/tlb.c | 2 +-
board/freescale/c29xpcie/tlb.c | 4 ++--
board
On 12/06/2017 12:42 PM, York Sun wrote:
> Most predefined TLB tables don't have memory coherence bit set for
> SDRAM. This wasn't an issue before invalidate_dcache_range() function
> was enabled. Without the coherence bit, dcache invalidation doesn't
> automatically flu
On 11/26/2017 07:10 PM, Ran Wang wrote:
> This issue is exposed after commit 9000eddbae0d
> ("drivers/usb/ehci: Use platform-specific accessors"),
> the wrong endian way of EHCI controller programing will cause
> USB function down.
>
> Signed-off-by: Ran Wang
> ---
Applied to u-boot-mpc85xx mast
On 11/26/2017 07:10 PM, Ran Wang wrote:
> This issue is exposed after commit 9000eddbae0d
> ("drivers/usb/ehci: Use platform-specific accessors"),
> the wrong endian way of EHCI controller programing will cause
> USB function down.
>
> Signed-off-by: Ran Wang
> ---
Applied to u-boot-mpc85xx mas
On 11/27/2017 09:22 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> ---
Applied to fsl-qoriq master. Thanks.
York
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On 11/27/2017 08:41 PM, Yogesh Gaur wrote:
> For case when MC is loaded but DPL is not deployed perform MC
> object [DPBP, DPIO, DPNI and DPRC] cleanup.
>
> Signed-off-by: Yogesh Gaur
> ---
> drivers/net/fsl-mc/mc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied to fsl-qoriq
On 11/21/2017 07:32 PM, Udit Agarwal wrote:
> Adds config CONFIG_FSL_LS_PPA and CONFIG_FSL_CAAM in
> LS2080AQDS and LS2080ARDB secure boot defconfig.
>
> Removes CONFIG_FIT, as with CONFIG_FSL_LS_PPA enabled,
> CONFIG_FIT is selected.
>
> Removes CONFIG_SPL_RSA as in NOR boot SPL boot is not done
On 11/21/2017 09:09 PM, Vinitha Pillai-B57223 wrote:
> Add fall back option, to boot from NOR/QSPI/SD for LS1043, LS1046,
> LS1021 in case of distro boot failure.
>
> LS1046: Add kernel validation in case of secure boot in sd_bootcmd
> and qspi_bootcmd
> LS1043 and LS1021: Add kernel validation in
On 11/21/2017 07:32 PM, Udit Agarwal wrote:
> Add the secure boot defconfigs for QSPI boot on LS1088ARDB
> and LS1088AQDS platforms.
>
> Signed-off-by: Udit Agarwal
> Signed-off-by: Vinitha Pillai-B57223
> ---
> Changes in v4:
> Adds Distro boot support defconfigs.
> Adds config to unset CONFIG_
On 11/21/2017 07:31 PM, Udit Agarwal wrote:
> Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase
> using esbc_validate command.
>
> Enable validation of boot.scr script prior to its execution dependent
> on "secureboot" flag in environment
>
> Add header address for PPA to be
On 11/13/2017 08:25 PM, Bhaskar Upadhaya wrote:
> Kernel is now located at 0x100 instead of 0xa0
> and envirorment variables are located at 3MB offset instead of
> 2MB in Flash
>
> Signed-off-by: Bhaskar Upadhaya
> ---
> Changes for V3: Updated Commit message
>
Applied to fsl-qoriq mast
On 11/13/2017 12:33 AM, Ran Wang wrote:
> This is suplement for patch which handle below errata:
> A-009007, A-009008, A-008997, A-009798
>
> Signed-off-by: Ran Wang
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27
On 11/09/2017 10:03 PM, Prabhakar Kushwaha wrote:
> Instruction prefetch feature is by default enabled during core
> release.
>
> This patch add support of disabling instruction prefetch by setting
> core mask in PPA. Here each core mask bit represents a core and
> prefetch is disabled at the time
On 11/08/2017 09:44 PM, Ashish Kumar wrote:
> IFC-NOR and QSPI-NOR signals are muxed on SoC to save pins
>
> Add fsl_fdt_fixup_flash() to disable IFC-NOR node in dts
> if QSPI is enabled and vice-versa
>
> Signed-off-by: Ashish Kumar
> ---
> board/freescale/ls1088a/ls1088a.c | 29 ++
On 11/14/2017 10:29 PM, Yogesh Gaur wrote:
> Existing MC driver framework is based on MC-9.x.x flib.
> This patch migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest
> MC flib which is MC-10.3.0.
>
> Changes introduced due to migration:
> 1. To get OBJ token, pair of create and open API re
On 11/23/2017 01:03 AM, Ashish Kumar wrote:
> Unset USE_BOOTCOMMAND for all ls1088 defconfig files to fix
> redefinition error
>
> USE_BOOTCOMMAND was introduced in commit-id b6251db8c3f
> ("Kconfig: Introduce USE_BOOTCOMMAND and migrate BOOTCOMMAND").
>
> Signed-off-by: Ashish Kumar
> ---
> co
On 12/07/2017 02:53 PM, Ahmed Mansour wrote:
> This patch adds changes necessary to move functionality present in
> PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
>
> - Created new board/freescale/common/portals.c to house shared device
> tree fixups for DPAA1 devices with
Tom,
The following changes since commit 9da7fb4a39149c3061cb148bfbaa76b4b52b9008:
Prepare v2018.01-rc1 (2017-12-04 18:27:17 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
d798a6ee6436c7d2bcbf3fa6bda01daa4411a493
for you to fetch changes up to d798a6ee
Update README file to note LS2088A and LS1088A don't support booting
from NAND flash.
Signed-off-by: York Sun
---
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsc
From: Yuan Yao
Again the image size increases and the length needs to be adjusted.
Signed-off-by: York Sun
---
include/configs/ls2080a_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index
On 11/17/2017 08:07 AM, Tom Rini wrote:
> On Fri, Nov 03, 2017 at 10:10:27AM +0800, Kever Yang wrote:
>
>> We need to update gd in assamble code after relocate,
>> this is a fix to:
>> adc421e arm: move gd handling outside of C code
>>
>> Signed-off-by: Kever Yang
>> Reviewed-by: Philipp Tomsich
Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18
without checking the return value of spl_relocate_stack_gd().
Signed-off-by: York Sun
CC: Kever Yang
CC: Philipp Tomsich
---
arch/arm/lib/crt0_64.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --
On 12/07/2017 12:10 AM, Y.b. Lu wrote:
>
>>
>>> printf("Error reading i2c boot information!\n");
>>> - return 0; /* Don't want to hang() on this error */
>>> + return 0;
>>
>> What does I2C failure mean here? Returning 0 will cause the code keep going
>> in
>> f
ic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.
Signed-off-by: York Sun
---
board/Arcturus/ucp1020/tlb.c | 2 +-
board/freescale/b4860qds/tlb.c | 2 +-
board/freescale/bsc9131rdb/tlb.c | 2 +-
On 12/06/2017 02:19 AM, Yangbo Lu wrote:
> For LS1012ARDB RevD and later versions, the I2C reading for DIP
> switch setting had been no longer reliable since the board was
> reworked. This patch is to add hwconfig support to enable/disable
I think this message is not accurate. How about saying "I2
On 12/05/2017 12:50 PM, Joe Hershberger wrote:
> On Wed, Nov 22, 2017 at 7:17 PM, Calvin Johnson
> wrote:
>> Hi York,
>>
>>> -Original Message-
>>> From: York Sun
>>> Sent: Thursday, November 23, 2017 12:00 AM
>>> To: Calvin Johnso
On 12/05/2017 08:38 AM, York Sun wrote:
> On 12/04/2017 04:31 PM, Masahiro Yamada wrote:
>>> Err: serial
>>> Net:
>>> MMC read: dev # 0, block # 2080, count 128 ...
>>> Fman1: Data at 7faf67d0 is not a firmware
>>> e1000#0: Out of Memory!
&
On 12/04/2017 04:31 PM, Masahiro Yamada wrote:
>> Err: serial
>> Net:
>> MMC read: dev # 0, block # 2080, count 128 ...
>> Fman1: Data at 7faf67d0 is not a firmware
>> e1000#0: Out of Memory!
>
>
> Looks like malloc() failed.
>
>
>> No ethernet found.
>> Hit any key to stop autoboot: 0
>> (Y
ng Fan
> Reviewed-by: Simon Glass
> Reviewed-by: Tomas Melin
> Cc: Pantelis Antoniou
> Cc: "Andrew F. Davis"
> Cc: Igor Grinberg
> Cc: "tomas.me...@vaisala.com"
> Cc: Kever Yang
> Cc: Andre Przywara
> Cc: York Sun
> Cc: Lokesh Vutla
> C
> On Dec 4, 2017, at 21:02, Peng Fan wrote:
>
>> On Tue, Nov 28, 2017 at 05:14:58PM +0000, York Sun wrote:
>>> On 11/27/2017 07:20 PM, Peng Fan wrote:
>>> For external data, FIT has a optional property "data-position" which
>>> can set the
On 12/04/2017 04:31 PM, Masahiro Yamada wrote:
> 2017-12-05 7:37 GMT+09:00 York Sun :
>> On 11/21/2017 09:47 AM, Masahiro Yamada wrote:
>>> From: Boris Brezillon
>>>
>>> The NAND framework provides several helpers to query timing modes supported
>>> b
On 11/21/2017 09:47 AM, Masahiro Yamada wrote:
> From: Boris Brezillon
>
> The NAND framework provides several helpers to query timing modes supported
> by a NAND chip, but this implies that all NAND controller drivers have
> to implement the same timings selection dance. Also currently NAND
> de
t 02907004294d9
Freescape/NXP has multiple configuration for each board, and sometimes
multiple boards for each SoC. I am not objecting "imply PANIC_HANG" for
all of them.
Reviewed-by: York Sun
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On 12/04/2017 01:31 AM, Yuantian Tang wrote:
> These PP2C and PP3C registers control the configuration of the PHY
> control OOB timing for the COMINIT/COMWAKE parameters respectively
> for sata port. Overwrite default values with calculated ones to get
> better OOB timing.
>
> Signed-off-by: Tang
The subject can be change to
armv8: ls1043a: check SoC by device ID
On 11/30/2017 10:55 PM, Wenbin song wrote:
> There are many variants for ls1043a. Modify the detecting way to
> make that the below fixup apply to all variants of ls1043a.
> - Fix GIC offset for rev1.1
> - Fix msi nod
On 11/29/2017 08:44 PM, Y.b. Lu wrote:
> Hi York,
>
> I copied hardware team Kinjalk's explain here.
>
> "Enabling SDHC2 on ‘00’ is not correct on revision D and later boards as the
> sd wifi is not on there on these revs.
> The IO expander was designed to override the dip switch values. So, the
On 11/29/2017 09:45 PM, Ashish Kumar wrote:
> Hello Joe, York,
>
>
> Any comments on V2 series?
>
Ashish,
I can't see if this set is correct. Did you look into the similar
PHY-less situation for Power-based platform? We don't have PHY-less
SGMII support there. I was hoping you can add the same
On 11/29/2017 07:16 PM, Wenbin song wrote:
> Using "cpu_pos_mask()" function to detect the real online cpus,
> and discard the needless cpu nodes on kernel dft.
>
> Signed-off-by: Wenbin Song
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4
> arch/arm/cpu/armv8/fsl-layerscape/fdt.c
On 11/27/2017 12:58 AM, Yangbo Lu wrote:
> For LS1012ARDB RevD and later versions, the I2C reading for DIP
> switch setting had been no longer reliable since the board was
> reworked. This patch is to add hwconfig support to enable/disable
> eSDHC1 manually.
What do you mean "no longer reliable"?
On 11/26/2017 11:59 PM, Yangbo Lu wrote:
> The BRDCFG5[SPISDHC] register field of Qixis device is used
> to control SPI and SDHC signal routing.
>
> 10 = Force SDHC Mode
> - SPI_CS[0] is routed to CPLD for SDHC_VS use.
> - SPI_CS[1] is unused.
> - SPI_CS[2:3] are routed to the TDMRiser slot.
On 11/23/2017 03:22 AM, Prabhakar Kushwaha wrote:
> The MAC addresses get fixed in the device tree for "ethernet" nodes
> is by using trailing number behind "ethernet" found in "/aliases".
> It may not be necessary for the "ethernet" nodes to be sequential.
> There can be gaps in between or any eth
On 11/08/2017 10:45 PM, Xiaowei Bao wrote:
>
> Hi York,
>
> For the general pcie devices, it will not bring delay, because the RC access
> these
> devices can get the link up state correctly, usually, if the slot have the
> device,
> return the L0 state, if the slot have not device, return DET
On 05/15/2017 09:16 AM, york sun wrote:
> From: Ruchika Gupta
>
> Make secure boot validation available without using command.
>
> Signed-off-by: Ruchika Gupta
> Signed-off-by: York Sun
> ---
Due to SPL image size increase, secure boot feature cannot be enabled
toge
On 10/05/2017 12:55 AM, Sumit Garg wrote:
>
> I will wait for SD boot patches to be accepted in upstream. As reducing SPL
> size
> for ls1088ardb in upstream does only makes sense once we have base platform
> support merged in upstream.
>
Please rework this patch set.
York
__
(3 << 0)
> #define PTE_TYPE_BLOCK (1 << 0)
> #define PTE_TYPE_VALID (1 << 0)
>
>
This looks familiar. We are lucky not hitting this issue earlier.
Reviewed-by: York Sun
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Peng Fan
> Cc: Simon Glass
> Cc: Pantelis Antoniou
> Cc: "Andrew F. Davis"
> Cc: Igor Grinberg
> Cc: "tomas.me...@vaisala.com"
> Cc: Kever Yang
> Cc: Andre Przywara
> Cc: York Sun
> Cc: Lokesh Vutla
> Cc: "Cooper Jr., Franklin"
On 11/21/2017 10:26 PM, Calvin Johnson wrote:
> This patch series fixes bug which fails tftp sometimes
> while using the pfe interfaces and also has some code clean up.
>
>
> Calvin Johnson (3):
> drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet
> processing
> drivers: net:
On 11/22/2017 03:52 AM, Prabhakar Kushwaha wrote:
>
>> -Original Message-
>> From: York Sun
>> Sent: Tuesday, November 21, 2017 10:52 PM
>> To: Prabhakar Kushwaha ; u-
>> b...@lists.denx.de
>> Subject: Re: [PATCH 1/3] common: Fix-up MAC addr in d
On 11/21/2017 10:40 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 18:35 +0000, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is sa
On 11/21/2017 10:20 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 18:04 +0000, York Sun wrote:
>>
>>
>> On 11/21/2017 09:52 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-11-21 at 17:45 +, York Sun wrote:
>>>>
>>>> On 11/21/2017 09:41 A
On 11/21/2017 09:52 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 17:45 +0000, York Sun wrote:
>>
>> On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
>>>> CAUTION: This email originated from outside of
On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 17:32 +0000, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is sa
On 11/21/2017 09:29 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 17:23 +0000, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is sa
On 11/21/2017 09:18 AM, Joakim Tjernlund wrote:
> On Tue, 2017-09-12 at 19:56 +0200, Joakim Tjernlund wrote:
>> Most FSL PCIe controllers expects 333 MHz PCI reference clock.
>> This clock is derived from the CCB but in many cases the ref.
>> clock is not 333 MHz and a divisor needs to be configure
On 11/21/2017 08:26 AM, Prabhakar Kushwaha wrote:
> Current implementation of MAC address fix-up of device tree uses
> tailing number behind "ethernet" found in "/aliases". It is not
> necessary for trailing number of “ethernet” to be sequential. There
> can be hole in between or any node disabled
On 11/21/2017 08:26 AM, Prabhakar Kushwaha wrote:
> Current implementation of MAC address fix-up of device tree uses
> tailing number behind "ethernet" found in "/aliases". It is not
> necessary for trailing number of “ethernet” to be sequential. There
> can be hole in between or any node disabled
On 11/18/2017 11:09 AM, York Sun wrote:
> Commit 72443c7f7d21 ("mtd: cfi: Add support for status register
> polling") added a feature check to determine if status register
> is available for certain flash chips. The "lower software bits"
> register used to determ
On 11/19/2017 10:47 PM, Vinitha Pillai-B57223 wrote:
> Add nor/sd/qspi fall back option for LS1043, LS1046, LS1021
Looks like you are adding a falling option to boot from NOR/SD/QSPI in
case of distro boot failure. Please rephrase your commit message. It
doesn't cover what you are doing.
>
> Sig
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