CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_OF_LIBFDT=y
Because environment variables are not avaiable during SPL stage for
SD boot, set "boot_os=y" as default.
Signed-off-by: York Sun
Reviewed-by: Simon Glass
---
Changes in v3:
Drop defconfig change
Not to enable falcon boot
gd->ram_size is reduced in this function to reserve secure memory.
Avoid running this function again to further reduce memory size.
This fixes issue for SPL boot with PPA image loaded in which case
secure memory is incorrectly allocated due to repeated calling.
Signed-off-by: York Sun
Revie
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.
Signed-off-by: York Sun
---
Changes in v3:
Minor cosmetic fix.
Changes in v2:
Drop checking secure boot in this patch after rebasing to latest mater.
Recent change in SPL
board info assignment is much earlier than proposed
board_init_r(). Create a new function to fill gd->bd and call this
function when needed.
Signed-off-by: York Sun
CC: Lokesh Vutla
CC: Ravi Babu
CC: Lukasz Majewski
CC: Tom Rini
---
Changes in v3:
Create new function to fill gd->bd for spl
CONFIG_CMD_SPL_WRITE_SIZE is used for writing parameters to non-volatile
storage. So far it is only used for NAND. Fix compiling error when this
macro is not used for SD.
Signed-off-by: York Sun
CC: Anatolij Gustschin
---
Changes in v3: None
Changes in v2:
New patch to fix compiling error
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
> Signed-off-by: Yangbo Lu
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 09/14/2017 07:09 PM, Yangbo Lu wrote:
> Current u-boot disables IFC support for SD boot on all ls1043a
> boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
> Only when QSPI is used, IFC should be disabled. Otherwise,
> the u-boot with ls1043aqds_sdcard_ifc_defconfig would not wor
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
> Signed-off-by: Yangbo Lu
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 09/14/2017 09:49 PM, Priyanka Jain wrote:
> As per current implementation, default value of board env is
> based on board filename i.e ls2080ardb.
>
> With distro support changes, this env is used to decide upon
> kernel dtb which is different for other SoCs (ls2088a, ls2081a)
> combination sup
On 08/29/2017 02:50 AM, Priyanka Jain wrote:
> For most of ls2080ardb use-cases, mc private DRAM block is required
> to be of 1.75GB.
> Henc set mcmemsize=0x7000 in default env
>
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl-qoriq mater. Thanks.
York
On 09/04/2017 03:15 AM, Sriram Dash wrote:
> I2C code is put under CONFIG_SYS_I2C
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 09/04/2017 03:14 AM, Sriram Dash wrote:
> IFC code is put under CONFIG_FSL_IFC
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
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On 08/31/2017 12:59 AM, Bharat Bhushan wrote:
> "pci: layerscape: Fixup device tree node for ls2088a" added
> support for LS208xA devices but fixing iommu-map property
> is missing. This patch adds support for fixing iommu-map.
>
> Signed-off-by: Bharat Bhushan
> Signed-off-by: Ioana Ciornei
> -
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> As per updated board design, different QSPI flash
> is connected on boards, hence change QSPI flash type
> from Micron n25q512a device to spansion s25fs512s
> device in dts and config.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Yogesh Ga
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
> the prints of boardinfo late in cycle during uboot boot.
> This feature is not required in case of QSPI_BOOT.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
> It is not necessary for every SoC to have 2 SATA controller.
> So put SATA1, SATA2 code under respective defines.
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
On 09/14/2017 12:53 PM, York Sun wrote:
> Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
> to CONFIG_LS102XA.
>
> Signed-off-by: York Sun
> ---
Applied to fsl-qoriq mater.
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U-Boo
d hooks to fsl-layerscape to enable falcon
>> boot.
>
> I'm trying to do the same on imx6q board (armv7).
>
>>
>> Signed-off-by: York Sun
>>
>> ---
>>
>> Changes in v2:
>> Relace getenv_f() with env_g
loading during SPL stage for SD boot
armv8: ls1046ardb: disable PPA loading during SPL stage for SD boot
York Sun (1):
armv7: ls1021a: Fix marco CONFIG_LS102XA
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 8 +++-
arch/arm/dts/fsl-ls2081a-rdb.dts | 4
On 09/15/2017 08:21 AM, York Sun wrote:
> common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
> from incompatible pointer type [-Wincompatible-pointer-types]
> src, &length))
>
> Signed-off-by: York Sun
> Reported-by: Heinrich Schuchardt
>
On 09/18/2017 08:47 AM, York Sun wrote:
> On 09/17/2017 10:55 AM, Simon Glass wrote:
>> Hi York,
>>
>> On 14 September 2017 at 13:01, York Sun wrote:
>>> This partially reverts commit 15eb1d43bf470b85e9031c2fce7e0ce7b27dd321
>>> which intended to move
On 09/18/2017 06:56 PM, Y.b. Lu wrote:
> Hi York,
>
> Yes. We got below crash on ls1046ardb if we write ppa to SD card.
>
> => cpld reset sd
> U-Boot SPL 2017.07-g25cd705 (Sep 15 2017 - 03:27:02)
> Initializing DDRusing SPD
> WARNING: Calling __hwconfig without a buffer and before environment
On 09/17/2017 10:55 AM, Simon Glass wrote:
> Hi York,
>
> On 14 September 2017 at 13:01, York Sun wrote:
>> This partially reverts commit 15eb1d43bf470b85e9031c2fce7e0ce7b27dd321
>> which intended to move assignment of board info earlier, into
>> board_
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
Once PPA is loaded during SPL boot, RAM version U-Boot won't load it
again. It is used for falcon boot. Does it hurt anything?
York
__
common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
src, &length))
Signed-off-by: York Sun
Reported-by: Heinrich Schuchardt
CC: Jean-Jacques Hiblot
---
Change log
v2: Update length after gunzip
common
On 09/15/2017 08:10 AM, Jean-Jacques Hiblot wrote:
> Hi York,
>
>
> On 14/09/2017 21:41, York Sun wrote:
>> common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
>> from incompatible pointer type [-Wincompatible-pointer-types]
>> src, &
On 09/15/2017 07:52 AM, Jean-Jacques Hiblot wrote:
> Hi Tom, York
>
>
> On 15/09/2017 14:53, Tom Rini wrote:
>> On Fri, Sep 15, 2017 at 09:46:29AM +0200, Jean-Jacques Hiblot wrote:
>>
>>> Warning introduced in commit 7264f29 (spl: fit: Eanble GZIP support for
>>> image decompression)
>>>
>>> Sign
On 08/30/2017 03:43 AM, Shengzhou Liu wrote:
> Signed-off-by: Shengzhou Liu
> ---
> include/configs/ls1043a_common.h | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/ls1043a_common.h
> b/include/configs/ls1043a_common.h
> index f064d5c24a..9
On 09/12/2017 11:03 PM, Yangbo Lu wrote:
> SD boot couldn't work with ls1043aqds_sdcard_ifc_defconfig since
> IFC in SPL is disabled. This patch is to fix this issue.
You subject matches the change. But the commit message is confusing.
Please rephrase it.
York
>
> Signed-off-by: Yangbo Lu
> -
On 09/12/2017 10:56 AM, Joakim Tjernlund wrote:
> Most FSL PCIe controllers expects 333 MHz PCI reference clock.
> This clock is derived from the CCB but in many cases the ref.
> clock is not 333 MHz and a divisor needs to be configured.
>
> This adds PEX_CCB_DIV #define which can be defined for e
On 09/05/2017 10:42 PM, Priyanka Jain wrote:
> As per current implementation, default value of board env is
> based on board filename i.e ls2080ardb.
>
> With distro support changes, this env is used to decide upon
> kernel dtb which is different for other SoCs (ls2088a, ls2081a)
> combination sup
On 09/04/2017 03:14 AM, Sriram Dash wrote:
> Remove dependency of SYS_HAS_SERDES for Layerscape Chasis 3.
>
> Signed-off-by: Sriram Dash
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++--
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 ++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c
You have a lot of magic numbers and delays. See inline comments.
On 09/03/2017 11:24 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
On 08/29/2017 02:50 AM, Priyanka Jain wrote:
> For most of ls2080ardb use-cases, mc private DRAM block is required
> to be of 1.75GB.
> Henc set mcmemsize=0x7000 in default env
>
> Signed-off-by: Priyanka Jain
> ---
> include/configs/ls2080ardb.h |1 +
> 1 files changed, 1 insertions(
On 08/29/2017 12:01 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 4k
> size of u-boot-spl.bin image. Following is breif description of
> changes to reduce SPL size:
> 1. Compile-off mp.c and libfdt.c in case of SPL build.
> 2. Keep MMU and DCACHE specific variabl
On 08/28/2017 04:26 AM, Udit Agarwal wrote:
> Add config CONFIG_FSL_LS_PPA and CONFIG_FSL_CAAM in
> LS2080AQDS and LS2080ARDB secure boot defconfig.
You also change other things. Please explain.
>
> Signed-off-by: Udit Agarwal
> ---
> configs/ls2080aqds_SECURE_BOOT_defconfig | 5 +++--
> con
On 08/25/2017 02:03 AM, Udit Agarwal wrote:
> Add the secure boot defconfigs for QSPI boot on LS1088ARDB
> and LS1088AQDS platforms.
>
> Signed-off-by: Udit Agarwal
> ---
> configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 32
> +++
> configs/ls1088ardb_qspi_SECURE_BOOT_
On 08/25/2017 02:03 AM, Udit Agarwal wrote:
> Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase
> using esbc_validate command. Add images validation in default environment
> under mcinitcmd prior to MC initialization.
>
> Add header address for PPA to be validated during ESBC
The subject doesn't represent your change. Please revise.
On 08/22/2017 03:47 AM, ying.zhang22...@nxp.com wrote:
> From: Zhang Ying-22455
>
> The SP805-WDT module on LS1088A requires configuration of PMU's
> PCTBENR register to enable watchdog counter decrement and reset
> signal generation. The
On 08/18/2017 03:21 AM, Prabhakar Kushwaha wrote:
>
>> -Original Message-
>> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Santan
>> Kumar
>> Sent: Friday, August 18, 2017 3:21 PM
>> To: u-boot@lists.denx.de; York Sun
>> Cc: Priya
On 08/15/2017 11:32 PM, Xiaowei Bao wrote:
> Hi York,
>
> Yes, it is my mean, I am not brief enough to express, thank you correct me.
Xiaowei,
Please update his patch as discussed.
York
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On 05/17/2017 05:05 AM, yinbo.zhu wrote:
> From: Rajat Srivastava
>
> Adds helper functions to enable snooping and outstanding burst beat
> settings.
>
> Signed-off-by: Rajat Srivastava
> Signed-off-by: Rajesh Bhagat
> ---
Please re-submit this set. Some of them are accepted as separated patc
On 09/14/2017 12:54 PM, York Sun wrote:
> On 07/27/2017 03:05 AM, yinbo@nxp.com wrote:
>> From: Rajesh Bhagat
>>
>> +#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
>
> Please use CONFIG_ARCH_LS1021A, not CONFIG_LS102XA.
>
Never mind. This is
On 07/27/2017 03:05 AM, yinbo@nxp.com wrote:
> From: Rajesh Bhagat
>
> Add USB EHCI support for ls1012aqds platform
>
> Signed-off-by: Rajat Srivastava
> Signed-off-by: Rajesh Bhagat
> Signed-off-by: yinbo.zhu
> ---
> arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
> incl
Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
to CONFIG_LS102XA.
Signed-off-by: York Sun
---
include/usb/ehci-ci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index cd3eb47..59bfc14 100644
--- a
common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
src, &length))
Signed-off-by: York Sun
Reported-by: Heinrich Schuchardt
---
common/spl/spl_fit.c | 4 +++-
1 file changed, 3 insertions(+), 1 dele
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
Signed-off-by: York Sun
---
Changes in v2:
Relace getenv_f() with env_get_f() after rebasing to latet master.
.../arm/cpu/armv8/fsl-laye
Update defconfig to enable falcon boot, add needed macros to board
header file. Because environment variables are not avaiable during
SPL stage for SD boot, set "boot_os=y" as default.
Signed-off-by: York Sun
---
Changes in v2: None
configs/ls1043ardb_sdcard_defconfig | 6 +
CONFIG_SPL_BOARD_INIT is used for SPL boot. Enable it in defconfig
for LS1043ARDB SPL targets.
Signed-off-by: York Sun
---
Changes in v2: None
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_nand_defconfig | 1 +
configs
ix gd->ram_size error after rebasing to latest mater.
Drop checking secure boot in this patch after rebasing to latest mater.
Recent change in SPL makes the image size bigger.
Relace getenv_f() with env_get_f() after rebasing to latet master.
York Sun (7):
spl: fix assignment of board info t
gd->ram_size is reduced in this function to reserve secure memory.
Avoid running this function again to further reduce memory size.
This fixes issue for SPL boot with PPA image loaded in which case
secure memory is incorrectly allocated due to repeated calling.
Signed-off-by: York
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.
Signed-off-by: York Sun
---
Changes in v2:
Drop checking secure boot in this patch after rebasing to latest mater.
Recent change in SPL makes the image size bigger.
board
assignment is much earlier than board_init_r().
Moving such assignment to board_init_r() would be moving it later.
Signed-off-by: York Sun
CC: Lokesh Vutla
CC: Ravi Babu
CC: Lukasz Majewski
CC: Tom Rini
---
Changes in v2:
New patch to fix spl after rebasing to latest master.
common/spl/spl.c | 8
CONFIG_CMD_SPL_WRITE_SIZE is used for writing parameters to non-volatile
storage. So far it is only used for NAND. Fix compiling error when this
macro is not used for SD.
Signed-off-by: York Sun
CC: Anatolij Gustschin
---
Changes in v2:
New patch to fix compiling error after rebasing to
On 09/13/2017 03:11 PM, Dr. Philipp Tomsich wrote:
> York,
>
>> On 13 Sep 2017, at 23:24, York Sun wrote:
>>
>> On 09/13/2017 02:21 PM, Dr. Philipp Tomsich wrote:
>>> York,
>>>
>>>> On 13 Sep 2017, at 23:16, York Sun wrote:
>>>
On 09/13/2017 09:27 PM, Heinrich Schuchardt wrote:
> On 09/13/2017 11:07 PM, York Sun wrote:
>> On 09/13/2017 01:38 PM, Heinrich Schuchardt wrote:
>>> On 08/08/2017 01:16 AM, York Sun wrote:
>>>> Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
On 09/13/2017 02:21 PM, Dr. Philipp Tomsich wrote:
> York,
>
>> On 13 Sep 2017, at 23:16, York Sun wrote:
>>
>> On 09/13/2017 12:30 PM, Philipp Tomsich wrote:
>>> To better support bootin through an ATF or OPTEE, we need to
>>> streamline some of th
On 09/13/2017 12:30 PM, Philipp Tomsich wrote:
> To better support bootin through an ATF or OPTEE, we need to
> streamline some of the logic for when the FDT is appended to an image:
> depending on the image type, we'd like to append the FDT not at all
> (the case for the OS boot), to the 'firmware
On 09/13/2017 01:38 PM, Heinrich Schuchardt wrote:
> On 08/08/2017 01:16 AM, York Sun wrote:
>> Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
>> SPL boot, eg. falcon boot compressed kernel image.
>>
>> Signed-off-by: York Sun
>> Reviewed-b
On 09/03/2017 08:05 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The pcie config space of ls1088a is different from ls2080a.
>
> Signed-off-by: Hou Zhiqiang
> ---
Applied to fsl-qoriq master. Thanks.
York
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On 09/04/2017 04:04 AM, Ran Wang wrote:
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXREFTUNE value to 0x9 is observed, change
> set the same value.
>
> Signed-off-by:
On 09/04/2017 04:04 AM, Ran Wang wrote:
> Rx Compliance tests may fail intermittently at high
> jitter frequencies using default register values.
>
> Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
> to make the Rx compliance test pass.
>
> Signed-off-by: Sriram Dash
> Signed-off-by:
On 09/04/2017 04:04 AM, Ran Wang wrote:
> The default setting for USB High Speed Squelch Threshold results
> in a threshold close to or lower than 100mV. This leads to Receiver
> Compliance test failure for a 100mV threshold.
>
> Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
>
On 09/04/2017 04:04 AM, Ran Wang wrote:
> The default setting for USB High Speed Squelch Threshold results
> in a threshold close to or lower than 100mV. This leads to Receive
> Compliance test failure for a 100mV threshold.
>
> Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
>
On 09/04/2017 04:04 AM, Ran Wang wrote:
> Rx Compliance tests may fail intermittently at high
> jitter frequencies using default register values
>
> Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
> to make the Rx compliance test pass.
>
> Signed-off-by: Sriram Dash
> Signed-off-by: R
On 09/04/2017 04:04 AM, Ran Wang wrote:
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXREFTUNE value to 0x9 is observed, change
> set the same value.
>
> Signed-off-by:
On 09/04/2017 04:04 AM, Ran Wang wrote:
> Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
> Output Voltage Test Compliance fails using default transmitter settings
>
> Change config of transmitter signal swings by setting register
> PCSTXSWINGFULL to 0x47 to pass compliance tests
On 09/04/2017 04:04 AM, Ran Wang wrote:
> Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
> Output Voltage Test Compliance fails using default transmitter
> settings
>
> Change config of transmitter signal swings by setting register
> PCSTXSWINGFULL to 0x47 to pass compliance test
On 08/31/2017 04:07 AM, Ashish Kumar wrote:
> This patch adds support for RGMII protocol
>
> NXP's LDPAA2 support RGMII protocol. LS1088A is the
> first Soc supporting both RGMII and SGMII.
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Amrita Kumari
> Signed-off-by: Ashish Kumar
> ---
On 09/03/2017 08:05 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Enabled PCIe support and PCI command feature.
>
> Signed-off-by: Hou Zhiqiang
> ---
Applied to fsl-qoriq master. Thanks.
York
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On 08/31/2017 04:07 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha
>
> EC1 and EC2 are RGMII interface on ls1088aqds platform.
> This patch add support of RGMII with PHY and MDIO
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Amrita Kumari
> Signed-off-by: Ashish Kumar
> ---
> v3:
On 09/04/2017 04:04 AM, Ran Wang wrote:
> Some erratum patch might need it to program registers.
>
> Signed-off-by: Ran Wang
> ---
> Change in v4:
> New patch file
Applied to fsl-qoriq master. Thanks.
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On 09/03/2017 08:05 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Signed-off-by: Hou Zhiqiang
> ---
Applied to fsl-qoriq master. Thanks.
York
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On 09/07/2017 01:17 PM, York Sun wrote:
> In case high region memory doesn't have enough space for Management
> Complex (MC), the return value should indicate a failure so the
> caller can handle it accordingly.
>
> Signed-off-by: York Sun
> Reported-by: Ebony Zhu
>
On 09/10/2017 09:48 PM, York Sun wrote:
> CCN-504 HPF registers were believed to be accessible only from EL3.
> However, recent tests proved otherwise. Remove checking for exception
> level to re-enable L3 cache flushing for all levels.
>
> Signed-off-by: York Sun
> ---
Ap
On 08/31/2017 03:43 AM, Ashish Kumar wrote:
> LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
> platform that supports the LS1088A family SoCs. This patch add basic
> support of the platform.
>
> Signed-off-by: Alison Wang
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by:
On 08/27/2017 07:57 PM, Ran Wang wrote:
> According current code base, CONFIG_LS1012A should be
> CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
> wrongly called to disable all dwc3 USB nodes on LS1012A, which
> cause Linux USB function stop working at all.
>
> Signed-off-by: Ran W
On 08/31/2017 03:43 AM, Ashish Kumar wrote:
> The QorIQ LS1088A processor is built on the Layerscape
> architecture combining eight ARM A53 processor cores
> with advanced, high-performance datapath acceleration
> and networks, peripheral interfaces required for
> networking, wireless infrastructur
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
> LS2080 family has CCN-504 cache coherent interconnet.
> Other SoCs from LSCH3 may have differnt interconnect like
> LS1088.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Prabhakar Kushwaha
> ---
Revised commit message. Applied to fsl-qoriq master
On 08/31/2017 03:43 AM, Ashish Kumar wrote:
> This patch add support of LS1088AQDS platform.
>
> The LS1088A QorIQTM Development System (QDS) is a
> high-performance computing, evaluation, and
> development platform that supports the LS1088A QorIQ Architecture
> processor.
>
> Signed-off-by: Prab
On 08/24/2017 04:14 AM, Priyanka Jain wrote:
> Update MC address calculation as per MC design requirement
> of address as least significant 512MB address
> of MC private allocated memory, i.e. address should point
> to end address masked with 512MB offset in private DRAM block.
>
> Signed-off-by:
On 08/29/2017 06:42 AM, Suresh Gupta wrote:
> For QSPI and IFC addresses execution shouldn't be allowed
> when u-boot running from DDR. Revise the MMU final table
> to enforce execute-never bits.
>
> Signed-off-by: Suresh Gupta
> ---
Applied to fsl-qoriq master. Thanks.
York
__
On 08/15/2017 11:15 AM, York Sun wrote:
> If CONFIG_SPL_OS_BOOT is enabled, boot OS if kernel image is found
> in FIT structure.
>
> Signed-off-by: York Sun
> Reviewed-by: Tom Rini
>
> ---
> This presums the kernel image doesn't exist in a FIT image intended
On 08/15/2017 11:15 AM, York Sun wrote:
> Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
> SPL boot, eg. falcon boot compressed kernel image.
>
> Signed-off-by: York Sun
> Reviewed-by: Tom Rini
>
> ---
>
> Changes in v3:
> Replace ifdef wi
On 08/15/2017 11:15 AM, York Sun wrote:
> SPL supports U-Boot image in FIT format which has data outside of
> FIT structure. This adds support for embedded data for normal FIT
> images.
>
> Signed-off-by: York Sun
> Reviewed-by: Tom Rini
>
> ---
>
> Changes
On 08/15/2017 11:15 AM, York Sun wrote:
> The image size should be added to the initial pbl command, not bit
> "ORed".
>
> Signed-off-by: York Sun
> ---
>
> Changes in v3: None
> Changes in v2: None
>
Applied to fsl-qoriq master.
York
_
On 08/15/2017 11:15 AM, York Sun wrote:
> Fix warning "cast from pointer to integer of different size".
>
> Signed-off-by: York Sun
> Reviewed-by: Tom Rini
> ---
>
> Changes in v3: None
> Changes in v2: None
Applied to fsl-qoriq master.
York
___
On 08/15/2017 09:45 PM, Sumit Garg wrote:
> From: Udit Agarwal
>
> Add the secure boot defconfig for QSPI boot on LS2088ARDB
> platform.
>
> Signed-off-by: Udit Agarwal
> ---
>
> Changes in v3:
> Rebasing of the patch on top commit.
> This patch supersedes https://patchwork.ozlabs.org/patch/76
On 08/15/2017 09:45 PM, Sumit Garg wrote:
> From: Udit Agarwal
>
> Adds header address for PPA to be validated during ESBC phase for
> ARCH_LS2088 and QSPI_BOOT.
>
> Moves sec_init prior to ppa_init as for validation of PPA, sec must
> be initialised before the PPA is initialised.
>
> Signed-of
On 08/15/2017 09:45 PM, Sumit Garg wrote:
> Unify memory map for Layerscape based platforms. This patch includes
> changes in bootscript, bootscript header and PPA header addresses
> change as per unified memory map.
>
> Signed-off-by: Sumit Garg
> Tested-by: Vinitha Pillai
> ---
>
> Changes in
On 08/13/2017 07:39 PM, Zhao Qiang wrote:
> QE_IRAM_READY should be set only after successfully uploading the
> firmware.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - modify commit msg to make it more understandable
Applied to fsl-qoriq master. Thanks.
York
__
On 08/10/2017 10:39 PM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
>
> This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
> mov
memory map for Layerscape based platforms
Suresh Gupta (1):
armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC
Udit Agarwal (2):
LS2080ARDB: QSPI boot: Secure Boot image validation
armv8: LS2080ARDB: Add secure boot defconfig for QSPI boot.
York Sun (7):
tools
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4
1 file changed, 4
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.
Signed-off-by: York Sun
Reported-by: Ebony Zhu
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ---
1 file ch
On 09/03/2017 08:05 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Enabled PCIe support and PCI command feature.
>
> Signed-off-by: Hou Zhiqiang
> ---
> configs/ls1088aqds_qspi_defconfig| 4
> configs/ls1088aqds_sdcard_qspi_defconfig | 4
> configs/ls1088ardb_qspi_defcon
On 08/31/2017 03:43 AM, Ashish Kumar wrote:
> LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
> platform that supports the LS1088A family SoCs. This patch add basic
> support of the platform.
>
> Signed-off-by: Alison Wang
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by:
On 09/06/2017 09:10 PM, Sumit Garg wrote:
>> -Original Message-
>> From: York Sun
>> Sent: Wednesday, September 06, 2017 9:47 PM
>> To: Sumit Garg ; u-boot@lists.denx.de
>> Cc: Ruchika Gupta ; Prabhakar Kushwaha
>> ; tr...@konsulko.com
>> Su
On 09/01/2017 02:54 AM, Bhaskar Upadhaya wrote:
> This patch adjusts memory map for images on LS1012A
> as per below memory map:
> Image Flash Offset
> RCW+PBI 0x
> Boot firmware (U-Boot) 0x0010
On 08/25/2017 03:03 AM, Sumit Garg wrote:
> As part of chain of trust with confidentiality along with distro
> boot, linux kernel image needs to be stored in encrypted form on
> ext4 boot partition. So enable CONFIG_CMD_EXT4_WRITE in case of
> Secure boot.
>
> Signed-off-by: Sumit Garg
> ---
>
>
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