Hi Bin,
> -Original Message-
> From: Bin Meng
> Sent: Thursday, February 27, 2020 9:27 PM
> To: Park, Aiden
> Cc: masahi...@kernel.org; s...@chromium.org; s...@denx.de; ag...@suse.de; u-
> b...@lists.denx.de
> Subject: Re: [PATCH] x86: Cache write back at 32-bi
Hi Aiden,
On Fri, Feb 28, 2020 at 12:54 PM Park, Aiden wrote:
>
> In a certain condition, invd causes cache coherence issue.
> 1. Pre-stage boot code passes memory address to U-Boot
> 2. The data of the memory address is still in data cache line
> 3. The invd marks data cache line as
In a certain condition, invd causes cache coherence issue.
1. Pre-stage boot code passes memory address to U-Boot
2. The data of the memory address is still in data cache line
3. The invd marks data cache line as invalid without write back
4. U-Boot accesses the memory address
5. Data is
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