On 4/7/20 3:19 PM, Patrick DELAUNAY wrote:
> Dear,
>
>> From: Marek Vasut
>> Sent: mardi 7 avril 2020 12:04
>>
>> On 4/7/20 11:49 AM, Patrick DELAUNAY wrote:
>>> Dear Marek,
>>
>> Hi,
>>
>>> To complete my test and to check the cache management in the driver,
>>>
>>> I test the sequence
On 3/23/20 2:45 AM, Marek Vasut wrote:
> The RX descriptor field 3 should contain only OWN and BUF1V bits before
> being used for receiving data by the DMA engine. However, right now, if
> the descriptor was already used for receiving data and is being cleared,
> the field 3 is only modified and
Dear,
> From: Marek Vasut
> Sent: mardi 7 avril 2020 12:04
>
> On 4/7/20 11:49 AM, Patrick DELAUNAY wrote:
> > Dear Marek,
>
> Hi,
>
> > To complete my test and to check the cache management in the driver,
> >
> > I test the sequence (CONFIG_SYS_NONCACHED_MEMORY is activated):
> >
> > 1) ping
On 4/7/20 11:49 AM, Patrick DELAUNAY wrote:
> Dear Marek,
Hi,
> To complete my test and to check the cache management in the driver,
>
> I test the sequence (CONFIG_SYS_NONCACHED_MEMORY is activated):
>
> 1) ping with dcache ON: Always OK
>
> STM32MP> dhcp
> STM32MP> ping 91.162.57.93
>
> 2)
Dear Marek,
> From: Patrick DELAUNAY
> Sent: lundi 6 avril 2020 17:11
>
> Dear Marek,
>
> > From: Marek Vasut
> > Sent: lundi 23 mars 2020 02:45
> >
> > The RX descriptor field 3 should contain only OWN and BUF1V bits
> > before being used for receiving data by the DMA engine. However, right
>
Dear Marek,
> From: Marek Vasut
> Sent: lundi 23 mars 2020 02:45
>
> The RX descriptor field 3 should contain only OWN and BUF1V bits before being
> used for receiving data by the DMA engine. However, right now, if the
> descriptor
> was already used for receiving data and is being cleared,
Dear Marek,
> From: Marek Vasut
> Sent: lundi 23 mars 2020 02:45
>
> The RX descriptor field 3 should contain only OWN and BUF1V bits before being
> used for receiving data by the DMA engine. However, right now, if the
> descriptor
> was already used for receiving data and is being cleared,
On 3/22/20 7:45 PM, Marek Vasut wrote:
> The RX descriptor field 3 should contain only OWN and BUF1V bits before
> being used for receiving data by the DMA engine. However, right now, if
> the descriptor was already used for receiving data and is being cleared,
> the field 3 is only modified and
On Mon, Mar 23, 2020 at 3:45 AM Marek Vasut wrote:
>
> The RX descriptor field 3 should contain only OWN and BUF1V bits before
> being used for receiving data by the DMA engine. However, right now, if
> the descriptor was already used for receiving data and is being cleared,
> the field 3 is only
The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the
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