On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> T30+ SOC have second PLLD - PLLD2 which can be actively used by
> DC and act as main DISP1/2 clock parent.
>
> Tested-by: Agneli # Toshiba AC100 T20
> Tested-by: Robert Eckelmann # ASUS TF101
> Tested-by: Andreas Westman Dorcsak #
T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by:
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