Re: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

Hi, On 29 July 2015 at 14:13, Tom Warren twar...@nvidia.com wrote: Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code

Re: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

On Tue, 2015-08-04 at 15:36 +, Tom Warren wrote: Thanks. My T20/T30 boards are moth-balled, so I don't test on them. T210 USB is fine. If you can provide CAR register dumps (0x60006000 - 0x60006FFF) on T20 I can take a look. I had a look at it. Looks like you missed the cpcon stuff for

Re: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

On Wed, 2015-07-29 at 13:13 -0700, Tom Warren wrote: Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on

Re: [U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

Marcel, -Original Message- From: Marcel Ziswiler [mailto:mar...@ziswiler.com] Sent: Tuesday, August 04, 2015 1:33 AM To: Tom Warren; u-boot@lists.denx.de Cc: tomcwarren3...@gmail.com; Stephen Warren; Thierry Reding; s...@chromium.org Subject: Re: [PATCH 2/2] Tegra: PLL: use per-SoC

[U-Boot] [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20 but needs test. Corrections to divm mask vs shift