> From: Stefan Roese [mailto:[EMAIL PROTECTED]
> On Monday 01 December 2008, Scott Wood wrote:
> > Please factor this out into arch code, and make it
> shareable with other
> > NAND code (such as nand_boot.c).
>
> Yes, please.
>
> > > + /*
> > > + * We need clean dcache and invalidate
> > > +
On Monday 01 December 2008, Scott Wood wrote:
> Please factor this out into arch code, and make it shareable with other
> NAND code (such as nand_boot.c).
Yes, please.
> > + /*
> > +* We need clean dcache and invalidate
> > +* to sync between icache and dcache
> > +* before jump to
On Fri, Nov 28, 2008 at 08:16:28PM +0800, Dave Liu wrote:
> +static void __flush_cache(ulong start, ulong size)
No gratuitous underscores.
> +{
> + ulong addr, end;
> + ulong cache_line = CONFIG_SYS_CACHELINE_SIZE;
> +
> + end = start + size;
> +
> + /* clean the dcache, make sure
we load the secondary stage u-boot image from NAND to
system memory by nand_load, we have not flush data cache
to memory, not invalidate instruction cache before we
jump to RAM. when the system is cache enable and the
TLB/page attribute of system memory is cacheable, it will
cause issue.
- 83xx fa
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