On Wed, Sep 04, 2019 at 04:01:39PM +0530, Lokesh Vutla wrote:
> The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
> in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
> Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
> 288 KB of L2
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain
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