On Tue, 2019-02-12 at 05:49 -0800, Dalon L Westergreen wrote:
> On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote:
> >
> > On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> > >
> > > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> > > >
> > > > On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote:
> On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> > > On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> > > [...]
> > >
> > > > > my preference for the fit image would be
> > > > >
> > > > >
On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
>> On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
>> [...]
>>
>>>
my preference for the fit image would be
...
images {
fpga@1 {
description = "FPGA Periph";
On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> [...]
>
> >
> > >
> > > my preference for the fit image would be
> > >
> > > ...
> > > images {
> > > fpga@1 {
> > > description = "FPGA Periph";
> > > ...
> > > type = "fpga_periph";
On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
[...]
>> my preference for the fit image would be
>>
>> ...
>> images {
>> fpga@1 {
>> description = "FPGA Periph";
>> ...
>> type = "fpga_periph";
>> ...
>> }
>> fpga@2 {
>> description = "FPGA Core";
>> ...
>>
On Mon, 2019-02-11 at 17:19 +, Westergreen, Dalon wrote:
> On Tue, 2019-02-12 at 01:01 +0800, Chee, Tien Fong wrote:
> >
> > On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> > >
> > > On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> > > >
> > > > On Tue, 2019-02-05 at 09:46 +0100, Marek
On Tue, 2019-02-12 at 01:01 +0800, Chee, Tien Fong wrote:
> On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> > On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> > > On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> > > > On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> > > > >
> > > > > On
On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
>
On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> > On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> > > On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> > > > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > > > > On 2/1/19 4:48 AM,
On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
>> On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
>>>
>>> On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-01-31 at
On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
>
On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
>> On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien
On Fri, 2019-02-01 at 12:29 -0800, Dalon L Westergreen wrote:
> On Fri, 2019-02-01 at 12:02 -0800, Dalon L Westergreen wrote:
> >
> > On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> > >
> > > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > > >
> > > > On 2/1/19 4:48 AM,
On Fri, 2019-02-01 at 12:02 -0800, Dalon L Westergreen wrote:
> On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > > >
On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > > >
> > > >
On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > This
On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
>> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> This patch adds description on properties about file name used for
>>> both
>>> peripheral bitstream and
On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> >
> > Signed-off-by: Tien
On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch adds description on properties about file name used for both
> peripheral bitstream and core bitstream.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v7
> - Provided example of setting FPGA
From: Tien Fong Chee
This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.
Signed-off-by: Tien Fong Chee
---
changes for v7
- Provided example of setting FPGA FIT image for both early IO release
and full release FPGA configuration.
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