On 17/03/15 17:29, Stephen Warren wrote:
Do the RPi 1 and RPi 2 use different kernel binaries in the RPi Foundation's
images? I'd assumed there was a single unified binary which supported both. The
reason I ask is that I see:
We ship separate kernel binaries (kernel.img for 2835 and
On 03/17/2015 08:57 AM, popcorn mix wrote:
On 17/03/15 03:04, Stephen Warren wrote:
It would be nice though if someone from the RPi Foundation could comment
on the exact effect of the upper bus address bits, and why 0xc would
work for RPi2 but 0x4 for the RPi 1. I wonder if the ARM cache status
On 17/03/15 03:04, Stephen Warren wrote:
It would be nice though if someone from the RPi Foundation could comment
on the exact effect of the upper bus address bits, and why 0xc would
work for RPi2 but 0x4 for the RPi 1. I wonder if the ARM cache status
(enabled, disabled) interacts with the GPU
On 03/15/2015 12:20 PM, Marek Vasut wrote:
On Sunday, March 15, 2015 at 05:04:05 PM, Stephen Warren wrote:
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that: ...
If you do end up applying this, the subject should say phys-bus not
phys-virt.
On Sunday, March 15, 2015 at 05:51:26 PM, Stephen Warren wrote:
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4:
On Sunday, March 15, 2015 at 05:04:05 PM, Stephen Warren wrote:
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that: ...
If you do end up
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache coherent (non allocaing)
8: L2 cached only
c: Direct
On Friday, March 13, 2015 at 07:39:08 PM, Stephen Warren wrote:
On 03/13/2015 12:13 PM, Marek Vasut wrote:
On Friday, March 13, 2015 at 05:35:53 PM, Stephen Warren wrote:
On 03/13/2015 08:30 AM, Marek Vasut wrote:
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus
On Friday, March 13, 2015 at 05:35:53 PM, Stephen Warren wrote:
On 03/13/2015 08:30 AM, Marek Vasut wrote:
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether
peripherals use or bypass the GPU L1 and L2 cache.
Stephen Warren swar...@wwwdotorg.org writes:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache coherent (non allocaing)
8: L2 cached only
c: Direct
On 03/13/2015 12:13 PM, Marek Vasut wrote:
On Friday, March 13, 2015 at 05:35:53 PM, Stephen Warren wrote:
On 03/13/2015 08:30 AM, Marek Vasut wrote:
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether
peripherals use
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache coherent (non allocaing)
8: L2 cached only
c: Direct uncached.
That document also states that Software accessing
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache coherent (non allocaing)
8: L2 cached only
On 03/13/2015 08:30 AM, Marek Vasut wrote:
On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache
15 matches
Mail list logo
