[U-Boot] CACHE: Misaligned operation for rpi_3_32b_defconfig

2019-06-27 Thread Elliot Cooper
Hi Guys, I have just built a u-boot.bin for rpi_3_32b_defconfig using all the defaults. I then used this on the new Raspbian Buster image that was released a few days ago i.e. 2019-06-20-raspbian-buster-lite.zip. This same u-boot.bin works fine on the old Raspbian Stretch version (

Re: [U-Boot] CACHE: Misaligned operation

2016-08-14 Thread Clemens Gruber
Hi, On Fri, Aug 12, 2016 at 09:27:29AM -0600, Simon Glass wrote: > Yes it means there is an error in the calling code. If you can figure > out who is calling this then it is worth fixing. But also see recent > discussions on the mailing list. Also possibly this patch? > >

Re: [U-Boot] CACHE: Misaligned operation

2016-08-13 Thread Lukasz Majewski
Hi Simon, > Hi, > > On 12 August 2016 at 08:13, Clemens Gruber > wrote: > > Hi, > > > > I just tested the current U-Boot master on my i.MX6Q board and the > > following two warnings showed up on the console: > > > > U-Boot 2016.09-rc1-00377-gb8698a2 > > > > CPU:

Re: [U-Boot] CACHE: Misaligned operation

2016-08-12 Thread Simon Glass
Hi, On 12 August 2016 at 08:13, Clemens Gruber wrote: > Hi, > > I just tested the current U-Boot master on my i.MX6Q board and the > following two warnings showed up on the console: > > U-Boot 2016.09-rc1-00377-gb8698a2 > > CPU: Freescale i.MX6Q rev1.5 at 792 MHz >

[U-Boot] CACHE: Misaligned operation

2016-08-12 Thread Clemens Gruber
Hi, I just tested the current U-Boot master on my i.MX6Q board and the following two warnings showed up on the console: U-Boot 2016.09-rc1-00377-gb8698a2 CPU: Freescale i.MX6Q rev1.5 at 792 MHz Reset cause: POR DRAM: 1 GiB CACHE: Misaligned operation at range [4fff, 4fff0004] CACHE: