On Wed, Oct 18, 2023 at 3:52 PM Marek Vasut wrote:
>
> The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors
> in case of an exception. Those high vectors are located at 0x, which
> is where the BootROM exception table is located as well. U-Boot should handle
>
On Wed, Oct 18, 2023 at 3:52 PM Marek Vasut wrote:
>
> The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors
> in case of an exception. Those high vectors are located at 0x, which
> is where the BootROM exception table is located as well. U-Boot should handle
>
2 matches
Mail list logo
