[U-Boot] [PATCH 1/3] arm: atmel: at91sam9x5: cleanup cs configure for spi
As the cs for spi is worked in gpio mode, so no need to configure it as peripheral and then configure to gpio. Signed-off-by: Bo Shen voice.s...@atmel.com --- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 28 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c |1 - 2 files changed, 6 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 6d94572..745dce6 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -130,20 +130,12 @@ void at91_spi0_hw_init(unsigned long cs_mask) writel(1 ATMEL_ID_SPI0, pmc-pcer); if (cs_mask (1 0)) - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); - if (cs_mask (1 1)) - at91_set_b_periph(AT91_PIO_PORTA, 7, 0); - if (cs_mask (1 2)) - at91_set_b_periph(AT91_PIO_PORTA, 1, 0); - if (cs_mask (1 3)) - at91_set_b_periph(AT91_PIO_PORTB, 3, 0); - if (cs_mask (1 4)) at91_set_pio_output(AT91_PIO_PORTA, 14, 0); - if (cs_mask (1 5)) + if (cs_mask (1 1)) at91_set_pio_output(AT91_PIO_PORTA, 7, 0); - if (cs_mask (1 6)) + if (cs_mask (1 2)) at91_set_pio_output(AT91_PIO_PORTA, 1, 0); - if (cs_mask (1 7)) + if (cs_mask (1 3)) at91_set_pio_output(AT91_PIO_PORTB, 3, 0); } @@ -159,20 +151,12 @@ void at91_spi1_hw_init(unsigned long cs_mask) writel(1 ATMEL_ID_SPI1, pmc-pcer); if (cs_mask (1 0)) - at91_set_b_periph(AT91_PIO_PORTA, 8, 0); - if (cs_mask (1 1)) - at91_set_b_periph(AT91_PIO_PORTA, 0, 0); - if (cs_mask (1 2)) - at91_set_b_periph(AT91_PIO_PORTA, 31, 0); - if (cs_mask (1 3)) - at91_set_b_periph(AT91_PIO_PORTA, 30, 0); - if (cs_mask (1 4)) at91_set_pio_output(AT91_PIO_PORTA, 8, 0); - if (cs_mask (1 5)) + if (cs_mask (1 1)) at91_set_pio_output(AT91_PIO_PORTA, 0, 0); - if (cs_mask (1 6)) + if (cs_mask (1 2)) at91_set_pio_output(AT91_PIO_PORTA, 31, 0); - if (cs_mask (1 7)) + if (cs_mask (1 3)) at91_set_pio_output(AT91_PIO_PORTA, 30, 0); } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 6f67c34..fb74a30 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -272,7 +272,6 @@ int board_init(void) #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 0); - at91_spi0_hw_init(1 4); #endif #ifdef CONFIG_MACB -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position
In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, move the CONFIG_SYS_NO_FLASH to proper position, then we don't need to undef these two commands. Signed-off-by: Bo Shen voice.s...@atmel.com --- include/configs/at91sam9x5ek.h |8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 4eeaf3b..f0a6757 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -61,14 +61,15 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + /* * Command line configuration. */ #include config_cmd_default.h #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -100,9 +101,6 @@ #define CONFIG_SF_DEFAULT_SPEED3000 #endif -/* no NOR flash */ -#define CONFIG_SYS_NO_FLASH - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] arm: atmel: clean up for at91sam9x5ek board
This patch series do a clean up for at91sam9x5ek board. Bo Shen (3): arm: atmel: at91sam9x5: cleanup cs configure for spi arm: atmel: at91sam9x5: cleanup unneeded undef arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 28 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c |1 - include/configs/at91sam9x5ek.h | 13 +++--- 3 files changed, 9 insertions(+), 33 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: atmel: at91sam9x5: cleanup unneeded undef
remove unneeded #undef for at91sam9x5ek board. Signed-off-by: Bo Shen voice.s...@atmel.com --- include/configs/at91sam9x5ek.h |5 - 1 file changed, 5 deletions(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index ea9a50e..4eeaf3b 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -44,7 +44,6 @@ #define LCD_BPPLCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -244,8 +243,4 @@ */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] FW: [PATCH 06/10] video: exynos: fimd: always use 16bpp display mode.
Hello Donghwa,
On 12/10/2013 06:47 AM, Donghwa Lee wrote:
Hi,
On 3 Dec 2013 18:03, Przemyslaw wrote:
This change updates exynos board files too.
16 bpp mode is required by LCD console mode.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
board/samsung/trats/trats.c |2 +-
board/samsung/trats2/trats2.c|2 +-
board/samsung/universal_c210/universal.c |2 +-
drivers/video/exynos_fimd.c | 10 ++
include/configs/s5pc210_universal.h |2 +-
include/configs/trats.h |2 +-
include/configs/trats2.h |2 +-
7 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index ce4b41f..db527c7 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -739,7 +739,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
-.vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+.vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 73b8cc1..6fa02c9 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -542,7 +542,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
-.vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+.vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 166d5ee..1ebea0f 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -446,7 +446,7 @@ vidinfo_t panel_info = {
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
-.vl_bpix= 5,/* Bits per pixel */
+.vl_bpix= 4,/* Bits per pixel */
/* LD9040 LCD Panel */
.vl_hspw= 2,
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f..847fbe8 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,12 @@ static void exynos_fimd_set_par(unsigned int win_id)
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
-if (pvid-logo_on) /* To get proprietary LOGO */
-cfg |= EXYNOS_WINCON_WSWP_ENABLE;
-else /* To get output console on LCD */
-cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
-if (pvid-logo_on) /* To get proprietary LOGO */
-cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-else /* To get output console on LCD */
-cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
Why does exynos fimd always use 16bpp display mode?
Good question. I switched fimd to 16BPP because of LCD framework which
supports in max 16BPP mode for LCD console. Leaving fimd 32BPP mode and
16BPP console is possible but it causes wrong setup of lcd console row
and columns, it also displays wrong size fonts.
It could be used as other bpp modes in exynos.
How do you use above vl_bpix variable in panel_info structure to check bpp
mode?
Actually vl_bpix was never used to check BPP mode in fimd driver, it was
only used to set proper memory space. Fimd BPP mode was set by checking
logo_on in panel_info structure.
This is good reason to use vl_bpix in fimd driver to set proper BPP. I
will change this to something like this:
if (pvid-vl_bpix == 4)
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
else
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
Do you agree?
BR,
Donghwa Lee.
Thank you,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH 2/7 V3] mmc: Get secure erase information from card
Hi Haijun,
On Dec 10, 2013, at 7:39 AM, Haijun Zhang wrote:
Read command class from csd register and secure erase
support bit from ext csd register. Also calculate the erase
timeout and secure erase timeout.
If read ext csd error, error status should be returned instead of
give some incorrect information.
s/give some/giving/
Error log:
=
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Change the erase group size to be block aligned.
drivers/mmc/mmc.c | 52 ++--
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index e1461a9..e8dbb8c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -871,6 +871,8 @@ static int mmc_startup(struct mmc *mmc)
}
}
+ mmc-cmdclass = cmd.response[1] 20;
+
^ use mask of cmd class maximum width (even if class is 12 bit wide)
/* divide frequency by 10, since the mults are 10x bigger */
freq = fbase[(cmd.response[0] 0x7)];
mult = multipliers[((cmd.response[0] 3) 0xf)];
@@ -939,7 +941,8 @@ static int mmc_startup(struct mmc *mmc)
capacity *= MMC_MAX_BLOCK_LEN;
if ((capacity 20) 2 * 1024)
mmc-capacity_user = capacity;
- }
+ } else
+ return COMM_ERR;
switch (ext_csd[EXT_CSD_REV]) {
case 1:
@@ -960,6 +963,39 @@ static int mmc_startup(struct mmc *mmc)
}
/*
+ * The granularity of the erasable units is the Erase Group:The
+ * smallest number of consecutive write blocks which can be
+ * addressed for erase. The size of the Erase Group is card
+ * specific and stored in the CSD when ERASE_GROUP_DEF is
+ * disabled, and in the EXT_CSD when ERASE_GROUP_DEF is
+ * enabled.
+ */
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF]) {
+ mmc-erase_grp_size =
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
+
+ mmc-erase_timeout_mult = 300 *
+ ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT];
+ } else {
+ /* Calculate the group size from the csd value. */
+ int erase_gsz, erase_gmul;
+ erase_gsz = (mmc-csd[2] 0x7c00) 10;
+ erase_gmul = (mmc-csd[2] 0x03e0) 5;
+ mmc-erase_grp_size = (erase_gsz + 1)
+ * (erase_gmul + 1);
+ }
+
+ if (ext_csd[EXT_CSD_REV] = 4) {
+ mmc-sec_feature_support =
+ ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT];
+ mmc-sec_erase_mult =
+ ext_csd[EXT_CSD_SEC_ERASE_MULT];
+ mmc-sec_erase_timeout = 300 *
+ ext_csd[EXT_CSD_SEC_ERASE_MULT] *
+ ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT];
+ }
+
+ /*
* Host needs to enable ERASE_GRP_DEF bit if device is
* partitioned. This bit will be lost every time after a reset
* or power off. This will affect erase size.
@@ -968,23 +1004,11 @@ static int mmc_startup(struct mmc *mmc)
(ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] PART_ENH_ATTRIB)) {
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_ERASE_GROUP_DEF, 1);
-
^ removed line for no reason
if (err)
return err;
-
- /* Read out group size from ext_csd */
- mmc-erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
- MMC_MAX_BLOCK_LEN * 1024;
- } else {
- /* Calculate the group size from the csd value. */
- int erase_gsz, erase_gmul;
- erase_gsz = (mmc-csd[2] 0x7c00) 10;
- erase_gmul = (mmc-csd[2] 0x03e0) 5;
- mmc-erase_grp_size = (erase_gsz + 1)
- * (erase_gmul + 1);
}
+
^ extra line
/* store the partition info of emmc */
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] PART_SUPPORT) ||
ext_csd[EXT_CSD_BOOT_MULT])
--
1.8.4.1
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Re: [U-Boot] [PATCH 3/7 V3] mmc: Enhance erase handling procedure
Hi Haijun,
On Dec 10, 2013, at 7:39 AM, Haijun Zhang wrote:
This patch enhances the currently implemented erase procedure in u-boot,
which has the following problems/missing features...
^ this is exactly what I responded earlier.
What are the problems?
What are the missing features?
Erass sequence:
1. check if erase command is support by card. If not return.
2. Check the erase range to see if it was aligned. The min erase size
should be one erase group. SD card it was one block(512), mmc card
it should be one erase group.
3. If not, aligned the erase rang according to the erase group size.
4. Send erase command to erase card once one erase group.
5. If it was SD card, erase with arg 0x should be send.
else if support secure feature, erase with arg 0x8000(Spec eMMC 4.41).
else erase with arg 0x.(Trim and discard is ingnored here)
6. Check card status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- update the commit message and secure feature supporting judgment.
drivers/mmc/mmc_write.c | 68 +
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index aa2fdef..c2dafa3 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -17,6 +17,10 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
struct mmc_cmd cmd;
ulong end;
int err, start_cmd, end_cmd;
+ uint arg = 0;
+
+ if (!(mmc-cmdclass CCC_ERASE))
+ return NOT_SUPPORT;
if (mmc-high_capacity) {
end = start + blkcnt - 1;
@@ -48,8 +52,15 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
if (err)
goto err_out;
+ /* SD card only support %MMC_ERASE_ARG */
+ if (!IS_SD(mmc)
+ (mmc-sec_feature_support EXT_CSD_SEC_ER_EN))
+ arg = MMC_SECURE_ERASE_ARG;
+ else
+ arg = MMC_ERASE_ARG;
+
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = arg;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, cmd, NULL);
@@ -69,24 +80,61 @@ unsigned long mmc_berase(int dev_num, lbaint_t start,
lbaint_t blkcnt)
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
+ int res;
+ bool align = true;
if (!mmc)
return -1;
+ if (!(mmc-cmdclass CCC_ERASE)) {
+ printf(\nErase operation is not support by card\n);
+ return NOT_SUPPORT;
+ }
+
if ((start % mmc-erase_grp_size) || (blkcnt % mmc-erase_grp_size))
+ align = false;
+
+ res = start % mmc-erase_grp_size;
+ if (res) {
+ res = mmc-erase_grp_size - res;
+ start += res;
+ if (blkcnt res)
+ blkcnt -= res;
+ else {
+ printf(\nErase size smaller than Erase group
+ size [0x%x] is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+ }
+
+ res = blkcnt % mmc-erase_grp_size;
+ if (res)
+ blkcnt -= res;
+
+ if (!blkcnt) {
+ printf(\nErase size smaller than Erase group size [0x%x]
+ is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+
+ if (!align)
printf(\n\nCaution! Your devices Erase group is 0x%x\n
-The erase range would be change to
-0x LBAF ~0x LBAF \n\n,
-mmc-erase_grp_size, start ~(mmc-erase_grp_size - 1),
-((start + blkcnt + mmc-erase_grp_size)
- ~(mmc-erase_grp_size - 1)) - 1);
+ The erase range would be change to
+ 0x LBAF ~0x LBAF \n\n,
+ mmc-erase_grp_size, start, start + blkcnt);
+
while (blk blkcnt) {
- blk_r = ((blkcnt - blk) mmc-erase_grp_size) ?
- mmc-erase_grp_size : (blkcnt - blk);
+ if ((blkcnt - blk) = mmc-erase_grp_size)
+ blk_r = mmc-erase_grp_size;
err = mmc_erase_t(mmc, start + blk, blk_r);
- if (err)
- break;
+ if (err) {
+ printf(\nErase range from 0x LBAF ~0x LBAF
+ Failed\n, start + blk, blkcnt);
+ return COMM_ERR;
+ }
blk += blk_r;
--
1.8.4.1
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Re: [U-Boot] BCH8 support when we do not have ELM h/w engine.
2013/12/4 Enric Balletbo Serra eballe...@gmail.com: Dear Pekon, I'm trying to enable the support for BCH8 for platforms that do not have ELM hardware engine. Maybe I'm missing something but my first and quick attempt was applying the following patch: http://pastebin.com/VUjuGChR With this patch I'm able to switch to OMAP_ECC_BCH8_CODE_HW_DETECTION_SW with the nandecc hw bch8 command. Then I tried to flash a ubi rootfs into the nand, but the kernel can't mount the filesystem, I see messages like that: [3.703582] ecc unrecoverable error [3.707244] UBI warning: ubi_io_read: error -74 (ECC error) while reading 64 bytes from PEB 2:0, read only 64 bytes, retry OTOH, if I flash the rootfs from the kernel (my board sets the ecc to bch8) I don't have any problem, I can mount without problems. I saw that the OOB layout is not the same when I flash the rootfs from the u-boot or from the kernel. For example: If the rootfs is flashed from the kernel the OOB data is like that: U-Boot # nand dump.oob 0x68 Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d ff 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff If the rootfs is flashed for the u-boot the OOB data is like data: Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Note that look the same except after byte number 16. In the first case is ff 52 3f 7d 2a 7f a2 98 70 and in the second case is 52 3f 7d 2a 7f a2 98 70 It's possible that something is wrong writting the OOB data ? Any clue ? I'm in the right direction or completely wrong ? Thanks in advance, Enric Any clue about this ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
Hi Bo,
Hi Lukasz,
On 12/09/2013 11:20 PM, Lukasz Majewski wrote:
diff --git a/drivers/usb/gadget/f_dfu.h b/drivers/usb/gadget/f_dfu.h
index cc2c455..0c29954 100644
--- a/drivers/usb/gadget/f_dfu.h
+++ b/drivers/usb/gadget/f_dfu.h
@@ -82,4 +82,6 @@ struct dfu_function_descriptor {
__le16 wTransferSize;
__le16 bcdDFUVersion;
} __packed;
+
+#define DFU_POLL_TIMEOUT_MASK (0xFFUL)
Why this value? How about (~0UL)?
According to DFU 1.1 standard, the bwPolTimeout field of DFU_GETSTATUS
request has 3 bytes in size.
#endif /* __F_DFU_H_ */
Best Regards,
Bo Shen
--
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Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 4/7 V3] mmc: Update the handling of returned erase block
Hi Haijun,
On Dec 10, 2013, at 7:39 AM, Haijun Zhang wrote:
If the block rang was not algined, We tried to algined the range,
range, aligned,
We try to align
then erase the block. So the block range erased should be less or
equal to the block range sent. If error occured during erase procedure
part of them will be erased. And use should resend the block rang to
User? range
continue erase the reset of them.
the rest
Error number and zero number mean erase operation was failed.
Error return, zero return, has failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- no changes
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 67a94a7..c124df0 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -397,6 +397,13 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
BUG();
}
+ if (state == MMC_ERASE) {
+ printf(%d blocks %s: %s\n,
+ ((n = cnt) (n 0)) ? n : 0, argv[1],
+ ((n = cnt) (n 0)) ? OK : ERROR);
+ return ((n = cnt) (n 0)) ? 0 : 1;
+ }
+
Drop the inside parentheses
(n = cnt n 0)
Or use a variable like
int valid = n = cnt n 0;
printf(%d blocks %s: %s\n,
n, argv[1], (n == cnt) ? OK : ERROR);
return (n == cnt) ? 0 : 1;
--
1.8.4.1
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Re: [U-Boot] [PATCH 2/4] usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
Hi Lukasz,
On 12/10/2013 04:27 PM, Lukasz Majewski wrote:
Hi Bo,
Hi Lukasz,
On 12/09/2013 11:20 PM, Lukasz Majewski wrote:
diff --git a/drivers/usb/gadget/f_dfu.h b/drivers/usb/gadget/f_dfu.h
index cc2c455..0c29954 100644
--- a/drivers/usb/gadget/f_dfu.h
+++ b/drivers/usb/gadget/f_dfu.h
@@ -82,4 +82,6 @@ struct dfu_function_descriptor {
__le16 wTransferSize;
__le16 bcdDFUVersion;
} __packed;
+
+#define DFU_POLL_TIMEOUT_MASK (0xFFUL)
Why this value? How about (~0UL)?
According to DFU 1.1 standard, the bwPolTimeout field of DFU_GETSTATUS
request has 3 bytes in size.
Thanks for clarify this.
Tested OK on sama5d3xek board.
Tested-by: Bo Shen voice.s...@atmel.com
#endif /* __F_DFU_H_ */
Best Regards,
Bo Shen
Best Regards,
Bo Shen
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Re: [U-Boot] BCH8 support when we do not have ELM h/w engine.
Hi Enric, Sorry I missed your earlier mail, so din't check this.. From: Enric Balletbo Serra [mailto:eballe...@gmail.com] I saw that the OOB layout is not the same when I flash the rootfs from the u-boot or from the kernel. For example: If the rootfs is flashed from the kernel the OOB data is like that: U-Boot # nand dump.oob 0x68 Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d ff 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff If the rootfs is flashed for the u-boot the OOB data is like data: Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Note that look the same except after byte number 16. In the first case is ff 52 3f 7d 2a 7f a2 98 70 and in the second case is 52 3f 7d 2a 7f a2 98 70 It's possible that something is wrong writting the OOB data ? Any clue ? I'm in the right direction or completely wrong ? Yes, there seems to be an mis-match between u-boot and kernel ecc-layout. Give me a day's time, and I'll try to root cause this. However, don't have OMAP3 boards, so I can test this only on other boards. with regards, pekon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] the relationship between CONFIG_LCD / CONFIG_VIDEO / CONFIG_CFB_CONSOLE
Hi, experts: I am confused by CONFIG_LCD / CONFIG_VIDEO / CONFIG_CFB_CONSOLE. Some board config files defined : CONFIG_VIDEO and CONFIG_CFB_CONSOLE. But not define CONFIG_LCD. It seemed CONFIG_LCD was out of date? Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] BCH8 support when we do not have ELM h/w engine.
Hi Pekon, 2013/12/10 Gupta, Pekon pe...@ti.com: Hi Enric, Sorry I missed your earlier mail, so din't check this.. From: Enric Balletbo Serra [mailto:eballe...@gmail.com] I saw that the OOB layout is not the same when I flash the rootfs from the u-boot or from the kernel. For example: If the rootfs is flashed from the kernel the OOB data is like that: U-Boot # nand dump.oob 0x68 Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d ff 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff If the rootfs is flashed for the u-boot the OOB data is like data: Page 0068 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Note that look the same except after byte number 16. In the first case is ff 52 3f 7d 2a 7f a2 98 70 and in the second case is 52 3f 7d 2a 7f a2 98 70 It's possible that something is wrong writting the OOB data ? Any clue ? I'm in the right direction or completely wrong ? Yes, there seems to be an mis-match between u-boot and kernel ecc-layout. Give me a day's time, and I'll try to root cause this. However, don't have OMAP3 boards, so I can test this only on other boards. with regards, pekon If I can help somehow just let me know. Thanks, Enric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10] video: exynos: fimd: always use 16bpp display mode.
On 10 Dec 2013 17:15, Przemyslaw Marczak wrote:
Hello Donghwa,
On 12/10/2013 06:47 AM, Donghwa Lee wrote:
Hi,
On 3 Dec 2013 18:03, Przemyslaw wrote:
This change updates exynos board files too.
16 bpp mode is required by LCD console mode.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
board/samsung/trats/trats.c |2 +-
board/samsung/trats2/trats2.c|2 +-
board/samsung/universal_c210/universal.c |2 +-
drivers/video/exynos_fimd.c | 10 ++
include/configs/s5pc210_universal.h |2 +-
include/configs/trats.h |2 +-
include/configs/trats2.h |2 +-
7 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index ce4b41f..db527c7 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -739,7 +739,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+ .vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 73b8cc1..6fa02c9 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -542,7 +542,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+ .vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 166d5ee..1ebea0f 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -446,7 +446,7 @@ vidinfo_t panel_info = {
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
- .vl_bpix= 5,/* Bits per pixel */
+ .vl_bpix= 4,/* Bits per pixel */
/* LD9040 LCD Panel */
.vl_hspw= 2,
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f..847fbe8 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,12 @@ static void exynos_fimd_set_par(unsigned int win_id)
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
- if (pvid-logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_WSWP_ENABLE;
- else /* To get output console on LCD */
- cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+ cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
- if (pvid-logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
- else /* To get output console on LCD */
- cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+ cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
Why does exynos fimd always use 16bpp display mode?
Good question. I switched fimd to 16BPP because of LCD framework which
supports in max 16BPP mode for LCD console. Leaving fimd 32BPP mode and
16BPP console is possible but it causes wrong setup of lcd console row
and columns, it also displays wrong size fonts.
It could be used as other bpp modes in exynos.
How do you use above vl_bpix variable in panel_info structure to check bpp
mode?
Actually vl_bpix was never used to check BPP mode in fimd driver, it was
only used to set proper memory space. Fimd BPP mode was set by checking
logo_on in panel_info structure.
This is good reason to use vl_bpix in fimd driver to set proper BPP. I
will change this to something like this:
if (pvid-vl_bpix == 4)
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
else
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
Do you agree?
There is many others bpp modes, but in most cases, we usually use 16bpp or
24bpp modes.
To support many bpp modes more than two, it looks good to use 'switch' like
below.
switch(pvid-vl_bpix) {
case 0;
...
case 1:
...
...
case 5:
...
}
BR,
Donghwa Lee.
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Re: [U-Boot] FW: [PATCH 06/10] video: exynos: fimd: always use 16bpp display mode.
Hi Marczak,
On Tue, Dec 10, 2013 at 1:45 PM, Przemyslaw Marczak
p.marc...@samsung.comwrote:
Hello Donghwa,
On 12/10/2013 06:47 AM, Donghwa Lee wrote:
Hi,
On 3 Dec 2013 18:03, Przemyslaw wrote:
This change updates exynos board files too.
16 bpp mode is required by LCD console mode.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
board/samsung/trats/trats.c |2 +-
board/samsung/trats2/trats2.c|2 +-
board/samsung/universal_c210/universal.c |2 +-
drivers/video/exynos_fimd.c | 10 ++
include/configs/s5pc210_universal.h |2 +-
include/configs/trats.h |2 +-
include/configs/trats2.h |2 +-
7 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index ce4b41f..db527c7 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -739,7 +739,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
-.vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+.vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/trats2/trats2.c
b/board/samsung/trats2/trats2.c
index 73b8cc1..6fa02c9 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -542,7 +542,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
-.vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+.vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 166d5ee..1ebea0f 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -446,7 +446,7 @@ vidinfo_t panel_info = {
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
-.vl_bpix= 5,/* Bits per pixel */
+.vl_bpix= 4,/* Bits per pixel */
/* LD9040 LCD Panel */
.vl_hspw= 2,
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f..847fbe8 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,12 @@ static void exynos_fimd_set_par(unsigned int win_id)
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
-if (pvid-logo_on) /* To get proprietary LOGO */
-cfg |= EXYNOS_WINCON_WSWP_ENABLE;
-else /* To get output console on LCD */
-cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
-if (pvid-logo_on) /* To get proprietary LOGO */
-cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-else /* To get output console on LCD */
-cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
Why does exynos fimd always use 16bpp display mode?
Good question. I switched fimd to 16BPP because of LCD framework which
supports in max 16BPP mode for LCD console. Leaving fimd 32BPP mode and
16BPP console is possible but it causes wrong setup of lcd console row
and columns, it also displays wrong size fonts.
It could be used as other bpp modes in exynos.
How do you use above vl_bpix variable in panel_info structure to check
bpp mode?
Actually vl_bpix was never used to check BPP mode in fimd driver, it was
only used to set proper memory space. Fimd BPP mode was set by checking
logo_on in panel_info structure.
This is good reason to use vl_bpix in fimd driver to set proper BPP. I
will change this to something like this:
if (pvid-vl_bpix == 4)
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
else
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
Do you agree?
This change makes sense.
We should actually be using vl_bpix for the check, and not logo_on.
BR,
Donghwa Lee.
Thank you,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH V3 00/14] ARM: AM43xx: Update support for AM4372 SoC
This Patch series updates support for AM4372 EPOS and GP EVM boards. AM4372 is a low cost Cortex-A9 based application processor targeted at existing ARM9/ARM11 base of customers that need more processing capabilities. Currently there are two boards with AM4372 SoC: EPOS and GP EVM. Except for few differences like oscillator clock and SDRAM both EPOS and GP EVM boards are similar. EPOS EVM: OSC clk : 25MHz DDR : LPDDR2 @ 266MHz (MT42L256M32D2LG-25 WT:A) GP EVM: OSC clk : 24MHz DDR : DDR3 @ 400MHz(MT41K512M8RH) This patch series is applied on top of Mainline U-Boot Tree and two patches mentioned below: git://git.denx.de/u-boot.git master http://patchwork.ozlabs.org/patch/288175/ Testing: - Boot tested on AM4372 EPOS and GP EVMs, Beaglebone Black. - verified MAKEALL -s am33xx. - Ran checkpatch on all patches. Changes Since V2: - Updating the base offsets only for AM43xx - Populated DPLLs data for all OPPs and SYS CLK inputs and the correct values to be read from eFuse. - Seperated out ioregs changes into a new patch. Changes Since V1: As per Vaibhav's and Tom's Comments: - Updated the mux data not to use DSPULLUDEN. - Reused the emif4d file for configuring emif4d5 registers. - Updated the code with comments. - Rebased on top of Current U-Boot mainline. Lokesh Vutla (12): ARM: AM43xx: Update the base addresses of modules ARM: AM43xx: Adapt to ti_armv7_common.h config file ARM: AM43xx: Add L2 Support ARM: AM43xx: Add extra ENV settings ARM: AM43xx: Select clk source for Timer2 ARM: AM43xx: Update Current Booting devices list ARM: AM43xx: mux: Update mux data ARM: AM43xx: clocks: Update DPLL details ARM: AM33xx+: Update ioregs to pass different values ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 ARM: AM43xx: GP_EVM: Add support for DDR3 ARM: AM43xx: Add Maintainer Sekhar Nori (2): ARM: AM43XX: board: add support for reading onboard EEPROM ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support arch/arm/cpu/armv7/am33xx/clock.c | 12 +- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 + arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 12 +- arch/arm/cpu/armv7/am33xx/ddr.c| 146 +++- arch/arm/cpu/armv7/am33xx/emif4.c | 25 +- arch/arm/cpu/armv7/omap-common/emif-common.c | 14 - arch/arm/include/asm/arch-am33xx/clock.h |7 +- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 + arch/arm/include/asm/arch-am33xx/cpu.h | 24 +- arch/arm/include/asm/arch-am33xx/ddr_defs.h| 41 ++- arch/arm/include/asm/arch-am33xx/gpio.h| 12 + arch/arm/include/asm/arch-am33xx/hardware.h|7 - arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |2 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 16 + arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 45 +++ arch/arm/include/asm/arch-am33xx/omap.h|4 +- arch/arm/include/asm/arch-am33xx/spl.h | 13 +- arch/arm/include/asm/emif.h| 26 ++ board/isee/igep0033/board.c| 10 +- board/phytec/pcm051/board.c| 12 +- board/siemens/dxr2/board.c | 10 +- board/siemens/pxm2/board.c | 10 +- board/siemens/rut/board.c | 10 +- board/ti/am335x/board.c| 40 ++- board/ti/am43xx/board.c| 355 +++- board/ti/am43xx/board.h| 36 ++ board/ti/am43xx/mux.c | 35 +- board/ti/ti814x/evm.c |4 +- board/ti/ti816x/evm.c | 12 +- boards.cfg |2 +- include/configs/am43xx_evm.h | 204 +-- 31 files changed, 983 insertions(+), 181 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 03/14] ARM: AM43xx: Add L2 Support
AM4372 uses PL310 L2 Cache. Enable the configs for the same. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- Changes since V2: - No change. include/configs/am43xx_evm.h |5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index cad6979..833e5fa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -30,6 +30,11 @@ #define CONFIG_SPL_MAX_SIZE(0x40337C00 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 01/14] ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- Dropped updating wrong address for TI81XX
arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++--
arch/arm/include/asm/arch-am33xx/hardware.h|7 ---
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |2 ++
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |2 ++
4 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 05752ce..19b8469 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -237,6 +237,14 @@ struct cm_perpll {
unsigned int cpswclkstctrl; /* offset 0x144 */
unsigned int lcdcclkstctrl; /* offset 0x148 */
};
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+ unsigned int resv1[2];
+ unsigned int clktimer2clk; /* offset 0x08 */
+ unsigned int resv2[10];
+ unsigned int clklcdcpixelclk; /* offset 0x34 */
+};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
@@ -392,15 +400,12 @@ struct cm_perpll {
unsigned int resv40[7];
unsigned int cpgmac0clkctrl;/* offset 0xB20 */
};
-#endif /* CONFIG_AM43XX */
-/* Encapsulating Display pll registers */
struct cm_dpll {
- unsigned int resv1[2];
- unsigned int clktimer2clk; /* offset 0x08 */
- unsigned int resv2[10];
- unsigned int clklcdcpixelclk; /* offset 0x34 */
+ unsigned int resv1;
+ unsigned int clktimer2clk; /* offset 0x04 */
};
+#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */
struct cm_rtc {
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h
b/arch/arm/include/asm/arch-am33xx/hardware.h
index ee5fce0..dd950e5 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -48,13 +48,6 @@
#define EMIF4_0_CFG_BASE 0x4C00
#define EMIF4_1_CFG_BASE 0x4D00
-/* PLL related registers */
-#define CM_DPLL0x44E00500
-#define CM_DEVICE 0x44E00700
-#define CM_RTC 0x44E00800
-#define CM_CEFUSE 0x44E00A00
-#define PRM_DEVICE 0x44E00F00
-
/* DDR Base address */
#define DDR_CTRL_ADDR 0x44E10E04
#define DDR_CONTROL_BASE_ADDR 0x44E11404
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index e4231c8..c67a080 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -30,6 +30,8 @@
#define PRCM_BASE 0x44E0
#define CM_PER 0x44E0
#define CM_WKUP0x44E00400
+#define CM_DPLL0x44E00500
+#define CM_RTC 0x44E00800
#define PRM_RSTCTRL(PRCM_BASE + 0x0F00)
#define PRM_RSTST (PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 3b665e6..8fee929 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -30,6 +30,8 @@
#define PRCM_BASE 0x44DF
#defineCM_WKUP 0x44DF2800
#defineCM_PER 0x44DF8800
+#define CM_DPLL0x44DF4200
+#define CM_RTC 0x44DF8500
#define PRM_RSTCTRL(PRCM_BASE + 0x4000)
#define PRM_RSTST (PRM_RSTCTRL + 4)
--
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[U-Boot] [PATCH V3 02/14] ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes Since V2:
- Updated SCRATCH SPACE address.
- Updated CONFIG_SPL_MAX_SIZE to end of image downloadable area.
arch/arm/include/asm/arch-am33xx/omap.h |2 +-
board/ti/am43xx/board.c |2 +-
include/configs/am43xx_evm.h| 129 +++
3 files changed, 29 insertions(+), 104 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 2250721..cf5f8b2 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -26,6 +26,6 @@
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END0x4034
-#define SRAM_SCRATCH_SPACE_ADDR0x4033C000
+#define SRAM_SCRATCH_SPACE_ADDR0x40337C00
#endif
#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 51b2576..dcd8cbb 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -44,7 +44,7 @@ void sdram_init(void)
int board_init(void)
{
- gd-bd-bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index d9b6c16..cad6979 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -10,127 +10,52 @@
#define __CONFIG_AM43XX_EVM_H
#define CONFIG_AM43XX
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
-#include asm/arch/omap.h
-
-#define CONFIG_DMA_COHERENT
-#define CONFIG_DMA_COHERENT_SIZE (1 20)
-
-#define CONFIG_ENV_SIZE(128 10) /* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN (1024 10)
-#define CONFIG_SYS_LONGHELP/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
-#define CONFIG_SYS_PROMPT U-Boot#
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/* commands to include */
-#include config_cmd_default.h
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_VERSION_VARIABLE
-
-/* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
-/* Clock Defines */
-#define V_OSCK 2400 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define CONFIG_CMD_ECHO
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 64
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
-
- /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_DRAM_10x8000 /* DRAM Bank #1 */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_MAX_RAM_BANK_SIZE (1024 20)/* 1GB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
- GENERATED_GBL_DATA_SIZE)
-/* Platform/Board specific defs */
-#define CONFIG_SYS_LOAD_ADDR 0x8100 /* Default load address */
-
#define CONFIG_SYS_TIMERBASE 0x4804 /* Use Timer2 */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) = 8 */
+
+#include asm/arch/omap.h
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE(-4)
-#define CONFIG_SYS_NS16550_CLK (4800)
-#define CONFIG_SYS_NS16550_COM10x44e09000 /* Base EVM has
UART0 */
+#define CONFIG_SYS_NS16550_CLK 4800
-#define CONFIG_BAUDRATE115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
-4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-#define CONFIG_ENV_IS_NOWHERE
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE 0x40300350
+#define CONFIG_SPL_MAX_SIZE(0x40337C00 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_YMODEM_SUPPORT
/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be
[U-Boot] [PATCH V3 05/14] ARM: AM43XX: board: add support for reading onboard EEPROM
From: Sekhar Nori nsek...@ti.com
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
arch/arm/include/asm/arch-am33xx/omap.h |2 ++
board/ti/am43xx/board.c | 46 +++
board/ti/am43xx/board.h | 32 +
include/configs/am43xx_evm.h|7 +
4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index cf5f8b2..7a7d91b 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -27,5 +27,7 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END0x4034
#define SRAM_SCRATCH_SPACE_ADDR0x40337C00
+#define AM4372_BOARD_NAME_STARTSRAM_SCRATCH_SPACE_ADDR
+#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
#endif
#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index dcd8cbb..4fc1a40 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,6 +9,8 @@
*/
#include common.h
+#include i2c.h
+#include asm/errno.h
#include spl.h
#include asm/arch/clock.h
#include asm/arch/sys_proto.h
@@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf(Could not probe the EEPROM at 0x%x\n,
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+sizeof(struct am43xx_board_id))) {
+ printf(Could not read the EEPROM\n);
+ return -EIO;
+ }
+
+ if (header-magic != 0xEE3355AA) {
+ /*
+* read the eeprom using i2c again,
+* but use only a 1 byte address
+*/
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+sizeof(struct am43xx_board_id))) {
+ printf(Could not read the EEPROM at 0x%x\n,
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -EIO;
+ }
+
+ if (header-magic != 0xEE3355AA) {
+ printf(Incorrect magic number (0x%x) in EEPROM\n,
+ header-magic);
+ return -EINVAL;
+ }
+ }
+
+ strncpy(am43xx_board_name, (char *)header-name, sizeof(header-name));
+ am43xx_board_name[sizeof(header-name)] = 0;
+
+ return 0;
+}
+
#ifdef CONFIG_SPL_BUILD
const struct dpll_params dpll_ddr = {
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 8ca098b..9268895 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -12,6 +12,38 @@
#ifndef _BOARD_H_
#define _BOARD_H_
+#include asm/arch/omap.h
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct am43xx_board_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+ return !strncmp(am43xx_board_name, AM43EPOS, HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+ return !strncmp(am43xx_board_name, AM43__GP, HDR_NAME_LEN);
+}
+
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
#endif
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 0f34078..4de495a 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -25,6 +25,13 @@
#define CONFIG_SYS_NS16550_REG_SIZE(-4)
#define CONFIG_SYS_NS16550_CLK 4800
+/* I2C Configuration */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE(0x40337C00 - CONFIG_SPL_TEXT_BASE)
--
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[U-Boot] [PATCH V3 04/14] ARM: AM43xx: Add extra ENV settings
Add Extra env settings.
This is derived from am335x Extra ENV settings.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
include/configs/am43xx_evm.h | 63 ++
1 file changed, 63 insertions(+)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 833e5fa..0f34078 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -72,4 +72,67 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ loadaddr=0x8020\0 \
+ fdtaddr=0x80F8\0 \
+ fdt_high=0x\0 \
+ rdaddr=0x8100\0 \
+ fdtfile=undefined\0 \
+ bootpart=0:2\0 \
+ bootdir=/boot\0 \
+ bootfile=zImage\0 \
+ console=ttyO0,115200n8\0 \
+ optargs=\0 \
+ mmcdev=0\0 \
+ mmcroot=/dev/mmcblk0p2 rw\0 \
+ mmcrootfstype=ext4 rootwait\0 \
+ ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0 \
+ ramrootfstype=ext2\0 \
+ mmcargs=setenv bootargs console=${console} \
+ ${optargs} \
+ root=${mmcroot} \
+ rootfstype=${mmcrootfstype}\0 \
+ bootenv=uEnv.txt\0 \
+ loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0 \
+ importbootenv=echo Importing environment from mmc ...; \
+ env import -t $loadaddr $filesize\0 \
+ ramargs=setenv bootargs console=${console} \
+ ${optargs} \
+ root=${ramroot} \
+ rootfstype=${ramrootfstype}\0 \
+ loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0 \
+ loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0 \
+ loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0 \
+ mmcboot=mmc dev ${mmcdev}; \
+ if mmc rescan; then \
+ echo SD/MMC found on device ${mmcdev}; \
+ if run loadbootenv; then \
+ echo Loaded environment from ${bootenv}; \
+ run importbootenv; \
+ fi; \
+ if test -n $uenvcmd; then \
+ echo Running uenvcmd ...; \
+ run uenvcmd; \
+ fi; \
+ if run loadimage; then \
+ run loadfdt; \
+ echo Booting from mmc${mmcdev} ...; \
+ run mmcargs; \
+ bootz ${loadaddr} - ${fdtaddr}; \
+ fi; \
+ fi;\0 \
+ findfdt=\
+ if test $board_name = AM43EPOS; then \
+ setenv fdtfile am43x-epos-evm.dtb; fi; \
+ if test $board_name = AM43__GP; then \
+ setenv fdtfile am437x-gp-evm.dtb; fi; \
+ if test $fdtfile = undefined; then \
+ echo WARNING: Could not determine device tree; fi; \0
+
+#define CONFIG_BOOTCOMMAND \
+ run findfdt; \
+ run mmcboot;
+
+#endif
#endif /* __CONFIG_AM43XX_EVM_H */
--
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[U-Boot] [PATCH V3 08/14] ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- Changes since V2: - Updated Boot device for CPGMAC. arch/arm/include/asm/arch-am33xx/spl.h | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 95de9aa..5cd1e95 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -13,11 +13,18 @@ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_MMC2 5 #define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_MMC2_2 0xFF +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR1 +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 7 +#define BOOT_DEVICE_MMC2 8 +#define BOOT_DEVICE_SPI10 +#define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 71 #else #define BOOT_DEVICE_XIP2 #define BOOT_DEVICE_NAND 5 -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -28,8 +35,8 @@ #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 -#define BOOT_DEVICE_MMC2_2 0xFF #endif +#define BOOT_DEVICE_MMC2_2 0xFF #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 07/14] ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index c4890f2..22963b7 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -18,6 +18,7 @@
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
const struct dpll_regs dpll_mpu_regs = {
.cm_clkmode_dpll= CM_WKUP + 0x560,
@@ -107,4 +108,7 @@ void enable_basic_clocks(void)
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+ /* Select the Master osc clk as Timer2 clock source */
+ writel(0x1, cmdpll-clktimer2clk);
}
--
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[U-Boot] [PATCH V3 06/14] ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
From: Sekhar Nori nsek...@ti.com
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.
Signed-off-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
board/ti/am43xx/board.c | 16
1 file changed, 16 insertions(+)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 4fc1a40..723d0ca 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -98,6 +98,22 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+ struct am43xx_board_id header;
+
+ if (read_eeprom(header) 0)
+ puts(Could not get board ID.\n);
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv(board_name, safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv(board_rev, safe_string);
+#endif
return 0;
}
#endif
--
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[U-Boot] [PATCH V3 09/14] ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 45 +
board/ti/am43xx/mux.c | 22 ++--
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index 0206912..98fc2b5 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -137,6 +137,51 @@ struct pad_signals {
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
};
#endif /* _MUX_AM43XX_H_ */
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 700e9a7..46bad01 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -12,8 +12,24 @@
#include board.h
static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
+ {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
{-1},
};
@@ -24,4 +40,6 @@ void enable_uart0_pin_mux(void)
void enable_board_pin_mux(void)
{
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(i2c0_pin_mux);
}
--
1.7.9.5
___
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[U-Boot] [PATCH V3 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
- Enable VTT regulator
- Configure VTP
- Configure DDR IO settings
- Disable initialization and refreshes until EMIF registers are programmed.
- Program Timing registers
- Program leveling registers
- Program PHY control and Temp alert and ZQ config registers.
- Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- No change.
arch/arm/cpu/armv7/am33xx/ddr.c |6 +-
arch/arm/cpu/armv7/omap-common/emif-common.c | 14
arch/arm/include/asm/arch-am33xx/ddr_defs.h |8 +++
arch/arm/include/asm/arch-am33xx/gpio.h | 12
arch/arm/include/asm/emif.h | 14
board/ti/am43xx/board.c | 93 +-
board/ti/am43xx/mux.c|8 +++
7 files changed, 136 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 243ec39..1ba2bb4 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int
nr)
writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
- configure_mr(nr, 0);
- configure_mr(nr, 1);
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+ configure_mr(nr, 0);
+ configure_mr(nr, 1);
+ }
}
/**
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index b0e1caa..d8a15be 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
return 0;
}
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- return (readl(emif-emif_sdram_config)
- EMIF_REG_SDRAM_TYPE_MASK) EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
u32 mr;
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index c98ab7f..646e50f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -138,6 +138,14 @@
#define LPDDR2_DATA2_IOCTRL_VALUE 0x2294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x2294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x
+#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
+#define DDR3_DATA0_IOCTRL_VALUE 0x84
+#define DDR3_DATA1_IOCTRL_VALUE 0x84
+#define DDR3_DATA2_IOCTRL_VALUE 0x84
+#define DDR3_DATA3_IOCTRL_VALUE 0x84
+
/**
* Configure DMM
*/
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h
b/arch/arm/include/asm/arch-am33xx/gpio.h
index 13a047f..a1ffd49 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -13,4 +13,16 @@
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
+#define GPIO_2222
+
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
+#define GPIO_CTRL_DISABLEMODULE_MASK (1 0)
+#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x) (1 x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x) (1 x)
#endif /* _GPIO_AM33xx_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ce6b229..b4a8c9f 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
EMIF_REG_MAJOR_REVISION_SHIFT;
}
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(emif-emif_sdram_config)
+ EMIF_REG_SDRAM_TYPE_MASK) EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 5a013e3..ed87cd9 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -16,6 +16,7 @@
#include asm/arch/sys_proto.h
#include asm/arch/mux.h
#include asm/arch/ddr_defs.h
[U-Boot] [PATCH V3 11/14] ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- New patch from V2, seperating out ioregs from sdram.
arch/arm/cpu/armv7/am33xx/ddr.c | 27 +++--
arch/arm/cpu/armv7/am33xx/emif4.c |5 ++---
board/isee/igep0033/board.c | 10 +-
board/phytec/pcm051/board.c | 12 +--
board/siemens/dxr2/board.c| 10 +-
board/siemens/pxm2/board.c| 10 +-
board/siemens/rut/board.c | 10 +-
board/ti/am335x/board.c | 40 +
board/ti/ti814x/evm.c |4 ++--
board/ti/ti816x/evm.c | 12 +++
10 files changed, 115 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fa697c7..f4eac5f 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -88,6 +88,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
*/
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
+ if (!cmd)
+ return;
+
writel(cmd-cmd0csratio, ddr_cmd_reg[nr]-cm0csratio);
writel(cmd-cmd0dldiff, ddr_cmd_reg[nr]-cm0dldiff);
writel(cmd-cmd0iclkout, ddr_cmd_reg[nr]-cm0iclkout);
@@ -108,6 +111,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
{
int i;
+ if (!data)
+ return;
+
for (i = 0; i DDR_DATA_REGS_NR; i++) {
writel(data-datardsratio0,
(ddr_data_reg[nr]+i)-dt0rdsratio0);
@@ -128,11 +134,20 @@ void config_ddr_data(const struct ddr_data *data, int nr)
}
}
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
{
- writel(val, ioctrl_reg-cm0ioctl);
- writel(val, ioctrl_reg-cm1ioctl);
- writel(val, ioctrl_reg-cm2ioctl);
- writel(val, ioctrl_reg-dt0ioctl);
- writel(val, ioctrl_reg-dt1ioctl);
+ if (!ioregs)
+ return;
+
+ writel(ioregs-cm0ioctl, ioctrl_reg-cm0ioctl);
+ writel(ioregs-cm1ioctl, ioctrl_reg-cm1ioctl);
+ writel(ioregs-cm2ioctl, ioctrl_reg-cm2ioctl);
+ writel(ioregs-dt0ioctl, ioctrl_reg-dt0ioctl);
+ writel(ioregs-dt1ioctl, ioctrl_reg-dt1ioctl);
+#ifdef CONFIG_AM43XX
+ writel(ioregs-dt2ioctrl, ioctrl_reg-dt2ioctrl);
+ writel(ioregs-dt3ioctrl, ioctrl_reg-dt3ioctrl);
+ writel(ioregs-emif_sdram_config_ext,
+ ioctrl_reg-emif_sdram_config_ext);
+#endif
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 59ad25c..adda650 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -87,7 +87,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
{
}
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr)
{
@@ -99,12 +99,11 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
- config_io_ctrl(ioctrl);
+ config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, ddrctrl-ddrckectrl);
#endif
-
/* Program EMIF instance */
config_ddr_phy(regs, nr);
set_sdram_timings(regs, nr);
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 0b8356d..2a1b75f 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -81,9 +81,17 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
void sdram_init(void)
{
- config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, ddr3_data,
+ config_ddr(400, ioregs, ddr3_data,
ddr3_cmd_ctrl_data, ddr3_emif_reg_data, 0);
}
#endif
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 034886a..f8e1951 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -96,10 +96,18 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm1ioctl =
[U-Boot] [PATCH V3 14/14] ARM: AM43xx: Add Maintainer
Adding Maintainer for AM43xx. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com --- Changes since V2: - No change. boards.cfg |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index e742746..7cd19f7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -263,7 +263,7 @@ Active arm armv7 am33xx ti am335x Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini tr...@ti.com Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini tr...@ti.com Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini tr...@ti.com -Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - +Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla lokeshvu...@ti.com Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter mpor...@ti.com Active arm armv7 am33xx ti ti816x ti816x_evm - - Active arm armv7 at91atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen voice.s...@atmel.com -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
- Configure VTP
- Configure DDR IO settings
- Disable initialization and refreshes until EMIF registers are programmed.
- Program Timing registers
- Program PHY control and Temp alert and ZQ config registers.
- Enable initialization and refreshes and configure SDRAM CONFIG register
- Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- Seperated ioregs changes into a new patch.
arch/arm/cpu/armv7/am33xx/ddr.c| 117
arch/arm/cpu/armv7/am33xx/emif4.c | 22 +++-
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
arch/arm/include/asm/arch-am33xx/cpu.h |5 +
arch/arm/include/asm/arch-am33xx/ddr_defs.h| 33 +-
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |1 +
arch/arm/include/asm/emif.h| 12 ++
board/ti/am43xx/board.c| 66 +++
8 files changed, 256 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index f4eac5f..243ec39 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -36,6 +36,71 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+ u32 mr;
+
+ mr_addr |= cs EMIF_REG_CS_SHIFT;
+ writel(mr_addr, emif_reg[nr]-emif_lpddr2_mode_reg_cfg);
+
+ mr = readl(emif_reg[nr]-emif_lpddr2_mode_reg_data);
+ debug(get_mr: EMIF1 cs %d mr %08x val 0x%x\n, cs, mr_addr, mr);
+ if (((mr 0xff00) 8) == (mr 0xff)
+ ((mr 0x00ff) 16) == (mr 0xff)
+ ((mr 0xff00) 24) == (mr 0xff))
+ return mr 0xff;
+ else
+ return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+ mr_addr |= cs EMIF_REG_CS_SHIFT;
+ writel(mr_addr, emif_reg[nr]-emif_lpddr2_mode_reg_cfg);
+ writel(mr_val, emif_reg[nr]-emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+ u32 mr_addr;
+
+ while (get_mr(nr, cs, LPDDR2_MR0) LPDDR2_MR0_DAI_MASK)
+ ;
+ set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+ set_mr(nr, cs, LPDDR2_MR1, 0x43);
+ set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+ set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+ writel(0x0, emif_reg[nr]-emif_pwr_mgmt_ctrl);
+ writel(0x0, emif_reg[nr]-emif_pwr_mgmt_ctrl_shdw);
+ writel(0x1, emif_reg[nr]-emif_iodft_tlgc);
+ writel(regs-zq_config, emif_reg[nr]-emif_zq_config);
+
+ writel(regs-temp_alert_config, emif_reg[nr]-emif_temp_alert_config);
+ writel(regs-emif_rd_wr_lvl_rmp_win,
+ emif_reg[nr]-emif_rd_wr_lvl_rmp_win);
+ writel(regs-emif_rd_wr_lvl_rmp_ctl,
+ emif_reg[nr]-emif_rd_wr_lvl_rmp_ctl);
+ writel(regs-emif_rd_wr_lvl_ctl, emif_reg[nr]-emif_rd_wr_lvl_ctl);
+ writel(regs-emif_rd_wr_exec_thresh,
+ emif_reg[nr]-emif_rd_wr_exec_thresh);
+
+ writel(regs-ref_ctrl, emif_reg[nr]-emif_sdram_ref_ctrl);
+ writel(regs-sdram_config, emif_reg[nr]-emif_sdram_config);
+
+ configure_mr(nr, 0);
+ configure_mr(nr, 1);
+}
+
/**
* Configure SDRAM
*/
@@ -72,15 +137,67 @@ void set_sdram_timings(const struct emif_regs *regs, int
nr)
writel(regs-sdram_tim3, emif_reg[nr]-emif_sdram_tim_3_shdw);
}
+void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+/*
+ * Configure EXT PHY registers
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ const u32 *ext_phy_ctrl_const_regs;
+ u32 i = 0;
+ u32 size;
+
+ ext_phy_ctrl_base = (u32 *)(regs-emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base =
+ (u32 *)(emif_reg[nr]-emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+ /*
+* external phy 6-24 registers do not change with
+* ddr frequency
+*/
+ emif_get_ext_phy_ctrl_const_regs(ext_phy_ctrl_const_regs, size);
+
+ if
[U-Boot] [PATCH V3 10/14] ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_COREVDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
Changes since V2:
- Populated DPLLs data for all OPPs and SYS CLK inputs and the correct values
to be read from eFuse.
arch/arm/cpu/armv7/am33xx/clock.c | 12 +-
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 +++
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |8 +-
arch/arm/include/asm/arch-am33xx/clock.h |7 +-
arch/arm/include/asm/arch-am33xx/cpu.h |2 +
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 13 ++
board/ti/am43xx/board.c| 138 +++-
board/ti/am43xx/board.h|4 +
board/ti/am43xx/mux.c |5 +
9 files changed, 187 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 8e5f3c6..0672798 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
static void setup_dplls(void)
{
const struct dpll_params *params;
- do_setup_dpll(dpll_core_regs, dpll_core);
- do_setup_dpll(dpll_mpu_regs, dpll_mpu);
- do_setup_dpll(dpll_per_regs, dpll_per);
+
+ params = get_dpll_core_params();
+ do_setup_dpll(dpll_core_regs, params);
+
+ params = get_dpll_mpu_params();
+ do_setup_dpll(dpll_mpu_regs, params);
+
+ params = get_dpll_per_params();
+ do_setup_dpll(dpll_per_regs, params);
writel(0x300, cmwkup-clkdcoldodpllper);
params = get_dpll_ddr_params();
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fabe259..92142c8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ return dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+ return dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+ return dpll_per;
+}
+
void setup_clocks_for_console(void)
{
clrsetbits_le32(cmwkup-wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 22963b7..97c00b4 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
.cm_idlest_dpll = CM_WKUP + 0x5A4,
.cm_clksel_dpll = CM_WKUP + 0x5AC,
.cm_div_m2_dpll = CM_WKUP + 0x5B0,
+ .cm_div_m4_dpll = CM_WKUP + 0x5B8,
};
-const struct dpll_params dpll_mpu = {
- -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
- -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_per = {
- -1, -1, -1, -1, -1, -1, -1};
-
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h
b/arch/arm/include/asm/arch-am33xx/clock.h
index 519249e..7637457 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;
-extern const struct dpll_params dpll_mpu;
-extern const struct dpll_params dpll_core;
-extern const struct dpll_params dpll_per;
-extern const struct dpll_params dpll_ddr;
extern struct cm_wkuppll *const cmwkup;
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
void do_setup_dpll(const struct dpll_regs
[U-Boot] [PATCH] powerpc/p1_p2_rdb_pc: Fix warnings for __iomem pointers
Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. p1_p2_rdb_pc.c:373:24: warning: incorrect type in assignment (different address spaces) p1_p2_rdb_pc.c:373:24:expected struct tsec_mii_mng [noderef] asn:2*regs p1_p2_rdb_pc.c:373:24:got struct tsec_mii_mng *noident Use TSEC_GET_MDIO_REGS_BASE() for the remaining mdio 'regs' initializations to remove the __iomem warnings and for consistency. Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 966abb2..5f3d6fd 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. * * SPDX-License-Identifier:GPL-2.0+ */ @@ -354,7 +354,7 @@ int board_eth_init(bd_t *bis) puts(No address specified for VSC7385 microcode.\n); #endif - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, mdio_info); -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7 V4] mmc: Enhance mmcinfo command
Once mmc initialization was failed has_init should be cleared to 0,
prepare for the next initialization.
Once mmcinfo command failed, error should be reported instead of printing
incorrect mmc device information.
Error log:
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
common/cmd_mmc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index d4225f6..5af1e92 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -115,7 +115,8 @@ static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
mmc = find_mmc_device(curr_device);
if (mmc) {
- mmc_init(mmc);
+ if (mmc_init(mmc))
+ return 1;
print_mmcinfo(mmc);
return 0;
@@ -191,9 +192,10 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
mmc-has_init = 0;
- if (mmc_init(mmc))
+ if (mmc_init(mmc)) {
+ mmc-has_init = 0;
return 1;
- else
+ } else
return 0;
} else if (strncmp(argv[1], part, 4) == 0) {
block_dev_desc_t *mmc_dev;
--
1.8.4.1
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[U-Boot] [PATCH 1/7 V4] mmc: Add some usefull macro definition
From: Haijun Zhang haijun.zh...@freescale.com
Add command class define.
Add mmc erase and secure erase define.
Add secure erase and trim support bit define.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
changes for V3:
- No changes
include/mmc.h | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/include/mmc.h b/include/mmc.h
index cb558da..08f0f3e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -53,6 +53,7 @@
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT-19
#define IN_PROGRESS-20 /* operation is in progress */
+#define NOT_SUPPORT-21 /* Operation is not support */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
@@ -105,6 +106,39 @@
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE0x6000
+/*
+ * Card Command Classes (CCC)
+ *
+ * (0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15)
+ * (and for SPI, CMD58,59)
+ * (1) Stream read commands (CMD11)
+ * (2) Block read commands (CMD16,17,18)
+ * (3) Stream write commands (CMD20)
+ * (4) Block write commands (CMD16,24,25,26,27)
+ * (5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39)
+ * (6) Able to write protect blocks (CMD28,29,30)
+ * (7) Able to lock down card (CMD16,CMD42)
+ * (8) Application specific (CMD55,56,57,ACMD*)
+ * (9) I/O mode (CMD5,39,40,52,53)
+ * (10) High speed switch (CMD6,34,35,36,37,50)
+ */
+#define CCC_BASIC (10)
+#define CCC_STREAM_READ(11)
+#define CCC_BLOCK_READ (12)
+#define CCC_STREAM_WRITE (13)
+#define CCC_BLOCK_WRITE(14)
+#define CCC_ERASE (15)
+#define CCC_WRITE_PROT (16)
+#define CCC_LOCK_CARD (17)
+#define CCC_APP_SPEC (18)
+#define CCC_IO_MODE(19)
+#define CCC_SWITCH (110)
+
+#define MMC_ERASE_ARG 0x
+#define MMC_SECURE_ERASE_ARG0x8000
+#define MMC_TRIM_ARG0x0001
+#define MMC_DISCARD_ARG 0x0003
+
#define SECURE_ERASE 0x8000
#define MMC_STATUS_MASK(~0x0206BF7F)
@@ -160,8 +194,12 @@
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_SEC_CNT212 /* RO, 4 bytes */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
+#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
+#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
+#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
+#define EXT_CSD_SEC_FEATURE_SUPPORT231 /* RO */
/*
* EXT_CSD field definitions
@@ -178,6 +216,12 @@
#define EXT_CSD_BUS_WIDTH_41 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_82 /* Card is in 8 bit mode */
+/* EXT_CSD[231] */
+#define EXT_CSD_SEC_ER_EN (10)
+#define EXT_CSD_SEC_BD_BLK_EN (12)
+#define EXT_CSD_SEC_GB_CL_EN (14)
+#define EXT_CSD_SEC_SANITIZE (16) /* v4.5 later */
+
#define EXT_CSD_BOOT_ACK_ENABLE(1 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 3)
#define EXT_CSD_PARTITION_ACCESS_ENABLE(1 0)
@@ -187,7 +231,6 @@
#define EXT_CSD_BOOT_PART_NUM(x) (x 3)
#define EXT_CSD_PARTITION_ACCESS(x)(x 0)
-
#define R1_ILLEGAL_COMMAND (1 22)
#define R1_APP_CMD (1 5)
@@ -268,10 +311,15 @@ struct mmc {
ushort rca;
char part_config;
char part_num;
+ ushort cmdclass;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
uint erase_grp_size;
+ uint erase_timeout_mult;
+ char sec_feature_support;
+ uint sec_erase_mult;
+ uint sec_erase_timeout;
u64 capacity;
u64 capacity_user;
u64 capacity_boot;
--
1.8.4.1
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[U-Boot] [PATCH 2/7 V4] mmc: Get secure erase information from card
Read command class from csd register and secure erase
support bit from ext csd register. Also calculate the erase
timeout and secure erase timeout.
If read ext csd error, error status should be returned instead of
giving some incorrect information.
Error log:
=
= mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 1-bit
=
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- update the commit message
- mask the cmdclass to 12 bit only
drivers/mmc/mmc.c | 50 +-
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index e1461a9..cf6de83 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -871,6 +871,8 @@ static int mmc_startup(struct mmc *mmc)
}
}
+ mmc-cmdclass = (cmd.response[1] 20) 0xfff;
+
/* divide frequency by 10, since the mults are 10x bigger */
freq = fbase[(cmd.response[0] 0x7)];
mult = multipliers[((cmd.response[0] 3) 0xf)];
@@ -939,7 +941,8 @@ static int mmc_startup(struct mmc *mmc)
capacity *= MMC_MAX_BLOCK_LEN;
if ((capacity 20) 2 * 1024)
mmc-capacity_user = capacity;
- }
+ } else
+ return COMM_ERR;
switch (ext_csd[EXT_CSD_REV]) {
case 1:
@@ -960,6 +963,39 @@ static int mmc_startup(struct mmc *mmc)
}
/*
+* The granularity of the erasable units is the Erase Group:The
+* smallest number of consecutive write blocks which can be
+* addressed for erase. The size of the Erase Group is card
+* specific and stored in the CSD when ERASE_GROUP_DEF is
+* disabled, and in the EXT_CSD when ERASE_GROUP_DEF is
+* enabled.
+*/
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF]) {
+ mmc-erase_grp_size =
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
+
+ mmc-erase_timeout_mult = 300 *
+ ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT];
+ } else {
+ /* Calculate the group size from the csd value. */
+ int erase_gsz, erase_gmul;
+ erase_gsz = (mmc-csd[2] 0x7c00) 10;
+ erase_gmul = (mmc-csd[2] 0x03e0) 5;
+ mmc-erase_grp_size = (erase_gsz + 1)
+ * (erase_gmul + 1);
+ }
+
+ if (ext_csd[EXT_CSD_REV] = 4) {
+ mmc-sec_feature_support =
+ ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT];
+ mmc-sec_erase_mult =
+ ext_csd[EXT_CSD_SEC_ERASE_MULT];
+ mmc-sec_erase_timeout = 300 *
+ ext_csd[EXT_CSD_SEC_ERASE_MULT] *
+ ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT];
+ }
+
+ /*
* Host needs to enable ERASE_GRP_DEF bit if device is
* partitioned. This bit will be lost every time after a reset
* or power off. This will affect erase size.
@@ -971,18 +1007,6 @@ static int mmc_startup(struct mmc *mmc)
if (err)
return err;
-
- /* Read out group size from ext_csd */
- mmc-erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
- MMC_MAX_BLOCK_LEN * 1024;
- } else {
- /* Calculate the group size from the csd value. */
- int erase_gsz, erase_gmul;
- erase_gsz = (mmc-csd[2] 0x7c00) 10;
- erase_gmul = (mmc-csd[2] 0x03e0) 5;
- mmc-erase_grp_size = (erase_gsz + 1)
- * (erase_gmul + 1);
}
/* store the partition info of emmc */
--
1.8.4.1
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[U-Boot] [PATCH 3/7 V4] mmc: Enhance erase handling procedure
This patch enhances the currently implemented erase procedure in u-boot,
Not all cards support secure erase feature. We should make a difference
between them. For eMMC card that support erase group feature, check the
the command class first, then try to align the erase group size before
we actually sending the command.
Erase sequence after this patch:
1. check if erase command is supported by the card. If not just return.
2. Check the erase range to see if it is group aligned. For mmc card the
minimum erase size should be one erase group. For SD card it is fixed
to one block(512),
3. If not, aligned the erase rang according to the erase group size.
4. Send erase command to erase card once one erase group.
5. If it's a SD card, erase with arg 0x should be send.
else if secure feature is supported, erase with arg 0x8000
(Spec eMMC 4.41).
else erase with arg 0x.(Trim and discard are ignored here)
6. Check card status after erase operation is completed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- Update the commit message
changes for V3:
- update the commit message and secure feature supporting judgment.
drivers/mmc/mmc_write.c | 68 +
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index aa2fdef..c2dafa3 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -17,6 +17,10 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
struct mmc_cmd cmd;
ulong end;
int err, start_cmd, end_cmd;
+ uint arg = 0;
+
+ if (!(mmc-cmdclass CCC_ERASE))
+ return NOT_SUPPORT;
if (mmc-high_capacity) {
end = start + blkcnt - 1;
@@ -48,8 +52,15 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
if (err)
goto err_out;
+ /* SD card only support %MMC_ERASE_ARG */
+ if (!IS_SD(mmc)
+ (mmc-sec_feature_support EXT_CSD_SEC_ER_EN))
+ arg = MMC_SECURE_ERASE_ARG;
+ else
+ arg = MMC_ERASE_ARG;
+
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = arg;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, cmd, NULL);
@@ -69,24 +80,61 @@ unsigned long mmc_berase(int dev_num, lbaint_t start,
lbaint_t blkcnt)
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
+ int res;
+ bool align = true;
if (!mmc)
return -1;
+ if (!(mmc-cmdclass CCC_ERASE)) {
+ printf(\nErase operation is not support by card\n);
+ return NOT_SUPPORT;
+ }
+
if ((start % mmc-erase_grp_size) || (blkcnt % mmc-erase_grp_size))
+ align = false;
+
+ res = start % mmc-erase_grp_size;
+ if (res) {
+ res = mmc-erase_grp_size - res;
+ start += res;
+ if (blkcnt res)
+ blkcnt -= res;
+ else {
+ printf(\nErase size smaller than Erase group
+ size [0x%x] is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+ }
+
+ res = blkcnt % mmc-erase_grp_size;
+ if (res)
+ blkcnt -= res;
+
+ if (!blkcnt) {
+ printf(\nErase size smaller than Erase group size [0x%x]
+ is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+
+ if (!align)
printf(\n\nCaution! Your devices Erase group is 0x%x\n
- The erase range would be change to
- 0x LBAF ~0x LBAF \n\n,
- mmc-erase_grp_size, start ~(mmc-erase_grp_size - 1),
- ((start + blkcnt + mmc-erase_grp_size)
- ~(mmc-erase_grp_size - 1)) - 1);
+ The erase range would be change to
+ 0x LBAF ~0x LBAF \n\n,
+ mmc-erase_grp_size, start, start + blkcnt);
+
while (blk blkcnt) {
- blk_r = ((blkcnt - blk) mmc-erase_grp_size) ?
- mmc-erase_grp_size : (blkcnt - blk);
+ if ((blkcnt - blk) = mmc-erase_grp_size)
+ blk_r = mmc-erase_grp_size;
err = mmc_erase_t(mmc, start + blk, blk_r);
- if (err)
- break;
+ if (err) {
+ printf(\nErase range from 0x LBAF ~0x LBAF
+Failed\n, start + blk, blkcnt);
+ return COMM_ERR;
+ }
[U-Boot] [PATCH 4/7 V4] mmc: Update the handling of returned erase block
If the block range was not aligned, we try to align the range size,
The block range actually erased should be less or equal to the block
range sent. If error occured during erase procedure witch part of them
being erased, users should resend the block rang to
continue erase the rest of them.
Error return, zero return, has failed.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- update commit message
changes for V3:
- no changes
common/cmd_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 67a94a7..d4225f6 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -397,6 +397,13 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
BUG();
}
+ if (state == MMC_ERASE) {
+ printf(%d blocks %s: %s\n,
+ (n = cnt) (n 0) ? n : 0, argv[1],
+ (n = cnt) (n 0) ? OK : ERROR);
+ return (n = cnt) (n 0) ? 0 : 1;
+ }
+
printf(%d blocks %s: %s\n,
n, argv[1], (n == cnt) ? OK : ERROR);
return (n == cnt) ? 0 : 1;
--
1.8.4.1
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[U-Boot] [PATCH 6/7 V4] Powerpc/esdhc: Add esdhc host version define
From: Haijun Zhang haijun.zh...@freescale.com
Esdhc host version number is incorrect in host capacity register.
The value read from was 0x14. Correct it to 0x13.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
arch/powerpc/include/asm/config_mpc85xx.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 99e16bd..15affdc 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -591,6 +591,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_FSL_SDHC_V2_3
#else
#define CONFIG_MAX_CPUS8
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
--
1.8.4.1
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[U-Boot] [PATCH 7/7 V4] powerpc/esdhc: Update esdhc command execution process
The max timeout value esdhc host can accept is about 2.69 sec.
At 50 Mhz SD_CLK period, the max busy timeout
value = 2^27 * SD_CLK period ~= 2.69 sec.
In case erase command CMD38 timeout is caculated by
mult * 300ms * num(unit by erase group), so the time one erase
group need should be more than 300ms, 5000ms should be enough.
1. Add data reset procedure for data error and command with busy error.
2. Add timeout value detecting during waiting for transfer complete.
3. Ignore Command inhibit (DAT) state when excuting CMD12.
4. Add command CRC error detecting.
5. Enlarged the timeout value used for busy state release.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- no changes
changes for V3:
- changed the '-1' to '0xU'
- redundant check command and data error after while loop.
drivers/mmc/fsl_esdhc.c | 164 +++-
1 file changed, 106 insertions(+), 58 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9f4d3a2..134a02d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -266,26 +266,36 @@ static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
uintxfertyp;
- uintirqstat;
+ uintirqstat = 0, mask;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc-priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg-esdhc_base;
+ int ret = 0, timeout;
+
+ esdhc_write32(regs-irqstat, 0xU);
+
+ sync();
+
+ mask = PRSSTAT_CICHB | PRSSTAT_CIDHB;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
+#else
+ if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ mask = ~PRSSTAT_CIDHB;
#endif
- esdhc_write32(regs-irqstat, -1);
-
- sync();
-
/* Wait for the bus to be idle */
- while ((esdhc_read32(regs-prsstat) PRSSTAT_CICHB) ||
- (esdhc_read32(regs-prsstat) PRSSTAT_CIDHB))
- ;
-
- while (esdhc_read32(regs-prsstat) PRSSTAT_DLA)
- ;
+ timeout = 1000;
+ while (esdhc_read32(regs-prsstat) mask) {
+ if (timeout == 0) {
+ printf(\nController never released inhibit bit(s).\n);
+ ret = COMM_ERR;
+ goto reset;
+ }
+ timeout--;
+ mdelay(1);
+ }
/* Wait at least 8 SD clock cycles before the next command */
/*
@@ -296,11 +306,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
/* Set up for a data transfer if we have one */
if (data) {
- int err;
-
- err = esdhc_setup_data(mmc, data);
- if(err)
- return err;
+ ret = esdhc_setup_data(mmc, data);
+ if (ret)
+ goto reset;
}
/* Figure out the transfer arguments */
@@ -325,43 +333,14 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
irqstat = esdhc_read32(regs-irqstat);
- /* Reset CMD and DATA portions on error */
- if (irqstat CMD_ERR) {
- esdhc_write32(regs-sysctl, esdhc_read32(regs-sysctl) |
- SYSCTL_RSTC);
- while (esdhc_read32(regs-sysctl) SYSCTL_RSTC)
- ;
-
- if (data) {
- esdhc_write32(regs-sysctl,
- esdhc_read32(regs-sysctl) |
- SYSCTL_RSTD);
- while ((esdhc_read32(regs-sysctl) SYSCTL_RSTD))
- ;
- }
+ if (irqstat IRQSTAT_CTOE) {
+ ret = TIMEOUT;
+ goto reset;
}
- if (irqstat IRQSTAT_CTOE)
- return TIMEOUT;
-
- if (irqstat CMD_ERR)
- return COMM_ERR;
-
- /* Workaround for ESDHC errata ENGcm03648 */
- if (!data (cmd-resp_type MMC_RSP_BUSY)) {
- int timeout = 2500;
-
- /* Poll on DATA0 line for cmd with busy signal for 250 ms */
- while (timeout 0 !(esdhc_read32(regs-prsstat)
- PRSSTAT_DAT0)) {
- udelay(100);
- timeout--;
- }
-
- if (timeout = 0) {
- printf(Timeout waiting for DAT0 to go high!\n);
- return TIMEOUT;
- }
+ if (irqstat CMD_ERR) {
+ ret = COMM_ERR;
+ goto reset;
}
/* Copy the response to the response buffer */
@@ -379,7 +358,20 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
} else
Re: [U-Boot] [PATCH 04/10] samsung: misc: move display logo function to misc.c file.
I tested this code using TRATS2 board, and it worked well.
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On
Behalf Of Przemyslaw Marczak
Sent: Wednesday, December 04, 2013 3:03 AM
To: u-boot@lists.denx.de
Cc: Przemyslaw Marczak
Subject: [U-Boot] [PATCH 04/10] samsung: misc: move display logo function
to misc.c file.
board/samsung/common/misc.c:
- move draw_logo() function from exynos_fb.c
- add get_tizen_logo_info() function call removed from board files
boards:
- update board files
- add CONFIG_MISC_INIT_R to Universal, Trats and Trats2
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Tested-by: Hyungwon Hwang human.hw...@samsung.com
---
board/samsung/common/misc.c | 39
++
board/samsung/trats/trats.c |3 ---
board/samsung/trats2/trats2.c|4 ---
board/samsung/universal_c210/universal.c |4 ---
drivers/video/exynos_fb.c| 28 -
include/configs/s5pc210_universal.h |3 +++
include/configs/trats.h |3 +++
include/configs/trats2.h |3 +++
8 files changed, 48 insertions(+), 39 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 465895b..fa97644 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -6,11 +6,50 @@
*/
#include common.h
+#include lcd.h
+#include libtizen.h
+
+#ifdef CONFIG_MISC_INIT_R
+#ifdef CONFIG_CMD_BMP
+static void draw_logo(void)
+{
+ int x, y;
+ ulong addr;
+
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(panel_info);
+#else
+ return;
+#endif
+
+ if (panel_info.vl_width = panel_info.logo_width) {
+ x = ((panel_info.vl_width - panel_info.logo_width) 1);
+ } else {
+ x = 0;
+ printf(Warning: image width is bigger than display
width\n);
+ }
+
+ if (panel_info.vl_height = panel_info.logo_height) {
+ y = ((panel_info.vl_height - panel_info.logo_height) 1);
+ } else {
+ y = 0;
+ printf(Warning: image height is bigger than display
height\n);
+ }
+
+ addr = panel_info.logo_addr;
+ bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
+#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_MISC_INIT_R
/* Common for Samsung boards */
int misc_init_r(void)
{
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 6bd106e..ce4b41f 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -767,9 +767,6 @@ void init_panel_info(vidinfo_t *vid)
vid-resolution = HD_RESOLUTION,
vid-rgb_mode = MODE_RGB_P,
-#ifdef CONFIG_TIZEN
- get_tizen_logo_info(vid);
-#endif
mipi_lcd_device.reverse_panel = 1;
strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 2442d96..73b8cc1 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -573,10 +573,6 @@ void init_panel_info(vidinfo_t *vid)
mipi_lcd_device.reverse_panel = 1;
-#ifdef CONFIG_TIZEN
- get_tizen_logo_info(vid);
-#endif
-
strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
dsim_platform_data.mipi_power = mipi_power;
dsim_platform_data.phy_enable = set_mipi_phy_ctrl; diff --git
a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 54d0e1e..166d5ee 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -484,10 +484,6 @@ void init_panel_info(vidinfo_t *vid)
vid-resolution = HD_RESOLUTION;
vid-rgb_mode = MODE_RGB_P;
-#ifdef CONFIG_TIZEN
- get_tizen_logo_info(vid);
-#endif
-
/* for LD9040. */
vid-pclk_name = 1; /* MPLL */
vid-sclk_div = 1;
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index
7d4c6e0..00a0a11 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid)
lcd_set_flush_dcache(1);
}
-#ifdef CONFIG_CMD_BMP
-static void draw_logo(void)
-{
- int x, y;
- ulong addr;
-
- if (panel_width = panel_info.logo_width) {
- x = ((panel_width - panel_info.logo_width) 1);
- } else {
- x = 0;
- printf(Warning: image width is bigger than display
width\n);
- }
-
- if (panel_height = panel_info.logo_height) {
- y = ((panel_height - panel_info.logo_height) 1) - 4;
- } else {
- y = 0;
- printf(Warning: image height is bigger than display
height\n);
- }
-
-
Re: [U-Boot] [PATCH 0/4] dfu: Provide proper Poll Timeout values
Hi Heiko, This patch series adds support for DFU's proper Poll Timeout setting. This fixes problem with dying transmission of a large files (like rootfs). Moreover some very simple clean-up patches have been included. I'd have a little request. Please check if those patches doesn't break anything on NAND related boards. Thanks in advance. Test HW: Exynos4210 - TRATS board Lukasz Majewski (4): dfu: Export allocated dfu buffer size usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value usb: f_dfu: cosmetic: Code cleanup ARM: trats: dfu: Enable default Poll Timeout for Trats board drivers/dfu/dfu.c |5 + drivers/usb/gadget/f_dfu.c | 43 ++- drivers/usb/gadget/f_dfu.h |2 ++ include/configs/trats.h| 1 + include/dfu.h |4 5 files changed, 50 insertions(+), 5 deletions(-) -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SMDK5250 not booting on latest U-boot-samsung
Hi again Rajeshwari, On Mon, 9 Dec 2013 20:35:18 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Rajeshwari, On Mon, 9 Dec 2013 13:24:28 +0530, Rajeshwari Birje rajeshwari.bi...@gmail.com wrote: Hi All, I have tried booting SMDK5250 on the latest U-boot-Samsung branch, It builds fine but does not boot. Observation: If revert the following patch it works fine: commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 Author: Albert ARIBAUD albert.u.b...@aribaud.net Date: Thu Nov 7 14:21:46 2013 +0100 arm: keep all sections in ELF file Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Kindly do let me know if any changes to be made. Can you try a debug build? Meanwhile, I have done a test branch on the u-boot-arm repo that you can use to perform tests. The branch is 'test-smdk5250-full-ELF'. You should try progressively: - test-smdk5250-full-ELF -- this is the commit before the ELF patch - test-smdk5250-full-ELF^^^ -- this limits sections that objcopy uses - test-smdk5250-full-ELF^^ -- this adds harmless sections to the ELF - test-smdk5250-full-ELF^ -- this moves .hash out of the .bin - test-smdk5250-full-ELF -- this moves .got.plt out of the .bin Please let me know which branch works and which does not. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] arm: rmobile: Add support r8a7790
Hi Nobuhiro, On Tue, 29 Oct 2013 17:39:14 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: Renesas R8A7790 is CPU with Cortex-A7 and A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Kouei Abe kouei.abe...@renesas.com Signed-off-by: Ryo Kataoka ryo.kataoka...@renesas.com Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com CC: Nobuhiro Iwamatsu iwama...@nigauri.org CC: Albert Aribaud albert.u.b...@aribaud.net --- v3: no changess. v2: no changess. Hmm, this and four other submissions from Nobuhiro have been set to Change Requested on patchwork even though there is absolutely no comment on them. Furthermore, they are also archived, and while I could have changed their state by accident, I never ever archive on patchwork. These are http://patchwork.ozlabs.org/patch/286762/ http://patchwork.ozlabs.org/patch/286760/ http://patchwork.ozlabs.org/patch/286763/ http://patchwork.ozlabs.org/patch/286761/ Therefore these did not show up on my todo list any more... Apologies for this. I've unarchived them and will go through them today. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 4/4] cmd_eeprom: bug fix for i2c read/write
On Mon, 2013-12-09 at 12:21 +0100, Heiko Schocher wrote:
I thought the v3 patch just rolls things back as patch comment states:
Changes for v3:
- It turns out that what we did before 2013-11-13
(i.e., cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM)
is still the best one, this patch simply rollback to it with coding
style fix.
Without this roll back, I think, some boards are broken now in current
mainline... so first we should go this step back.
I'd say it's very questionable. For example if you look at I2C driver
that Kuo-Jung refers to (soft_i2c) you'll find that with my patch
applied (the one you've just rolled back) it will work flawlessly
because:
1. chip address there has double applied MSB bits of offset (the first
time it gets applied in cmd_eeprom)
2. Only LSB byte of offset gets written in I2C device if addr_len = 1.
This one makes IMHO much more sense because it excludes an extra chip
address modification - so it's clear that it will be done by particular
I2C driver so people won't be confused with their expectations.
BTW what I cannot understand is why soft_i2c_read has this chip
modification part while soft_i2c_write doesn't? Is it done on purpose?
And how it actually works at all then?
Good question ... maybe currently only used on i2c reads ?
Frankly I have only 1 supposition regarding this strange state of things
in soft_i2c_write. Because without any doubts the same modification of
chip address is applicable to both read and write because it is an
integral part of data addressing.
But due to discussed a lot in this thread double chip address
modification (application of MSB bits of offset) proper support of
chip address was never implemented in soft_i2c_write. As you
correctly mentioned - real ancient code works and nobody has problems
with it. Well, just because we have current implementation of
eeprom_write that does chip address modification soft_i2c may not
have this feature in both read and write.
So I'd prefer to go with previous version of patch sent by Kuo-Jung
http://patchwork.ozlabs.org/patch/294733/
And indeed this will break functionality of currently incomplete
implementation of soft_i2c_write.
Regards,
Alexey
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Re: [U-Boot] [PATCH v2] net: Add fixed phy driver
Hi Joe On Mon, Sep 2, 2013 at 8:16 PM, Andy Fleming aflem...@gmail.com wrote: On Mon, Sep 2, 2013 at 7:30 AM, Christian Gmeiner christian.gmei...@gmail.com wrote: This patch is needed if the MAC is directly connected to a ethernet switch. In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to is configure my fixed phy/link like: #define IMX_FEC_BASEENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE MII100 #define CONFIG_ETHPRIME FEC #define CONFIG_FEC_MXC_PHYADDR 0x5 #define CONFIG_PHYLIB #define CONFIG_PHY_FIXED #define CONFIG_PHY_FIXED_SPEED SPEED_100 #define CONFIG_PHY_FIXED_DUPLEX DUPLEX_FULL Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com This doesn't work very well if you ever have more than one switch, or need more than one fixed link for some other reason. It needs to be possible to instantiate the fixed PHY interface(s) at runtime, IMO. Do you plan to implement this in a more flexible way? I am working on the final version of u-boot for two devices. If i still need it to get networking running I will send a patch. greets -- Christian Gmeiner, MSc ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] dfu: Provide proper Poll Timeout values
Hello Lukasz, How are you? Am 10.12.2013 10:54, schrieb Lukasz Majewski: Hi Heiko, This patch series adds support for DFU's proper Poll Timeout setting. This fixes problem with dying transmission of a large files (like rootfs). Moreover some very simple clean-up patches have been included. I'd have a little request. Please check if those patches doesn't break anything on NAND related boards. I had them on my list, but I am hopelessly under water ... I try to test them today ... feel free to trigger my again, if I forget it ... bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: ep9315: Return back Cirrus Logic EDB9315A board support
Hi Albert, On Mon, 2 Dec 2013 18:30:34 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi sergey.kostanbaev, On Tue, 22 Oct 2013 17:18:45 +0400, sergey.kostanbaev sergey.kostanb...@gmail.com wrote: From: Sergey Kostanbaev sergey.kostanb...@gmail.com This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev sergey.kostanb...@fairwaves.ru Cc: albert.u.b...@aribaud.net --- This patch seems not to apply cleanly on current ARM. Can you rebase and send V3? Also, I see that the patches changes some copyright lines. If you reinstate code from a given author, you must keep their copyright; if you also add significant changes, then you can also add your own copyright (or that of your company as the case may be). Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] toolchain problems when building iMX6 mx6qsabreauto (and another bootloader tool)
2013/12/4 Måns Rullgård m...@mansr.com: Robert Nelson robertcnel...@gmail.com writes: On Fri, Nov 29, 2013 at 4:28 PM, Wolfgang Denk w...@denx.de wrote: Dear Christian Gmeiner, In message cah9nwweb6s+3s4o25d7cifob9y3_7jmhosjo6o78fijquwz...@mail.gmail.com you wrote: I am running into the same problem. Me wonders which patch/change triggers this problem. I am using the same toolchain since I started to work with u-boot and it fails with the latest rc. Maybe Linaro started using a hard-float configuration only recently? For what it's worth, i just ran a git bisect on this issue today, as this compiler worked fine with v2013.10 toolchain: arm-linux-gnueabihf-gcc (crosstool-NG linaro-1.13.1-4.8-2013.10 - Linaro GCC 2013.10) 4.8.2 20131014 (prerelease) 762a88ccf8540948fbf8c31b40a29d1e0684a25b is the first bad commit commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b Author: Pierre Aubert p.aub...@staubli.com Date: Thu Sep 19 17:48:59 2013 +0200 mx6: compute PLL PFD frequencies rather than using defines That commit introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Try this patch: diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..752b3c8 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -5,6 +5,7 @@ */ #include common.h +#include div64.h #include asm/io.h #include asm/errno.h #include asm/arch/imx-regs.h @@ -123,8 +124,8 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) return 0; } - return (freq * 18) / ((div ANATOP_PFD_FRAC_MASK(pfd_num)) - ANATOP_PFD_FRAC_SHIFT(pfd_num)); + return lldiv(freq * 18, (div ANATOP_PFD_FRAC_MASK(pfd_num)) + ANATOP_PFD_FRAC_SHIFT(pfd_num)); } static u32 get_mcu_main_clk(void) -- works here too... can we get this patch into git asap? thanks -- Christian Gmeiner, MSc ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] arm: rmobile: Add support r8a7790
On Tue, 10 Dec 2013 11:17:51 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Nobuhiro, On Tue, 29 Oct 2013 17:39:14 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: Renesas R8A7790 is CPU with Cortex-A7 and A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Kouei Abe kouei.abe...@renesas.com Signed-off-by: Ryo Kataoka ryo.kataoka...@renesas.com Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com CC: Nobuhiro Iwamatsu iwama...@nigauri.org CC: Albert Aribaud albert.u.b...@aribaud.net --- v3: no changess. v2: no changess. Hmm, this and four other submissions from Nobuhiro have been set to Change Requested on patchwork even though there is absolutely no comment on them. Furthermore, they are also archived, and while I could have changed their state by accident, I never ever archive on patchwork. These are http://patchwork.ozlabs.org/patch/286762/ http://patchwork.ozlabs.org/patch/286760/ http://patchwork.ozlabs.org/patch/286763/ http://patchwork.ozlabs.org/patch/286761/ Therefore these did not show up on my todo list any more... Apologies for this. I've unarchived them and will go through them today. Scratch that -- I had my gitk search set on exact which is why I could not find the later patches which got accepted on nov 21. Re-set the above to superseded (as there was no change requests) and archived. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] dfu: Export allocated dfu buffer size
Hello Lukasz, Am 09.12.2013 16:20, schrieb Lukasz Majewski: The method for exporting size of allocated buffer is provided. It is afterwards used by USB's dfu function code. Signed-off-by: Lukasz Majewskil.majew...@samsung.com --- drivers/dfu/dfu.c |5 + include/dfu.h |1 + 2 files changed, 6 insertions(+) Tested on the dxr2 board. dfu -l dfu -U and dfu -D worked. Tested-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] usb: f_dfu: cosmetic: Code cleanup
Hello Lukasz, Am 09.12.2013 16:20, schrieb Lukasz Majewski: Code cleanup for dfu_bind_config function Signed-off-by: Lukasz Majewskil.majew...@samsung.com --- drivers/usb/gadget/f_dfu.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Tested on the dxr2 board. dfu -l dfu -U and dfu -D worked. Tested-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] ARM: trats: dfu: Enable default Poll Timeout for Trats board
Hello Lukasz, Am 09.12.2013 16:20, schrieb Lukasz Majewski: Provide default Poll Timeout value for Trats board. Signed-off-by: Lukasz Majewskil.majew...@samsung.com --- include/configs/trats.h |1 + 1 file changed, 1 insertion(+) Tested on the dxr2 board. dfu -l dfu -U and dfu -D worked. Tested-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
Hello Lukasz, Am 09.12.2013 16:20, schrieb Lukasz Majewski: It is necessary to deter the host from sending subsequent DFU_GETSTATUS request in the case of e.g. writing the buffer to medium. Here the timeout is increased when we fill up the whole buffer. This delay allows eMMC memory to perform its internal operations. Otherwise we end up with HOST's error regarding GET_STATUS receive timeout. Signed-off-by: Lukasz Majewskil.majew...@samsung.com --- drivers/usb/gadget/f_dfu.c | 39 --- drivers/usb/gadget/f_dfu.h |2 ++ include/dfu.h |3 +++ 3 files changed, 41 insertions(+), 3 deletions(-) Tested on the dxr2 board. dfu -l dfu -U and dfu -D worked. Tested-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] am335x, siemens boards: adapt default environment setting
commit 16297cfb2a20c9d89834cd9e31edac5184a777a1
Author: Mateusz Zalega m.zal...@samsung.com
Date: Fri Oct 4 19:22:26 2013 +0200
usb: new board-specific USB init interface
introduced a new parameter to the dfu command. Adapt the default environment
for the siemens boards.
Signed-off-by: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Mateusz Zalega m.zal...@samsung.com
---
include/configs/siemens-am33x-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/siemens-am33x-common.h
b/include/configs/siemens-am33x-common.h
index f37653f..b37856c 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -394,7 +394,7 @@
dfu_args=run bootargs_defaults; \
setenv bootargs ${bootargs} ; \
mtdparts default; \
- dfu nand 0; \0 \
+ dfu 0 nand 0; \0 \
dfu_alt_info= DFU_ALT_INFO_NAND \0 \
net_args=run bootargs_defaults; \
mtdparts default; \
--
1.8.3.1
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Re: [U-Boot] Creating U-Boot env image
Hi Alexey, on: Monday, December 09, 2013 3:34 PM, Alexey Smishlayev wrote: I would like to flash the environment variable values to my board, rather than setting them at the prompt. I've founa a tool mkenvimage is made specially for that. I used it to create a binary image of the U-Boot environment. However, when I flash it to my board, I get the message *** Warning - bad CRC, using default environment I thought it is due to that redundant memory wasn't written aswell, so I commented out #define CONFIG_ENV_REDUND_OFFSET in the include/configs/at91sam9g20ek.h, and tried once again, but I'm still getting this error. I can definitely see the use case in producing a complete flash image, e.g. for production use and maybe be able to select the env image from one of many depending on some factor. What you describe should definitely be possible. Are you sure that it's not something simple like a missmatch in env size? You could use U-Boots Linux fw_printenv tools and/or dd to read the flashed env image and perhaps compare it to an image saved by U-Boot to figure out what is going wrong. BR // Mats ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] serial: zynq: Remove unused #defines
Hi Michal,
On Wed, 30 Oct 2013 15:49:32 +0100, Michal Simek
michal.si...@xilinx.com wrote:
From: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/serial/serial_zynq.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 050b9c0..ff28f3c 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -21,10 +21,6 @@
#define ZYNQ_UART_MR_PARITY_NONE 0x0020 /* No parity mode */
-/* Some clock/baud constants */
-#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
-#define ZYNQ_UART_BASECLK3125000L /* master / (bdiv + 1) */
-
struct uart_zynq {
u32 control; /* Control Register [8:0] */
u32 mode; /* Mode Register [10:0] */
--
1.8.2.3
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH] serial: zynq: Remove unused #defines
On 12/10/2013 01:06 PM, Albert ARIBAUD wrote:
Hi Michal,
On Wed, 30 Oct 2013 15:49:32 +0100, Michal Simek
michal.si...@xilinx.com wrote:
From: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/serial/serial_zynq.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 050b9c0..ff28f3c 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -21,10 +21,6 @@
#define ZYNQ_UART_MR_PARITY_NONE0x0020 /* No parity mode */
-/* Some clock/baud constants */
-#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
-#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
-
struct uart_zynq {
u32 control; /* Control Register [8:0] */
u32 mode; /* Mode Register [10:0] */
--
1.8.2.3
Applied to u-boot-arm/master, thanks!
This has been already applied to Tom's tree.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [U-Boot] [PATCH] serial: zynq: Remove unused #defines
Hi Michal,
On Tue, 10 Dec 2013 13:11:47 +0100, Michal Simek mon...@monstr.eu
wrote:
On 12/10/2013 01:06 PM, Albert ARIBAUD wrote:
Hi Michal,
On Wed, 30 Oct 2013 15:49:32 +0100, Michal Simek
michal.si...@xilinx.com wrote:
From: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/serial/serial_zynq.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 050b9c0..ff28f3c 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -21,10 +21,6 @@
#define ZYNQ_UART_MR_PARITY_NONE 0x0020 /* No parity mode */
-/* Some clock/baud constants */
-#define ZYNQ_UART_BDIV15 /* Default/reset BDIV value */
-#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
-
struct uart_zynq {
u32 control; /* Control Register [8:0] */
u32 mode; /* Mode Register [10:0] */
--
1.8.2.3
Applied to u-boot-arm/master, thanks!
This has been already applied to Tom's tree.
Well then, it was in my patchwork todo in error. :)
But never mind: it'll merge just fine, that's what git is for.
Thanks,
Michal
Amicalement,
--
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Re: [U-Boot] Creating U-Boot env image
Hello, Mats, On 2013.12.10. 13:39, Mats Kärrman wrote: Hi Alexey, I can definitely see the use case in producing a complete flash image, e.g. for production use and maybe be able to select the env image from one of many depending on some factor. Yes, the use case is exactly as you described. What you describe should definitely be possible. Are you sure that it's not something simple like a missmatch in env size? I'm not sure, if that's not something simple, that's why I wrote to this list. I just don't know every little detail about using U-Boot. You could use U-Boots Linux fw_printenv tools and/or dd to read the flashed env image and perhaps compare it to an image saved by U-Boot to figure out what is going wrong. That's what I've thought also - if I just dd the environment contents to a file, can I then use it as a valid image for production? That could be the most simple way to achieve what I want. Best regards, Alexey Smishlayev ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com
---
arch/powerpc/include/asm/fsl_enet.h | 24
board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
board/freescale/mpc837xemds/mpc837xemds.c | 1 -
drivers/net/fm/dtsec.c| 1 -
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/init.c | 1 +
drivers/net/fm/memac.c| 1 -
drivers/net/fm/tgec.c | 1 -
drivers/net/fsl_mdio.c| 1 -
drivers/qe/uec.h | 1 -
include/fm_eth.h | 2 +-
include/fsl_mdio.h| 13 -
include/tsec.h| 2 +-
13 files changed, 17 insertions(+), 35 deletions(-)
delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include phy.h
-
-struct tsec_mii_mng {
- u32 miimcfg;/* MII management configuration reg */
- u32 miimcom;/* MII management command reg */
- u32 miimadd;/* MII management address reg */
- u32 miimcon;/* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind;/* MII management indication reg */
- u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
#include i2c.h
#include miiphy.h
#include phy.h
+#include fsl_mdio.h
#if defined(CONFIG_PCI)
#include pci.h
#endif
#include spd_sdram.h
#include asm/mmu.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/mmu.h
#if defined(CONFIG_OF_LIBFDT)
#include libfdt.h
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
#include i2c.h
#include asm/io.h
#include asm/fsl_mpc83xx_serdes.h
-#include asm/fsl_enet.h
#include spd_sdram.h
#include tsec.h
#include libfdt.h
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
#include common.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_dtsec.h
#include fsl_mdio.h
#include phy.h
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 43de114..c8eba4f 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
#define __FM_H__
#include common.h
+#include phy.h
#include fm_eth.h
-#include asm/fsl_enet.h
#include asm/fsl_fman.h
/* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index cd787f4..7371dbf 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_serdes.h
+#include fsl_mdio.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_tgec.h
#include fm.h
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6 @@
#include fsl_mdio.h
#include asm/io.h
#include asm/errno.h
-#include asm/fsl_enet.h
Re: [U-Boot] Creating U-Boot env image
On: Tuesday, December 10, 2013 1:32 PM, Alexey Smishlayev wrote: I'm not sure, if that's not something simple, that's why I wrote to this list. I just don't know every little detail about using U-Boot. I was thinking something like: [flash-sector-size] = [U-Boot-configured-env-size] and you must give the right number to the env image generation program. That's what I've thought also - if I just dd the environment contents to a file, can I then use it as a valid image for production? That could be the most simple way to achieve what I want. Yes, should be possible. If you're using redundant environments, you probably want to use the env copy that has 0x01 in the 5:th byte. See common/env_flash.c and include/environment.h. // Mats ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Creating U-Boot env image
Hello Mats, On 2013.12.10. 15:33, Mats Kärrman wrote: On: Tuesday, December 10, 2013 1:32 PM, Alexey Smishlayev wrote: I'm not sure, if that's not something simple, that's why I wrote to this list. I just don't know every little detail about using U-Boot. I was thinking something like: [flash-sector-size] = [U-Boot-configured-env-size] and you must give the right number to the env image generation program. That's what I've thought also - if I just dd the environment contents to a file, can I then use it as a valid image for production? That could be the most simple way to achieve what I want. Yes, should be possible. If you're using redundant environments, you probably want to use the env copy that has 0x01 in the 5:th byte. See common/env_flash.c and include/environment.h. Thank you, I will check that. How can I see if I'm compiling U-Boot with redundant environment, or not? Best regards, Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] net: tsec: Fix NULL access in case init_phy() fails
If the PHY is not recognized don't access phydev (NULL) and return 0 to signal failure. Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com --- drivers/net/tsec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e9138f0..65fb2b0 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -590,6 +590,8 @@ static int init_phy(struct eth_device *dev) tsec_configure_serdes(priv); phydev = phy_connect(priv-bus, priv-phyaddr, dev, priv-interface); + if (!phydev) + return 0; phydev-supported = supported; phydev-advertising = phydev-supported; -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: add IPL support
On Mon, Dec 09, 2013 at 04:07:29PM +0800, Kuo-Jung Su wrote: 2013/12/6 Tom Rini tr...@ti.com: On Wed, Dec 04, 2013 at 11:50:48AM +0800, Kuo-Jung Su wrote: Initial Program Loader (IPL) usually runs with .text and .rodata in ROM, while .data and .bss reside in RAM. This patch uses the AT keyword to specify load address, and a small code snippet in crt0.S to restore .data section at runtime. Example usage: Assume the target device has a 4KB ROM at 0x and a 4KB SRAM at 0xA000, the IPL/SPL config could be: #define CONFIG_SPL_MAX_SIZE 0x1000 /* text + data, no bss */ #define CONFIG_SPL_TEXT_BASE 0x #define CONFIG_SPL_DATA_BASE 0xA000 #define CONFIG_SPL_STACK 0xA0001000 Signed-off-by: Kuo-Jung Su dant...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Can you provide an example user of this functionality? Thanks. -- Tom If you're looking for a real device, unfortunately there is no such device right now, it's a shiny new design which just came out last week. If you're looking for a way for verification: 1. A real device with a NOR flash for ROM emulation. (e.g., Faraday A369 EVB) 2. A virtual device emulator. (e.g., Qemu) This is the best option for you, the Qemu model for Faraday A369 is available at my github account. Please use the command bellow to grab the source tree if necessary. $ git clone -b qemu-1.5.1 https://github.com/dantesu1218/qemu.git $ cd qemu $ ./configure --target-list=arm-softmmu $ make The example IPL code for the up-coming Faraday A369 U-boot is also available: $ git clone -b u-boot-2014.01 https://github.com/dantesu1218/u-boot.git $ cd u-boot $ make a369evb_ipl_config $ make You could also directly grab the pre-built binaries for quick verification. $ wget https://drive.google.com/file/d/0BwfiewvSmUgAMlBnUkZQb3FMVkE/edit?usp=sharing $ tar xf u-boot-a369-ipl.tar.bz2 $ cd u-boot-a369-ipl $ make What I'm asking for, is can you upstream the a369evb board? In the README in board/... you should just document how to use it via QEMU. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] bootm: Reinstate special case for standalone images
On Tue, Dec 10, 2013 at 06:37:40AM +0100, Michal Simek wrote:
On 12/07/2013 12:26 AM, Simon Glass wrote:
For standalone images, bootm had a special case where the OS boot function
was NULL but did actually exist. It was just called manually.
This was removed by commit 35fc84fa which checks for the non-existence of
this function before the special case is examined.
There is no obvious reason why standalone is handled with a special case.
Adjust the code so that standalone has a normal OS boot function. We still
need a special case for when the function returns, but at least we can
avoid the main problem.
This is intended to fix the reported:
ERROR: booting os 'U-Boot' (17) is not supported
but needs testing.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_bootm.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index ba73f57..2120aa0 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -77,6 +77,9 @@ static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[]);
static void fixup_silent_linux(void);
#endif
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+ bootm_headers_t *images);
+
static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[], bootm_headers_t *images,
ulong *os_data, ulong *os_len);
@@ -131,6 +134,7 @@ static boot_os_fn do_bootm_integrity;
#endif
static boot_os_fn *boot_os[] = {
+ [IH_TYPE_STANDALONE] = do_bootm_standalone,
This should be IH_OS_U_BOOT
#ifdef CONFIG_BOOTM_LINUX
[IH_OS_LINUX] = do_bootm_linux,
#endif
@@ -487,17 +491,18 @@ static int bootm_load_os(bootm_headers_t *images,
unsigned long *load_end,
return 0;
}
-static int bootm_start_standalone(int argc, char * const argv[])
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
char *s;
int (*appl)(int, char * const []);
/* Don't start if autostart is set to no */
if (((s = getenv(autostart)) != NULL) (strcmp(s, no) == 0)) {
- setenv_hex(filesize, images.os.image_len);
+ setenv_hex(filesize, images-os.image_len);
return 0;
}
- appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep);
+ appl = (int (*)(int, char * const []))(ulong)ntohl(images-ep);
(*appl)(argc, argv);
return 0;
}
@@ -523,14 +528,12 @@ static cmd_tbl_t cmd_bootm_sub[] = {
static int boot_selected_os(int argc, char * const argv[], int state,
bootm_headers_t *images, boot_os_fn *boot_fn)
{
- if (images-os.type == IH_TYPE_STANDALONE) {
- /* This may return when 'autostart' is 'no' */
- bootm_start_standalone(argc, argv);
- return 0;
- }
arch_preboot_os();
boot_fn(state, argc, argv, images);
- if (state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
+
+ /* Stand-alone may return when 'autostart' is 'no' */
+ if (images-os.type == IH_TYPE_STANDALONE ||
+ state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
return 0;
bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
#ifdef DEBUG
But anyway I have tested this in zynq.
Image generation by this command
./tools/mkimage -n hello -A arm -O u-boot -T standalone -C none -a c10
-d examples/standalone/hello_world.bin -v /tftpboot/hello.ub
on 2013.04 is behaviour
U-Boot bootm
## Booting kernel from Legacy Image at 1000 ...
Image Name: hello
Image Type: ARM U-Boot Standalone Program (uncompressed)
Data Size:594 Bytes = 594 Bytes
Load Address: 0c10
Entry Point: 0c10
Verifying Checksum ... OK
Loading Standalone Program ... OK
OK
Example expects ABI version 6
Actual U-Boot ABI version 6
Hello World
argc = 0
data abort
MAYBE you should read doc/README.arm-unaligned-accesses
pc : [3ffd8e74]lr : [3ffd9574]
sp : 3fbadc20 ip : 0043 fp : 3ffea2c4
r10: r9 : 3fbaddd4 r8 : 3fbadf40
r7 : 0c100232 r6 : ea14 r5 : r4 : 3fbadcaf
r3 : ea14 r2 : ea14 r1 : ea13 r0 : ea14
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
on the latestgreatest with fix above
U-Boot 2013.10-00793-gc9ca75a-dirty (Dec 10 2013 - 06:30:03)
I2C: ready
Memory: ECC disabled
DRAM: 1 GiB
MMC: zynq_sdhci: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: Gem.e000b000
Hit any key to stop autoboot: 0
zynq-uboot set serverip
Re: [U-Boot] [PATCH 0/4] dfu: Provide proper Poll Timeout values
On Monday, December 09, 2013 at 04:20:12 PM, Lukasz Majewski wrote: This patch series adds support for DFU's proper Poll Timeout setting. This fixes problem with dying transmission of a large files (like rootfs). Moreover some very simple clean-up patches have been included. Test HW: Exynos4210 - TRATS board Lukasz Majewski (4): dfu: Export allocated dfu buffer size usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value usb: f_dfu: cosmetic: Code cleanup ARM: trats: dfu: Enable default Poll Timeout for Trats board drivers/dfu/dfu.c |5 + drivers/usb/gadget/f_dfu.c | 43 ++- drivers/usb/gadget/f_dfu.h | 2 ++ include/configs/trats.h|1 + include/dfu.h |4 5 files changed, 50 insertions(+), 5 deletions(-) Applied all, thanks Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fuelgauge: max17042: fix i2c read issue which causes infinity loop.
Issues:
- reading i2c data by passing u16 pointer causes errors in read data.
- max17042 status register fields have not only Power On Reset meaning
so using proper mask is required.
Changes:
- read i2c data to type u32 instead of u16 - avoids buffer overflow
- compare FG status register using mask not just one bit value
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
drivers/power/fuel_gauge/fg_max17042.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/power/fuel_gauge/fg_max17042.c
b/drivers/power/fuel_gauge/fg_max17042.c
index c285747..2cbf8cf 100644
--- a/drivers/power/fuel_gauge/fg_max17042.c
+++ b/drivers/power/fuel_gauge/fg_max17042.c
@@ -28,11 +28,14 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16
*data, int num)
static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num)
{
+ unsigned int dat = 0;
int ret = 0;
int i;
- for (i = 0; i num; i++, addr++)
- ret |= pmic_reg_read(p, addr, (u32 *) (data + i));
+ for (i = 0; i num; i++, addr++) {
+ ret |= pmic_reg_read(p, addr, dat);
+ *(data + i) = (u16) dat;
+ }
return ret;
}
@@ -178,7 +181,7 @@ static int power_check_battery(struct pmic *p, struct pmic
*bat)
ret |= pmic_reg_read(p, MAX17042_STATUS, val);
debug(fg status: 0x%x\n, val);
- if (val == MAX17042_POR)
+ if (val MAX17042_POR)
por_fuelgauge_init(p);
ret |= pmic_reg_read(p, MAX17042_VERSION, val);
--
1.7.9.5
___
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[U-Boot] patchwork not responding
Is it just me not able to access this server, or the server is down for some reason? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patchwork not responding
On Tue, Dec 10, 2013 at 10:24 AM, York Sun york...@freescale.com wrote: Is it just me not able to access this server, or the server is down for some reason? I am also unable to access patchwork. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
On Tue, 2013-12-10 at 13:12 +0530, Prabhakar Kushwaha wrote: CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Please add CONFIG_SPL_NAND_BOOT to README. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote: On 12/9/2013 11:21 PM, Scott Wood wrote: On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote: On 12/7/2013 6:51 AM, Scott Wood wrote: Prabhakar, why did you extend that to other uses? Why are both entries ifdeffed here, but only the 0xe000 entry on existing boards? both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does not have this. i dont think NOR boot tested after this patch. NOR boot will not work after applying this patch. So what happens if there's a speculative access to the non-ifdeffed 0xf000 when we're not booting from that (e.g. ramboot, SPL payload, SD/SPI...)? If I understand the question correctly, Ideally ramboot, SPL payload, SD/SPI should not make access to this address. They assumed to be running from DDR whose TLB has already been created by IBR, or First stage boot loader. Speculative accesses don't come (directly) from software. They are initiated by the hardware and are not predictable. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board_f: explicitly disable console on early boot
On Thu, 2013-11-28 at 13:55 +0400, Alexey Brodkin wrote: On Wed, 2013-11-27 at 18:43 -0700, Simon Glass wrote: I have a similar patch locally, but it actually does memset() on the whole structure. Some archs handle this setup differently. For example both ARM and x86 now allocate it in low level code so there is no need for the board_f code to allocate a global data structure. Another approach would be to move zero_global_data from init_sequence_f to the very beginning of board_init_f right after global data allocation. But IMHO it is a bit more significant modification so I decided to start from the simplest fix that resolves a particular issue I see. Any chance for this patch to be applied or described problem has to be resolved/worked-around in any other way? -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-arm/master
Hi Tom, The following changes since commit f44483b57c49282299da0e5c10073b909cdad979: Merge branch 'serial' of git://git.denx.de/u-boot-microblaze (2013-12-02 08:48:02 -0500) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to f15ea6e1d67782a1626d4a4922b6c20e380085e5: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-12-10 22:23:59 +0100) Note: two in-merge fixes were necessary. They are listed in f15ea6e1. Albert ARIBAUD (7): Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' arm: keep all sections in ELF file Merge branch 'u-boot/master' into 'u-boot-arm/master' Andreas Bießmann (10): video: remove AT91 legacy API from bus_vcxk i2c: switch from AT91 legacy to ATMEL legacy at91sam9m10g45ek: remove unused CONFIG_AT91_LEGACY snapper9260: remove unused AT91_LEGACY net: remove unused CONFIG_AT91_LEGACY at91: remove all occourances of CONFIG_AT91_LEGACY at91: add new gpio pin definitions at91: redefine legacy GPIO PIN_BASE at91: nand: switch atmel_nand to generic GPIO API at91: switch coloured LED to gpio API Andrew Bradford (1): am335x_evm: Fix CONS_INDEX numbering Bo Shen (8): arm: atmel: sama5d3: correct the ID for DBGU and PIT arm: at91: pm9261: remove undefined bit in mckr arm: atmel: sama5d3: correct the error define of DIV arm: atmel: sama5d3: the offset of MULA is 18 arm: atmel: sama5d3: early enable PIO peripherals arm: atmel: add ddr2 initialization function arm: atmel: sama5d3: spl boot from fat fs SD card arm: atmel: sam9m10g45ek: let CONFIG_SYS_NO_FLASH at proper position Chin Liang See (1): socfpga: Adding Freeze Controller driver Hardik Patel (1): pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAM Heiko Schocher (6): bootcount: store bootcount var in environment arm, am33x: make RTC32K OSC enable configurable usb, g_dnl: make bcdDevice value configurable arm926ejs, at91: add common phy_reset function arm, at91: add Siemens board taurus and axm arm, at91: add siemens corvus board Ian Campbell (1): vexpress: use correct timer address on extended memory map systems Igor Grinberg (1): cm-t35: use gpio_led driver for status led Ilya Ledvich (3): cm_t335: add cm_t335 board support cm_t335: add support for status LED cm_t335: add support for pca9555 i2c gpio extender Jaehoon Chung (3): arm: exynos: fix set_mmc_clk for exynos4x12 arm: exynos/goni: fix the return type for s5p_mmc_init arm: exynos: remove the unused define. Jens Scharsig (BuS Elektronik) (1): arm: atmel: eb_cpux9k2: config clean up Lars Poeschel (1): pcm051: Support for revision 3 Lokesh Vutla (1): ARM: OMAP5+: Remove unnecessary EFUSE settings Lubomir Popov (1): ARM: OMAP4: Fix bug in omap4470_volts struct Luka Perkov (1): config: arm: exynos5250: remove duplicate defines Masahiro Yamada (1): ARM: align MVBAR on 32 byte boundary Mateusz Kulikowski (1): arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263) Matt Porter (1): boards.cfg: update email address for ti814x_evm maintainer Michael Trimarchi (2): arm: omap3: Add uart4 omap3 adddress arm: omap3: Enable clocks for peripherals only if they are used Michal Simek (1): arm: zynq: Do not remap OCM to high address Minkyu Kang (3): arm: exynos: fix the align for exynos4_power structure arm: exynos: adds ifdef for spi boot arm: arndale: disable spi boot Nobuhiro Iwamatsu (7): arm: rmobile: Move lowlevel_init.o to taget of each CPU arm: rmobile: Add support R8A7790 arm: rmobile: Add support lager board arm: rmobile: Add support R8A7791 arm: rmobile: Add support koelsch board arm: kzm9g: Fix undefined reference to `__aeabi_uldivmod' error arm: rmobile: Remove config.mk Oleg Kosheliev (2): ARMV7: OMAP4: Add struct for twl603x data ARMV7: OMAP4: Add twl6032 support Piotr Wilczek (7): driver:usb:s3c_udc: add support for Exynos4x12 trats2: enable ums support on Trats2 trats2: enable dfu and thor protocol for Tizen download board: trats2: remove unused defines from config file board: trats2: fix environmental variables board: trats2: fix access to samsung registers board: trats2: update Tizen partition definitions Przemyslaw Marczak (1): trats: usb: Add usb_cable_connected() function Radhey Shyam Pandey (1):
Re: [U-Boot] [PATCH] board_f: explicitly disable console on early boot
On 10 December 2013 14:47, Alexey Brodkin alexey.brod...@synopsys.com wrote: On Thu, 2013-11-28 at 13:55 +0400, Alexey Brodkin wrote: On Wed, 2013-11-27 at 18:43 -0700, Simon Glass wrote: I have a similar patch locally, but it actually does memset() on the whole structure. Some archs handle this setup differently. For example both ARM and x86 now allocate it in low level code so there is no need for the board_f code to allocate a global data structure. Another approach would be to move zero_global_data from init_sequence_f to the very beginning of board_init_f right after global data allocation. But IMHO it is a bit more significant modification so I decided to start from the simplest fix that resolves a particular issue I see. Any chance for this patch to be applied or described problem has to be resolved/worked-around in any other way? I say apply it. Tom would you like me to do a pull request, or do you want to pick it up? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] spl/Makefile: merge LIBS-y += arch/$(ARCH)/imx-common
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- spl/Makefile | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/spl/Makefile b/spl/Makefile index 2a787af..25f8b3c 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -90,17 +90,13 @@ LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ -ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) LIBS-y += arch/$(ARCH)/imx-common/ endif LIBS-$(CONFIG_ARM) += arch/arm/cpu/ LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ -ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) -LIBS-y += arch/$(ARCH)/imx-common/ -endif - LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) # Add GCC lib -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 4/4] cmd_eeprom: bug fix for i2c read/write
2013/12/10 Alexey Brodkin alexey.brod...@synopsys.com:
On Mon, 2013-12-09 at 12:21 +0100, Heiko Schocher wrote:
I thought the v3 patch just rolls things back as patch comment states:
Changes for v3:
- It turns out that what we did before 2013-11-13
(i.e., cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM)
is still the best one, this patch simply rollback to it with coding
style fix.
Without this roll back, I think, some boards are broken now in current
mainline... so first we should go this step back.
I'd say it's very questionable. For example if you look at I2C driver
that Kuo-Jung refers to (soft_i2c) you'll find that with my patch
applied (the one you've just rolled back) it will work flawlessly
because:
1. chip address there has double applied MSB bits of offset (the first
time it gets applied in cmd_eeprom)
2. Only LSB byte of offset gets written in I2C device if addr_len = 1.
But if addr_len = 2, everything goes wrong. This is the real problem here...
This one makes IMHO much more sense because it excludes an extra chip
address modification - so it's clear that it will be done by particular
I2C driver so people won't be confused with their expectations.
BTW what I cannot understand is why soft_i2c_read has this chip
modification part while soft_i2c_write doesn't? Is it done on purpose?
And how it actually works at all then?
Good question ... maybe currently only used on i2c reads ?
Frankly I have only 1 supposition regarding this strange state of things
in soft_i2c_write. Because without any doubts the same modification of
chip address is applicable to both read and write because it is an
integral part of data addressing.
But due to discussed a lot in this thread double chip address
modification (application of MSB bits of offset) proper support of
chip address was never implemented in soft_i2c_write. As you
correctly mentioned - real ancient code works and nobody has problems
with it. Well, just because we have current implementation of
eeprom_write that does chip address modification soft_i2c may not
have this feature in both read and write.
So I'd prefer to go with previous version of patch sent by Kuo-Jung
http://patchwork.ozlabs.org/patch/294733/
And indeed this will break functionality of currently incomplete
implementation of soft_i2c_write.
No, it will works just fine.
1. eeprom_read:
The overflowed address was shifted to chip address by cmd_eeprom.c, and then
the same operations would be repeated by soft_i2c.c, but it's no harm
to do a OR operation twice
on the same bits, so everything is all right.
2. eeprom_write:
The overflowed address was shifted to chip address by cmd_eeprom.c,
and get passed to soft_i2c.c
without further modification. So everything is all right.
The 'CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW' in soft_i2c.c is actually a
redundant code snippet.
And it would be better to move/copied its comment to cmd_eeprom.c.
Which means if we don't rollback, none of the EEPROMs with addr_len
1 will work on u-boot.
And this rollback actually does no harm to the EEPROMs with addr_len = 1 or 2.
P.S: The designware_i2c.c should work just fine with this rollback, too
--
Best wishes,
Kuo-Jung Su
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Re: [U-Boot] [PATCH v3 1/2] arm: rmobile: Add support r8a7790
Hi, Albert. Since these patches were taken into your repository from u-boot-sh/rmobile, I have updated the patchwork. This was not a correct change. Sorry about this, and thanks for your work. Best regards, Nobuhiro 2013/12/10 Albert ARIBAUD albert.u.b...@aribaud.net: On Tue, 10 Dec 2013 11:17:51 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Nobuhiro, On Tue, 29 Oct 2013 17:39:14 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: Renesas R8A7790 is CPU with Cortex-A7 and A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Kouei Abe kouei.abe...@renesas.com Signed-off-by: Ryo Kataoka ryo.kataoka...@renesas.com Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com CC: Nobuhiro Iwamatsu iwama...@nigauri.org CC: Albert Aribaud albert.u.b...@aribaud.net --- v3: no changess. v2: no changess. Hmm, this and four other submissions from Nobuhiro have been set to Change Requested on patchwork even though there is absolutely no comment on them. Furthermore, they are also archived, and while I could have changed their state by accident, I never ever archive on patchwork. These are http://patchwork.ozlabs.org/patch/286762/ http://patchwork.ozlabs.org/patch/286760/ http://patchwork.ozlabs.org/patch/286763/ http://patchwork.ozlabs.org/patch/286761/ Therefore these did not show up on my todo list any more... Apologies for this. I've unarchived them and will go through them today. Scratch that -- I had my gitk search set on exact which is why I could not find the later patches which got accepted on nov 21. Re-set the above to superseded (as there was no change requests) and archived. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fuelgauge: max17042: fix i2c read issue which causes infinity loop.
Dear Przemyslaw Marczak,
On 11/12/13 00:19, Przemyslaw Marczak wrote:
Issues:
- reading i2c data by passing u16 pointer causes errors in read data.
- max17042 status register fields have not only Power On Reset meaning
so using proper mask is required.
Changes:
- read i2c data to type u32 instead of u16 - avoids buffer overflow
- compare FG status register using mask not just one bit value
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
drivers/power/fuel_gauge/fg_max17042.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/power/fuel_gauge/fg_max17042.c
b/drivers/power/fuel_gauge/fg_max17042.c
index c285747..2cbf8cf 100644
--- a/drivers/power/fuel_gauge/fg_max17042.c
+++ b/drivers/power/fuel_gauge/fg_max17042.c
@@ -28,11 +28,14 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16
*data, int num)
static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num)
{
+ unsigned int dat = 0;
initial value is unnecessary.
int ret = 0;
int i;
- for (i = 0; i num; i++, addr++)
- ret |= pmic_reg_read(p, addr, (u32 *) (data + i));
+ for (i = 0; i num; i++, addr++) {
+ ret |= pmic_reg_read(p, addr, dat);
I think, need check return value.
if failed to read then you should not update data.
and such a case, do we need to read end of num?
why don't you return error directly?
I think this code should be..
ret = pmic_reg_read(p, addr, dat);
if (ret)
return ret;
*(data + i) = (u16)dat;
+ *(data + i) = (u16) dat;
please remove space between ) and dat.
+ }
return ret;
then it can be return 0; and initial value ( = 0) is unnecessary.
}
@@ -178,7 +181,7 @@ static int power_check_battery(struct pmic *p, struct
pmic *bat)
ret |= pmic_reg_read(p, MAX17042_STATUS, val);
debug(fg status: 0x%x\n, val);
- if (val == MAX17042_POR)
+ if (val MAX17042_POR)
if (val MAX17042_POR) ?
por_fuelgauge_init(p);
ret |= pmic_reg_read(p, MAX17042_VERSION, val);
Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH] arm: add IPL support
2013/12/10 Tom Rini tr...@ti.com: On Mon, Dec 09, 2013 at 04:07:29PM +0800, Kuo-Jung Su wrote: 2013/12/6 Tom Rini tr...@ti.com: On Wed, Dec 04, 2013 at 11:50:48AM +0800, Kuo-Jung Su wrote: Initial Program Loader (IPL) usually runs with .text and .rodata in ROM, while .data and .bss reside in RAM. This patch uses the AT keyword to specify load address, and a small code snippet in crt0.S to restore .data section at runtime. Example usage: Assume the target device has a 4KB ROM at 0x and a 4KB SRAM at 0xA000, the IPL/SPL config could be: #define CONFIG_SPL_MAX_SIZE 0x1000 /* text + data, no bss */ #define CONFIG_SPL_TEXT_BASE 0x #define CONFIG_SPL_DATA_BASE 0xA000 #define CONFIG_SPL_STACK 0xA0001000 Signed-off-by: Kuo-Jung Su dant...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Can you provide an example user of this functionality? Thanks. -- Tom If you're looking for a real device, unfortunately there is no such device right now, it's a shiny new design which just came out last week. If you're looking for a way for verification: 1. A real device with a NOR flash for ROM emulation. (e.g., Faraday A369 EVB) 2. A virtual device emulator. (e.g., Qemu) This is the best option for you, the Qemu model for Faraday A369 is available at my github account. Please use the command bellow to grab the source tree if necessary. $ git clone -b qemu-1.5.1 https://github.com/dantesu1218/qemu.git $ cd qemu $ ./configure --target-list=arm-softmmu $ make The example IPL code for the up-coming Faraday A369 U-boot is also available: $ git clone -b u-boot-2014.01 https://github.com/dantesu1218/u-boot.git $ cd u-boot $ make a369evb_ipl_config $ make You could also directly grab the pre-built binaries for quick verification. $ wget https://drive.google.com/file/d/0BwfiewvSmUgAMlBnUkZQb3FMVkE/edit?usp=sharing $ tar xf u-boot-a369-ipl.tar.bz2 $ cd u-boot-a369-ipl $ make What I'm asking for, is can you upstream the a369evb board? In the README in board/... you should just document how to use it via QEMU. Thanks! Got it, thanks. I will make it a part of Faraday A36x patch series, and resend it later. -- Best wishes, Kuo-Jung Su ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Sorry for late reply since the email system crash.
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Sent: Saturday, December 07, 2013 9:22 AM
To: Liu Po-B43644
Cc: u-boot@lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579
Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot
support base on TPL/SPL
On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
diff --git a/board/freescale/c29xpcie/spl.c
b/board/freescale/c29xpcie/spl.c new file mode 100644 index
000..7bc8ce1
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,73 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include ns16550.h
+#include malloc.h
+#include mmc.h
+#include nand.h
+#include i2c.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(gur-porpllsr) MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio = 1;
+ gd-bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd-bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0,
+CONFIG_SPL_RELOC_TEXT_BASE); }
+
+void board_init_r(gd_t *gd, ulong dest_addr) {
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd-bd = bd;
+ bd-bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd-bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+(uchar *)CONFIG_ENV_ADDR);
+gd-env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd-env_valid = 1;
+
+ i2c_init_all();
+
+ gd-ram_size = initdram(0);
+
+ puts(\nTertiary program loader running in sram...);
Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or was it
a copy/paste error that you added things to the board config file for
SD/SPI (after all, the subject line says it's a NAND patch)?
Yes, I assume this patch only for NAND boot for C29XPCIE.
+void board_init_r(gd_t *gd, ulong dest_addr) {
+ puts(\nSecond program loader running in sram...);
I see that this isn't new to this patch, but we ought to be consistent
and either change this to secondary, or change tertiary to third.
It's also probably too verbose... Simply saying SPL\n or TPL\n
would suffice to indicate progress and verify that console output is
working (if nothing is printed, then that path doesn't get tested in the
absence of a load error).
diff --git a/board/freescale/c29xpcie/tlb.c
b/board/freescale/c29xpcie/tlb.c index 84844ee..11f8a37 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xf000, 0xf000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+ SET_TLB_ENTRY(1, 0xe000, 0xe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
CONFIG_SPL_NAND_MINIMAL should not exist. It was introduced by accident
after a different approach was chosen in patch review (and even then,
this wasn't what it meant).
Prabhakar, why did you extend that to other uses? Why are both entries
ifdeffed here, but only the 0xe000 entry on existing boards?
If this needs to be ifdeffed (and it probably does, if only to avoid
possible speculative instruction fetches), use (and document)
CONFIG_SPL_NAND_BOOT.
I'll replace the CONFIG_SPL_NAND_MINIMAL with CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
No.
SET_TLB_ENTRY(1,
Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
-Original Message- From: Scott Wood [mailto:scottw...@freescale.com] Sent: Wednesday, December 11, 2013 2:20 AM To: Kushwaha Prabhakar-B32579 Cc: Liu Po-B43644; u-boot@lists.denx.de; Sun York-R58495 Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote: On 12/9/2013 11:21 PM, Scott Wood wrote: On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote: On 12/7/2013 6:51 AM, Scott Wood wrote: Prabhakar, why did you extend that to other uses? Why are both entries ifdeffed here, but only the 0xe000 entry on existing boards? both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does not have this. i dont think NOR boot tested after this patch. NOR boot will not work after applying this patch. So what happens if there's a speculative access to the non-ifdeffed 0xf000 when we're not booting from that (e.g. ramboot, SPL payload, SD/SPI...)? If I understand the question correctly, Ideally ramboot, SPL payload, SD/SPI should not make access to this address. They assumed to be running from DDR whose TLB has already been created by IBR, or First stage boot loader. Speculative accesses don't come (directly) from software. They are initiated by the hardware and are not predictable. Remove the: -#ifdef CONFIG_SPL_NAND_MINIMAL - SET_TLB_ENTRY(1, 0xf000, 0xf000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), - SET_TLB_ENTRY(1, 0xe000, 0xe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_4K, 1), -#endif Do not effect the NAND/NOR boot after I test on C29XPCIE. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7 V3] mmc: Enhance erase handling procedure
Hi
On Tue, Dec 10, 2013 at 6:39 AM, Haijun Zhang
haijun.zh...@freescale.com wrote:
This patch enhances the currently implemented erase procedure in u-boot,
which has the following problems/missing features...
Erass sequence:
1. check if erase command is support by card. If not return.
2. Check the erase range to see if it was aligned. The min erase size
should be one erase group. SD card it was one block(512), mmc card
it should be one erase group.
3. If not, aligned the erase rang according to the erase group size.
4. Send erase command to erase card once one erase group.
5. If it was SD card, erase with arg 0x should be send.
else if support secure feature, erase with arg 0x8000(Spec eMMC 4.41).
else erase with arg 0x.(Trim and discard is ingnored here)
6. Check card status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- update the commit message and secure feature supporting judgment.
drivers/mmc/mmc_write.c | 68
+
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index aa2fdef..c2dafa3 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -17,6 +17,10 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
struct mmc_cmd cmd;
ulong end;
int err, start_cmd, end_cmd;
+ uint arg = 0;
+
+ if (!(mmc-cmdclass CCC_ERASE))
+ return NOT_SUPPORT;
if (mmc-high_capacity) {
end = start + blkcnt - 1;
@@ -48,8 +52,15 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start,
lbaint_t blkcnt)
if (err)
goto err_out;
+ /* SD card only support %MMC_ERASE_ARG */
+ if (!IS_SD(mmc)
+ (mmc-sec_feature_support EXT_CSD_SEC_ER_EN))
+ arg = MMC_SECURE_ERASE_ARG;
+ else
+ arg = MMC_ERASE_ARG;
+
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = arg;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, cmd, NULL);
@@ -69,24 +80,61 @@ unsigned long mmc_berase(int dev_num, lbaint_t start,
lbaint_t blkcnt)
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
+ int res;
+ bool align = true;
if (!mmc)
return -1;
+ if (!(mmc-cmdclass CCC_ERASE)) {
+ printf(\nErase operation is not support by card\n);
+ return NOT_SUPPORT;
+ }
+
if ((start % mmc-erase_grp_size) || (blkcnt % mmc-erase_grp_size))
+ align = false;
+
+ res = start % mmc-erase_grp_size;
+ if (res) {
...
Well I don't know if it works
end = start + bkcnt;
start += group_size - (start % group_size);
end -= (end % group_size);
if (start = end)
printf(invalid size\n);
But why not somenthing like this?
Michael
+ start += mmc-erase_grp_size - res;
if (res blkcnt) {
}
+ if (blkcnt res)
+ blkcnt -= res;
+ else {
+ printf(\nErase size smaller than Erase group
+ size [0x%x] is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+ }
+
+ res = (blkcnt - res) % mmc-erase_grp_size;
+ if (res)
+ blkcnt -= res;
+
+ if (!blkcnt) {
+ printf(\nErase size smaller than Erase group size [0x%x]
+ is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+
+ if (!align)
printf(\n\nCaution! Your devices Erase group is 0x%x\n
- The erase range would be change to
- 0x LBAF ~0x LBAF \n\n,
- mmc-erase_grp_size, start ~(mmc-erase_grp_size -
1),
- ((start + blkcnt + mmc-erase_grp_size)
- ~(mmc-erase_grp_size - 1)) - 1);
+ The erase range would be change to
+ 0x LBAF ~0x LBAF \n\n,
+ mmc-erase_grp_size, start, start + blkcnt);
+
while (blk blkcnt) {
- blk_r = ((blkcnt - blk) mmc-erase_grp_size) ?
- mmc-erase_grp_size : (blkcnt - blk);
+ if ((blkcnt - blk) = mmc-erase_grp_size)
+ blk_r = mmc-erase_grp_size;
err = mmc_erase_t(mmc, start + blk, blk_r);
- if (err)
- break;
+ if (err) {
+ printf(\nErase range from 0x LBAF
Re: [U-Boot] [PATCH 3/7 V3] mmc: Enhance erase handling procedure
Regards Thanks.
-- Haijun
-Original Message-
From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
Sent: Wednesday, December 11, 2013 11:10 AM
To: Zhang Haijun-B42677
Cc: pa...@antoniou-consulting.com; u-boot@lists.denx.de; Xie Xiaobo-
R63061; Sun York-R58495; Tom Rini; Stefano Babic;
rjbar...@rockwellcollins.com; jh80.ch...@samsung.com
Subject: Re: [PATCH 3/7 V3] mmc: Enhance erase handling procedure
Hi
On Tue, Dec 10, 2013 at 6:39 AM, Haijun Zhang haijun.zh...@freescale.com
wrote:
This patch enhances the currently implemented erase procedure in
u-boot, which has the following problems/missing features...
Erass sequence:
1. check if erase command is support by card. If not return.
2. Check the erase range to see if it was aligned. The min erase size
should be one erase group. SD card it was one block(512), mmc card it
should be one erase group.
3. If not, aligned the erase rang according to the erase group size.
4. Send erase command to erase card once one erase group.
5. If it was SD card, erase with arg 0x should be send.
else if support secure feature, erase with arg 0x8000(Spec eMMC
4.41).
else erase with arg 0x.(Trim and discard is ingnored here)
6. Check card status after erase.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- update the commit message and secure feature supporting
judgment.
drivers/mmc/mmc_write.c | 68
+
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index
aa2fdef..c2dafa3 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -17,6 +17,10 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong
start, lbaint_t blkcnt)
struct mmc_cmd cmd;
ulong end;
int err, start_cmd, end_cmd;
+ uint arg = 0;
+
+ if (!(mmc-cmdclass CCC_ERASE))
+ return NOT_SUPPORT;
if (mmc-high_capacity) {
end = start + blkcnt - 1; @@ -48,8 +52,15 @@ static
ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
if (err)
goto err_out;
+ /* SD card only support %MMC_ERASE_ARG */
+ if (!IS_SD(mmc)
+ (mmc-sec_feature_support EXT_CSD_SEC_ER_EN))
+ arg = MMC_SECURE_ERASE_ARG;
+ else
+ arg = MMC_ERASE_ARG;
+
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = arg;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, cmd, NULL); @@ -69,24 +80,61 @@
unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
int timeout = 1000;
+ int res;
+ bool align = true;
if (!mmc)
return -1;
+ if (!(mmc-cmdclass CCC_ERASE)) {
+ printf(\nErase operation is not support by card\n);
+ return NOT_SUPPORT;
+ }
+
if ((start % mmc-erase_grp_size) || (blkcnt %
mmc-erase_grp_size))
+ align = false;
+
+ res = start % mmc-erase_grp_size;
+ if (res) {
...
Well I don't know if it works
end = start + bkcnt;
start += group_size - (start % group_size);
end -= (end % group_size);
if (start = end)
printf(invalid size\n);
But why not somenthing like this?
Michael
Yes, it's simpler. I'll update it in my next patch version V5.
And how about other patches?
Haijun
+ start += mmc-erase_grp_size - res;
if (res blkcnt) {
}
+ if (blkcnt res)
+ blkcnt -= res;
+ else {
+ printf(\nErase size smaller than Erase group
+ size [0x%x] is not support by the
device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+ }
+
+ res = (blkcnt - res) % mmc-erase_grp_size;
+ if (res)
+ blkcnt -= res;
+
+ if (!blkcnt) {
+ printf(\nErase size smaller than Erase group size
[0x%x]
+ is not support by the device.\n,
+ mmc-erase_grp_size);
+ return NOT_SUPPORT;
+ }
+
+ if (!align)
printf(\n\nCaution! Your devices Erase group is
0x%x\n
- The erase range would be change to
- 0x LBAF ~0x LBAF \n\n,
- mmc-erase_grp_size, start ~(mmc-
erase_grp_size - 1),
- ((start + blkcnt + mmc-erase_grp_size)
- ~(mmc-erase_grp_size -
Re: [U-Boot] [PATCH 00/11 V10] EXYNOS5420: Add SMDK5420 board support
Hi Minkyu Kang, Please do let me know if any coments on this patch set. On Mon, Dec 9, 2013 at 2:20 PM, Rajeshwari S Shinde rajeshwar...@samsung.com wrote: This patch adds basic board support for SMDK5420 board. These patches are tested for booting fine on EVT1 SMDK5420. Changes in V2: - Corrected a compilation issue for SMDK5420. Changes in V3: - Add patch to support variable size SPL support - Add patch to disable SMU for eMMC. Changes in V4: - Added check for MAX77686 pmic compilation. - Added correct calculation of gpio based addresses. - Rebased on the latest u-boot code. - Removed patches for UART and TZPC changes as they were not needed. - Added flag to disable SMU for eMMC. Changes in V5: - Moved functions board_mmc_init and board_eth_init to common/board.c in case of device tree support. Changes in V6: - Rebased on the latest mainline branch. - Moved the definitions for SMU to arch/arm dwmmc.h Changes in V7: - Removed below patch as it is already merged DWMMC: SMDK5420: Disable SMU for eMMC - Corrected the multi line comments and removal of blank spaces and lines. - Corrected the license. Changes in V8: - corrected the if loops with if conditions of pro_id and cpu_id. Changes in V9: - Added macros to get the base address - Rebased on latest code. Changes in V10: - Added new structures for Power and DMC registers for 5420. - Changed the input parameters for common dmc functions. - Removed unnecesarry blank lines and added where ever required. Rajeshwari S Shinde (11): EXYNOS5: Create a common board file Exynos5420: Add base addresses for 5420 EXYNOS5420: Add power register structure. EXYNOS5420: Add dmc and phy_control register structure Exynos5420: Add clock initialization for 5420 Exynos5420: Add DDR3 initialization for 5420 Exynos5420: Add support for 5420 in pinmux and gpio Exynos5420: Add base patch for SMDK5420 DTS: Add dts support for SMDK5420 Config: Add initial config for SMDK5420 SPL: EXYNOS: Prepare for variable size SPL support arch/arm/cpu/armv7/exynos/clock.c | 280 - arch/arm/cpu/armv7/exynos/clock_init.h | 17 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 ++- arch/arm/cpu/armv7/exynos/dmc_common.c | 60 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 439 - arch/arm/cpu/armv7/exynos/exynos5_setup.h | 764 -- arch/arm/cpu/armv7/exynos/pinmux.c | 260 +++- arch/arm/dts/exynos5.dtsi | 198 ++ arch/arm/dts/exynos5250.dtsi | 194 +- arch/arm/dts/exynos5420.dtsi | 70 +++ arch/arm/include/asm/arch-exynos/board.h | 17 + arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 494 +++ arch/arm/include/asm/arch-exynos/cpu.h | 52 +- arch/arm/include/asm/arch-exynos/dmc.h | 177 ++ arch/arm/include/asm/arch-exynos/gpio.h| 143 - arch/arm/include/asm/arch-exynos/periph.h | 3 + arch/arm/include/asm/arch-exynos/power.h | 837 + board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 410 board/samsung/dts/exynos5420-smdk5420.dts | 169 + board/samsung/smdk5250/exynos5-dt.c| 352 +-- board/samsung/smdk5250/smdk5250.c | 182 +- board/samsung/smdk5420/Makefile| 11 + board/samsung/smdk5420/smdk5420.c | 159 + board/samsung/smdk5420/smdk5420_spl.c | 52 ++ boards.cfg | 1 + include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 289 + include/configs/exynos5250-dt.h| 283 + include/configs/smdk5420.h | 56 ++ spl/Makefile | 7 +- tools/Makefile | 3 +- tools/mkexynosspl.c| 167 +++-- 34 files changed, 5189 insertions(+), 1315 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h --
Re: [U-Boot] [PATCH] netbsd:fix documentation typo.
-Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Kees Jongenburger Sent: 09 December 2013 10:28 To: u-boot@lists.denx.de Cc: Kees Jongenburger; Kumar Gala Subject: [U-Boot] [PATCH] netbsd:fix documentation typo. From: Kees Jongenburger kees.jongenbur...@gmail.com The documentation suggested the arguments where passed over r3-r6 while the code bellow simply does that over r0-r3. s/bellow/below/ Cc: Kumar Gala ga...@kernel.crashing.org --- common/cmd_bootm.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index ba73f57..084c0e9 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -1531,10 +1531,10 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], /* * NetBSD Stage-2 Loader Parameters: - * r3: ptr to board info data - * r4: image address - * r5: console device - * r6: boot args string + * r0: ptr to board info data + * r1: image address + * r3: console device You mean r2 here I believe. Qais + * r3: boot args string */ (*loader)(gd-bd, os_hdr, consdev, cmdline); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] netbsd:fix documentation typo.
The documentation suggested the arguments where passed over r3-r6 while the code bellow simply does that over r0-r3. Cc: Kumar Gala ga...@kernel.crashing.org --- common/cmd_bootm.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index ba73f57..d5a1b4a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -1531,10 +1531,10 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], /* * NetBSD Stage-2 Loader Parameters: -* r3: ptr to board info data -* r4: image address -* r5: console device -* r6: boot args string +* r0: ptr to board info data +* r1: image address +* r2: console device +* r3: boot args string */ (*loader)(gd-bd, os_hdr, consdev, cmdline); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040. In this mode, a differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-sourec clocking whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Priyanka Jain priyanka.j...@freescale.com --- Changes for v2: Incorporated York's comment to separate out DDR_CLK_FREQ and SINGLE_SOURCE_CLK code arch/powerpc/cpu/mpc85xx/speed.c | 22 -- arch/powerpc/include/asm/config_mpc85xx.h |1 + arch/powerpc/include/asm/immap_85xx.h |3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 46ae80c..ef52669 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -76,10 +76,28 @@ void get_sys_info(sys_info_t *sys_info) uint mem_pll_rat; sys_info-freq_systembus = sysclk; +#ifdef CONFIG_SINGLE_SOURCE_CLK + /* +* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS +* are driven by separate DDR Refclock or single source +* differential clock. +*/ + uint single_src; + single_src = (in_be32(gur-rcwsr[5]) + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* +* For single source clocking, both ddrclock and syclock +* are driven by differential sysclock. +*/ + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) + sys_info-freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else +#endif #ifdef CONFIG_DDR_CLK_FREQ - sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ; + sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else - sys_info-freq_ddrbus = sysclk; + sys_info-freq_ddrbus = sysclk; #endif sys_info-freq_systembus *= (in_be32(gur-rcwsr[0]) 25) 0x1f; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 99e16bd..370bd21 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x3 +#define CONFIG_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.4 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 672e8c6..68c3c82 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL20x0004 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL10x0002 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL20x0001 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK0x0011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] tool for visualizing the map files?
Hello, I'm trying to understand the ARM booting process for omap4 systems by studying the linker generated map files and was wondering if some such tool already exists? Specifically, the connection between the linker .lds file and how it is used to generate the .map and .bin files. What I understand so far is this: when the linker is called (from the Makefile?), it scans the .lds file to understand the layout of the final binary. It then searches over all the folders looking for object files and according to instructions in .lds positions the different binary bits (in specified alignment) in the output .bin file. The .map file is a human-readable text file that can be used to confirm the output layout. Do I have this correct? Also, where is the map file for the the MLO image? For the u-boot binary (u-boot.img), I'm assuming its the file called u-boot.map or System.map. What is the corresponding file for the MLO binary? I can't find anything called MLO.map. Searching, Abraham V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: Samsung: Change GONI and Universal_C210 maintainers.
Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers entry. Change-Id: Idac259bdefc8547ec10c7f5b9556be09c2484a3a Signed-off-by: Lukasz Majewski l.majew...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- boards.cfg |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index 114cc86..5988c5f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -276,7 +276,7 @@ Active arm armv7 exynos samsung smdk5250 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap k.chan...@samsung.com Active arm armv7 exynos samsung trats trats- Lukasz Majewski l.majew...@samsung.com Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek p.wilc...@samsung.com -Active arm armv7 exynos samsung universal_c210 s5pc210_universal- Minkyu Kang mk7.k...@samsung.com +Active arm armv7 exynos samsung universal_c210 s5pc210_universal- Przemyslaw Marczak p.marc...@samsung.com Active arm armv7 highbank- highbank highbank - Rob Herring rob.herr...@calxeda.com Active arm armv7 mx5 denxm53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut marek.va...@gmail.com Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - @@ -341,7 +341,7 @@ Active arm armv7 omap5 ti dra7xx Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800evaarmadillo-800eva - Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Active arm armv7 rmobile kmc kzm9g kzm9g- Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com:Tetsuyuki Kobayashi k...@kmckk.co.jp -Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang mk7.k...@samsung.com +Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega m.zal...@samsung.com Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.k...@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 u8500 st-ericsson snowball
Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
No.
Without MAS3_SX, the board can't run in booting from NAND.
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@
struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
+ !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
This will have the result of mapping DDR in the SPL where it's not used,
but not in the TPL where it is.
For the TPL the ddr initial by initdram(), so don't need to mapping ddr here.
I intend to change it to #if defined(CONFIG_SYS_RAMBOOT) ||
!defined(CONFIG_SPL_COMMON_INIT_DDR)
Is it more clear?
-Scott
-Po Liu
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Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
On 12/10/2013 11:50 PM, Scott Wood wrote: On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote: On 12/9/2013 11:21 PM, Scott Wood wrote: On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote: On 12/7/2013 6:51 AM, Scott Wood wrote: Prabhakar, why did you extend that to other uses? Why are both entries ifdeffed here, but only the 0xe000 entry on existing boards? both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does not have this. i dont think NOR boot tested after this patch. NOR boot will not work after applying this patch. So what happens if there's a speculative access to the non-ifdeffed 0xf000 when we're not booting from that (e.g. ramboot, SPL payload, SD/SPI...)? If I understand the question correctly, Ideally ramboot, SPL payload, SD/SPI should not make access to this address. They assumed to be running from DDR whose TLB has already been created by IBR, or First stage boot loader. Speculative accesses don't come (directly) from software. They are initiated by the hardware and are not predictable. Please help me in understanding this. What are the scenario where it is possible? means how hardware can initiate any access? do hardware initiated transaction require TLB? Regards, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] rcar_i2c: Fix receiving wait condition
From: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- drivers/i2c/rcar_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index ba2cadb..01c98d4 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -122,8 +122,8 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) /* start master receive */ writel(MCR_MDBS | MCR_MIE | MCR_ESG, dev-icmcr); - while ((readl(dev-icmsr) (MSR_MAT | MSR_MDE)) - != (MSR_MAT | MSR_MDE)) + while ((readl(dev-icmsr) (MSR_MAT | MSR_MDR)) + != (MSR_MAT | MSR_MDR)) udelay(10); /* clear ESG */ -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] rcar_i2c: Clear status before start master receive
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- drivers/i2c/rcar_i2c.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index 01c98d4..50cebd6 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -119,6 +119,8 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) /* set slave address, receive */ writel((chip 1) | 1, dev-icmar); + /* clear status */ + writel(0, dev-icmsr); /* start master receive */ writel(MCR_MDBS | MCR_MIE | MCR_ESG, dev-icmcr); -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3 V2] esdhc: Workaround for card can't be detected on T4240QDS
Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V2: - Add the judgement condition for this broken card drivers/mmc/fsl_esdhc.c| 9 + include/configs/T4240QDS.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 134a02d..b3b5f37 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -548,6 +548,15 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg-esdhc_base; int timeout = 1000; + /* +* Card detecting pin is not functional on T4240QDS with rev 1.0 SoC. +* Presuming card is present. +*/ +#if defined(CONFIG_T4240QDS) + if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) QIXIS_MUX_SDHC) || + IS_SVR_REV(get_svr(), 1, 0)) + return 1; +#endif while (!(esdhc_read32(regs-prsstat) PRSSTAT_CINS) --timeout) udelay(1000); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..955e6b9 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 #define QIXIS_BASE_PHYS(0xfull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) -- 1.8.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3 V2] eSDHC: Calculate envaddr accroding to the address format
On BSC9131 and BSC9132: For High Capacity SD Cards ( 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Use 0xu instead of UINT_MAX
board/freescale/common/sdhc_boot.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/board/freescale/common/sdhc_boot.c
b/board/freescale/common/sdhc_boot.c
index f6e2b2b..b5ae489 100644
--- a/board/freescale/common/sdhc_boot.c
+++ b/board/freescale/common/sdhc_boot.c
@@ -16,6 +16,8 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
+#define ESDHC_DEFAULT_ENVADDR 0x400
+
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
@@ -39,6 +41,34 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32
*env_addr)
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+ /*
+* On soc BSC9131, BSC9132:
+* In High Capacity SD Cards ( 2 GBytes), the 32-bit source address and
+* code length of these soc specify the memory address in block address
+* format. Block length is fixed to 512 bytes as per the SD High
+* Capacity specification.
+*/
+ if ((SVR_SOC_VER(get_svr()) == SVR_9131) ||
+ (SVR_SOC_VER(get_svr()) == SVR_9132)) {
+ u64 tmp;
+
+ if (mmc-high_capacity) {
+ tmp = (u64)code_offset * blklen;
+ tmp += code_len * blklen;
+ } else
+ tmp = code_offset + code_len;
+
+ if ((tmp + CONFIG_ENV_SIZE mmc-capacity) ||
+ (tmp 0xU))
+ *env_addr = ESDHC_DEFAULT_ENVADDR;
+ else
+ *env_addr = tmp;
+
+ free(tmp_buf);
+
+ return 0;
+ }
+
*env_addr = code_offset + code_len;
free(tmp_buf);
--
1.8.4.1
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[U-Boot] [PATCH 2/3 V2] esdhc: Detecting 8 bit width before mmc initialization
The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changs for V2: - No changes drivers/mmc/fsl_esdhc.c| 5 + include/configs/T4240QDS.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b3b5f37..a5fee3c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -646,6 +646,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc-host_caps = ~MMC_MODE_4BIT; } + /* Detect if the upper 4 pins are used for ESDHC */ +#if defined(CONFIG_T4240QDS) + if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) QIXIS_MUX_SDHC_WIDTH8)) + mmc-host_caps = ~MMC_MODE_8BIT; +#endif if (caps ESDHC_HOSTCAPBLT_HSS) mmc-host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 955e6b9..4799d38 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BRDCFG5 0x55 #define QIXIS_MUX_SDHC 2 +#define QIXIS_MUX_SDHC_WIDTH8 1 #define QIXIS_BASE_PHYS(0xfull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) -- 1.8.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
On 12/11/2013 8:24 AM, Liu Po-B43644 wrote: -Original Message- From: Scott Wood [mailto:scottw...@freescale.com] Sent: Wednesday, December 11, 2013 2:20 AM To: Kushwaha Prabhakar-B32579 Cc: Liu Po-B43644; u-boot@lists.denx.de; Sun York-R58495 Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote: On 12/9/2013 11:21 PM, Scott Wood wrote: On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote: On 12/7/2013 6:51 AM, Scott Wood wrote: Prabhakar, why did you extend that to other uses? Why are both entries ifdeffed here, but only the 0xe000 entry on existing boards? both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does not have this. i dont think NOR boot tested after this patch. NOR boot will not work after applying this patch. So what happens if there's a speculative access to the non-ifdeffed 0xf000 when we're not booting from that (e.g. ramboot, SPL payload, SD/SPI...)? If I understand the question correctly, Ideally ramboot, SPL payload, SD/SPI should not make access to this address. They assumed to be running from DDR whose TLB has already been created by IBR, or First stage boot loader. Speculative accesses don't come (directly) from software. They are initiated by the hardware and are not predictable. Remove the: -#ifdef CONFIG_SPL_NAND_MINIMAL - SET_TLB_ENTRY(1, 0xf000, 0xf000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), - SET_TLB_ENTRY(1, 0xe000, 0xe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_4K, 1), -#endif Do not effect the NAND/NOR boot after I test in C29XPCIE. I just wonder how it is working without both TLBs. I can guess what is happening - NOR boot: After coming to AS1-- AS0, system is running with NOR TLB entry - NAND boot: after coming to AS1-- AS0, It is usingCONFIG_SYS_INIT_L2_ADDR TLB entry so, it can be removed for c293PCIe. Regards, Prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.
So, use CONFIG_SPL_NAND_BOOT config.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Incorporated Scott's comments
- Add CONFIG_SPL_NAND_BOOT in README
README |3 +++
board/freescale/bsc9131rdb/tlb.c |2 +-
board/freescale/bsc9132qds/tlb.c |2 +-
board/freescale/p1010rdb/tlb.c |2 +-
include/configs/BSC9131RDB.h |2 +-
include/configs/BSC9132QDS.h |2 +-
include/configs/P1010RDB.h |2 +-
7 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/README b/README
index 265e81e..88a4722 100644
--- a/README
+++ b/README
@@ -3245,6 +3245,9 @@ FIT uImage format:
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
+ CONFIG_SPL_NAND_BOOT
+ Add support NAND boot
+
CONFIG_SYS_NAND_U_BOOT_OFFS
Location in NAND to read U-Boot from
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 669fe8a..c8ecf5d 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xe000, 0xe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1),
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 02655e9..07febc2 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xe000, 0xe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1),
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index a7af0f6..a3d36b3 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xf000, 0xf000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xe000, 0xe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1),
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 499d8c2..783d996 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -29,7 +29,7 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index a6601fe..f7cd955 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -38,7 +38,7 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index eab386a..22538fc 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -37,7 +37,7 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
--
1.7.9.5
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[U-Boot] [PATCH] powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16. So, update its value as default. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 99e16bd..244ccbf 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -711,7 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x3 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.4 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
