2014-09-09 16:41 GMT+02:00 Christian Gmeiner christian.gmei...@gmail.com:
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
The main difference between the different models of the OT1200
series is how
Hi Masahiro,
On Fri, 2014-09-12 at 17:06 +0900, Masahiro Yamada wrote:
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+ /* access to main area */
+ writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
+
+ page_size =
If board_mmc_init failed and returns with -1, cpu_mmc_init will invoke
fsl_esdhc_mmc_init. fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR
to initialize SDHCx, so use USDHCx_BASE_ADDR to redefine the config macro.
If not use USDHCx_BASE_ADDR to define CONFIG_SYS_FSL_ESDHC_ADDR,
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC2_BASE_ADDR which is
used in board_mmc_init.
Signed-off-by: Peng Fan peng@freescale.com
---
include/configs/mx6slevk.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index
On Tue, 2014-09-09 at 14:26 +0200, ZY - pavel wrote:
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index
Hi Pavel,
On Mon, 2014-09-08 at 14:08 +0200, ZY - pavel wrote:
Hi!
I know coding style leaves something to be desired.
But.. it recognizes MMC/ethernet, and can load linux kernel.
Unfortunately, 1MB of memory at 0 is not available for some reason;
but linux works ok if you avoid that
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.
If board_mmc_init failed, cpu_mmc_init-fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.
Signed-off-by: Peng Fan peng@freescale.com
---
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR.
USDHC3 and USDHC4 are both initialized in board_mmc_init. There is
no restriction on USDHC3 addr or USDHC4 addr should be assigned to
CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid
errors when fsl_esdhc_mmc_init is
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Try to correct the return code per Fabio's comments, but send
Add clear print log to show pfuze200 or pfuze100 found on mx6 sabre
boards.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Separate the patch from patch set
- Add the clear print to factorized pfuze function
Initialize the Pfuze on I2C1 at mx6slekv board late init.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Use the factorized pfuze common function in pfuze init
board/freescale/mx6slevk/mx6slevk.c | 22
Enable the MXC I2C driver for mx6slevk and setup the I2C1.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Split the I2C1 pad setting to another new patch.
board/freescale/mx6slevk/mx6slevk.c | 26 ++
Add I2C1 SDA/SCL pad settings for mx6 sololite
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
Changes since v3:
- Split the I2C1 pad settings to a new patch since it is board independent.
arch/arm/include/asm/arch-mx6/mx6sl_pins.h |5 +
Hi Pavel,
On Mon, 2014-09-08 at 14:08 +0200, ZY - pavel wrote:
Hi!
I know coding style leaves something to be desired.
But.. it recognizes MMC/ethernet, and can load linux kernel.
Unfortunately, 1MB of memory at 0 is not available for some reason;
but linux works ok if you avoid that
Gentle ping.
On Mon, Sep 08, 2014 at 07:04:16PM +0200, Maxin B. John wrote:
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD
Signed-off-by: Maxin B. John maxin.j...@enea.com
---
drivers/mtd/mtdcore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi,
On 09/14/14 21:28, Simon Glass wrote:
Hi Masahiro,
On 12 September 2014 05:25, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
I have a qustion about lists_driver_lookup_name() function.
for (entry = drv; entry != drv + n_ents; entry++) {
if
Hi
On Fri, Sep 12, 2014 at 10:00 PM, Michael Trimarchi
mich...@amarulasolutions.com wrote:
Hi
Il 12/set/2014 21:53 Mariusz Boguszewski mariusz.boguszew...@csr.com ha
scritto:
Hello,
I need to get this new version of u-boot for my PandaBoard A6 rev.
I tried Linaro release 14.08 from July
Hi!
I know coding style leaves something to be desired.
But.. it recognizes MMC/ethernet, and can load linux kernel.
Unfortunately, 1MB of memory at 0 is not available for some reason;
but linux works ok if you avoid that area.
fpga load 0 now seems to work.
For some
Hi!
Wolfgang's advice is valuable and noted. However, it is in Altera's
best interest that we have 1 central gathering point for all our
opensource software support.
Full agreement here. But I would like to point out that your point of
view appears to be biased: U-Boot mainline
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: York Sun york...@freescale.com
---
Change log:
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: York Sun york...@freescale.com
---
Change log
v2: Added a common function run_descriptor_jr to avoid
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name
USBO2H_USB_BASE_ADDR in imx-regs.h. The driver hard codes
the USB base address name to USBOH3, which causes the driver
failed to build for mx6sl/mx6sx.
This patch uniform the address name to USB_BASE_ADDR for all
mx6 series.
Signed-off-by:
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: York Sun york...@freescale.com
---
Change log:
Hi Heiko,
Hello Stephen,
add Lukasz to Cc ...
Am 12.09.2014 16:53, schrieb Stephen Warren:
On 09/12/2014 12:27 AM, Heiko Schocher wrote:
when uplaoding a file, at least from a nand partition, the complete
mtd nand partition size is transferred. This leads in a wrong
md5sum as the
Hi, Boris
On 9/2/2014 4:23 PM, Boris BREZILLON wrote:
Disable subpage write when using PMECC to prevent buggy partial page write.
This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Hi Heiko,
DFU now can use also fullspeed.
Applied to u-boot-dfu
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi Heiko,
Siemens boards are now using DFU in fullspeed only. For
this CONFIG_USB_GADGET_DUALSPEED is undefined.
Applied to u-boot-dfu
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
___
U-Boot mailing
Hi Lukasz,
This code is not used anymore in the current DFU implementation and
can be safely removed.
Applied to u-boot-dfu
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
___
U-Boot mailing list
Hello Lukasz,
Am 15.09.2014 11:45, schrieb Lukasz Majewski:
Hi Heiko,
Hello Stephen,
add Lukasz to Cc ...
Am 12.09.2014 16:53, schrieb Stephen Warren:
On 09/12/2014 12:27 AM, Heiko Schocher wrote:
when uplaoding a file, at least from a nand partition, the complete
mtd nand partition size
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc:
From: Pavel Machek pa...@denx.de
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom
From: Pavel Machek pa...@denx.de
Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
Sort the list of functional block addresses and fix indentation.
No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk
This entire RFC series is the first stab at making SoCFPGA usable with
mainline U-Boot again. There are still some bits missing, but in general,
this allows me to use mainline U-Boot on my SoCFPGA systems. The big
missing part is the SPL generation, which still needs a lot of additional
work.
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc:
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.
Signed-off-by: Marek Vasut
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
From: Pavel Machek pa...@denx.de
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek pa...@denx.de
From: Pavel Machek pa...@denx.de
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
From: Pavel Machek pa...@denx.de
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not
From: Charles Manning cdhmann...@gmail.com
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed
Clean up the system manager register definition and add the missing
register definitions in place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang
From: Pavel Machek pa...@denx.de
Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
From: Pavel Machek pa...@denx.de
Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.
Also fix calloc() misuse.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut
From: Pavel Machek pa...@denx.de
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by:
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
From: Pavel Machek pa...@denx.de
Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc:
The inlining is done by GCC whe needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
From: Pavel Machek pa...@denx.de
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Hi Heiko,
Hello Lukasz,
Am 15.09.2014 11:45, schrieb Lukasz Majewski:
Hi Heiko,
Hello Stephen,
add Lukasz to Cc ...
Am 12.09.2014 16:53, schrieb Stephen Warren:
On 09/12/2014 12:27 AM, Heiko Schocher wrote:
when uplaoding a file, at least from a nand partition, the
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
2014-01-16 12:44 GMT+01:00 Christian Gmeiner christian.gmei...@gmail.com:
Hi all
2014/1/14 Christian Gmeiner christian.gmei...@gmail.com:
2014/1/12 Anatolij Gustschin ag...@denx.de:
Hi Stefano,
On Wed, 08 Jan 2014 11:53:39 +0100
Stefano Babic sba...@denx.de wrote:
...
Agree that we have
Up until now driver model has not been used for any type of bus. Buses
have some unique properties and needs, so we cannot claim that driver
model can cover all the common cases unless we have converted a bus over
to driver model.
SPI is a reasonable choice for this next step. It has a fairly
In preparation for changing the error handling in this code for driver
model, move it into its own function.
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_spi.c | 53
Some files are using SPI functions but not explitly including the SPI
header file. Fix this, since driver model needs it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add spi.h header to dfu_sf.c and some renesas boards
board/renesas/sh7752evb/sh7752evb.c | 1 +
Driver model does its own init, so we don't need this.
There is still a call in board_f.c but it is only enabled by CONFIG_HARD_SPI.
It is easy enough to disable that option when converting boards which use
it to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
-
Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes in v2:
U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.
Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an
A merge error ended up repeating a similar sentence twice. Fix it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to fix README merge error
README | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/README b/README
index 0a0f528..298e8d6
Add a SPI device which can be used for testing SPI flash features in
sandbox.
Also add a cros_ec device since with driver model the Chrome OS EC
emulation will not otherwise be available.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Adjust binding to avoid Linux-specific
Some of the #defines in spi.h are not bracketed. To avoid future mistakes
add brackets. Also add an explanatory comment for SPI_CONN_DUAL_...
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes in v2: None
include/spi.h | 24
Adjust this board to use the driver model soft_spi implementation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/arm/dts/exynos4210-universal_c210.dts | 13
board/samsung/universal_c210/universal.c | 52 --
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sf_params.c | 1 +
1 file changed, 1
Add a uclass which provides access to SPI buses and includes operations
required by SPI.
For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are
Driver model uses a different way to find the SPI bus and slave from the
numbered devices given on the command line. Adjust the code to suit.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_spi.c | 34 +++---
1 file changed, 27
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/buffalo/lsxl/lsxl.c | 3 +-
common/cmd_sf.c| 1 +
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.
A few device tree additions are needed to make the SPI flash available.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.
This enables us to expand the number of chips that sandbox supports.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by:
Add support for driver model if enabled. This involves minimal changes
to the code, mostly just plumbing around the edges.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cros_ec.c | 30 ++
drivers/misc/cros_ec.c | 122
Adjust spi_flash_probe_slave() to return an error value instead of a
pointer so we get the correct error return.
Have the caller allocate memory for spi_flash to simplify error handling,
and also so that driver model can use its existing allocated memory.
Add a spi.h include in the sf_params
Adjust the sandbox cros_ec emulation driver to work with driver model, and
switch over to driver model for sandbox cros_ec.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/cros_ec_sandbox.c | 90 +++---
Add a simple test for SPI that uses SPI flash. It operates by creating a
SPI flash file and using the 'sf test' command to test that all
operations work correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
test/dm/Makefile | 1 +
test/dm/sf.c | 43
Add a new implementation of soft_spi that uses device tree to specify the
GPIOs. This will replace soft_spi_legacy for boards which use driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
doc/device-tree-bindings/spi/soft-spi.txt | 32
drivers/spi/Makefile
Use driver model for exynos5 board SPI flash.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/configs/exynos-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 0ec2ed7..47136b3 100644
Reserve the 'normal' name for use by driver model, and rename the old
driver so that it is clear that it is for 'legacy' drivers only.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/Makefile | 2 +-
drivers/spi/{soft_spi.c =
Add a driver model uclass for SPI flash which supports the common
operations (read, write, erase). Since we must keep support for the
non-dm interface, some modification of the spi_flash header is required.
CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash.
Signed-off-by: Simon
These tests use SPI flash (and the sandbox emulation) to operate.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Create a 'spi.bin' file for the SPI tests
test/dm/Makefile | 1 +
test/dm/spi.c | 47 +++
test/dm/test-dm.sh |
We want the SPI flash probing feature to operate as a standard driver.
Add a driver for the basic probing feature used by most boards. This
will be activated by device_probe() as with any other driver.
The 'sf probe' command currently keeps track of the SPI slave that it
last used. This doesn't
Convert sandbox's spi flash emulation driver to use driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/include/asm/spi.h | 13 --
arch/sandbox/include/asm/state.h | 1 -
drivers/mtd/spi/sandbox.c| 326
This README is intended to help maintainers move their SPI drivers over to
driver model. It works through the required steps with an example.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update for changes to exynos driver
- Fix typos reported by Jagannadha Sutradharudu Teki
Adjust the sandbox SPI driver to support driver model and move sandbox over
to driver model for SPI.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Correct sandbox's xfer() method signature
- Use 'bus' instead of 'dev' to make the API clearer
arch/sandbox/include/asm/state.h
This feature provides for init of a single SPI port for the soft SPI
feature. It is not really compatible with driver model since it assumes a
single SPI port. Also, inserting SPI init into the driver by means of
a #define is not very nice.
This feature is not used by any active boards, so let's
Adjust this driver to use driver model and move smdk5420 boards over to
use it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/cros_ec_spi.c | 68 +++--
include/configs/peach-pit.h | 1 +
2 files changed, 60
The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/core/device.c | 7 +--
1 file changed, 5 insertions(+),
This series adjusts the IMX serial and GPIO drivers to support driver model.
As an example of its use, the recently-added cm_fx6 board is converted over
to driver model.
Some minor driver model core changed are required to make this work and
these are included with this series.
Simon Glass
Add driver model support with this driver. In this case the platform data
is in the driver. It would be better to put this into an SOC-specific file,
but this is best attempted when more boards are moved over to use driver
model.
Signed-off-by: Simon Glass s...@chromium.org
---
GPIOs should be requested before use. Without this, driver model will not
permit the GPIO to be used.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/imx-common/i2c-mxv7.c | 14 ++
board/compulab/cm_fx6/cm_fx6.c | 9 +
board/compulab/cm_fx6/common.c | 3 +++
3
Avoid duplicating the code which deals with getc() and putc(). It is fairly
simple, but may expand later.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/serial/serial-uclass.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git
This seems to break mkimage:
Invalid imximage commands Type - valid names are: BOOT_FROM, BOOT_OFFSET, DATA,
CSF, IMAGE_VERSION
Error: board/compulab/cm_fx6/imximage.cfg[1] - Invalid command(/*)
Signed-off-by: Simon Glass s...@chromium.org
---
board/compulab/cm_fx6/imximage.cfg | 6 --
1
The U_BOOT_DEVICE macro allows the declaration of a single U-Boot device.
Add an equivalent macro to declare an array of devices, for convenience.
Signed-off-by: Simon Glass s...@chromium.org
---
include/dm/platdata.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dm/platdata.h
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