Now that serial and GPIO are available for iMX.6, move cm_fx6 over as an
example.
Signed-off-by: Simon Glass s...@chromium.org
---
board/compulab/cm_fx6/cm_fx6.c | 10 ++
include/configs/cm_fx6.h | 11 +++
2 files changed, 21 insertions(+)
diff --git
Add driver model support with this driver. Boards which use this driver
should define platform data in their board files.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/serial/serial_mxc.c | 170 +---
include/serial_mxc.h| 14
2
The existing ll_entry_declare() permits a single element of the list to
be added to a linker list. Sometimes we want to add several objects at
once. To avoid lots of messy declarations, add a macro to support this.
Signed-off-by: Simon Glass s...@chromium.org
---
include/linker_lists.h | 21
Allow serial_find_console_or_panic() to work without a device tree.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/serial/serial-uclass.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index
There may be some custom boards in the field which have
an seperate eeprom chip to store edid informations in it.
To make use of those edid information in the board code
this patch add a function to convert edid to fb_videomode.
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
This new function is used to set all display-timings
properties based on fb_videomode.
display-timings {
timing0 {
clock-frequency = 2500;
hactive = 640;
vactive = 480;
hback-porch = 48;
hfront-porch = 16;
We support one base print with different panel sizes. In order
to keep it simple we use one devicetree for the linux kernel.
The timing values for each panel is stored on an i2c EEPROM.
This EDID gets transformed to fb_videomode and later stored
in the dtb.
Signed-off-by: Christian Gmeiner
On Tue, Sep 02, 2014 at 02:49:36PM +0300, Vasili Galka wrote:
Hi Tom,
On Thu, Aug 21, 2014 at 2:07 PM, Vasili Galka vvv...@gmail.com wrote:
Hi Nobuhiro,
I'm trying to verify the correct build of all SH boards in U-Boot. What is
the recommended toolchain to use?
I tried the one
On Tue, Sep 09, 2014 at 01:42:59PM -0600, Simon Glass wrote:
Hi,
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is
On Fri, Sep 12, 2014 at 02:52:05PM +0530, jags gediya wrote:
I want to implement fail-safe booting feature in my project. Basically
my logic is, i will increase any u-boot environment variable each time
and up on successful bring up, i want to decrease the value of that
again. If the value of
On Mon, Sep 15, 2014 at 10:54 AM, Tom Rini tr...@ti.com wrote:
On Tue, Sep 09, 2014 at 01:42:59PM -0600, Simon Glass wrote:
Hi,
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote:
Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the
Dear Marek Vasut,
In message 1410779188-6880-13-git-send-email-ma...@denx.de you wrote:
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
...
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) 0) 0x0001)
+#define
From: Nitin Garg nitin.g...@freescale.com
Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
Hi Christian,
On 15/09/2014 08:37, Christian Gmeiner wrote:
2014-09-09 16:41 GMT+02:00 Christian Gmeiner christian.gmei...@gmail.com:
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
The main difference
On 09/15/2014 06:05 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
Dear Marek Vasut,
In message 1410779188-6880-26-git-send-email-ma...@denx.de you wrote:
From: Pavel Machek pa...@denx.de
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it
On 09/15/2014 06:05 AM, Marek Vasut wrote:
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split
On 09/15/2014 06:05 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.
Signed-off-by: Pavel Machek
On 09/15/2014 06:06 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
Hi Simon,
On 09/15/14 15:57, Simon Glass wrote:
GPIOs should be requested before use. Without this, driver model will not
permit the GPIO to be used.
Right. That should have been done from the start... Sorry for that...
A question below though..
Signed-off-by: Simon Glass s...@chromium.org
Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
Add the Snoop Control Unit register definition file.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
Add register definition for the NIC-301 used on SoCFPGA.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek
From: Pavel Machek pa...@denx.de
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin
Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the remap register of NIC-301 and sets the
required 'mpuzero' bit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
On 09/14/2014 12:00 PM, Hans de Goede wrote:
Hi Karsten,
Thanks for testing this!
On 09/14/2014 05:43 PM, Karsten Merker wrote:
Hello,
I am currently testing the new bootcmd handling introduced at
http://git.denx.de/?p=u-boot.git;a=commit;h=8cc96848f0a467922820895b6b2363b0c64163b5
on a
Hi,
On 09/15/2014 07:22 PM, Stephen Warren wrote:
On 09/14/2014 12:00 PM, Hans de Goede wrote:
Hi Karsten,
Thanks for testing this!
On 09/14/2014 05:43 PM, Karsten Merker wrote:
Hello,
I am currently testing the new bootcmd handling introduced at
On 09/15/14 15:57, Simon Glass wrote:
This seems to break mkimage:
Invalid imximage commands Type - valid names are: BOOT_FROM, BOOT_OFFSET,
DATA, CSF, IMAGE_VERSION
Error: board/compulab/cm_fx6/imximage.cfg[1] - Invalid command(/*)
That is really strange, because there are multiple
Hello everyone,
I am using u-boot from the xilinx repo on github with the zedboard and
whenever I start the zedboard I get the No boot file defined.
I have checked that all the variables boot_image kernel_image and
devicetree_image are normally set in zynq-common.h.
If I use fatload mmc 0
Current code sets reserved CG1 bits instead of CG6 bits
for pl301_mx6qper1_bch clock. Fix it.
Signed-off-by: Anatolij Gustschin ag...@denx.de
Cc: Heiko Schocher h...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Tim Harvey thar...@gateworks.com
---
board/aristainetos/aristainetos.c |2 +-
Hi Igor,
On 15 September 2014 11:13, Igor Grinberg grinb...@compulab.co.il wrote:
Hi Simon,
On 09/15/14 15:57, Simon Glass wrote:
GPIOs should be requested before use. Without this, driver model will not
permit the GPIO to be used.
Right. That should have been done from the start... Sorry
On 09/15/2014 11:59 AM, Hans de Goede wrote:
Hi,
On 09/15/2014 07:22 PM, Stephen Warren wrote:
On 09/14/2014 12:00 PM, Hans de Goede wrote:
Hi Karsten,
Thanks for testing this!
On 09/14/2014 05:43 PM, Karsten Merker wrote:
Hello,
I am currently testing the new bootcmd handling introduced
Hi Simon,
On 09/15/14 15:57, Simon Glass wrote:
Add driver model support with this driver. In this case the platform data
is in the driver. It would be better to put this into an SOC-specific file,
but this is best attempted when more boards are moved over to use driver
model.
On 09/15/14 21:04, Simon Glass wrote:
Hi Igor,
On 15 September 2014 11:13, Igor Grinberg grinb...@compulab.co.il wrote:
Hi Simon,
On 09/15/14 15:57, Simon Glass wrote:
GPIOs should be requested before use. Without this, driver model will not
permit the GPIO to be used.
[...]
In all
On 09/15/14 15:57, Simon Glass wrote:
Now that serial and GPIO are available for iMX.6, move cm_fx6 over as an
example.
Signed-off-by: Simon Glass s...@chromium.org
---
board/compulab/cm_fx6/cm_fx6.c | 10 ++
include/configs/cm_fx6.h | 11 +++
2 files changed, 21
On Monday, September 15, 2014 at 06:00:47 PM, Dinh Nguyen wrote:
On 09/15/2014 06:05 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious.
On Monday, September 15, 2014 at 05:40:54 PM, Dinh Nguyen wrote:
On 09/15/2014 06:05 AM, Marek Vasut wrote:
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up.
On 09/15/2014 06:06 AM, Marek Vasut wrote:
The inlining is done by GCC whe needed, there is no need to do it
s/whe/when.
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
thanks...
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the
On 09/15/2014 06:06 AM, Marek Vasut wrote:
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
On 09/15/2014 06:06 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Hi!
Dear Marek Vasut,
In message 1410779188-6880-13-git-send-email-ma...@denx.de you wrote:
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
...
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) 0)
0x0001)
+#define
On Mon 2014-09-15 13:06:11, Marek Vasut wrote:
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See
On Mon 2014-09-15 13:06:12, Marek Vasut wrote:
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin
On Mon 2014-09-15 13:06:17, Marek Vasut wrote:
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
On Mon 2014-09-15 13:06:19, Marek Vasut wrote:
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state
On Mon 2014-09-15 13:06:21, Marek Vasut wrote:
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen
On Mon 2014-09-15 13:06:22, Marek Vasut wrote:
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini
On Mon 2014-09-15 13:59:25, Marek Vasut wrote:
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc:
On Monday, September 15, 2014 at 11:21:22 PM, Pavel Machek wrote:
Hi!
Dear Marek Vasut,
In message 1410779188-6880-13-git-send-email-ma...@denx.de you wrote:
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
...
Masahiro Yamada (3):
SPDX: Add ISC SPDX-License-Identifier
tools: Import Kconfiglib
tools/genboardscfg.py: improve performance more with Kconfiglib
Licenses/README |1 +
Licenses/isc.txt | 17 +
tools/buildman/kconfiglib.py | 3799
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Wolfgang Denk w...@denx.de
---
Changes in v3: None
Changes in v2:
- Newly added
Licenses/README | 1 +
Licenses/isc.txt | 17 +
2 files changed, 18 insertions(+)
create mode 100644 Licenses/isc.txt
diff --git
The idea of using Kconfiglib was given by Tom Rini.
It allows us to scan lots of defconfigs very quickly.
This commit also uses multiprocessing for further acceleration.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Suggested-by: Tom Rini tr...@ti.com
Acked-by: Simon Glass
Hi Tom,
I think this series (v2) is under review now,
but I have noticed my big mistake in terms of the license.
In v2, I accidentally added GPL-2.0+ SPDX
but it should have been ISC SPDX.
I'd like you to replace it with v3.
On Mon, 1 Sep 2014 19:57:37 +0900
Masahiro Yamada
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
Xiubo Li (4):
ARM: HYP/non-sec: add the pen address byte reverting support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls102xa: HYP/non-sec: support for ls102xa boards
ARM: ls102xa: allow all device accessable in non-secure state
arch/arm/cpu/armv7/ls102xa/cpu.c
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function
to set the start address for secondary cores in the LS1021A specific
For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the
Kconfiglib is the flexible Python Kconfig parser and library
created by Ulf Magnusson.
(https://github.com/ulfalizer/Kconfiglib)
This commit imports kconfiglib.py from
commit ce84c22e58fa59cb93679d4ead03c3cd1387965e
of https://github.com/ulfalizer/Kconfiglib
with an ISC SPDX-License-Identifier.
The S:Orphan in MAINTAINERS means that the maintainer in the
M: field is unreachable (i.e. the email address is not working).
(Refer to the definition of Orphan adopted in U-Boot
in the log of commit 31f1b654b2f395b69faa5d0d3c1eb0803923bd3b,
boards.cfg: move boards with invalid emails to
We are still keeping invalid email addressed in MAINTAINERS
because they carry information.
The problem is that scripts/get_maintainer.pl adds emails in the
M: field including invalid ones.
We want to comment out invalid email addresses in MAINTAINERS
to prevent scripts/get_maintainer.pl from
Masahiro Yamada (3):
tools/genboardscfg.py: pick up also commented maitainers
MAINTAINERS: comment out invalid maintainers
MAINTAINERS: comment out blank M: field
board/LaCie/net2big_v2/MAINTAINERS| 2 +-
board/LaCie/netspace_v2/MAINTAINERS | 2 +-
Since commit ddaf5c8f3030050fcd356a1e49e3ee8f8f52c6d4
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of Invalid MAINTAINERS address: '-'
error messages for patches with global changes.
It takes too long for Patman to process them.
Anyway, M:- does not carry
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