At present U-Boot sort-of supports the standard way of reading GPIOs from
device tree nodes, but the support is incomplete, a bit clunky and only
works for GPIO bindings where #gpio-cells is 2.
Also, this support can now be built into the uclass, rather than parked in
a separate file.
Add
The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.
There is already a driver for the mv88e61xx in U-Boot, and this patch
updates it to also work with the
Add support for a sun4i board built by Linksprite. This addition covers
both v1 and v2 versions. As the board has been working with 408MHz memory
setting in the u-boot-sunxi branch, and has been proven to be running stable
during my tests as well, a respective new DRAM config file is added as
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
include/configs/chromebook_link.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/chromebook_link.h
Hi Simon,
On Mon, 15 Dec 2014 07:19:39 -0700
Simon Glass s...@chromium.org wrote:
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 7b1f368..ed790cc 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -11,6 +11,8 @@
#ifndef
On 5 January 2015 at 02:28, Tom Rini tr...@ti.com wrote:
On Sun, Jan 04, 2015 at 11:23:29PM +0100, Michal Suchanek wrote:
Hello,
when using a hardfloat toolchain linking u-boot fails.
What version of U-Boot are you building? There's a few rc releases that
fail with hardfp-only because a
Hi,
On 05-01-15 11:46, B.R. Oake wrote:
On 05/01/15 01:28, Tom Rini wrote:
On Sun, Jan 04, 2015 at 11:23:29PM +0100, Michal Suchanek wrote:
when using a hardfloat toolchain linking u-boot fails.
What version of U-Boot are you building? There's a few rc releases that
fail with hardfp-only
On 05/01/15 01:28, Tom Rini wrote:
On Sun, Jan 04, 2015 at 11:23:29PM +0100, Michal Suchanek wrote:
when using a hardfloat toolchain linking u-boot fails.
What version of U-Boot are you building? There's a few rc releases that
fail with hardfp-only because a few things leaked in with 64bit
Hi,
On Mon, Jan 5, 2015 at 1:27 PM, anupamdev dev.anu...@gmail.com wrote:
Hi,
I am trying to understand the uboot code for etsec initialization for
ethernet on p2020ds board
The function
int tsec_init(struct eth_device *dev,bd_t bd)
is a pointer to dev-init in the function tsec_initialize
Hi Heiko,
On 01/05/2015 03:59 PM, Heiko Schocher wrote:
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
void spl_board_init(void)
+#else
+void s_init(void)
+#endif
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
... and adding this ifdefs could be prevented ...
What do you think?
Hello Bo,
Am 05.01.2015 09:19, schrieb Bo Shen:
Hi Heiko,
On 01/05/2015 03:59 PM, Heiko Schocher wrote:
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
void spl_board_init(void)
+#else
+void s_init(void)
+#endif
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
... and adding this
Hello Bo,
Am 29.12.2014 08:53, schrieb Bo Shen:
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into
Hi
On Mon, Jan 5, 2015 at 11:51 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05-01-15 11:46, B.R. Oake wrote:
On 05/01/15 01:28, Tom Rini wrote:
On Sun, Jan 04, 2015 at 11:23:29PM +0100, Michal Suchanek wrote:
when using a hardfloat toolchain linking u-boot fails.
What version
On 05/01/15 10:51, Hans de Goede wrote:
Ah, ok, thanks for figuring that out, so this only happens to people
following my sunxi-wip branch, because that commit is not upstream yet.
So I guess I will need to fix this somehow without using 64 bit math,
any suggestions?
Hi Simon,
On Mon, Jan 5, 2015 at 9:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 January 2015 at 01:08, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Dec 30, 2014 at 9:12 AM, Simon Glass s...@chromium.org wrote:
Enable an environment area.
Signed-off-by: Simon Glass
Hi Simon,
On Mon, Jan 5, 2015 at 10:11 AM, Simon Glass s...@chromium.org wrote:
Hi Masahiro,
I notice that when compiling I get the full paths to the source when I
use __FILE__:
/home/sjg/c/src/third_party/u-boot/files/cros/lib/readwrite.c:
vboot_rw_select_kernel: VbSelectAndLoadKernel:
Hi Simon,
On Tue, Nov 25, 2014 at 3:32 AM, Simon Glass s...@chromium.org wrote:
This is an early preview of some recent work to support PCI in driver model.
It was prompted by fiddling with bare x86 support and finding that PCI has
its own device model, but no actual storage as to what devices
Hi Simon,
On Mon, Jan 5, 2015 at 9:45 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 3 January 2015 at 22:54, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Dec 30, 2014 at 10:32 AM, Simon Glass s...@chromium.org wrote:
Add code to the generic pci_rom file to access the VGA ROM
Hi,
On 02-01-15 09:53, Daniel Kochmański wrote:
This is a series of patches to enable nand read functionality on sunxi
devices. It uses DMA and is able to read from syndrome partitions and
normal ones. Additionaly mksunxiboot tool is patched to be able to
format resulting binary to be able to
On Mon, Jan 05, 2015 at 12:24:13PM +, B.R. Oake wrote:
On 05/01/15 10:51, Hans de Goede wrote:
Ah, ok, thanks for figuring that out, so this only happens to people
following my sunxi-wip branch, because that commit is not upstream yet.
So I guess I will need to fix this somehow
Hi Simon,
On Mon, Jan 5, 2015 at 9:44 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 3 January 2015 at 20:26, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Jan 2, 2015 at 6:23 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 30 December 2014 at 22:51, Bin Meng
Hi Simon,
On Mon, Jan 5, 2015 at 9:49 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 January 2015 at 00:49, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Dec 30, 2014 at 9:12 AM, Simon Glass s...@chromium.org wrote:
The memory reference code takes a very long time to 'train'
Hi Simon,
2015-01-05 11:11 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
I notice that when compiling I get the full paths to the source when I
use __FILE__:
/home/sjg/c/src/third_party/u-boot/files/cros/lib/readwrite.c:
vboot_rw_select_kernel: VbSelectAndLoadKernel: 65552
Hi Heiko,
2015-01-05 15:52 GMT+09:00 Heiko Schocher h...@denx.de:
Hello Masahiro,
Am 26.12.2014 04:07, schrieb Masahiro Yamada:
This commit adds on-chip I2C driver used on some old Panasonic
UniPhier SoCs.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Reviewed-by: Simon Glass
Hi Simon,
2014-12-22 3:53 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
On 20 December 2014 at 00:25, Masahiro YAMADA yamad...@jp.panasonic.com
wrote:
Hi Simon,
2014-12-20 6:34 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
On 19 December 2014 at 11:34, Masahiro Yamada
Hi,
On 05-01-15 13:24, B.R. Oake wrote:
On 05/01/15 10:51, Hans de Goede wrote:
Ah, ok, thanks for figuring that out, so this only happens to people
following my sunxi-wip branch, because that commit is not upstream yet.
So I guess I will need to fix this somehow without using 64 bit math,
On Thu, Jan 01, 2015 at 11:31:34AM -0700, Simon Glass wrote:
Hi,
This one got lost in another thread and the pull request did not
appear in patchwork, so I'm resending it copied from Tom's email...it
should be applied to mainline.
http://patchwork.ozlabs.org/patch/419415/
Please
On Mon, Dec 29, 2014 at 10:37:52PM +0530, Jagannadha Sutradharudu Teki wrote:
Hi Tom,
Please pull this PR.
thanks!
Jagan.
The following changes since commit e3bf81b1e841ecabe7c8b3d48621256db8b8623e:
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2014-12-16
15:20:02
On Fri, Jan 02, 2015 at 02:15:21AM +0530, Jagannadha Sutradharudu Teki wrote:
Hi Tom,
Please pull this PR.
thanks!
Jagan.
The following changes since commit babe6994ca28e5a354ee32b33b7a54b0276d9df1:
sf: sf_params: Add S25FL164K flash identifier info (2014-12-18 18:48:30
+0530)
On Sun, Jan 04, 2015 at 07:11:42PM +0100, Albert ARIBAUD wrote:
Hi Tom,
The following changes since commit e3bf81b1e841ecabe7c8b3d48621256db8b8623e:
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2014-12-16
15:20:02 -0500)
are available in the git repository at:
Hi,
On 02-01-15 06:17, Siarhei Siamashka wrote:
On Mon, 10 Nov 2014 14:11:51 +0100
Hans de Goede hdego...@redhat.com wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de
Hi,
On 01-01-15 21:21, Siarhei Siamashka wrote:
On Wed, 31 Dec 2014 13:07:20 +0100
Hans de Goede hdego...@redhat.com wrote:
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.
Signed-off-by: Hans de Goede hdego...@redhat.com
snip
This fixes us never programming ALDO2, and programming the ALDO2 voltage
into ALDo1.
Reported-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
include/axp221.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Ian (et al),
Trivial patch fixing an important bug for the new sun6i / axp221 support in
v2015.01, if someone can give me a quick ack, then I'll send a pull-req to
Tom to get this included in v2015.01.
Thanks Regards,
Hans
___
U-Boot mailing list
Hi Hans,
On 5 January 2015 at 00:10, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05-01-15 03:49, Simon Glass wrote:
Hi Hans,
On 4 January 2015 at 12:05, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 04-01-15 19:21, B.R. Oake wrote:
(This started on the linux-sunxi mailing
On Mon, 2015-01-05 at 17:18 +0100, Hans de Goede wrote:
This fixes us never programming ALDO2, and programming the ALDO2 voltage
into ALDo1.
Reported-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Move the bootcmd commands into a seperate distro_bootcmd environment
variable. Allowing a user to easily launch the distro boot sequence if
the default bootcmd did not default to distro boot commands.
Also set CONFIG_BOOTCOMMAND to run distro_bootcmd if it hasn't been
configured yet rather then
Add an optional third argument to the part list command which puts a
space seperated list of valid partitions into the given environment
variable. This is useful for allowing boot scripts to iterate of all
partitions of a device.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
Hi,
On 5 January 2015 at 10:22, Graeme Russ gr...@tss-engineering.com wrote:
Hi Simon Bin,
On Tue, Jan 6, 2015 at 12:40 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Mon, Jan 5, 2015 at 9:44 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 3 January 2015 at 20:26, Bin Meng
Not all devices use the convention that the boot scripts are on the
first partition. For example on chromebooks it seems common for the
first two partitions to be ChromeOS kernel partitions.
So instead of just the first partition scan all partitions on a device
with a filesystem u-boot can
Not all devices use the convention of the first partition holding the boot
files. E.g. on chromebooks partition 1 and 2 are usually of the Chromeos
kernel data type. So instead of hardcoding just the first partitions scan all
partition on a storage device.
First two patches add some supporting
New command to determine the filesystem type of a given partition.
Optionally stores the filesystem type in a environment variable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
---
common/cmd_fs.c | 15 +++
fs/fs.c | 27 +++
include/fs.h
On 1 January 2015 at 16:17, Simon Glass s...@chromium.org wrote:
This should default to the size of the ROM for faster execution before
relocation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
Applied to u-boot-x86/next.
On 3 January 2015 at 19:26, Bin Meng bmeng...@gmail.com wrote:
On Fri, Jan 2, 2015 at 7:17 AM, Simon Glass s...@chromium.org wrote:
We don't need this in U-Boot since we calculate it based on available memory.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove
On 1 January 2015 at 16:17, Simon Glass s...@chromium.org wrote:
This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.
Signed-off-by: Simon Glass s...@chromium.org
Tested-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng
On 3 January 2015 at 19:31, Bin Meng bmeng...@gmail.com wrote:
On Fri, Jan 2, 2015 at 7:18 AM, Simon Glass s...@chromium.org wrote:
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
On 1 January 2015 at 16:17, Simon Glass s...@chromium.org wrote:
Provide a way to display this address when booting.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/video/x86_fb.c | 1 +
1 file changed, 1 insertion(+)
Applied to u-boot-x86/next.
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Signed-off-by: Simon
On 3 January 2015 at 20:28, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sun, Jan 4, 2015 at 11:20 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 3 January 2015 at 20:18, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Jan 2, 2015 at 7:18 AM, Simon Glass s...@chromium.org
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
On Tue, Jan 06, 2015 at 12:37:24AM +0900, Masahiro YAMADA wrote:
Tom,
Is there any reason why this patch is not applied?
Eh?
$ git log --pretty=fuller 1bf0979f5ff4c297149a705d129ab8db4bec7763 -n1
commit 1bf0979f5ff4c297149a705d129ab8db4bec7763
Author: Tom Rini tr...@ti.com
AuthorDate:
On 3 January 2015 at 21:13, Bin Meng bmeng...@gmail.com wrote:
On Fri, Jan 2, 2015 at 7:18 AM, Simon Glass s...@chromium.org wrote:
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove unused Lhlt code
- Use a simple
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass
On 3 January 2015 at 20:53, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Jan 2, 2015 at 7:18 AM, Simon Glass s...@chromium.org wrote:
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass
On 1 January 2015 at 16:18, Simon Glass s...@chromium.org wrote:
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now,
Albert,
I guess it is too late for that now. Thought it would make it into
2015.01, since your last comment in v2 suggested that you would treat it
as bugfix...
--
Stefan
On 2014-12-18 18:10, Stefan Agner wrote:
Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode
Hi,
I noticed that mx25pdk (ARM926) does not boot anymore with top of tree U-boot.
Doing a git bisect resulted in the following commit as being the guilty one:
commit 3ff46cc42b9d73d01c86df904425704410958470
Author: Georges Savoundararadj savou...@gmail.com
Date: Tue Oct 28 23:16:11 2014
From: Fabio Estevam fabio.este...@freescale.com
Since commit (arm: relocate the exception vectors) mx25pdk hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
We need to add a specific relocate_vectors macro, just like
From: Fabio Estevam fabio.este...@freescale.com
Since commit (arm: relocate the exception vectors) mx25pdk hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
We need to add a specific relocate_vectors macro, just like
On 5 Jan 2015, feste...@gmail.com wrote:
I noticed that mx25pdk (ARM926) does not boot anymore with top of tree
U-boot.
Doing a git bisect resulted in the following commit as being the
guilty one:
commit 3ff46cc42b9d73d01c86df904425704410958470
Author: Georges Savoundararadj
Hi Bill,
On Mon, Jan 5, 2015 at 8:25 PM, Bill Pringlemeir bpringlem...@nbsps.com wrote:
$ git show 3ff46cc42b9d73d01c86df9044257
/*
* Default/weak exception vectors relocation routine
*
* This routine covers the standard ARM cases: normal (0x),
* high (0x) and VBAR.
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws-fifo_len setting because it assumes the latest
register write fails so the latest valid value should be fifo - 1.
On 5 January 2015 at 08:27, Bin Meng bmeng...@gmail.com wrote:
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
nit: coreboot-specific defines
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
board/coreboot/coreboot/coreboot.c | 2
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to configure pci memory regions
arch/x86/cpu/coreboot/pci.c |
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to remove
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to update
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to hide ROM chip size when
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to move
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board
On Mon, Jan 5, 2015 at 8:41 PM, Fabio Estevam feste...@gmail.com wrote:
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+ ldr r1, =32 /* size of vector table */
+ add r0, r0, r1 /* skip to indirect
Hi Tom,
This didn't go through last time, it is on branch 'misc'.
The following changes since commit d622ac39274a949b6445f1bfd92dc1644014388b:
powerpc: mpc824x: remove MPC824X cpu support (2015-01-05 12:08:55 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git
Hi Tom,
On 29 December 2014 at 19:26, Tom Rini tr...@ti.com wrote:
On Mon, Dec 29, 2014 at 03:07:41PM -0700, Simon Glass wrote:
Hi Tom,
Here are a few misc fixes and updates. Note that the branch is 'misc'
(there is also a 'master' branch pull out there).
The following changes since
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
nit: coreboot-specific defines
OK.
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT,
Hi Tom,
Please see my patch carefully.
http://patchwork.ozlabs.org/patch/415041/
Your commit (1bf0979f5ff4c297) added the expert menu at the root menu.
Mine moves it under the General setup menu like Linux.
On Mon, 5 Jan 2015 12:41:56 -0500
Tom Rini tr...@ti.com wrote:
On Tue, Jan 06,
Hi Bin,
On 5 January 2015 at 19:31, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng bmeng...@gmail.com wrote:
Update README.x86 to include new build instructions for U-Boot as
Hi Simon,
On Tue, Jan 6, 2015 at 10:38 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 January 2015 at 19:14, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 6, 2015 at 9:50 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero,
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Hi,
On Tue, Jan 6, 2015 at 12:20 PM, Bin Meng bmeng...@gmail.com wrote:
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to hide ROM chip size when
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to configure pci memory regions
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3:
- Fix several typos in README.x86
Changes
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