Since commit 843125daebd7 (ppc4xx: remove HH405 board), CONFIG_HH405
is not defined.
Since commit d52633047913 (ppc4xx: remove PMC405), CONFIG_PMC405
is not defined.
Signed-off-by: Masahiro Yamada
Cc: Matthias Fuchs
---
arch/powerpc/cpu/ppc4xx/4xx_pci.c | 4
drivers/video/cfb_console.c
Now TQM8xx is the only remaining board family of mpc8xx.
It uses its own linker script, board/tqc/tqm8xx/u-boot.lds.
arch/powerpc/cpu/mpc8xx/u-boot.lds is not used by any boards.
Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
---
arch/powerpc/cpu/mpc8xx/u-boot.lds | 82 -
Yes, and it is working (linux kernel was booted without problem).
On Thursday 08 January 2015 22:53:18 Georges Savoundararadj
wrote:
> Hi Pali Rohár,
>
> Have you tested this patch on a secure device (as the nokia
> n900)?
>
> Regards,
>
> Georges
>
> Le 08/01/2015 10:11, Pali Rohár a écrit :
Fake option is enabled only when CONFIG_TRACE is
enabled in common/bootm.c:do_boot_states().
Signed-off-by: Michal Simek
---
common/cmd_bootm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 67233600b157..48199bfff3ed 100644
--- a/common/cmd
Hello Peg,
On 01/08/2015 02:00 PM, Peng Fan wrote:
This patch is to implement pmic_mode_init function, and add prototype
in header file.
This function is to set switching mode for pmic buck regulators to
improve system efficiency.
Mode:
OFF: The regulator is switched off and the output voltage
Hi, York,
> On 11/13/2014 06:12 AM, Alison Wang wrote:
> > CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
> > S0 will cause CAAM self test failure. This patch is to enable
> snooping
> > for S0 slave interface.
> >
> > Signed-off-by: Alison Wang
> > ---
> > board/freescale
Hello,
when starting U-Boot (from git master) on Nokia N900 it show lot
of these lines on N900 screen:
Timed out in wait_for_event: status=
Check if pads/pull-ups of bus 1 are properly configured
Timed out in wait_for_event: status=
Check if pads/pull-ups of bus 1 are properly configured
On Thursday 15 January 2015 10:07:05 Pali Rohár wrote:
> Hello,
>
> when starting U-Boot (from git master) on Nokia N900 it show
> lot of these lines on N900 screen:
>
> Timed out in wait_for_event: status=
> Check if pads/pull-ups of bus 1 are properly configured
> Timed out in wait_for_even
Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine.
There is no visible difference between legacy and generic board code.
Signed-off-by: Pali Rohár
---
include/configs/nokia_rx51.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/nokia_rx51.h b/include/conf
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop request
Hi,
Any updates or anyone succeed in enable the ttyUSB support in imx6 uboot ?
Shabeer
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Hi, Przemyslaw
On 1/15/2015 5:00 PM, Przemyslaw Marczak wrote:
Hello Peg,
On 01/08/2015 02:00 PM, Peng Fan wrote:
This patch is to implement pmic_mode_init function, and add prototype
in header file.
This function is to set switching mode for pmic buck regulators to
improve system efficiency.
This patch is to implement pfuze_mode_init and pfuze_regulator_mode_set
function, and add prototype in header file.
pfuze_mode_init is to set switching mode for all buck regulators to
improve system efficiency.
pfuze_regulator_mode_set is to set the regulator's mode according input
parameter.
Mod
This patch set is to support buck regulator can
working in different switching modes. To improve
system efficiency the buck regulators can operate
in different switching modes.
patch 1/3 is to add related bit definitions and registers.
patch 2/3 is to implement the switching mode init function.
pa
To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.
Signed-off-by: Peng Fan
---
Changes:
none
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 6 ++
board/freescale/mx6sabresd/mx6sabresd.c | 6 +-
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 6 +
Add more pfuze register offset.
And switch mode definition.
Signed-off-by: Peng Fan
---
Changes v2:
none
include/power/pfuze100_pmic.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
> > The SET_ADDRESS request is received just fine, it then sets
> > musb->ep0_state = MUSB_EP0_STAGE_STATUSIN; but no IRQ arrives to trigger
> > another call to musb_g_ep0_irq. Eventually, the host just sends back
> > another SET_REQUEST. Looking at dmesg on the host (Device not responding
> > to s
MCP7941x RTCs are very similar to ds1307. So add support in the ds1307 driver,
as it is done in the linux kernel
Signed-off-by: Soeren Moch
---
Cc: Tom Rini
Tom,
since the merge window is open now, can you pick up this patch?
Or do you think this should go through some other tree?
Thanks,
Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.
Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116
Signed-off-by: Volodymyr Riazantsev
---
drivers/mmc/fsl_esdhc.c | 8 ++--
include/fsl_esdhc.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
d
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay Saraswa
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos54
This patch series does following changes -
1. Removing compiler warnings for clock_get_periph_rate.
2. Adding and enabling support for Exynos542x in
clock_get_periph_rate.
3. Replacing peripheral specific function calls with
clock_get_periph_rate.
4. Remove code from clocks file which became
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Signed-off-by: Akshay Saraswat
---
Changes since v1:
- Separated exynos5_get_periph_rate fixes into another patch.
arch/arm/cpu/armv7/exynos/clock.c | 52 +
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat
---
Changes since v1:
Removing dead code of peripheral and SoC specific function
implementations which was used for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat
---
Changes since v1:
- No ch
This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.
Akshay Saraswat (10):
Exynos542x: Config: Add various configs
Exynos542x: CPU: Power down all secondary cores
Exynos542x: Add workaround for ARM errata 798870
Exynos542x: Add workaround for ARM er
This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4).
This is a part of iROM logic. Rest other flags are being
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a rece
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core s
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the log
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay Sara
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat
---
arch/arm/cpu/armv7/exynos/soc
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switc
From: Doug Anderson
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't ta
Hi Michal,
On 15 January 2015 at 01:53, Michal Simek wrote:
> Fake option is enabled only when CONFIG_TRACE is
> enabled in common/bootm.c:do_boot_states().
>
> Signed-off-by: Michal Simek
> ---
>
> common/cmd_bootm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/common/cmd_bootm.
On 14 January 2015 at 16:05, Simon Glass wrote:
> On 14 January 2015 at 01:07, Masahiro Yamada
> wrote:
>> The common/board_r.c has show_model_r() to display the model name
>> if the DTB has a "model" property. It sounds useful to have a similar
>> function in common/board_f.c too because most
Hi,
On 14 January 2015 at 01:18, Alexey Brodkin wrote:
> Hi Simon, Masahiro-san,
>
> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>> >
>> >> Probably I'm missing details of our Kconfig migration plan if one
>> >> exists. Then I'd like to get a reference to the plan so I'm not
>> >> attem
Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set
According to the "Cortex-A7 MPCore Technical Reference Manual":
"You must ensure this bit is set to 1 before the caches and MMU are enabled,
or any cache and TLB maintenance operations are performed."
Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
we should thus en
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .
Note for reviewers, cpu.h is effectively renamed tp cpu_sun4i.h by this
commit, the
Hi Ian, ChenYu,
I'm very happy to present this patch series which adds initial A80 support,
with this series a u-boot.bin can be build which can then be fel booted
using Allwinners boot0 fel binary, and then can load linux from a sdcard
using a standard extlinux.conf setup.
Next step getting RSB
As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/a
The DRAM Base differs between sun9i and the others and we cannot use
math in various places like the environment setting and linker scripts,
so "simply" define everything which contains the SDRAM_BASE twice.
Signed-off-by: Hans de Goede
---
include/configs/sunxi-common.h | 88 +++
Add a headerfile with all the base addresses from the sun9i blocks.
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 108
2 files changed, 112 insertions(+)
create mode 100755 arch/a
Add a headerfile with the sun9i ccu register layout.
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/clock.h | 2 +
arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 139 ++
2 files changed, 141 insertions(+)
create mode 100644 arch/arm/include/asm
The clocks on the A80 are hooked up slightly different, add support for this.
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/mmc.h | 5 -
drivers/mmc/sunxi_mmc.c | 14 --
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/inc
Wait 1 second for the sdcard to respond, rather then waiting for
0xf milliseconds.
Signed-off-by: Hans de Goede
---
drivers/mmc/sunxi_mmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6234981..ee8ad5c 100644
--
On 01/15/2015 03:25 PM, Simon Glass wrote:
> Hi Michal,
>
> On 15 January 2015 at 01:53, Michal Simek wrote:
>> Fake option is enabled only when CONFIG_TRACE is
>> enabled in common/bootm.c:do_boot_states().
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> common/cmd_bootm.c | 3 +++
>> 1 file ch
Hi Masahiro,
On 15 January 2015 at 00:29, Masahiro Yamada wrote:
> Hi Simon,
>
>
> A nit
>
>
> On Mon, 5 Jan 2015 20:05:26 -0700
> Simon Glass wrote:
>
>> For GPIOs and other functions we want to look up a phandle and then decode
>> a list of arguments for that phandle. Each phandle can have a
Hi Masahiro,
On 15 January 2015 at 00:28, Masahiro Yamada wrote:
> Hi Simon,
>
>
> You have already applied this patch.
>
> It might be too late, but...
>
>
>
> You can remove "#include "
> from lib/fdtdec.c.
>
>
>
> This is important for me to delete
> my dummy file arch/arm/include/asm/arch-un
On Wed, Jan 14, 2015 at 08:58:41AM +, Ian Campbell wrote:
> On Wed, 2015-01-14 at 08:57 +0100, Thierry Reding wrote:
> > > I also pushed my tree to gitorious:
> > > https://gitorious.org/ijc/u-boot jetson-psci-v1
> > >
> > > I would Ack your patch, but I don't think you've posted it an
On Tue, Oct 21, 2014 at 10:14:10PM +0200, Wolfgang Denk wrote:
> Prepare code to make later modifications checkpatch-clean.
>
> Signed-off-by: Wolfgang Denk
Applied to u-boot/master, thanks!
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On Wed, Jan 14, 2015 at 10:20:54PM +0100, Anatolij Gustschin wrote:
> Hey Tom,
>
> The following changes since commit 4c8c485ad9249e1ca1822474954b78799ca937e9:
>
> arc: introduce "mdbtrick" target (2015-01-09 23:59:54 +0300)
>
> are available in the git repository at:
>
> git://git.denx.de
On Tue, Dec 02, 2014 at 01:17:31PM -0700, Simon Glass wrote:
> Prior to commit d455d87 there was an inconsistency between the position of
> the 'address' parameter in 'sb load' and 'sb save'. This was corrected but
> it broke some tests. Fix the tests and also the help for 'sb save'.
>
> Signed-o
On Tue, Dec 02, 2014 at 01:17:29PM -0700, Simon Glass wrote:
> Commit 4d3b8a0d fixed a problem with lzma decompress where it would
> run out of bytes to decompress. The algorithm needs to know how many
> uncompressed bytes it is expected to produce.
>
> However, the fix introduced a potential buf
On Wed, Nov 19, 2014 at 03:26:18PM +0100, Meier, Roger wrote:
> From: "Meier, Roger"
>
> Goal:
> - building all variants of U-Boot with multiple configurations
> - code quality checks and metrics
> - https://travis-ci.org/u-boot/u-boot/builds
Applied to u-boot/master, thanks!
--
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s
On Tue, Dec 02, 2014 at 01:17:30PM -0700, Simon Glass wrote:
> This code is repeated in several places, and does not detect a common
> fault where the image is too large. Move it into its own function and
> provide a more helpful messages in this case, for compression schemes
> which support this.
On Tue, Dec 02, 2014 at 01:17:34PM -0700, Simon Glass wrote:
> Try to keep the names of the unit test commands consistent.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:32PM -0700, Simon Glass wrote:
> Sometimes it is useful to see the output from U-Boot, so add an option to
> make this easier.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:33PM -0700, Simon Glass wrote:
> Export this function for testing. Also add a parameter so that values other
> than CONFIG_SYS_BOOTM_LEN can be used for the maximum uncompressed size.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:35PM -0700, Simon Glass wrote:
> Use each compression method (including uncompressed). Test for normal
> operation, insufficient space and corrupted data.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:37PM -0700, Simon Glass wrote:
> Adjust the code so that the error reporting can all be done at the end,
> and is the same for each decompression method. Try to detect when
> decompression fails due to lack of space. Keep the behaviour of
> resetting on failure even t
On Tue, Dec 02, 2014 at 01:17:38PM -0700, Simon Glass wrote:
> This allows the caller to easily detect how much of the destination buffer
> has been used.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:39PM -0700, Simon Glass wrote:
> This allows the caller to easily detect how much of the destination buffer
> has been used.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Wed, Dec 03, 2014 at 01:40:58PM -0500, Bill Pringlemeir wrote:
> Some MTD defines are repeated twice; once with UBI and then with MTD.
> Remove the duplicate MTD defines from the UBI grouping.
>
> Signed-off-by: Bill Pringlemeir
Applied to u-boot/master, thanks!
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On Tue, Dec 16, 2014 at 02:07:21PM +0100, Marek Vasut wrote:
> Add separate image type for the Wittenstein OpenRTOS .
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
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Hello Peng,
On 01/15/2015 11:18 AM, Peng Fan wrote:
This patch is to implement pfuze_mode_init and pfuze_regulator_mode_set
function, and add prototype in header file.
pfuze_mode_init is to set switching mode for all buck regulators to
improve system efficiency.
pfuze_regulator_mode_set is to s
On Tue, Dec 16, 2014 at 02:07:22PM +0100, Marek Vasut wrote:
> Allow booting the OpenRTOS payloads via fitImage image type.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
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On Tue, Dec 02, 2014 at 01:17:40PM -0700, Simon Glass wrote:
> This allows the caller to easily detect how much of the destination buffer
> has been used.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
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On Wed, Jan 14, 2015 at 03:36:34PM +0100, Michal Simek wrote:
> Trivial fix.
>
> Signed-off-by: Michal Simek
Applied to u-boot/master, thanks!
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On Mon, Dec 08, 2014 at 05:49:42PM +0100, Evgeni Dobrev wrote:
> Add support for Seagate BlackArmor NAS220
>
> Signed-off-by: Evgeni Dobrev
Applied to u-boot/master, thanks!
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On Thu, Jan 08, 2015 at 07:23:35PM +0900, Masahiro Yamada wrote:
> If CONFIG_SPL_NOR_SUPPORT is defined, spl_nor_load_image() requires
> spl_start_uboot(), CONFIG_SYS_OS_BASE, CONFIG_SYS_SPL_ARGS_ADDR,
> CONFIG_SYS_FDT_BASE to be defined even if users just want to run
> U-Boot, not Linux. This is
Hey Wolfgang,
Hmm, I think I might not have made my point clear enough ... my
apologies! Either that or I have a fundamental misunderstanding of the
issue (more likely).
No. See the FAQ entry. The entry point address really depends on te
code. If you add code, it can be basically anywehre
On Wed, Jan 14, 2015 at 03:36:35PM +0100, Michal Simek wrote:
> Signed-off-by: Michal Simek
Applied to u-boot/master, thanks!
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On Wed, Jan 14, 2015 at 04:00:39PM +0100, Michal Simek wrote:
> Use phys_addr_t instead of int for addresses.
> Addresses can't be < 0.
>
> Signed-off-by: Michal Simek
Note that this introduces:
w+(microblaze-generic) ../drivers/net/xilinx_ll_temac.c: In function
'll_temac_init':
w+(microblaze
On Tue, Jan 13, 2015 at 06:49:01PM +0300, Alexey Brodkin wrote:
> It makes sense to specify CONFIG_SYS_CLK_FREQ in "configs/xx_defconfig"
> instead of "include/configs/xxx.h" because then header will be reusable
> across boards with different CPU clocks.
>
> Also this nice to have an ability for
On Tue, Dec 02, 2014 at 01:17:36PM -0700, Simon Glass wrote:
> Refactor to allow this function to be used to announce the image being
> loaded regardless of compression type and even when there is no
> decompression.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
si
On 15 January 2015 at 07:55, Michal Simek wrote:
> On 01/15/2015 03:25 PM, Simon Glass wrote:
>> Hi Michal,
>>
>> On 15 January 2015 at 01:53, Michal Simek wrote:
>>> Fake option is enabled only when CONFIG_TRACE is
>>> enabled in common/bootm.c:do_boot_states().
>>>
>>> Signed-off-by: Michal Sim
Dear all,
i would like to post a patch with the m68k generic board
support, tested and working here, but of course not tested
for all the other m68k boards except mine.
My coldfire board is the "amcore" board not yet accepted.
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/193661
http:/
The Fusion LCD needs the 32bit color depth to properly work; the
default is different on the 3.10.17 kernels and it is better to ensure
it work out of box using proper default color setting.
Signed-off-by: Otavio Salvador
---
include/configs/wandboard.h | 2 +-
1 file changed, 1 insertion(+), 1
Hello list,
I'm using u-boot-2014.10 and trying to build it with LCD support for the
Beaglebone black to include a Boot logo image.
It seems that spl hangs while loading a 2.8MB sized u-boot.img !
I reduced the the logo header file and rebuild u-boot, that worked for a
1.6MB sized u-boot.img.
Is
Signed-off-by: Hans de Goede
---
configs/Merrii_A80_Optimus_defconfig | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 configs/Merrii_A80_Optimus_defconfig
diff --git a/configs/Merrii_A80_Optimus_defconfig
b/configs/Merrii_A80_Optimus_defconfig
new file mode 100644
index 000.
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 68 ++
2 files changed, 69 insertions(+)
create mode 100644 a
Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile| 2 ++
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi/cpu_info.c | 5 +
arch/arm/cpu/armv7/sunxi/lowlevel_in
Since GPIO support has now moved to the driver model uclass, we can drop
this include.
Signed-off-by: Simon Glass
---
lib/fdtdec.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3306028..fe30305 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -11,8 +11,6
On 01/15/2015 01:29 AM, Alison Wang wrote:
> CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
> S0 will cause CAAM self test failure. This patch is to enable snooping
> for S0 slave interface. These CCI-400 operations are moved to
> board_early_init_f() to be initialized earli
This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical addre
On 01/15/2015 03:59 PM, Tom Rini wrote:
> On Wed, Jan 14, 2015 at 04:00:39PM +0100, Michal Simek wrote:
>
>> Use phys_addr_t instead of int for addresses.
>> Addresses can't be < 0.
>>
>> Signed-off-by: Michal Simek
>
> Note that this introduces:
> w+(microblaze-generic) ../drivers/net/xilinx_ll
Yuantian,
On 12/17/2014 05:55 PM, Tang Yuantian wrote:
> A new deep sleep interface is introduced to support generic
> board structure. Converts it to use new interface.
>
> Signed-off-by: Tang Yuantian
> ---
> board/freescale/t102xqds/ddr.c | 19 +++
> board/freescale/t102
Hi Alexey,
2015-01-14 17:18 GMT+09:00 Alexey Brodkin :
> Hi Simon, Masahiro-san,
>
> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>> >
>> >> Probably I'm missing details of our Kconfig migration plan if one
>> >> exists. Then I'd like to get a reference to the plan so I'm not
>> >> atte
On 01/15/2015 12:13 AM, Masahiro Yamada wrote:
> All the 74xx_7xx boards are still non-generic boards:
> P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
>
> Signed-off-by: Masahiro Yamada
> Cc: Wolfgang Denk
> Cc: Nye Liu
> Cc: Roy Zang
> ---
7xx or 74xx are pretty old. I don't even have any board
Hi
2015-01-15 23:46 GMT+09:00 Simon Glass :
> Hi,
>
> On 14 January 2015 at 01:18, Alexey Brodkin
> wrote:
>> Hi Simon, Masahiro-san,
>>
>> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>>> >
>>> >> Probably I'm missing details of our Kconfig migration plan if one
>>> >> exists. Then I'd
On Thu, Jan 15, 2015 at 06:10:57AM +, bhupesh.sha...@freescale.com wrote:
> Hi York,
>
> > -Original Message-
> > From: Sun York-R58495
> > Sent: Wednesday, January 14, 2015 9:44 PM
> > On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
> > > This patch adds basic constructs in the ARMv8 u-
Vijay,
On 12/19/2014 04:35 AM, Vijay Rai wrote:
> Add support of 2 stage SD boot loader using SPL framework.
> here, PBL initialise the internal SRAM and copy SPL(160KB). This further
> initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR.
> Finally SPL transer control to
Hi Mark,
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: Friday, January 16, 2015 12:35 AM
> To: Sharma Bhupesh-B45370
> Cc: Sun York-R58495; u-boot@lists.denx.de; albert.u.b...@aribaud.net;
> Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [U-Boot] [P
On 01/15/2015 11:05 AM, Mark Rutland wrote:
> On Thu, Jan 15, 2015 at 06:10:57AM +, bhupesh.sha...@freescale.com wrote:
>> Hi York,
>>
>>> -Original Message-
>>> From: Sun York-R58495
>>> Sent: Wednesday, January 14, 2015 9:44 PM
>>> On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
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