Update t4160/t4080 serdes according to latest reference manual rev2.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git
-Original Message-
From: Sun York-R58495
Sent: Thursday, July 16, 2015 2:06 AM
To: Wang Dongsheng-B40534
Cc: Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; Zhang
Zhuoyu-
B46552; u-boot@lists.denx.de
Subject: Re: [PATCH] arm/layerscape: Fix non-boot cpus cannot
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.
To handle indirect transfer we need to issue addresses
There is no need to check for sram fill level. If sram is empty, cpu will go in
the wait state till the time data is available from flash.
Also Relying on SRAM fill level only for deciding when the data should be
fetched from the local SRAM is not most efficient approach, particularly
if we are
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..1ae7edf 100644
---
This patchset:
- removes sram polling while reading/writing from flash.
- fixes trigger base transfer start address register programming. This fix
superseeds the previous patch spi: cadence_qspi: Fix the indirect ahb trigger
address setting.
- adds support to get fifo width from device tree
There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c | 61
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |6 --
* Extend imximage DCD version 2 to support DCD commands
CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:
while ((*address ~mask) != 0);
CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
while ((*address mask) != mask);
CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
*address =
On 12 July 2015 at 22:17, Masahiro Yamada yamada.masah...@socionext.com wrote:
As you see in driver/Makefile, Kbuild descends into the driver/core/
directory only when CONFIG_DM is enabled.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2:
- Newly added
On 07/15/2015 05:49 PM, Adrian Alonso wrote:
* Add pmic pfuze300 support for imx7 and iMX6 DL/SL/SX SoC's
* Implement power_pfuze300_init to be used in power_init_board
callback function.
Signed-off-by: Adrian Alonso aalo...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
Hello Stefan,
On Tue, 14 Jul 2015 12:29:52 +0200, Stefan Agner ste...@agner.ch
wrote:
Hi Stefano,
On 2015-07-10 10:14, Stefano Babic wrote:
On 19/06/2015 14:18, Albert ARIBAUD (3ADEV) wrote:
imximage header size is 4-byte, not 8-byte aligned.
This produces .imx images that a Vybrid
This patch series mainly add MP support to QEMU as well as some
other necessary fixes for x86.
Verified by booting Linux kernel on QEMU i440FX and Q35, and make
sure I/O APIC interrupt is being used by the kernel with the help
of MP table provided by U-Boot.
This series is the prerequisite for
The mv78260 needs atleast 10ms after setting the ddr3 training patterns
or else the cpu will hang.
This patch increases said delay to 20ms just to be safe.
Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov luka.per...@sartura.hr
---
Hi, Mark
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Wednesday, July 15, 2015 5:14 PM
To: Wang Huan-B18965
Cc: Sun York-R58495; u-boot@lists.denx.de; Wang Huan-B18965;
marc.zyng...@arm.com
Subject: Re: [U-Boot] [PATCH] arm: ls1021a: Ensure LS1021 ARM
Now, a simple pinctrl patch is being proposed by Simon.
http://patchwork.ozlabs.org/patch/487801/
In the design above, as you see, the uclass is just like a wrapper layer
to invoke .request and .get_periph_id of low-level drivers.
In other words, it is Do-It-Yourself thing, so it is up to you how
The pinctrl driver is tightly integrated with the each SoC,
so it is reasonable to select it from Kconfig.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/mach-uniphier/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-uniphier/Kconfig
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/dts/uniphier-ph1-ld4.dtsi | 30 ++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 34
arch/arm/dts/uniphier-ph1-sld8.dtsi | 30 ++
arch/arm/dts/uniphier-pinctrl.dtsi | 80
Add pinmux support for UniPhier PH1-LD4 SoC.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
drivers/pinctrl/uniphier/Kconfig | 4 ++
drivers/pinctrl/uniphier/Makefile | 2 +
drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c | 69 ++
3
I'd like to propose antoher pinctrl design, which is closer to Linux's one.
1/7 adds the uclass support.
2/7 - 5/7 show how low-level drivers can be implemeted on my SoCs as example.
You can implement them in your own way, but they are often done with
architecture-specific operation +
Turn on PCIe ECAM address range decoding on Q35.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/qemu/pci.c | 4
arch/x86/include/asm/arch-qemu/qemu.h | 4
2 files changed, 8 insertions(+)
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index
Enable writing MP table for QEMU boads (i440fx and q35).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/qemu/pci.c| 34 +++---
configs/qemu-x86_defconfig | 1 +
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/qemu/pci.c
Hi Simon,
It seems that we don't update the source image name to u-boot-dtb.bin in
case of enabling CONFIG_OF_SEPARATE when generate u-boot-with-spl.bin file.
ifdef CONFIG_TPL
SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
else
SPL_PAYLOAD := u-boot.bin
endif
OBJCOPYFLAGS_u-boot-with-spl.bin = -I
On Wed, Jul 8, 2015 at 4:53 AM, Simon Glass s...@chromium.org wrote:
This binding differs from that of Linux. Update it and change existing
users.
Signed-off-by: Simon Glass s...@chromium.org
I'm confused by this. Isn't devicet...@vger.kernel.org the place to discuss
device tree bindings?
Hello Wolfgang,
Wolfgang Denk wrote on 2015-07-15:
2. For some time now, we provide not only the classic FTP server for
download of the U-Boot release tarballs, but also a public
directory in the Amazon Cloud Drive [1]. The ACD is supposed to
provide much better connectivity
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/pci.c | 27 +--
arch/x86/include/asm/pci.h | 3 +--
arch/x86/lib/pirq_routing.c | 3 +--
3 files changed, 19
Turn on cache on the pci option rom area to improve the performance.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/cpu.c | 27 ---
arch/x86/include/asm/mtrr.h | 2 ++
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/chromebook_link.dts| 1 +
arch/x86/dts/chromebox_panther.dts | 1 +
arch/x86/dts/galileo.dts| 1 +
arch/x86/dts/minnowmax.dts | 1 +
Memory footprint analysis:
This uclass support increased 2.5KB on my board (ARM).
Additional 1-2KB would be necessary to implement your
low-level driver.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi Wolfgang,
On Wed, Jul 15, 2015 at 3:24 PM, Wolfgang Denk w...@denx.de wrote:
Hello all,
we're planning some reorganization / updates for our servers:
1. We will move all git repositories to a new, faster machine.
In this process, the web interface will change (moving from
gitweb
Hello Masahiro,
On Wed, 15 Jul 2015 17:16:16 +0900, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Now, a simple pinctrl patch is being proposed by Simon.
http://patchwork.ozlabs.org/patch/487801/
In the design above, as you see, the uclass is just like a wrapper layer
to invoke
I forgot to mention this:
This series needs libfdt fixes as prerequisites:
http://patchwork.ozlabs.org/patch/495166/
http://patchwork.ozlabs.org/patch/495168/
This patch depends on some libfdt helpers that are fatally buggy.
Masahiro
___
U-Boot
Hi,
Isn't this the same patch as a couple of days ago [2], which I replied
to [3]?
On Wed, Jul 15, 2015 at 08:13:05AM +0100, Alison Wang wrote:
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5
From: Shaohui Xie shaohui@freescale.com
T4160 and T4080 support same serdes options, which serdes 2 3 support 8
Lanes, same as T4240, but serdes 1 4 support only 4 Lanes, Lanes A, B,
C, D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui
Hello Stefano,
On Wed, 15 Jul 2015 09:19:55 +0200, Stefano Babic sba...@denx.de
wrote:
I think my patch back then solves the issue nicer. The struct dcd_v2_t
is not the reason the whole header is not aligned by 8-byte, it is a
problem of the boot_data_t header which is 12 bytes long. So
Hi Wolfgang,
On 07/15/15 10:24, Wolfgang Denk wrote:
Hello all,
we're planning some reorganization / updates for our servers:
1. We will move all git repositories to a new, faster machine.
In this process, the web interface will change (moving from
gitweb to cgit). In this
Hello Albert,
On 15.07.2015 10:05, Albert ARIBAUD wrote:
Hello Vladimir,
On Tue, 14 Jul 2015 23:23:57 +0300, Vladimir Zapolskiy v...@mleia.com
wrote:
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers
to communicate
Wolfgang wrote...
{snip}
2. For some time now, we provide not only the classic FTP server for
download of the U-Boot release tarballs, but also a public
directory in the Amazon Cloud Drive [1]. The ACD is supposed to
provide much better connectivity (especially for non-european
2015-07-15 17:53 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
Hello Masahiro,
On Wed, 15 Jul 2015 17:16:16 +0900, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Now, a simple pinctrl patch is being proposed by Simon.
http://patchwork.ozlabs.org/patch/487801/
In the design
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Signed-off-by: Anton Schubert anton.schub...@gmx.de
Cc: Stefan Roese s...@denx.de
Cc: Luka Perkov
Hello Vladimir,
On Wed, 15 Jul 2015 11:49:01 +0300, Vladimir Zapolskiy v...@mleia.com
wrote:
Hello Albert,
On 15.07.2015 10:05, Albert ARIBAUD wrote:
Hello Vladimir,
On Tue, 14 Jul 2015 23:23:57 +0300, Vladimir Zapolskiy v...@mleia.com
wrote:
The change adds support of LPC32xx SLC
Add pinmux support for UniPhier PH1-sLD8 SoC.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
drivers/pinctrl/uniphier/Kconfig| 4 ++
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c | 65 +
Add pinmux support for UniPhier PH1-Pro4 SoC.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
drivers/pinctrl/uniphier/Kconfig| 4 ++
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c | 69 +
The core support for the pinctrl drivers for all the UniPhier SoCs.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
drivers/pinctrl/Kconfig | 2 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/uniphier/Kconfig
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/lib/mpspec.c
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/qemu/pci.c | 7 ++-
arch/x86/include/asm/arch-qemu/qemu.h | 6 +-
2
The existing MP initialization process works on QEMU multicore,
except that we need increase delay time for BSP to wait APs to
show up online. Use a Kconfig option to control the delay time
factor to the normal one.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/mp_init.c
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/include/asm/mpspec.h | 17 +
IRQ 0 is reserved and should not be assigned to pci device.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index fdfd5f7..f8da080 100644
--- a/arch/x86/cpu/pci.c
+++
On Wed, Jul 15, 2015 at 11:38 AM, Arnd Bergmann a...@arndb.de wrote:
The CHRP ISA binding defines that a 8250 compatible UART must have this
property:
clock-frequency S
Standard property, encoded as with encode-int, that shall be the baud-rate
generator's clock input frequency (in
To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with
cd u-boot/tools/patman python setup.py install
There are also the usual distutils options for creating source/binary
distributions of patman.
Signed-off-by: Chris Packham
Dear Tom,
In message 20150714175627.GJ23886@bill-the-cat you wrote:
I've pushed v2015.07 out to the repository and tarballs should exist
soon.
Tarballs are both on the ACD [1] and the FTP server [2].
[1]
Hello.
Im trying to compile U-Boot for a RK3168 cpu with make rk30xx, but when
flashing the resulting binary (RK3066Loader_miniall.bin) I receive a
check chip fail error and cannot flash the new bootloader.
Im guessing that the rk30xx config is not compatible with this cpu?
This is a tablet
Hello Vladimir,
On Tue, 14 Jul 2015 23:23:57 +0300, Vladimir Zapolskiy v...@mleia.com
wrote:
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver
On 14/07/2015 21:05, Baruch Siach wrote:
Hi Stefano,
On Thu, Jul 09, 2015 at 06:04:17PM +0200, Stefano Babic wrote:
On 09/07/2015 17:19, Baruch Siach wrote:
When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine
generates is empty. This causes HAB to complain that the
Hi Stefan,
On 14/07/2015 12:29, Stefan Agner wrote:
Applied to u-boot-imx, thanks !
Sorry, just stumbled over this message now.
We discussed exactly this issue already more than a year ago, see:
http://lists.denx.de/pipermail/u-boot/2014-April/177580.html
I admit that I have forgotten
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29
Hello all,
we're planning some reorganization / updates for our servers:
1. We will move all git repositories to a new, faster machine.
In this process, the web interface will change (moving from
gitweb to cgit). In this process, for a (hopefully) short time,
access to the git
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
This code allows using DFU defined mediums for storing data received via
TFTP protocol.
It reuses legacy code at common/update.c.
To run update_tftp() during boot one needs to define
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
Documentation file for DFU extension. With this functionality it is now
possible to transfer FIT images with firmware updates via TFTP and use
DFU backend for storing them.
Signed-off-by: Lukasz Majewski
Hi Vitaly,
On Wed, Jul 8, 2015 at 10:56 AM, Vitaly Andrianov vita...@ti.com wrote:
The MCAST_TFTP support requires that network drivers has mcast functon
implemented. This commit adds dummy keystone2_eth_bcast_addr() to meet
the requirement. As far as the driver doesn't use ALE and doesn't
On 07/14/2015 12:09 AM, Wang Dongsheng-B40534 wrote:
Hi Alison Jason,
Could you ACK this patch?
Regards,
-Dongsheng
-Original Message-
From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
Sent: Thursday, June 18, 2015 6:33 PM
To: Sun York-R58495
Cc: Jin
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
Up till now it was impossible to use code from update.c when system
was not equipped with raw FLASH memory.
Such behavior prevented DFU from reusing this code.
Signed-off-by: Lukasz Majewski
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
This change gives the ability to reuse the tftp.h header file by other
subsystems (like e.g. dfu).
Without this change compilation error emerges for the legacy update.c file.
Signed-off-by: Lukasz
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
This function allows writing via DFU data stored from fixed buffer address
(like e.g. loadaddr env variable).
Such predefined buffers are used in the update_tftp() code. In fact this
function is a
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
The new 'dfutftp' command has syntax similar to 'dfu' command.
This new command however, requires some extra env variables to allow
update_tftp() code to work properly. For more explanation, please consult
Hi Albert,
On 2015-07-15 09:54, Albert ARIBAUD wrote:
Hello Stefano,
On Wed, 15 Jul 2015 09:19:55 +0200, Stefano Babic sba...@denx.de
wrote:
I think my patch back then solves the issue nicer. The struct dcd_v2_t
is not the reason the whole header is not aligned by 8-byte, it is a
Hi Anton,
On 15.07.2015 11:01, Anton Schubert wrote:
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
But it doesn't enable the IDE interface and
1/2: refactors a little because NDS32 actually need not the symbolic link
2/2: introduce a new config to avoid broken symbolic links.
Masahiro Yamada (2):
nds32: include asm/arch-*/*.h instead of asm/arch/*.h
kbuild: create symbolic link only for ARM, AVR32, SPARC, PowerPC, x86
The symbolic link to SoC/CPU specific header directory is created
during the build, while it is only necessary for ARM, AVR32, SPARC,
x86, and some CPUs of PowerPC. For the other architectures, it just
results in a broken symbolic link.
Introduce CONFIG_CREATE_ARCH_SYMLINK to not create unneeded
On Wednesday 15 July 2015 12:08:05 Linus Walleij wrote:
On Wed, Jul 15, 2015 at 11:38 AM, Arnd Bergmann a...@arndb.de wrote:
The CHRP ISA binding defines that a 8250 compatible UART must have this
property:
clock-frequency S
Standard property, encoded as with encode-int, that
Hello Thierry,
On Wed, 15 Jul 2015 13:17:18 +0200, Thierry Reding
thierry.red...@gmail.com wrote:
On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
+Scott, Masahiro
Hi Thierry,
On 25 March 2015 at 17:23, Simon Glass s...@chromium.org wrote:
Hi Thierry,
On 8
Hello Stefan (and sorry for the duplicate),
On Wed, 15 Jul 2015 12:41:59 +0200, Stefan Agner ste...@agner.ch
wrote:
Hi Albert,
On 2015-07-15 09:54, Albert ARIBAUD wrote:
Hello Stefano,
On Wed, 15 Jul 2015 09:19:55 +0200, Stefano Babic sba...@denx.de
wrote:
I think my patch back
There are only two SoC-specific headers for this architecture:
- arch/nds32/include/asm/arch-ag101/ag101.h
- arch/nds32/include/asm/arch-ag102/ag102.h
Those two have different file names, so there is no advantage to
include them via symbolic linked directory.
Signed-off-by: Masahiro Yamada
On Wed, Jul 15, 2015 at 01:35:26PM +0200, Albert ARIBAUD wrote:
Hello Thierry,
On Wed, 15 Jul 2015 13:17:18 +0200, Thierry Reding
thierry.red...@gmail.com wrote:
On Tue, Jul 14, 2015 at 01:48:45PM -0600, Simon Glass wrote:
+Scott, Masahiro
Hi Thierry,
On 25 March 2015 at
Hi Anton,
On 15.07.2015 14:03, Anton Schubert wrote:
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Changes v2:
- add second bus offset
- only
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Signed-off-by: Anton Schubert anton.schub...@gmx.de
Tested-by: Stefan Roese s...@denx.de
Cc: Luka Perkov
Dear Bin,
In message caeuhbmuxs5de_un0fvjo+cawalfp-1gu1j+ra_wplypjfo0...@mail.gmail.com
you wrote:
Is the U-Boot mailing list hosted on the same machine as git? Will
this move also fix the mailing list occasional hiccup issue?
Yes, at the moment this is on the same, old and slow machine.
We
Dear Thomas,
In message 593aef6c47f46446852b067021a273d6fbc78...@mucse037.lantiq.com you
wrote:
I tried to find a way to download a file with wget or a similar tool, which
would be used by a distribution builder (like Yocto, Buildroot, OpenWrt, ...).
Why would any build environment use
On 07/15/2015 10:14 AM, Tom Rini wrote:
On Wed, Jul 15, 2015 at 09:54:41AM -0600, Simon Glass wrote:
Hi Stephen,
On 15 July 2015 at 09:50, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/14/2015 05:33 PM, Tom Rini wrote:
On Tue, Jul 14, 2015 at 04:39:01PM -0600, Stephen Warren wrote:
On
Hi Vladimir Albert,
As stated before, I tested this patch and the 3 patches listed below using a
Micrel KSZ8031RNL phy connected over RMII. Everything is working properly.
1) http://patchwork.ozlabs.org/patch/489100/
2) http://patchwork.ozlabs.org/patch/489190/
3)
hi joe,
maybe my email got lost ...
best regards,
Hannes
On 2015-06-22 14:23, Hannes Schmelzer wrote:
Hi joe,
you did introduce callbacks on setting up ip,dns, ... in net.c
Why it did become necessary to do following ?
if (flags H_PROGRAMMATIC)
return 0;
I have
Simon,
Did it happen to you with this warning?
lib/fdtdec.c:108:4: warning: format ‘%x’ expects argument of type ‘unsigned
int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug(addr=%08lx, size=%08x\n,
^
I think when we have 64-bit physical address, as defined in fdtdec.h, this
Hi Vladimir and Albert,
During this merge window (once our issues with our exchange server are
resolve), we were planning on submitting a few patches for the LPC32xx.
Some of the patches are the porting of the legacy NXP BSP (u-boot) drivers into
the latest version; the drivers are the DMA,
Hi Simon,
On Thu, Jul 9, 2015 at 9:15 AM, Simon Glass s...@chromium.org wrote:
With driver model drivers can have things stored in several places. There is
driver-private data, then the uclass can attach things to a device. If the
device is on a bus then its bus may attach parent data to the
Hi Stephen,
On 15 July 2015 at 10:28, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/15/2015 09:54 AM, Simon Glass wrote:
Hi Stephen,
On 15 July 2015 at 09:50, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/14/2015 05:33 PM, Tom Rini wrote:
On Tue, Jul 14, 2015 at 04:39:01PM
Hi Lukasz,
On Sun, Jul 12, 2015 at 10:30 AM, Lukasz Majewski l.majew...@majess.pl wrote:
This commit adds initial support for using tftp for downloading and
upgrading firmware on the device.
Signed-off-by: Lukasz Majewski l.majew...@majess.pl
---
drivers/dfu/Makefile | 1 +
Hi,
On 15 July 2015 at 02:42, Wang Haikun haikun.w...@freescale.com wrote:
Hi Simon,
It seems that we don't update the source image name to u-boot-dtb.bin in
case of enabling CONFIG_OF_SEPARATE when generate u-boot-with-spl.bin file.
ifdef CONFIG_TPL
SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
fdt_addr_t and fdt_size_t can be either 64-bit or 32-bit, depending
on the architecture. Change the type to phys_addr_t and phys_size_t.
Signed-off-by: York Sun york...@freescale.com
---
include/fdtdec.h |7 +++
lib/fdtdec.c |4 ++--
2 files changed, 5 insertions(+), 6
Hi Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Monday, July 13, 2015 2:01 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi:
Hello York,
On Wed, 15 Jul 2015 13:02:07 -0700, York Sun york...@freescale.com
wrote:
Simon,
Did it happen to you with this warning?
lib/fdtdec.c:108:4: warning: format ‘%x’ expects argument of type ‘unsigned
int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug(addr=%08lx,
Hi York,
On 15 July 2015 at 14:25, York Sun york...@freescale.com wrote:
On 07/15/2015 01:23 PM, Albert ARIBAUD wrote:
Hello York,
On Wed, 15 Jul 2015 13:02:07 -0700, York Sun york...@freescale.com
wrote:
Simon,
Did it happen to you with this warning?
lib/fdtdec.c:108:4: warning:
On Wed, Jul 15, 2015 at 7:06 AM, Chris Packham judge.pack...@gmail.com wrote:
To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with
cd u-boot/tools/patman python setup.py install
There are also the usual distutils options for
On Wed, Jul 15, 2015 at 02:12:15PM -0600, Stephen Warren wrote:
On 07/15/2015 10:14 AM, Tom Rini wrote:
On Wed, Jul 15, 2015 at 09:54:41AM -0600, Simon Glass wrote:
Hi Stephen,
On 15 July 2015 at 09:50, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/14/2015 05:33 PM, Tom Rini wrote:
Hello SYLVAIN,
On Wed, 15 Jul 2015 19:23:33 +, LEMIEUX, SYLVAIN
slemi...@tycoint.com wrote:
Hi Vladimir and Albert,
During this merge window (once our issues with our exchange server
are resolve), we were planning on submitting a few patches for the
LPC32xx.
Some of the patches are
On 07/15/2015 01:23 PM, Albert ARIBAUD wrote:
Hello York,
On Wed, 15 Jul 2015 13:02:07 -0700, York Sun york...@freescale.com
wrote:
Simon,
Did it happen to you with this warning?
lib/fdtdec.c:108:4: warning: format ‘%x’ expects argument of type ‘unsigned
int’, but argument 3 has type
On 07/15/2015 01:29 PM, Simon Glass wrote:
Hi York,
On 15 July 2015 at 14:25, York Sun york...@freescale.com wrote:
On 07/15/2015 01:23 PM, Albert ARIBAUD wrote:
Hello York,
On Wed, 15 Jul 2015 13:02:07 -0700, York Sun york...@freescale.com
wrote:
Simon,
Did it happen to you with
From: Jiandong Zheng jdzh...@broadcom.com
Add Ethernet PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng jdzh...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
drivers/net/phy/broadcom.c | 29 +
1 file changed, 29 insertions(+)
diff --git
From: Jiandong Zheng jdzh...@broadcom.com
Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng jdzh...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
arch/arm/include/asm/arch-bcmcygnus/configs.h | 11 +++
board/broadcom/bcm_ep/board.c
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