[U-Boot] [PATCH] tools/kwbimage: add BAUDRATE option

Offset 0x18 in some Marvell datasheets this field is redacted as "reserved". This offset is actually a set of options and bits 2:0 allow the selection of the UART baudrate. Allow a BAUDRATE option to set the UART baudrate for any messages coming from the BootROM firmware. Signed-off-by: Chris

Re: [U-Boot] [RFC PATCH 00/10] sunxi: Allwinner A64 SPL support

Hi, On 03/11/16 09:38, Andre Przywara wrote: > Hi, > > On 03/11/16 08:49, Alexander Graf wrote: >> On 11/03/2016 02:36 AM, Andre Przywara wrote: >>> Hi, >>> >>> this is my first take on the SPL support for the Allwinner A64 SoC. >>> The actual meat - the DRAM initialization code - has been

[U-Boot] [PATCH] tools/kwbimage: add DEBUG option

Offset 0x1 in the generated kwb image file is a set of flags, bit 0 enables debug output from the BootROM firmware. Allow a DEBUG option in the kwb configuration to request debug output from the BootROM firmware. Signed-off-by: Chris Packham --- tools/kwbimage.c | 9

[U-Boot] [PATCH v2 5/7] arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial support

From: Jagan Teki Boot from MMC: - U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model:

[U-Boot] [PATCH v2 7/7] imx6: icorem6: Rename engicam icorem6 defconfig files

From: Jagan Teki Rename defconfig files for better compatible with respective board names and dts files. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki

[U-Boot] [PATCH v2 4/7] net: fec: Zap local mac variable

From: Jagan Teki Call dev->enetaddr or pdata->enetaddr directly in eth_ops instead of local mac variable. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Acked-by: Joe Hershberger

[U-Boot] [PATCH v2 6/7] arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial support

From: Jagan Teki Boot from MMC: - U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Model:

[U-Boot] [PATCH v2 2/7] arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support

From: Jagan Teki Boot Log: U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU:

[U-Boot] [PATCH v2 1/7] arm: dts: Add devicetree for i.MX6UL

From: Jagan Teki Add i.MX6UL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Stefano Babic Cc: Matteo Lisi

[U-Boot] [PATCH v2 0/7] imx6: Add Engicam GEAM6UL/i.CoreM6 RQS board support

From: Jagan Teki Changes for v2: - Add 'Acked-by' from Joe - Add new i.CoreM6 RQS patches Jagan Teki (7): arm: dts: Add devicetree for i.MX6UL arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support dm: net: fec: Add .read_rom_hwaddr net: fec: Zap local

[U-Boot] [PATCH v2 3/7] dm: net: fec: Add .read_rom_hwaddr

From: Jagan Teki Add .read_rom_hwaddr on dm eth_ops. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki

Re: [U-Boot] [PATCH 0/7] sunxi: Add support for the CHIP Pro

Hi Heiko, On Wed, Nov 09, 2016 at 08:47:12AM +0100, Heiko Schocher wrote: > Am 08.11.2016 um 17:21 schrieb Maxime Ripard: > > The CHIP Pro is a SoM made by NextThing Co, and that embeds a GR8 SIP, an > > AXP209 PMIC, a WiFi BT chip and a 512MB SLC NAND. > > > > Since the first Allwinner device

Re: [U-Boot] [PATCH] driver: net: fsl-mc: Use aligned address for MC FW load

Hello York, Please see inline. Regards -Original Message- From: york sun Sent: Tuesday, November 08, 2016 11:38 PM To: Ashish Kumar ; Priyanka Jain ; u-boot@lists.denx.de Cc: Prabhakar Kushwaha Subject: Re:

Re: [U-Boot] [PATCH RESEND 0/9] sunxi: chip: Enable the DIP auto-detection

Hi Tom, On Tue, Nov 08, 2016 at 10:44:18PM -0500, Tom Rini wrote: > On Tue, Nov 08, 2016 at 11:19:20AM +0100, Maxime Ripard wrote: > > [snip] > > I think the biggest drawback at the moment is that we maintain a list of > > DIPs and the actions needed directly into the C code, which will make it

Re: [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system

On 07/11/2016 22:26, Stephen Warren wrote: On 11/06/2016 03:24 AM, Alexander Graf wrote: On 05/11/2016 23:01, Stephen Warren wrote: On 11/02/2016 03:36 AM, Alexander Graf wrote: The rpi has a pretty simple way of resetting the whole system. All it takes is to poke a few registers at a

Re: [U-Boot] [PATCH 3/7] sunxi: Enable UBI and NAND support

Hi Boris, On Tue, Nov 08, 2016 at 05:27:48PM +0100, Boris Brezillon wrote: > On Tue, 8 Nov 2016 17:21:13 +0100 > Maxime Ripard wrote: > > > From: Hans de Goede > > > > Enable the NAND and UBI support in the configuration header so that

Re: [U-Boot] [PATCH 3/7] sunxi: Enable UBI and NAND support

On Wed, 9 Nov 2016 15:32:37 +0100 Maxime Ripard wrote: > Hi Boris, > > On Tue, Nov 08, 2016 at 05:27:48PM +0100, Boris Brezillon wrote: > > On Tue, 8 Nov 2016 17:21:13 +0100 > > Maxime Ripard wrote: > > > > > From: Hans de

Re: [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system

On 11/09/2016 04:43 AM, Alexander Graf wrote: On 07/11/2016 22:26, Stephen Warren wrote: On 11/06/2016 03:24 AM, Alexander Graf wrote: On 05/11/2016 23:01, Stephen Warren wrote: On 11/02/2016 03:36 AM, Alexander Graf wrote: The rpi has a pretty simple way of resetting the whole system.

Re: [U-Boot] [PATCH v2 1/4] serial: pxa: use kconfig for serial configuration

On 11/08/2016 10:34 AM, Marcel Ziswiler wrote: > Migrate the PXA serial driver to be configured via Kconfig. > > Signed-off-by: Marcel Ziswiler > --- > > Changes in v2: None Reviewed-by: Marek Vasut -- Best regards, Marek Vasut

Re: [U-Boot] [PATCH v2 2/4] serial: pxa: integrate optional driver model handling

On 11/08/2016 10:34 AM, Marcel Ziswiler wrote: > Optional driver model handling integration. > > Signed-off-by: Marcel Ziswiler > --- > > Changes in v2: None [...] > @@ -164,6 +130,7 @@ void pxa_putc_dev(unsigned int uart_index, const char c) > if

Re: [U-Boot] [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related erratum

On 11/08/2016 10:04 PM, Shengzhou Liu wrote: >> > If we keep A009942 workaround in fsl_ddr_gen4.c, > 1) we have to duplicate 3 same implement of A009942 separately in > mpc85xx_ddr_gen3.c, arm_ddr_gen3.c and fsl_ddr_gen4.c, that is not a good > idea. > 2) we have to modify more code struct to

[U-Boot] xhci USB controller driver for x86 board

Hi there I'm having problem getting USB 3.0 controller working properly on the Intel Denverton x86 board. First I tried to use xhci driver, but there doesn't seem to be any xhci driver or generic driver for x86 I only found the following xhci-exynos5.c: { .compatible =

Re: [U-Boot] [PATCH] driver: net: fsl-mc: Use aligned address for MC FW load

On 11/09/2016 04:03 AM, Ashish Kumar wrote: >> >> Do you have substantial change beside the changing name from mc_ram_addr to >> mc_ram_aligned_base_addr? >> [Ashish Kumar] It is not exactly name change. Here intent is to use >> userdefine memory size for MC before this only 512MB of memory can

[U-Boot] [PATCH] board: am335x/mux: Do not hang when encountering a bad EEPROM

In most cases, the SPL and u-boot.img will be on the same boot media. Since the SPL was loaded by the boot rom, the pinmux will already have been configured for this media. This, the board will still be able to boot successfully, or at least reach the u-boot console, where more recovery options

Re: [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system

On 09/11/2016 10:50, Stephen Warren wrote: On 11/09/2016 04:43 AM, Alexander Graf wrote: On 07/11/2016 22:26, Stephen Warren wrote: On 11/06/2016 03:24 AM, Alexander Graf wrote: On 05/11/2016 23:01, Stephen Warren wrote: On 11/02/2016 03:36 AM, Alexander Graf wrote: The rpi has a

Re: [U-Boot] [linux-sunxi] [PATCH 1/3] net: phy: realtek: Use the BIT() macro

Hi, On 09-11-16 22:42, Priit Laes wrote: On Tue, 2016-11-08 at 17:38 +0100, Olliver Schinagl wrote: The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations. Signed-off-by: Olliver Schinagl ---

Re: [U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster

Hi, On 09-11-16 11:21, Chen-Yu Tsai wrote: Hi everyone, This series adds basic PSCI support for the A80 to enable SMP on the first cluster. This at least allows people to use more than one core. The term "basic" is used because the series does not add support for multi-cluster cache and power

Re: [U-Boot] net: use random ethernet address if invalid and not zero

On 7.11.2016 18:31, Joe Hershberger wrote: > Hi Michal, > > https://patchwork.ozlabs.org/patch/690374/ was applied to u-boot-net.git. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster

On Wed, Nov 9, 2016 at 6:38 PM, Hans de Goede wrote: > Hi, > > On 09-11-16 11:21, Chen-Yu Tsai wrote: >> >> Hi everyone, >> >> This series adds basic PSCI support for the A80 to enable SMP on the >> first cluster. This at least allows people to use more than one core. >> The

Re: [U-Boot] [linux-sunxi] [PATCH 2/3] net: phy: realtek: make define more concistent

Crap! I thought I spotted it but wasn't sure :) If there needs to be a v2 i'll fix it; if the v1 is accepted, Joe could hopefully fix that in the message *wink* :) Olliver On 09-11-16 00:17, Emilio López wrote: Small nitpick: El 08/11/16 a las 13:38, Olliver Schinagl escribió: All

[U-Boot] [PATCH 01/10] ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80

The A80 is a big.LITTLE SoC with 4x Cortex-A7 in cluster 0 and 4x Cortex-A15 in cluster 1. Signed-off-by: Chen-Yu Tsai --- arch/arm/cpu/armv7/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index

[U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster

Hi everyone, This series adds basic PSCI support for the A80 to enable SMP on the first cluster. This at least allows people to use more than one core. The term "basic" is used because the series does not add support for multi-cluster cache and power management. The PSCI code is based on

[U-Boot] [PATCH 06/10] sunxi: Add CPUCFG register definitions for sun9i/A80

The A80 has a different CPUCFG register layout, likely due to having 2 clusters. Signed-off-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++ 1 file changed, 51 insertions(+) create mode 100644

[U-Boot] [PATCH 08/10] sunxi: Add basic PSCI implementation for A80

The A80 is a big.LITTLE multi-cluster SoC, with a different layout for the PRCM and CPUCFG registers. As such it needs a different PSCI implementation. This patch adds a basic version that allows bringing up the four cores in the first cluster. The structure is based on existing sunxi PSCI code.

[U-Boot] [PATCH 10/10] sunxi: Add PSCI core power off support for A80's first cluster

This patch adds the ability to power off cores in the first cluster of the A80 SoC. Following the single cluster sunxi PSCI implementation, the core being powered down signals core0 via secure monitor FIQ that it should be shut down, and enters WFI. Signed-off-by: Chen-Yu Tsai ---

[U-Boot] [PATCH 05/10] sunxi: Add PRCM register definition for sun9i/A80

The A80 has a different PRCM register layout. Signed-off-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 1 file changed, 55 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h diff --git

[U-Boot] [PATCH 07/10] sunxi: Add support for TZPC on sun9i/A80

The A80 also has the TrustZone Protection Controller (TZPC), called the Secure Memory Touch Arbiter (SMTA). Enable non-secure access to all the peripherals at boot time. Signed-off-by: Chen-Yu Tsai --- arch/arm/cpu/armv7/sunxi/Makefile | 1 +

[U-Boot] [PATCH 04/10] sunxi: Use secure SRAM B for secure RAM for sun9i/A80

The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved for CPU0 hotplug flags. Signed-off-by: Chen-Yu Tsai --- include/configs/sun9i.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h index

[U-Boot] [PATCH 09/10] sunxi: Enable PSCI on sun9i/A80

Now that we have a basic version of PSCI firmware, enable non-secure boot and PSCI on the A80. Signed-off-by: Chen-Yu Tsai --- board/sunxi/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index e1d4ab148f08..ae2fba1368cc

[U-Boot] [PATCH 03/10] sunxi: Add base address of secure SRAM B for sun9i/A80

The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved for CPU0 hotplug flags. Signed-off-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h

[U-Boot] [PATCH 02/10] sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80

The A80, having 2 clusters of 4 cores each, has an ARM CCI-400 hardware block for cache coherency. Add the base address for CCI-400, and also add the base address for CPUCFG. Signed-off-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 3 +++ 1 file changed, 3

[U-Boot] [PATCH] sata: fix sata command not being executed bug

From: Tang Yuantian Variable sata_curr_device is used to indicate if there is a available sata disk on board. Previously, sata_curr_device is set in sata_initialize(). Now, sata_initialize() is separated from other sata commands. Accordingly, sata_curr_device is removed

Re: [U-Boot] xhci USB controller driver for x86 board

Hi Chi, On 11/10/2016 12:51 AM, Ding, ChiX wrote: Hi there I'm having problem getting USB 3.0 controller working properly on the Intel Denverton x86 board. First I tried to use xhci driver, but there doesn't seem to be any xhci driver or generic driver for x86 I only found the following

[U-Boot] [PATCH v8 0/3] armv8: Support loading 32-bit OS in AArch32 execution state

This series is to support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Spin-table method is used for

[U-Boot] [PATCH v8 1/3] armv8: Support loading 32-bit OS in AArch32 execution state

To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu

[U-Boot] [PATCH v8 3/3] armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled

As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware

[U-Boot] [PATCH v8 2/3] armv8: fsl-layerscape: SMP support for loading 32-bit OS

Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison

Re: [U-Boot] xhci USB controller driver for x86 board

Hi Chi, On 10.11.2016 03:16, Kever Yang wrote: Hi Chi, On 11/10/2016 12:51 AM, Ding, ChiX wrote: Hi there I'm having problem getting USB 3.0 controller working properly on the Intel Denverton x86 board. First I tried to use xhci driver, but there doesn't seem to be any xhci driver or generic

Re: [U-Boot] [PATCH v7 1/2] armv8: Support loading 32-bit OS in AArch32 execution state

> On 7 November 2016 at 02:21, Alison Wang wrote: > >> On 11/04/2016 10:12 AM, Alexander Graf wrote: > >> > > >> > > >> > On 04/11/2016 17:08, york sun wrote: > >> >> On 11/04/2016 09:53 AM, Alexander Graf wrote: > >> >>> > >> >>> > >> >>> On 04/11/2016 16:43, york sun wrote:

[U-Boot] [PATCH] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect

[U-Boot] [PATCH 1/4] rsa: cosmetic: rename pad_len to key_len

From: Andrew Duda checksum_algo's pad_len field isn't actually used to store the length of the padding but the total length of the RSA key (msg_len + pad_len) Signed-off-by: Andrew Duda Signed-off-by: aduda --- include/image.h | 2