From: Rick Chen
ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df213c629191139e5c6705e069b6214f.
But other platforms or SoCs maybe support this
From: Rick Chen
Enable High-Speed mode with cap-sd-highspeed in dts
Signed-off-by: Rick Chen
Signed-off-by: Rick Chen
---
arch/nds32/dts/ag101p.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/nds32/dts/ag101p.dts
From: Rick Chen
Enable High-Speed mode with cap-sd-highspeed in dts.
Signed-off-by: Rick Chen
Signed-off-by: Rick Chen
---
arch/riscv/dts/ae250.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/ae250.dts
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ld11.dtsi| 3 +++
arch/arm/dts/uniphier-ld4.dtsi | 21 +
arch/arm/dts/uniphier-pro4-ref.dts | 4
arch/arm/dts/uniphier-pro4.dtsi| 25 +
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT
In the past the Hush shell would print a variable when edited, and on
could back arrow (move position) or backspace (delete characters).
Currently is does not print the command on edit, and if one hits
carriage return the variable is deleted.
Is this an enhancement, or do I have the
Hi,
On Wed, 14 Mar 2018 at 19:27 Stephen Warren wrote:
> On 03/14/2018 05:15 PM, Liam Beguin wrote:
> > Add basic tests for the spi_flash subsystem.
> >
> > Signed-off-by: Liam Beguin
> > Reviewed-by: Stephen Warren
>
> It's
On 03/14/2018 05:15 PM, Liam Beguin wrote:
Add basic tests for the spi_flash subsystem.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
It's useful if you put a brief description of what changed between patch
versions below the --- line so
Fix a minor typo causing vim (and possibly other) to get confused with
coloring.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
test/py/README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/py/README.md
As opposed to PATH, HOSTNAME is not appended to PYTHONPATH
automatically. Lets add it to the examples to make it more
obvious to new users.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
test/py/README.md | 4 ++--
1 file changed, 2
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
test/py/u_boot_utils.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9acb92ddc448..64584494e463 100644
--- a/test/py/u_boot_utils.py
Add basic tests for the spi_flash subsystem.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
test/py/tests/test_sf.py | 218 +++
1 file changed, 218 insertions(+)
create mode 100644
Add a generic function which can be used to compute the CRC32 value of
a region of RAM.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
test/py/u_boot_utils.py | 23 +++
1 file changed, 23 insertions(+)
diff --git
Make sure 0x00 is a valid address to read to. If `addr` is 0x00 then
map_physmem() will return 0 which should be a valid address.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
cmd/sf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi all,
This is the inital step to adding tests for the SF subsystem plus very
minor fixes. It is based on work I found on the mailing list[1].
For now, it doesn't do much but I plan on adding code to reset the flash
to its initial state (based on an env flag) and more code to test the
`sf
Make sure the user is notified instead of silently returning an error.
Signed-off-by: Liam Beguin
Reviewed-by: Stephen Warren
---
drivers/mtd/spi/spi_flash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Alexander,
device_type = "memory";
reg = <0x0 0x4000>;
};
chosen {
- stdout-path = "serial0:115200n8";
Nack. By default graphical output is quite unusable on this board, so we
want to output to serial.
If your Linux
On 28 February 2018 at 00:31, Tom Rini wrote:
> On Wed, Feb 28, 2018 at 12:26:15AM +0200, Sam Protsenko wrote:
>
>> serial# variable is needed to show the device correctly in "fastboot
>> devices" output. It's useful when we have several devices (in fastboot
>> mode) connected
In the Blt service of the EFI_GRAPHICS_OUTPUT_PROTOCOL the parameter delta
is measured in bytes and not in pixels.
The coding only supports delta being a multiple of four. The UEFI
specification does not explicitly require this but as pixels have a size of
four bytes we should be able to assume
On Thu, Mar 15, 2018 at 12:08 AM, Adam Ford wrote:
> On Wed, Mar 14, 2018 at 12:39 PM, Jagan Teki
> wrote:
>> On Wed, Mar 14, 2018 at 10:57 PM, Tom Rini wrote:
>>> On Wed, Mar 14, 2018 at 07:32:07PM +0530, Jagan Teki wrote:
On Wed, Mar 14, 2018 at 12:39 PM, Jagan Teki wrote:
> On Wed, Mar 14, 2018 at 10:57 PM, Tom Rini wrote:
>> On Wed, Mar 14, 2018 at 07:32:07PM +0530, Jagan Teki wrote:
>>
>>> Hi Tom,
>>>
>>> Please pull this PR.
>>>
>>> thanks,
>>> Jagan.
>>>
>>>
On Wed, 2018-03-14 at 18:21 +0100, Heinrich Schuchardt wrote:
@@ -87,7 +93,7 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, void
> > *buffer,
> > for (i = 0; i < height; i++) {
> > u32 *dest = fb + ((i + dy) * line_len32) +
> >
On Wed, Mar 14, 2018 at 11:15 PM, Jagan Teki wrote:
> omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
>
> error:
> drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
> drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of
Hi Tom,
Please pull this PR.
Change for v2:
- include missing patch
thanks,
Jagan.
The following changes since commit f95ab1fb6e37f0601f397091bb011edf7a98b890:
Prepare v2018.03 (2018-03-13 08:02:19 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-spi.git master
We need lzop now in order to make some FIT images that use LZO
compression on the contents.
Signed-off-by: Tom Rini
---
.travis.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.travis.yml b/.travis.yml
index 7b53b3dddc1b..6cad65fd378d 100644
--- a/.travis.yml
+++
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of
symbol
struct udevice *bus = dev->parent;
Signed-off-by: Jagan Teki
On Wed, Mar 14, 2018 at 10:57 PM, Tom Rini wrote:
> On Wed, Mar 14, 2018 at 07:32:07PM +0530, Jagan Teki wrote:
>
>> Hi Tom,
>>
>> Please pull this PR.
>>
>> thanks,
>> Jagan.
>>
>> The following changes since commit f95ab1fb6e37f0601f397091bb011edf7a98b890:
>>
>> Prepare
On 14/03/2018 18:02, Patrice CHOTARD wrote:
Hi Jean Jacques
On 03/14/2018 05:18 PM, Jean-Jacques Hiblot wrote:
This drivers supports the USB2 PHY found on omap5 and dra7 SOCs.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- omap-usb2-phy: Implement power_on and
On Wed, Mar 14, 2018 at 07:32:07PM +0530, Jagan Teki wrote:
> Hi Tom,
>
> Please pull this PR.
>
> thanks,
> Jagan.
>
> The following changes since commit f95ab1fb6e37f0601f397091bb011edf7a98b890:
>
> Prepare v2018.03 (2018-03-13 08:02:19 -0400)
>
> are available in the Git repository at:
The boot count is enabled in both SPL and proper u-boot.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- None
configs/display5_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index
If the CONFIG_SPL_BOOTCOUNT_LIMIT is defined, the bootcount variable is
already incremented after each boot attempt.
For that reason we shall not increment it again in u-boot.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- None
common/autoboot.c | 2 ++
1 file changed, 2
This patch series provides support for controlling bootcount limits in SPL.
It also enables this feature on display5 board to present usage patterns.
This patch has been applied on top of u-boot/master:
SHA1 (tag): v2018.03
Changes in v2:
- New patch
- None
- None
- New patch - as suggested by
This patch adds support for incrementation of the bootcount in SPL.
Such feature is necessary when we do want to use this feature with
'falcon' boot mode (which loads OS directly in SPL).
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch - as suggested by Stefan
This patch is necessary for providing basic bootcount checking in the case
of using "falcon" boot mode in that board.
It forces u-boot proper boot, when we exceed the number of errors.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- Remove bootcount_init() from SPL specific
Those two functions can be used to provide easy bootcount management.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- None
include/bootcount.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/include/bootcount.h b/include/bootcount.h
index
New, SPL related config option - CONFIG_SPL_BOOTCOUNT_LIMIT has been
added to allow drivers/bootcount code re-usage in SPL.
This code is necessary to use and setup bootcount in SPL in the case of
falcon boot mode.
Signed-off-by: Lukasz Majewski
---
Changes in v2: None
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch
include/bootcount.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/bootcount.h b/include/bootcount.h
index 06fb4d3578..e3b3f7028e 100644
--- a/include/bootcount.h
+++ b/include/bootcount.h
@@ -4,6
On 03/14/2018 04:31 AM, Ivan Gorinov wrote:
> Current implementation of Blt() in EFI_GRAPHICS_OUTPUT_PROTOCOL
> assumes the memory buffer stride (number of bytes in a row)
> always matches the rectangle Width, ignoring non-zero Delta.
>
> Signed-off-by: Ivan Gorinov
> ---
Signed-off-by: Christophe Leroy
---
arch/powerpc/dts/mcr3000.dts | 3 +++
board/cssi/MCR3000/MCR3000.c | 19 +++
configs/MCR3000_defconfig| 2 ++
include/configs/MCR3000.h| 1 +
4 files changed, 25 insertions(+)
diff --git
Some malloc memory is needed at startup for DM model.
Lets reorganise the use of the CPM dpram.
The MPC866/885 dpram, we have 8kbytes dual port RAM, which is usable as:
IMMR + 0x2000..0x2800: BD/Data/Microcode
IMMR + 0x2800..0x2e00: BD/Data
IMMR + 0x2e00..0x3800: BD/Data/Microcode
IMMR +
Add mcr3000 device tree and activate CONFIG_DM and CONFIG_OF_CONTROL
Signed-off-by: Christophe Leroy
---
arch/powerpc/dts/Makefile | 16
arch/powerpc/dts/mcr3000.dts | 12
board/cssi/MCR3000/u-boot.lds | 6 ++
In preparation of DM watchdog, move basic actions into drivers/watchdog
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig| 2 +-
arch/powerpc/cpu/mpc8xx/Kconfig | 4
arch/powerpc/cpu/mpc8xx/cpu.c | 13 -
drivers/watchdog/Makefile
This patch adds a DM driver for the MPC8xx watchdog.
Basically, the watchdog is enabled by default from the start and
SYPCR register has to be writen once to set the timeout and/or
deactivate the watchdog. Once written, it cannot be written again.
It means that wdt_stop() can be called before
In order to use CONFIG_DM, some initial RAM is needed for
malloc()
Signed-off-by: Christophe Leroy
---
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
arch/powerpc/cpu/mpc8xx/start.S| 5 +++--
include/configs/MCR3000.h | 7 ---
3 files changed, 8
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm
Signed-off-by: Christophe Leroy
---
arch/powerpc/cpu/mpc8xx/cpu.c| 2 +-
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
This serie is the beginning of MPC8xx migration to DM model.
Please comment and help me get the good direction.
Christophe Leroy (7):
powercp: mpc8xx: move commproc.h
powerpc: mpc8xx: redistribute data in CPM dpram
board: MCR3000: properly setup initial RAM
board: MCR3000: Activate
Hi Jean Jacques
On 03/14/2018 05:18 PM, Jean-Jacques Hiblot wrote:
> This drivers supports the USB2 PHY found on omap5 and dra7 SOCs.
>
> Signed-off-by: Jean-Jacques Hiblot
>
> ---
>
> Changes in v2:
> - omap-usb2-phy: Implement power_on and power_off callbacks
>
>
From: Patrice Chotard
Add generic_phy_power_on() and generic_phy_power_off()
calls to switch ON/OFF phy during probe and remove functions.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/ohci-generic.c | 17 +
1 file changed,
From: Patrice Chotard
Factorize PHY get/init/poweron and PHY poweroff/exit operations
into separate function, it simplify the error path.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/ohci-generic.c | 99
From: Patrice Chotard
As we get access to struct udevice, use dev_err() instead
of pr_err().
Signed-off-by: Patrice Chotard
---
drivers/usb/host/ehci-generic.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git
From: Patrice Chotard
As we get access to struct udevice, use dev_err() instead
of pr_err().
Signed-off-by: Patrice Chotard
---
drivers/usb/host/ohci-generic.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git
From: Patrice Chotard
Factorize PHY get/init/poweron and PHY poweroff/exit operations
into separate function, it simplify the error path.
Signed-off-by: Patrice Chotard
---
drivers/usb/host/ehci-generic.c | 99
From: Patrice Chotard
Add generic_phy_power_on() and generic_phy_power_off()
calls to switch ON/OFF phy during probe and remove functions.
Signed-off-by: Christophe Kerello
Signed-off-by: Patrice Chotard
---
From: Patrice Chotard
This series updates ohci-generic and ehci-generic drivers by:
_ Add generic_phy_power_on() and generic_phy_power_off() needed
to work with phy driver which implement these callbacks.
_ Factorize PHY operations.
_ Replace pr_err() with
Supporting DM USB is required to support DM_ETH and USB network adapters
with the same binary.
This series adds support for DM_USB for the DRA7/AM57 families. It
leverages the work done for the STi family.
This series applies on top of "xhci-dwc3: Couple of fixes for USB3 support"
limitation:
-
From: Vignesh R
Enable DM_USB for AM57xx based boards.
Signed-off-by: Vignesh R
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- Enable DM_USB in am57xx_evm_defconfig. USB3 (super speed) is supported.
configs/am57xx_evm_defconfig |
This is required when DM_USB is used, to bind the USB phys.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- split dts changes in 2 commits: one for binding the children of
ocp2scp@4a08, and one to disable USB1 on all DRA7 EVMs
arch/arm/dts/omap5-u-boot.dtsi |
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
---
Changes in v2: None
configs/dra7xx_evm_defconfig| 2 ++
configs/dra7xx_hs_evm_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/dra7xx_evm_defconfig
On all the EVMs featuring a SOC of the DRA7 family, the USB1 port is used
as a device for DFU. This port is managed by the platform code and must not
be advertised to the DWC3 DM driver.
This will be changed when/if support for the device mode is added to the
dwc3-omap driver.
Signed-off-by:
From: Vignesh R
Enable USB clocks in late init stage to support ports under DM_USB.
Signed-off-by: Vignesh R
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- am57xx boards: when DM_USB is used, turn on the required USB clocks
This drivers supports the USB2 PHY found on omap5 and dra7 SOCs.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- omap-usb2-phy: Implement power_on and power_off callbacks
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile| 1 +
For USB ports that use the Driver Model, turn on the clocks during the
late init stage.
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
---
Changes in v2: None
board/ti/dra7xx/evm.c | 19 +++
1 file changed, 19 insertions(+)
diff
From: Vignesh R
Add support to handle USB3 PHYs present on AM57xx/DRA7xx SoCs. This is
needed to move AM57xx to DM_USB.
Signed-off-by: Vignesh R
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- Add USB3 support to ti-pipe3-phy driver
The omap5 uses the dwc3. The dwc3 supports the driver model but it requires
some glue logic to load the the driver.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/host/Kconfig | 10 +
drivers/usb/host/Makefile | 1 +
syscon_regmap_lookup_by_phandle() can be used to the regmap of a syscon
device from a reference in the DTS. It operates similarly to the linux
version of the namesake function.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/core/syscon-uclass.c | 23
On 03/13/2018 08:03 PM, Liam Beguin wrote:
Add basic tests for the spi_flash subsystem.
Reviewed-by: Stephen Warren
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Hi Michal,
On Wed, 14 Mar 2018 at 10:35 Michal Simek wrote:
> On 14.3.2018 03:03, Liam Beguin wrote:
> > Add basic tests for the spi_flash subsystem.
> >
> > Signed-off-by: Liam Beguin
> > ---
> > test/py/tests/test_sf.py | 217
>
On 03/14/2018 04:31 AM, Ivan Gorinov wrote:
Current implementation of Blt() in EFI_GRAPHICS_OUTPUT_PROTOCOL
assumes the memory buffer stride (number of bytes in a row)
always matches the rectangle Width, ignoring non-zero Delta.
Signed-off-by: Ivan Gorinov
Hello
On 14.3.2018 03:03, Liam Beguin wrote:
> Add basic tests for the spi_flash subsystem.
>
> Signed-off-by: Liam Beguin
> ---
> test/py/tests/test_sf.py | 217
> +++
> 1 file changed, 217 insertions(+)
> create mode 100644
On Tue, Feb 27, 2018 at 11:45:03PM +0200, Sam Protsenko wrote:
> When enabling CONFIG_FASTBOOT_FLASH in am335x_boneblack_defconfig, next
> build errors and warnings occur:
>
> arch/arm/mach-omap2/utils.c: In function ‘omap_set_fastboot_cpu’:
> arch/arm/mach-omap2/utils.c:26:16: warning:
On Wed, Feb 28, 2018 at 04:49:55PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Enable DOS_PARTITION for boards STM32F429-eval, STM32F469-disco
> and STM32F746-disco.
> This allows to read FAT partition on mmc.
>
> Signed-off-by: Patrice Chotard
On Fri, Feb 16, 2018 at 01:27:03PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This board offers:
> _ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM
> _ Six 5 V power supply options:
> Power jack
>
On Tue, Feb 27, 2018 at 05:05:47PM +0100, Jean-Jacques Hiblot wrote:
> Add a common device-tree include file with MMC/SD IOdelay data
> for DRA76x SoC based on the linux DTSI file.
>
> In the most common case, IOdelay data available in datamanual
> can directly be used. This file caters to that
On Mon, Feb 26, 2018 at 11:18:00PM +0200, Sam Protsenko wrote:
> Refactor the code for "part start" and "part size" commands to avoid
> code duplication.
>
> Signed-off-by: Sam Protsenko
> Reviewed-by: Lukasz Majewski
Applied to u-boot/master,
On Mon, Feb 26, 2018 at 11:17:59PM +0200, Sam Protsenko wrote:
> Allow passing the partition name to "part start" and "part size"
> commands, so we can avoid magic numbers in the environment.
>
> Consider one real use-case: in include/environment/ti/boot.h we have
> commands like these:
>
>
On Sat, Feb 10, 2018 at 05:55:38PM +0800, Kever Yang wrote:
> Do not need to scan disk every time when we get part info
> by name.
>
> Signed-off-by: Kever Yang
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Fri, Feb 09, 2018 at 01:09:54PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Instead to have 3 identical gpio.h for all STM32 SoCs,
> migrate them in one file in include/asm.
>
> Signed-off-by: Patrice Chotard
Applied to
On Sat, Feb 10, 2018 at 05:55:37PM +0800, Kever Yang wrote:
> If a DUT do not have partition table, and we write one with 'gpt write'
> cmd, we should able to list the partition with 'part list' cmd.
> It's reasonable to scan the disk again if the initial part_type is
> unknown in case we just
On Tue, Feb 27, 2018 at 11:45:04PM +0200, Sam Protsenko wrote:
> Signed-off-by: Sam Protsenko
> Acked-by: Lukasz Majewski
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP
On Tue, Feb 27, 2018 at 05:05:48PM +0100, Jean-Jacques Hiblot wrote:
> Now that we have a device-tree include file with common
> MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree
> file to using that.
> Also fix the name of the IO voltage regulator for mmc1.
>
> Signed-off-by:
On Fri, Feb 09, 2018 at 01:09:53PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> fmc.h file is no more used, remove it.
> All FMC related defines are declared in drivers/ram/stm32_sdram.c
> which is common to all STM32 SoCs.
>
> Signed-off-by: Patrice
On Wed, Feb 07, 2018 at 05:19:58PM +0100, patrice.chot...@st.com wrote:
> From: Patrick Delaunay
>
> The hardware flow control functionality is used to avoid
> FIFO underrun (TX mode) and overrun (RX mode) errors.
> The behavior is to stop SDMMC_CK during data transfer
On Thu, Feb 08, 2018 at 05:25:19PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This avoids the following errors while reading on mmc:
> Read data bytes CRC error: 0x2
> switch to partitions #0, OK
> mmc0 is current device
> Read data bytes
On Thu, Feb 08, 2018 at 05:20:45PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Wrong parameter was passed to stm32_clk_pll48clk_rate().
> sysclk (PLL_p output value) was passed instead of VCO value.
>
> Signed-off-by: Patrice Chotard
On Thu, Feb 08, 2018 at 05:20:50PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Implement set_rate() for LTDC clock only, set_rate for other
> clocks will be added if needed. This is needed by future LTDC driver
> improvements.
>
> Signed-off-by:
On Fri, Feb 09, 2018 at 01:09:55PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
> Some common defines are duplicated or even unused in each of
> these stm32.h.
>
> Factorize all common
On Mon, Feb 26, 2018 at 05:52:57PM -0600, Derald D. Woods wrote:
> BeagleBoard 'xM' does not really have NAND. CONFIG_MTDIDS_DEFAULT and
> CONFIG_MTDPARTS_DEFAULT can/should be empty for 'xM'. This commit sets
> the defined values if they exist.
>
> Signed-off-by: Derald D. Woods
On Mon, Feb 26, 2018 at 05:52:59PM -0600, Derald D. Woods wrote:
> This commit does the following for OMAP3 EVM:
>
> - Track omap3_beagle changes where possible
> - Remove CONFIG_SYS_MPUCLK and CONFIG_MTD which are not needed for the
> default board configuration to work.
> - Remove
On Mon, Feb 26, 2018 at 05:52:58PM -0600, Derald D. Woods wrote:
> This commit does the following for BeagleBoard{-xM}:
>
> - Enable DM_SERIAL which also enables SPL_DM_SERIAL
> - Misc. config updates in support of DM_SERIAL
> - Use updated NAND layout (BeagleBoard):
>
> device nand0 , #
On Thu, Feb 08, 2018 at 05:20:46PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
On Tue, Feb 27, 2018 at 05:05:50PM +0100, Jean-Jacques Hiblot wrote:
> The SPL can't use high speed MMC modes if the associated pinctrl and
> IOdelays are described in the DTS.
> Make them available in SPL by tagging the nodes with 'u-boot,dm-spl;'
>
> Signed-off-by: Jean-Jacques Hiblot
On Tue, Feb 20, 2018 at 12:51:54PM -0700, Stephen Warren wrote:
> From: Stephen Warren
>
> Add a standalone MMC block read test. This allows direct testing of MMC
> access rather than relying on doing so as a side-effect of e.g. DFU or
> UMS testing, which may not be enabled
On Tue, Feb 27, 2018 at 05:05:49PM +0100, Jean-Jacques Hiblot wrote:
> Beside enabling the support for HS200 in mmc core, enabling the HS200
> support in the SPL requires multi-dtb support in the SPL because pinctrl
> and IOdelays vary across SOCs.
>
> Also we need to make sure that the pinctrl
On Thu, Feb 08, 2018 at 05:20:51PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> DSI clock is available on STM32F769-disco and
> STM32F469-disco board.
>
> Signed-off-by: Yannick Fertre
> Signed-off-by: Patrice Chotard
On Fri, Feb 09, 2018 at 01:09:56PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Remove arch/arm/include/asm/arch-stm32fx/stm32_periph.h
> as all defines or enums are no more used.
>
> Signed-off-by: Patrice Chotard
Applied
On Wed, Feb 28, 2018 at 05:15:00PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires
> uncachable regions. These regions are defined in DT.
> Since kernel linux v4.15, on ARMv7-M Cortex,
On Wed, Feb 07, 2018 at 10:44:50AM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Use available DM stm32_timer driver instead of dedicated
> mach-stm32/stm32fx/timer.c.
>
> Remove all defines or files previously used for timer usage in
>
On Thu, Feb 08, 2018 at 05:20:47PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Initially, 48Mhz for SDIO clock was generated from SAI pll for
> STM32F469 and STM32F746 SoCs, but this solution was not suitable
> for STM32F429 SoCs.
>
> A generic
On Thu, Feb 08, 2018 at 05:20:49PM +0100, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Configure SAI PLL configuration to generate LTDC pixel clock on
> the PLLSAIR output.
>
> PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.
>
> Signed-off-by:
On Tue, Feb 20, 2018 at 12:51:55PM -0700, Stephen Warren wrote:
> From: Stephen Warren
>
> Currently, if a test emits a warning message but otherwise passes, there's
> no indication of this in the log summary, which can lead to warnings being
> missed. Enhance the test logic
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