Re: [U-Boot] [PATCH 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, Apr 23, 2019 at 4:17 PM Chuanhua Han wrote:
>
> Modify the Freescale ESPI driver to support the driver model.
> Also resolved the following problems:
>
> = WARNING ==
> This board does not use CONFIG_DM_SPI. Please update
> the board before v2019.04 for no dm conversion
> and v2019.07 for partially dm converted drivers.
> Failure to update can lead to driver/board removal
> See doc/driver-model/MIGRATION.txt for more info.
>
> = WARNING ==
> This board does not use CONFIG_DM_SPI_FLASH. Please update
> the board to use CONFIG_SPI_FLASH before the v2019.07 release.
> Failure to update by the deadline may result in board removal.
> See doc/driver-model/MIGRATION.txt for more info.
>
>
> Signed-off-by: Chuanhua Han
> ---
> depends on:
> - https://patchwork.ozlabs.org/project/uboot/list/?series=99439
>
> drivers/spi/fsl_espi.c | 450 +
> 1 file changed, 316 insertions(+), 134 deletions(-)
>
> diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
> index 7444ae1a06..6ebe57c30b 100644
> --- a/drivers/spi/fsl_espi.c
> +++ b/drivers/spi/fsl_espi.c
> @@ -4,17 +4,27 @@
> *
> * Copyright 2010-2011 Freescale Semiconductor, Inc.
> * Author: Mingkai Hu (mingkai...@freescale.com)
> + *Chuanhua Han (chuanhua@nxp.com)
> */
>
> #include
> -
> #include
> #include
> #include
> +#include
> +#include
> +#include
> +
> +struct fsl_espi_platdata {
> + uint flags;
> + uint speed_hz;
> + uint num_chipselect;
> + fdt_addr_t regs_addr;
> +};
>
> -struct fsl_spi_slave {
> - struct spi_slave slave;
> +struct fsl_espi_priv {
> ccsr_espi_t *espi;
> + u32 speed_hz;
> unsigned intdiv16;
> unsigned intpm;
> int tx_timeout;
> @@ -25,9 +35,18 @@ struct fsl_spi_slave {
> unsigned intmax_transfer_length;
> };
>
> +struct fsl_spi_slave {
> + struct spi_slave slave;
> + struct fsl_espi_priv priv;
> +};
> +
> #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
> +#define to_fsl_spi_priv(p) container_of(p, struct fsl_spi_slave, priv)
> #define US_PER_SECOND 100UL
>
> +/* default SCK frequency, unit: HZ */
> +#define FSL_ESPI_DEFAULT_SCK_FREQ 1000
> +
> #define ESPI_MAX_CS_NUM4
> #define ESPI_FIFO_WIDTH_BIT32
>
> @@ -62,121 +81,46 @@ struct fsl_spi_slave {
>
> #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
>
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> - unsigned int max_hz, unsigned int mode)
> -{
> - struct fsl_spi_slave *fsl;
> - sys_info_t sysinfo;
> - unsigned long spibrg = 0;
> - unsigned long spi_freq = 0;
> - unsigned char pm = 0;
> -
> - if (!spi_cs_is_valid(bus, cs))
> - return NULL;
> -
> - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> - if (!fsl)
> - return NULL;
> -
> - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> - fsl->mode = mode;
> - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> -
> - /* Set eSPI BRG clock source */
> - get_sys_info(&sysinfo);
> - spibrg = sysinfo.freq_systembus / 2;
> - fsl->div16 = 0;
> - if ((spibrg / max_hz) > 32) {
> - fsl->div16 = ESPI_CSMODE_DIV16;
> - pm = spibrg / (max_hz * 16 * 2);
> - if (pm > 16) {
> - pm = 16;
> - debug("Requested speed is too low: %d Hz, %ld Hz "
> - "is used.\n", max_hz, spibrg / (32 * 16));
> - }
> - } else
> - pm = spibrg / (max_hz * 2);
> - if (pm)
> - pm--;
> - fsl->pm = pm;
> -
> - if (fsl->div16)
> - spi_freq = spibrg / ((pm + 1) * 2 * 16);
> - else
> - spi_freq = spibrg / ((pm + 1) * 2);
> -
> - /* set tx_timeout to 10 times of one espi FIFO entry go out */
> - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
> - * 10), spi_freq);
> -
> - return &fsl->slave;
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> +#ifndef CONFIG_DM_SPI
Would you try for full dm-conversion? it would be hard to move all
respective defconfigs to use but better try since we have next version
deadline for full dm-conversion. thanks!
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Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code
On Mon, Apr 22, 2019 at 12:11 AM Tom Rini wrote: > > On Fri, Apr 19, 2019 at 03:32:55PM +0200, Michael Nazzareno Trimarchi wrote: > > Hi Tom > > > > On Fri, Apr 19, 2019 at 2:42 PM Tom Rini wrote: > > > > > > On Fri, Apr 19, 2019 at 11:25:47AM +0200, Marek Vasut wrote: > > > > On 4/19/19 8:55 AM, Jagan Teki wrote: > > > > > Dropped > > > > > - mxs_spi driver > > > > > - CONFIG_MXS_SPI > > > > > > > > > > Dropped due to: > > > > > - no active updates > > > > > - no dm conversion > > > > > - multiple pings for asking dm-conversion > > > > > > > > This is the first information I received ... sigh. > > > > > > Sigh, I thought you had seen this before and noted at the time that you > > > hadn't heard anything before then. > > > > > > So, are the mx28 family boards something we still want to support? I > > > assume there's going to be other things that need converting there too. > > > > I have one mx28 long term support. We have added spl support and > > booting. Can you please > > wait to drop it? > > I have no problem with actively maintained platforms regardless of age. > If you're willing to maintain things, that's great. Perhaps have a > conversion with Marek about taking over the mx28 and related stuff, > keeping the relevant-to-you boards functional and up to date? Thanks! We (Akash) tried multiple iterations about the dm-conversion and look like it is failed to conclude. if someone or akash can come up with next version, it would be good. [1] https://patchwork.ozlabs.org/patch/1087964/ ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: Zap lpc32xx_ssp driver-related code
On Tue, Apr 23, 2019 at 2:20 AM Vladimir Zapolskiy wrote: > > Hi Jagan, Tom, > > On 04/19/2019 09:48 AM, Jagan Teki wrote: > > Dropped > > - lpc32xx_ssp driver > > - CONFIG_LPC32XX_SSP, LPC32XX_SSP_TIMEOUT items > > > > Dropped due to: > > - no active updates > > - no dm conversion > > - multiple pings for asking dm-conversion > > I really don't want to rush into moaning, however let me ask you to drop > the reason given above as invalid, otherwise please clarify who were > the addressees of these 'multiple pings'. Here is the number iterations around the ML, this indeed a notification for dm-conversion. [1] [2][4][5] > > > - no response for dm converted patch > > I believe there was no DM conversion patch for this particular driver, > could it happen that I've missed it? [3] [1] https://patchwork.ozlabs.org/patch/1002858/ [2] https://patchwork.ozlabs.org/patch/1000463/ [3] https://patchwork.ozlabs.org/patch/910751/ [4] https://gitlab.incom.co/CM-Shield/u-boot/commit/c4e68d3aa8178f6aa63a79c4f8f459c0e3ed58e8?view=parallel [5] https://lists.denx.de/pipermail/u-boot/2018-March/322135.html ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram
From: Rick Chen When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index e13c7de..54b65f1 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a41f918..0ff4de8 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] riscv: configs: Support AE350 SMP booting from flash flow
From: Rick Chen Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_xip_defconfig | 36 configs/ae350_rv64_xip_defconfig | 37 + 2 files changed, 73 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig new file mode 100644 index 000..7c46769 --- /dev/null +++ b/configs/ae350_rv32_xip_defconfig @@ -0,0 +1,36 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x8000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig new file mode 100644 index 000..67633d6 --- /dev/null +++ b/configs/ae350_rv64_xip_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x8000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled
From: Rick Chen
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.
When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/cpu/cpu.c | 2 ++
arch/riscv/cpu/start.S | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 768c44c..a17d37f 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,9 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
#ifndef CONFIG_XIP
u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 41d9a32..9ede1a7 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,7 +111,9 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
#endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
la t0, prior_stage_fdt_address
+#endif
SREGs1, 0(t0)
jal board_init_f_init_reserve
--
2.7.4
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[U-Boot] [PATCH v2 1/4] riscv: hart_lottery and available harts features can be selectable
From: Rick Chen
In smp flow these two features only can be enabled when U-Boot
booting from ram. It shall be disabled when U-Boot booting from
flash.
Add CONFIG_XIP to NOT select this two features. It's default value
will say NO for booting from ram.
AE350 will encounter the the write failure problem since
hart_lottery and available_harts_lock was not in ram address but
in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350
booting from flash by disabling this two features.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/Kconfig | 10 ++
arch/riscv/cpu/cpu.c | 3 ++-
arch/riscv/cpu/start.S | 7 ++-
arch/riscv/include/asm/global_data.h | 2 ++
arch/riscv/lib/asm-offsets.c | 2 ++
arch/riscv/lib/smp.c | 2 ++
6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..fb9a8c6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,16 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
+config XIP
+ bool "XIP mode"
+ default n
+ help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a serial NOR flash memory without copying the code to ram.
+ This must NOT support hart lottery and available harts features.
+ These two feature only can be enabled when U-Boot booting from
+ ram, but shall be disabled when booting from flash.
+
config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..768c44c 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,13 +16,14 @@
* before the bss section is available.
*/
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifndef CONFIG_XIP
u32 hart_lottery __attribute__((section(".data"))) = 0;
-
/*
* The main hart running U-Boot has acquired available_harts_lock until it has
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
+#endif
static inline bool supports_extension(char ext)
{
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..41d9a32 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv sp, a0
#endif
+#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+ bneztp, secondary_hart_loop
+#endif
la t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP
la t0, available_harts_lock
fence rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,7 +146,7 @@ wait_for_gd_init:
* secondary_hart_loop.
*/
bnezs2, secondary_hart_loop
-
+#endif
/* Enable cache */
jal icache_enable
jal dcache_enable
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index dffcd45..b74bd7e 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
};
#include
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..4fa4fd3 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
return 0;
}
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..cc66f15 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
--
2.7.4
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[U-Boot] [PATCH v2 0/4] AE350 support SMP boot from flash
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by disabling this two features. Changes in v2: - Fix some typos - Also surround the declaration of prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE - Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS Rick Chen (4): riscv: hart_lottery and available harts features can be selectable riscv: configs: Support AE350 SMP booting from flash flow riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram arch/riscv/Kconfig | 10 ++ arch/riscv/cpu/cpu.c | 5 - arch/riscv/cpu/start.S | 9 - arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 36 +++ configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 37 10 files changed, 103 insertions(+), 4 deletions(-) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [linux-sunxi] [PATCH v4] sun50i: a64: Add Olimex A64-Teres-I board initial support
On Sat, Apr 20, 2019 at 3:54 PM Icenowy Zheng wrote: > > From: Jonas Smedegaard > > Olimex A64-Teres-I board is a mainboard (the only one so far) > for Olimex Teres-I DIY laptop kit. > > Key features: > - Allwinner A64 Cortex-A53 > - Mali-400MP2 GPU > - AXP803 PMIC > - 2GB DDR3 RAM > - MicroSD Slot > - 16GB eMMC Flash > - eDP LCD display > - HDMI > - USB Host > - Battery management > - 5V DC power supply > - Certified Open Source Hardware (OSHW) > > Works: > - i2C > - MMC/SD > - PWM backlight > > Known broken: > - Internal keyboard (seems to be because the keyboard firmware loads a > bootloader first, and then disconnects bootloader and connect real > keyboard). External ones connected to the USB port work fine. > > This patch enables support for the A64-Teres-I board to u-boot, > including enabling screen backlight (lacking from Linux device-tree). > > Linux commit details about the sun50i-a64-teres-i.dts sync: > "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" > (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) > > Cosmetic warnings regarding whitespace and placement of SPDX notice for > dts file was ignored. > > config and .dtsi file are adapted from pinebook files. > > Tested-by: Jonas Smedegaard > Signed-off-by: Jonas Smedegaard > Signed-off-by: Icenowy Zheng > --- > Changes for v4: > * Added Vbus activision for USB. > * Dropped links in the commit message. > * Dropped Jonas's personal tree in MAINTAINERS item. > * Moved board-related MAINTAINERS item to board/sunxi/MAINTAINERS. > > Changes for v3: > * Use tags sun50i a64 (not sunxi) > * List key, working, and known broken features > * Reference upstream pages. > * Reference linux commit > > Changes for v2: > * List Icenowy and Jonas as MAINTAINERS > * Add commit hash in linux tree for sun50i-a64-teres-i.dts > * Drop superfluous and unsupported Author: tag > > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi | 41 +++ > arch/arm/dts/sun50i-a64-teres-i.dts | 270 > board/sunxi/MAINTAINERS | 6 + Moved the entry in proper loaction and Applied to u-boot-sunxi/master ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 05/11] env: save UEFI non-volatile variables in dedicated storage
We need a variant of env_save()/env_load() to handle dedicated storage
for UEFI variables.
It is assumed that env_efi_load() will be called only ince at init
and that env_efi_save() will be called at every SetVariable.
In this patch, new parameters will be expected to be configured:
CONFIG_ENV_EFI_FAT_DEVICE_AND_PART
CONFIG_ENV_EFI_FAT_FILE
in case of CONFIG_ENV_IS_IN_FAT.
Signed-off-by: AKASHI Takahiro
---
env/Kconfig | 34 ++
env/env.c | 98 ++-
env/fat.c | 109 ++
include/asm-generic/global_data.h | 1 +
include/environment.h | 24 +++
5 files changed, 265 insertions(+), 1 deletion(-)
diff --git a/env/Kconfig b/env/Kconfig
index 78300660c720..8f59e9347d4b 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -438,6 +438,34 @@ config ENV_FAT_FILE
It's a string of the FAT file name. This file use to store the
environment.
+config ENV_EFI_FAT_DEVICE_AND_PART
+ string "Device and partition for where to store the UEFI non-volatile
variables in FAT"
+ depends on ENV_IS_IN_FAT
+ depends on EFI_LOADER
+ help
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+ - "D:P": device D partition P. Error occurs if device D has no
+ partition table.
+ - "D:0": device D.
+ - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+ - "D:auto": first partition in device D with bootable flag set.
+ If none, first valid partition in device D. If no
+ partition table then means device D.
+
+config ENV_EFI_FAT_FILE
+ string "Name of the FAT file to use for the UEFI non-volatile variables"
+ depends on ENV_IS_IN_FAT
+ depends on EFI_LOADER
+ default "uboot_efi.env"
+ help
+ It's a string of the FAT file name. This file use to store the
+ UEFI non-volatile variables.
+
config ENV_EXT4_INTERFACE
string "Name of the block device for the environment"
depends on ENV_IS_IN_EXT4
@@ -470,6 +498,12 @@ config ENV_EXT4_FILE
It's a string of the EXT4 file name. This file use to store the
environment (explicit path to the file)
+config ENV_EFI_SIZE
+ hex "UEFI Variables Environment Size"
+ default 0x2
+ help
+ Size of the UEFI variables storage area
+
if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL ||
ARC
config ENV_OFFSET
diff --git a/env/env.c b/env/env.c
index 4b417b90a291..d5af761ba57e 100644
--- a/env/env.c
+++ b/env/env.c
@@ -24,6 +24,10 @@ void env_fix_drivers(void)
entry->load += gd->reloc_off;
if (entry->save)
entry->save += gd->reloc_off;
+ if (entry->efi_load)
+ entry->efi_load += gd->reloc_off;
+ if (entry->efi_save)
+ entry->efi_save += gd->reloc_off;
if (entry->init)
entry->init += gd->reloc_off;
}
@@ -125,7 +129,8 @@ __weak enum env_location env_get_location(enum
env_operation op, int prio)
if (prio >= ARRAY_SIZE(env_locations))
return ENVL_UNKNOWN;
- gd->env_load_prio = prio;
+ if (op != ENVOP_EFI)
+ gd->env_load_prio = prio;
return env_locations[prio];
}
@@ -280,3 +285,94 @@ int env_init(void)
return ret;
}
+
+#ifdef CONFIG_EFI_LOADER
+extern struct hsearch_data efi_var_htab;
+extern struct hsearch_data efi_nv_var_htab;
+
+/* TODO: experimental */
+int env_efi_save(void)
+{
+ struct env_driver *drv = NULL;
+ int ret;
+
+ if (!efi_nv_var_htab.table)
+ return 0;
+
+ if (gd->env_efi_prio == -1) {
+ printf("Cannot save UEFI non-volatile variable\n");
+ return -1;
+ }
+
+ drv = _env_driver_lookup(env_get_location(ENVOP_EFI, gd->env_efi_prio));
+ if (!drv) {
+ printf("Cannot save UEFI non-volatile variable\n");
+ return -1;
+ }
+
+ ret = drv->efi_save();
+ if (ret)
+ printf("Saving UEFI non-volatile variable failed\n");
+
+ return ret;
+}
+
+/* TODO: experimental */
+/* This function should be called only once at init */
+int env_efi_load(void)
+{
+ struct env_driver *drv = NULL;
+ int prio, ret;
+ enum env_location loc;
+
+ gd->env_efi_prio = -1;
+
+ /* volatile variables */
+ if (!efi_var_htab.table) {
+ ret = himport_r(&efi_var_htab, NULL, 0, '\0', 0, 0, 0, NULL
[U-Boot] [PATCH v2 06/11] efi_loader: variable: support non-volatile attribute
The attribute, EFI_VARIABLE_NON_VOLATILE, should be encoded as "nv" flag
in U-Boot variable if specified.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_variable.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 37728c3c165d..2f489ab9db97 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -125,6 +125,8 @@ static const char *parse_attr(const char *str, u32 *attrp)
if ((s = prefix(str, "ro"))) {
attr |= READ_ONLY;
+ } else if ((s = prefix(str, "nv"))) {
+ attr |= EFI_VARIABLE_NON_VOLATILE;
} else if ((s = prefix(str, "boot"))) {
attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
} else if ((s = prefix(str, "run"))) {
@@ -452,7 +454,7 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name,
}
}
- val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
+ val = malloc(2 * data_size + strlen("{ro,run,boot,nv}(blob)") + 1);
if (!val) {
ret = EFI_OUT_OF_RESOURCES;
goto out;
@@ -464,12 +466,16 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name,
* store attributes
* TODO: several attributes are not supported
*/
- attributes &= (EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS);
+ attributes &= (EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS);
s += sprintf(s, "{");
while (attributes) {
u32 attr = 1 << (ffs(attributes) - 1);
- if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
+ if (attr == EFI_VARIABLE_NON_VOLATILE)
+ s += sprintf(s, "nv");
+ else if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
s += sprintf(s, "boot");
else if (attr == EFI_VARIABLE_RUNTIME_ACCESS)
s += sprintf(s, "run");
--
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[U-Boot] [PATCH v2 08/11] efi_loader: load saved non-volatile variables at init
Data cache will be read in from persistent storage after (re)boot to restore UEFI non-volatile variables. Signed-off-by: AKASHI Takahiro --- lib/efi_loader/efi_setup.c | 4 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 05d8d754f4c7..490e3c5eb81a 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -7,6 +7,7 @@ #include #include +#include #if 1 /* TEMPORARILY */ #define DXE_SERVICES_TABLE_GUID \ @@ -96,6 +97,9 @@ efi_status_t efi_init_obj_list(void) if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED) return efi_obj_list_initialized; + /* Load non-volatile variables */ + env_efi_load(); + /* Define supported languages */ ret = efi_init_platform_lang(); if (ret != EFI_SUCCESS) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 09/11] efi_loader: bootmgr: handle BootNext as non-volatile
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_bootmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 4ccba2287572..e8f48684257f 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -206,7 +206,8 @@ efi_status_t efi_bootmgr_load(efi_handle_t *handle)
ret = EFI_CALL(efi_set_variable(
L"BootNext",
(efi_guid_t *)&efi_global_variable_guid,
- 0, 0, &bootnext));
+ EFI_VARIABLE_NON_VOLATILE, 0,
+ &bootnext));
/* load BootNext */
if (ret == EFI_SUCCESS) {
--
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[U-Boot] [PATCH v2 10/11] cmd: env: add -nv option for UEFI non-volatile variable
With this option, -nv, at "setenv -e" command, a variable will be defined
as non-volatile.
Signed-off-by: AKASHI Takahiro
---
cmd/nvedit.c | 3 ++-
cmd/nvedit_efi.c | 15 ---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 24a6cf7824ad..52c242b4f622 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -1344,8 +1344,9 @@ U_BOOT_CMD_COMPLETE(
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
#if defined(CONFIG_CMD_NVEDIT_EFI)
- "-e name [value ...]\n"
+ "-e [-nv] name [value ...]\n"
"- set UEFI variable 'name' to 'value' ...'\n"
+ " 'nv' option makes the variable non-volatile\n"
"- delete UEFI variable 'name' if 'value' not specified\n"
#endif
"setenv [-f] name value ...\n"
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index e65b38dbf399..ae0d9c18ad43 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -346,6 +346,7 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
u16 *var_name16 = NULL, *p;
size_t len;
efi_guid_t guid;
+ u32 attributes;
efi_status_t ret;
if (argc == 1)
@@ -359,6 +360,16 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return CMD_RET_FAILURE;
}
+ attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+EFI_VARIABLE_RUNTIME_ACCESS;
+ if (!strcmp(argv[1], "-nv")) {
+ attributes |= EFI_VARIABLE_NON_VOLATILE;
+ argc--;
+ argv++;
+ if (argc == 1)
+ return CMD_RET_SUCCESS;
+ }
+
var_name = argv[1];
if (argc == 2) {
/* delete */
@@ -385,9 +396,7 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
utf8_utf16_strncpy(&p, var_name, len + 1);
guid = efi_global_variable_guid;
- ret = EFI_CALL(efi_set_variable(var_name16, &guid,
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
+ ret = EFI_CALL(efi_set_variable(var_name16, &guid, attributes,
size, value));
ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
out:
--
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[U-Boot] [PATCH v2 11/11] cmd: efidebug: make some boot variables non-volatile
Boot, BootOrder and BootNext should be non-volatile. Signed-off-by: AKASHI Takahiro --- cmd/efidebug.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 8890dd7268f1..ff3cad53f1b7 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -554,6 +554,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, } ret = EFI_CALL(RT->set_variable(var_name16, &guid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, data)); @@ -911,6 +912,7 @@ static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag, guid = efi_global_variable_guid; size = sizeof(u16); ret = EFI_CALL(RT->set_variable(L"BootNext", &guid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, &bootnext)); @@ -966,6 +968,7 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag, guid = efi_global_variable_guid; ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, bootorder)); -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 07/11] efi_loader: variable: split UEFI variables from U-Boot environment
UEFI volatile variables are managed in efi_var_htab while UEFI non-volatile
variables are in efi_nv_var_htab. At every SetVariable API, env_efi_save()
will also be called to save data cache (hash table) to persistent storage.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_variable.c | 162 --
1 file changed, 155 insertions(+), 7 deletions(-)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 2f489ab9db97..f7b1ce2f3350 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -48,6 +48,115 @@
* converted to utf16?
*/
+/*
+ * We will maintain two variable database: one for volatile variables,
+ * the other for non-volatile variables. The former exists only in memory
+ * and will go away at re-boot. The latter is currently backed up by the same
+ * device as U-Boot environment and also works as variables cache.
+ */
+
+enum efi_var_type {
+ EFI_VAR_TYPE_VOLATILE,
+ EFI_VAR_TYPE_NON_VOLATILE,
+};
+
+struct hsearch_data efi_var_htab;
+struct hsearch_data efi_nv_var_htab;
+
+static char *env_efi_get(const char *name, int type)
+{
+ struct hsearch_data *htab;
+ ENTRY e, *ep;
+
+ /* WATCHDOG_RESET(); */
+
+ if (type == EFI_VAR_TYPE_VOLATILE)
+ htab = &efi_var_htab;
+ else
+ htab = &efi_nv_var_htab;
+
+ e.key = name;
+ e.data = NULL;
+ hsearch_r(e, FIND, &ep, htab, 0);
+
+ return ep ? ep->data : NULL;
+}
+
+static int env_efi_set(const char *name, const char *value, int type)
+{
+ struct hsearch_data *htab;
+ ENTRY e, *ep;
+ int ret;
+
+ if (type == EFI_VAR_TYPE_VOLATILE)
+ htab = &efi_var_htab;
+ else
+ htab = &efi_nv_var_htab;
+
+ /* delete */
+ if (!value || *value == '\0') {
+ ret = hdelete_r(name, htab, H_PROGRAMMATIC);
+ return !ret;
+ }
+
+ /* set */
+ e.key = name;
+ e.data = (char *)value;
+ hsearch_r(e, ENTER, &ep, htab, H_PROGRAMMATIC);
+ if (!ep) {
+ printf("## Error inserting \"%s\" variable, errno=%d\n",
+ name, errno);
+ return 1;
+ }
+
+ return 0;
+}
+
+int efi_variable_import(const char *buf, int check)
+{
+ env_t *ep = (env_t *)buf;
+
+ if (check) {
+ u32 crc;
+
+ memcpy(&crc, &ep->crc, sizeof(crc));
+
+ if (crc32(0, ep->data, CONFIG_ENV_EFI_SIZE) != crc) {
+ pr_err("bad CRC of UEFI variables\n");
+ return -ENOMSG; /* needed for env_load() */
+ }
+ }
+
+ if (himport_r(&efi_nv_var_htab, (char *)ep->data, CONFIG_ENV_EFI_SIZE,
+ '\0', 0, 0, 0, NULL))
+ return 0;
+
+ pr_err("Cannot import environment: errno = %d\n", errno);
+
+ /* set_default_env("import failed", 0); */
+
+ return -EIO;
+}
+
+/* Export the environment and generate CRC for it. */
+int efi_variable_export(env_t *env_out)
+{
+ char *res;
+ ssize_t len;
+
+ res = (char *)env_out->data;
+ len = hexport_r(&efi_nv_var_htab, '\0', 0, &res, CONFIG_ENV_EFI_SIZE,
+ 0, NULL);
+ if (len < 0) {
+ pr_err("Cannot export environment: errno = %d\n", errno);
+ return 1;
+ }
+
+ env_out->crc = crc32(0, env_out->data, CONFIG_ENV_EFI_SIZE);
+
+ return 0;
+}
+
#define PREFIX_LEN (strlen("efi_----_"))
/**
@@ -184,7 +293,9 @@ efi_status_t EFIAPI efi_get_variable(u16 *variable_name,
EFI_PRINT("get '%s'\n", native_name);
- val = env_get(native_name);
+ val = env_efi_get(native_name, EFI_VAR_TYPE_VOLATILE);
+ if (!val)
+ val = env_efi_get(native_name, EFI_VAR_TYPE_NON_VOLATILE);
free(native_name);
if (!val)
return EFI_EXIT(EFI_NOT_FOUND);
@@ -326,7 +437,7 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t
*variable_name_size,
u16 *variable_name,
const efi_guid_t *vendor)
{
- char *native_name, *variable;
+ char *native_name, *variable, *tmp_list, *merged_list;
ssize_t name_len, list_len;
char regex[256];
char * const regexlist[] = {regex};
@@ -382,10 +493,39 @@ efi_status_t EFIAPI
efi_get_next_variable_name(efi_uintn_t *variable_name_size,
efi_cur_variable = NULL;
snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_.*");
- list_len = hexport_r(&env_htab, '\n',
+ list_len = hexport_r(&efi_var_htab, '\n',
H_MATCH_REGEX | H_MATCH_KEY,
&efi_variables_list, 0, 1, regexlist);
- /* 1 indicates that no match was found */
+
[U-Boot] [PATCH v2 02/11] lib: charset: add u16_strncmp()
u16_strncmp() works like u16_strcmp() but only at most n characters
(in u16) are compared.
This function will be used in a later patch.
Signed-off-by: AKASHI Takahiro
---
include/charset.h | 5 +
lib/charset.c | 13 +
2 files changed, 18 insertions(+)
diff --git a/include/charset.h b/include/charset.h
index 747a9b376c03..49842a88bc8b 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -171,6 +171,11 @@ s32 utf_to_upper(const s32 code);
*/
int u16_strcmp(const u16 *s1, const u16 *s2);
+/*
+ * u16_strncmp() - strncmp() for u16 strings
+ */
+int u16_strncmp(const u16 *s1, const u16 *s2, size_t n);
+
/**
* u16_strlen - count non-zero words
*
diff --git a/lib/charset.c b/lib/charset.c
index 4a25ac0bdb9c..85f08db68fe2 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -345,6 +345,19 @@ int u16_strcmp(const u16 *s1, const u16 *s2)
return (*(uint16_t *)s1 - *(uint16_t *)s2);
}
+int u16_strncmp(const u16 *s1, const u16 *s2, size_t n)
+{
+ while ((n-- > 0) && (*s1 == *s2++)) {
+ if (*s1++ == 0)
+ return 0;
+ if (!n)
+ return 0;
+ }
+ --s2;
+
+ return (*(uint16_t *)s1 - *(uint16_t *)s2);
+}
+
size_t u16_strlen(const u16 *in)
{
size_t i;
--
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[U-Boot] [PATCH v2 01/11] lib: charset: add u16_strcmp()
u16 version of strcmp()
AUTHER: Patrick Wildt
Signed-off-by: AKASHI Takahiro
---
include/charset.h | 5 +
lib/charset.c | 10 ++
2 files changed, 15 insertions(+)
diff --git a/include/charset.h b/include/charset.h
index 65087f76d1fc..747a9b376c03 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -166,6 +166,11 @@ s32 utf_to_lower(const s32 code);
*/
s32 utf_to_upper(const s32 code);
+/*
+ * u16_strcmp() - strcmp() for u16 strings
+ */
+int u16_strcmp(const u16 *s1, const u16 *s2);
+
/**
* u16_strlen - count non-zero words
*
diff --git a/lib/charset.c b/lib/charset.c
index 5e349ed5ee45..4a25ac0bdb9c 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -335,6 +335,16 @@ s32 utf_to_upper(const s32 code)
return ret;
}
+int u16_strcmp(const u16 *s1, const u16 *s2)
+{
+ while (*s1 == *s2++)
+ if (*s1++ == 0)
+ return (0);
+ --s2;
+
+ return (*(uint16_t *)s1 - *(uint16_t *)s2);
+}
+
size_t u16_strlen(const u16 *in)
{
size_t i;
--
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[U-Boot] [PATCH v2 03/11] cmd: efidebug: rework "boot dump" sub-command using GetNextVariableName()
Efidebug command should be implemented using well-defined EFI interfaces,
rather than using internal functions/data. This change will be needed in
a later patch where UEFI variables are re-implemented.
Signed-off-by: AKASHI Takahiro
---
cmd/efidebug.c | 92 --
1 file changed, 66 insertions(+), 26 deletions(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index a40c4f4be286..8890dd7268f1 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -509,7 +509,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag,
if (argc < 6 || argc > 7)
return CMD_RET_USAGE;
- id = (int)simple_strtoul(argv[1], &endp, 16);
+ id = simple_strtoul(argv[1], &endp, 16);
if (*endp != '\0' || id > 0x)
return CMD_RET_USAGE;
@@ -595,7 +595,7 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag,
guid = efi_global_variable_guid;
for (i = 1; i < argc; i++, argv++) {
- id = (int)simple_strtoul(argv[1], &endp, 16);
+ id = simple_strtoul(argv[1], &endp, 16);
if (*endp != '\0' || id > 0x)
return CMD_RET_FAILURE;
@@ -693,6 +693,27 @@ static void show_efi_boot_opt(int id)
free(data);
}
+static bool u16_isxdigit(u16 c)
+{
+ if (c & 0xff00)
+ return false;
+
+ return isxdigit((u8)c);
+}
+
+static int u16_tohex(u16 c)
+{
+ if (c >= '0' && c < '9')
+ return c - '0';
+ if (c >= 'A' && c < 'F')
+ return c - 'A' + 10;
+ if (c >= 'a' && c < 'f')
+ return c - 'a' + 10;
+
+ /* dummy */
+ return -1;
+}
+
/**
* show_efi_boot_dump() - dump all UEFI load options
*
@@ -709,38 +730,57 @@ static void show_efi_boot_opt(int id)
static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- char regex[256];
- char * const regexlist[] = {regex};
- char *variables = NULL, *boot, *value;
- int len;
- int id;
+ u16 *var_name16, *p;
+ efi_uintn_t buf_size, size;
+ efi_guid_t guid;
+ int id, i;
+ efi_status_t ret;
if (argc > 1)
return CMD_RET_USAGE;
- snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_Boot[0-9A-F]+");
-
- /* TODO: use GetNextVariableName? */
- len = hexport_r(&env_htab, '\n', H_MATCH_REGEX | H_MATCH_KEY,
- &variables, 0, 1, regexlist);
+ buf_size = 128;
+ var_name16 = malloc(buf_size);
+ if (!var_name16)
+ return CMD_RET_FAILURE;
- if (!len)
- return CMD_RET_SUCCESS;
+ var_name16[0] = 0;
+ for (;;) {
+ size = buf_size;
+ ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16,
+ &guid));
+ if (ret == EFI_NOT_FOUND)
+ break;
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ buf_size = size;
+ p = realloc(var_name16, buf_size);
+ if (!p) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+ var_name16 = p;
+ ret = EFI_CALL(efi_get_next_variable_name(&size,
+ var_name16,
+ &guid));
+ }
+ if (ret != EFI_SUCCESS) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
- if (len < 0)
- return CMD_RET_FAILURE;
+ if (u16_strncmp(var_name16, L"Boot", 4) || var_name16[8] ||
+ !u16_isxdigit(var_name16[4]) ||
+ !u16_isxdigit(var_name16[5]) ||
+ !u16_isxdigit(var_name16[6]) ||
+ !u16_isxdigit(var_name16[7]))
+ continue;
- boot = variables;
- while (*boot) {
- value = strstr(boot, "Boot") + 4;
- id = (int)simple_strtoul(value, NULL, 16);
+ for (id = 0, i = 0; i < 4; i++)
+ id = (id << 4) + u16_tohex(var_name16[4 + i]);
show_efi_boot_opt(id);
- boot = strchr(boot, '\n');
- if (!*boot)
- break;
- boot++;
}
- free(variables);
+
+ free(var_name16);
return CMD_RET_SUCCESS;
}
@@ -914,7 +954,7 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
for (i = 0; i < argc; i++) {
- id = (int)simple_strtoul(argv[i], &endp, 16);
+ id = simple_strtoul(argv[i], &endp, 16);
if (*endp != '\0' ||
[U-Boot] [PATCH v2 04/11] efi_loader: set OsIndicationsSupported at init
UEFI variable should be installed using well-defined API.
Currently we don't support much, but the value fo OsIndicationsSupported
will be updated once some features are added in the future.
Signed-off-by: AKASHI Takahiro
---
cmd/bootefi.c | 4
lib/efi_loader/efi_setup.c | 9 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index efaa548be4d8..b93d8c6a32cd 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -303,10 +303,6 @@ static efi_status_t do_bootefi_exec(efi_handle_t handle)
if (ret != EFI_SUCCESS)
return ret;
- /* we don't support much: */
-
env_set("efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported",
- "{ro,boot}(blob)");
-
/* Call our payload! */
ret = EFI_CALL(efi_start_image(handle, NULL, NULL));
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 7d67a5506335..05d8d754f4c7 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -89,6 +89,7 @@ out:
*/
efi_status_t efi_init_obj_list(void)
{
+ u64 val = 0;
efi_status_t ret = EFI_SUCCESS;
/* Initialize once only */
@@ -100,6 +101,14 @@ efi_status_t efi_init_obj_list(void)
if (ret != EFI_SUCCESS)
goto out;
+ ret = EFI_CALL(efi_set_variable(L"OsIndicationsSupported",
+ &efi_global_variable_guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(val), &val));
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Initialize system table */
ret = efi_initialize_system_table();
if (ret != EFI_SUCCESS)
--
2.20.1
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[U-Boot] [PATCH v2 00/11] efi_loader: non-volatile variables support
This patch set is an attempt to implement non-volatile attribute for UEFI variables. Under the current implementation, * SetVariable API doesn't recognize non-volatile attribute * While some variables are defined non-volatile in UEFI specification, they are NOT marked as non-volatile in the code. * env_save() (or "env save" command) allows us to save all the variables into persistent storage, but it may cause volatile UEFI variables, along with irrelevant U-Boot variables, to be saved unconditionally. Those observation rationalizes that the implementation of UEFI variables should be revamped utilizing dedicated storage for them. This patch set is yet experimental and rough-edged(See known issues below), but shows how UEFI variables can be split from U-Boot environment. This enhancement will also be vital when we introduce UEFI secure boot where secure and tamper-resistant storage (with authentication) is required. Usage: To enable this feature, the following configs must be enabled: CONFIG_ENV_IS_IN_FAT CONFIG_ENV_FAT_INTERFACE CONFIG_ENV_EFI_FAT_DEVICE_AND_PART CONFIG_ENV_EFI_FAT_FILE You can also define a non-volatile variable from command interface: => setenv -e -nv FOO baa Known issues/restriction: * UEFI spec defines "globally defined variables" with specific attributes, but with this patch, we don't check against the user-supplied attribute for any variable. * Only FAT can be enabled for persistent storage for UEFI non-volatile variables. * The whole area of storage will be saved at every update of one variable. It can be optimized. * An error during saving may cause inconsistency between cache (hash table) and the storage. * Cache is of fixed size and can be quite big for normal usage. Patch#1 to #4 are preparatory so that we won't rely on U-Boot environment, that is, env_get/set() helper functions. Patch#5 to #8 are core part of changes. Patch#9 to #11 are for modifying variable attributes. Changes in v2 (Apr 24, 2019) * rebased on efi-2019-07 * revamp the implementation v1 (Nov 28, 2018) * initial AKASHI Takahiro (11): lib: charset: add u16_strcmp() lib: charset: add u16_strncmp() cmd: efidebug: rework "boot dump" sub-command using GetNextVariableName() efi_loader: set OsIndicationsSupported at init env: save UEFI non-volatile variables in dedicated storage efi_loader: variable: support non-volatile attribute efi_loader: variable: split UEFI variables from U-Boot environment efi_loader: load saved non-volatile variables at init efi_loader: bootmgr: handle BootNext as non-volatile cmd: env: add -nv option for UEFI non-volatile variable cmd: efidebug: make some boot variables non-volatile cmd/bootefi.c | 4 - cmd/efidebug.c| 95 +++- cmd/nvedit.c | 3 +- cmd/nvedit_efi.c | 15 ++- env/Kconfig | 34 ++ env/env.c | 98 - env/fat.c | 109 +++ include/asm-generic/global_data.h | 1 + include/charset.h | 10 ++ include/environment.h | 24 + lib/charset.c | 23 lib/efi_loader/efi_bootmgr.c | 3 +- lib/efi_loader/efi_setup.c| 13 +++ lib/efi_loader/efi_variable.c | 174 -- 14 files changed, 560 insertions(+), 46 deletions(-) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/9] pico-imx7d: Correct uart clock root
Peng Fan 于2019年4月24日周三 下午1:15写道：
>
>
> > Subject: [PATCH v3 4/9] pico-imx7d: Correct uart clock root
> >
> > Correct uart clock root ID. Incorrect ID may result the clock is gated
> > because
> > rate value 0 is returned in
> > imx_get_uartclk()
>
> Yes. hardcoding to UART1_ROOT_CLK in imx_get_uartclk is not good.
> But actually init_clk_uart configures all the uart with same root clk,
> so it should work as expected.
Right, but init_clk_uart is not called in SKIP_LOWLEVEL_INIT case.
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit() -> lowlevel_init() -> s_init() -> clock_init() ->
init_clk_uart()
#endif
>
> Regards,
> Peng.
>
> >
> > Signed-off-by: Jun Nie
> > ---
> > arch/arm/include/asm/arch-mx7/clock.h | 18 ++
> > arch/arm/mach-imx/Kconfig | 7 +++
> > arch/arm/mach-imx/mx7/clock.c | 2 +-
> > 3 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/include/asm/arch-mx7/clock.h
> > b/arch/arm/include/asm/arch-mx7/clock.h
> > index f56564e..dc9 100644
> > --- a/arch/arm/include/asm/arch-mx7/clock.h
> > +++ b/arch/arm/include/asm/arch-mx7/clock.h
> > @@ -175,6 +175,24 @@ enum clk_root_index {
> > CLK_ROOT_MAX,
> > };
> >
> > +#if (CONFIG_IMX_CONSOLE_UART_ID == 1)
> > +#define UART_CLK_ROOT UART1_CLK_ROOT
> > +#elif (CONFIG_IMX_CONSOLE_UART_ID == 2) #define UART_CLK_ROOT
> > +UART2_CLK_ROOT #elif (CONFIG_IMX_CONSOLE_UART_ID == 3) #define
> > +UART_CLK_ROOT UART3_CLK_ROOT #elif
> > (CONFIG_IMX_CONSOLE_UART_ID == 4)
> > +#define UART_CLK_ROOT UART4_CLK_ROOT #elif
> > (CONFIG_IMX_CONSOLE_UART_ID
> > +== 5) #define UART_CLK_ROOT UART5_CLK_ROOT #elif
> > +(CONFIG_IMX_CONSOLE_UART_ID == 6) #define UART_CLK_ROOT
> > UART6_CLK_ROOT
> > +#elif (CONFIG_IMX_CONSOLE_UART_ID == 7) #define UART_CLK_ROOT
> > +UART7_CLK_ROOT #else #error "Invalid IMX UART ID for serial console is
> > +defined"
> > +#endif
> > +
> > struct clk_root_setting {
> > enum clk_root_index root;
> > u32 setting;
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index
> > ec09ef2..7c5db30 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -27,6 +27,13 @@ config IMX_BOOTAUX
> > help
> > bootaux [addr] to boot auxiliary core.
> >
> > +config IMX_CONSOLE_UART_ID
> > + int "UART ID for console"
> > + default 1
> > + depends on ARCH_MX7
> > + help
> > + Specify the UART ID that's for serial console.
> > +
> > config USE_IMXIMG_PLUGIN
> > bool "Use imximage plugin code"
> > depends on ARCH_MX7 || ARCH_MX6
> > diff --git a/arch/arm/mach-imx/mx7/clock.c
> > b/arch/arm/mach-imx/mx7/clock.c index 8cda71c..e364b16 100644
> > --- a/arch/arm/mach-imx/mx7/clock.c
> > +++ b/arch/arm/mach-imx/mx7/clock.c
> > @@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
> >
> > u32 imx_get_uartclk(void)
> > {
> > - return get_root_clk(UART1_CLK_ROOT);
> > + return get_root_clk(UART_CLK_ROOT);
> > }
> >
> > u32 imx_get_fecclk(void)
> > --
> > 2.7.4
>
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[U-Boot] [PATCH v2] arm: socfpga: Move Stratix 10 SDRAM driver to DM
Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan
---
v1->v2:
- Change sdr device tree node enabled by default.
- Probe UCLASS_RAM only if CONFIG_ALTERA_SDRAM is enabled.
---
arch/arm/dts/socfpga_stratix10.dtsi | 9 +
arch/arm/mach-socfpga/spl_s10.c | 11 +-
configs/socfpga_stratix10_defconfig | 1 +
drivers/ddr/altera/Kconfig| 6 +-
drivers/ddr/altera/sdram_s10.c| 246 --
.../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
include/configs/socfpga_stratix10_socdk.h | 5 -
7 files changed, 192 insertions(+), 90 deletions(-)
rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h
(97%)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
index d1ae2fabae..bd68a78a37 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -258,6 +258,15 @@
u-boot,dm-pre-reloc;
};
+ sdr: sdr@f8000400 {
+compatible = "altr,sdr-ctl-s10";
+reg = <0xf8000400 0x80>,
+ <0xf801 0x190>,
+ <0xf8011000 0x500>;
+resets = <&rst DDRSCH_RESET>;
+u-boot,dm-pre-reloc;
+};
+
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a141ffe82a..3d44eabf91 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -15,9 +15,9 @@
#include
#include
#include
-#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -119,6 +119,7 @@ void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
+ struct udevice *dev;
#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
@@ -175,11 +176,13 @@ void board_init_f(ulong dummy)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- debug("DDR: Initializing Hard Memory Controller\n");
- if (sdram_mmr_init_full(0)) {
- puts("DDR: Initialization failed.\n");
+#ifdef CONFIG_ALTERA_SDRAM
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
hang();
}
+#endif /* CONFIG_ALTERA_SDRAM */
mbox_init();
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_defconfig
index 4848013b21..bda6ab6637 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ALTERA_SDRAM=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 8f60b56eb8..112c4ad7c3 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,7 +1,7 @@
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
- depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select RAM if TARGET_SOCFPGA_GEN5
- select SPL_RAM if TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 ||
TARGET_SOCFPGA_STRATIX10
+ select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+ select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index e4d4a02ca2..d2f3272609 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -5,17 +5,32 @@
*/
#include
+#include
#include
#include
#include
-#include
+#include
+#include
+#include "sdram_s10.h"
#include
#include
-#include
#include
#include
+#include
#include
+#ifdef CONFIG_SPL_BUILD
+
+struct altera_sdram_priv {
+ struct ram_info info;
+};
+
+struct altera_sdram_platdata {
+ void __iomem *hmc;
+ void __iomem *ddr_sch;
+ void __iomem *iomhc;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_system_manager *sysmgr_regs =
@@ -51,25 +66,26 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
};
-static u32 hmc_readl(u32 reg)
+static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO4
Re: [U-Boot] EFIBootGuard for CIP and SecureBoot
[prolonging the CCs with the efibootguard mailing list] On 24.04.19 03:23, daniel.sangor...@toshiba.co.jp wrote: Hello Francois, Jan, Christian, and all EFI Boot Guard is now shipped in quite a few devices, to my knowledge not only at Sorry for the late reply, I was waiting for the administrator of the Boot Architecture mailing list to accept my subscription request, but it seems it will take a bit more time. I will send this reply and hope it will not be blocked. I have also added the u-boot mailing list to Cc, as Tom suggested (although I'm not a member), the CIP mailing list, Jan Kiszka (one of the main developers of Efibootguard) and Christian (an expert in software updates). Background: during the last Linaro connect in Bangkok I was told that Linaro Edge (LEDGE) were working on a secure software update mechanism based on UEFI capsules that would flash firmware updates from a UEFI application, instead of using a Linux agent such as SWUpdate. How would capsules help with writing to arbitrary storage, updating only files on filesystem, reducing the update size (binary diffs), or talking to the cloud? Then, I had an online meeting with Francois, director of LEDGE. I explained to Francois that in CIP we are using the Linux agent approach right now, and we are also considering the use of a UEFI application (Efibootguard) to arm a watchdog and deal with the state-machine variables (installed, testing, ok, failed..) needed for A/B software updates. Efibootguard sounds like an excellent place to collaborate with Linaro (particularly on the watchdog drivers front) because it does not strictly depend on where the firmware is flashed (UEFI capsule or Linux agent). On Fri, Apr 19, 2019 at 12:48:51PM +0200, Francois Ozog wrote: Hi Daniel, We will be conducting a UEFI gap analysis to support EFIBootGuard in U-Boot. As we are working on UEFI SecureBoot implementation in U-Boot, how do you expect the boot process to be secured? Would U-Boot UEFI SecureBoot verify EFIBootGuard signature and in turn EFIBootGuard will check either grub or Linux signature? Please elaborate on your vision of a secured boot process. Efibootguard is composed of two parts. - A UEFI application that can arm a watchdog and decide what environment (kernel, boot args, etc.) to use next depending on a set of variables (update status, highest revision, etc.) stored in FAT16 partitions. - A Linux application that can read and set those variables from Linux (similar to u-boot's fw_setenv). This functionality is also available in the form of a library. As far as I know, there is no concept of "Secure Booting" in Efibootguard at the moment. Adding signature checks before booting into the selected kernel would be a possible solution. Secure boot is a pending feature on our to-do list. It's a bit more complicated than that, like secure boot is "a bit" more complicated than you think once you actually try to implement it. Once we do that, it's really about adding signature checks or relying on UEFI validating the payloads we boot for us PLUS ensuring the our config sections can either be validated (despite being volatile) or split the security-wise critical parts (specifically EFI payload parameters) from the less critical ones (update states) and remove the latter from the validation. BTW, what we do in EFI Board Guard could also be done in any other UEFI bootloader, may it be grub (if you like to use that complex and fragile beast in production), systemd-boot or even TianoCore. But for now, it was easier - and more robust - to add our requirements in form of this tiny bootloader to the ecosystem. EFI Boot Guard is now shipped in quite a few devices, to my best knowledge not only at Siemens. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-boot
Thanks for looking at this Simon!
On Tue, 2019-04-23 at 21:54 -0600, Simon Glass wrote:
> Hi Matti,
>
> On Mon, 8 Apr 2019 at 04:28, Matti Vaittinen
> wrote:
> >
> > https://source.codeaurora.org/external/imx/uboot-imx
> >
> > cherry picked, styled and merged commits:
> > - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
> > - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96
> >
> > Signed-off-by: Ye Li
> > Signed-off-by: Matti Vaittinen
> > ---
> >
> > Based on RFC:
> > https://lists.denx.de/pipermail/u-boot/2019-March/363076.html
> >
> > drivers/power/pmic/Kconfig| 7 +++
> > drivers/power/pmic/Makefile | 2 +
> > drivers/power/pmic/bd71837.c | 89
> > +++
> > drivers/power/pmic/pmic_bd71837.c | 31 +++
> > include/power/bd71837.h | 64 ++
> > 5 files changed, 193 insertions(+)
> > create mode 100644 drivers/power/pmic/bd71837.c
> > create mode 100644 drivers/power/pmic/pmic_bd71837.c
> > create mode 100644 include/power/bd71837.h
// Snip.
> > diff --git a/drivers/power/pmic/pmic_bd71837.c
> > b/drivers/power/pmic/pmic_bd71837.c
> > new file mode 100644
> > index 00..3bb8db4081
> > --- /dev/null
> > +++ b/drivers/power/pmic/pmic_bd71837.c
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +//
> > +// Copyright (C) 2014 Gateworks Corporation
> > +//
> > +// Tim Harvey
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +static const char bd71837_name[] = "BD71837";
> > +int power_bd71837_init(unsigned char bus)
> > +{
> > + struct pmic *p = pmic_alloc();
>
> This is the old PMIC interface. This should not be needed.
Do you mean I can drop whole pmic_bd71837.c? I'll do that at the next
patch version =)
>
> > +
> > + if (!p) {
> > + printf("%s: POWER allocation error!\n", __func__);
> > + return -ENOMEM;
> > + }
> > +
> > + p->name = bd71837_name;
> > + p->interface = PMIC_I2C;
> > + p->number_of_regs = BD71837_REG_NUM;
> > + p->hw.i2c.addr = 0x4b;
> > + p->hw.i2c.tx_num = 1;
> > + p->bus = bus;
> > +
> > + return 0;
> > +}
> > diff --git a/include/power/bd71837.h b/include/power/bd71837.h
> > new file mode 100644
> > index 00..9c74f6fc61
> > --- /dev/null
> > +++ b/include/power/bd71837.h
> > @@ -0,0 +1,64 @@
> > +/* SPDX-License-Identifier: GPL-2.0-or-later */
> > +/* Copyright (C) 2018 ROHM Semiconductors */
> > +
> > +#ifndef BD71837_H_
> > +#define BD71837_H_
> > +
> > +#define BD71837_REGULATOR_DRIVER "bd71837_regulator"
> > +
> > +enum {
> > + BD71837_REV = 0x00,
> > + BD71837_SWRESET = 0x01,
> > + BD71837_I2C_DEV = 0x02,
> > + BD71837_PWRCTRL0= 0x03,
> > + BD71837_PWRCTRL1= 0x04,
> > + BD71837_BUCK1_CTRL = 0x05,
> > + BD71837_BUCK2_CTRL = 0x06,
> > + BD71837_BUCK3_CTRL = 0x07,
> > + BD71837_BUCK4_CTRL = 0x08,
> > + BD71837_BUCK5_CTRL = 0x09,
> > + BD71837_BUCK6_CTRL = 0x0A,
> > + BD71837_BUCK7_CTRL = 0x0B,
> > + BD71837_BUCK8_CTRL = 0x0C,
> > + BD71837_BUCK1_VOLT_RUN = 0x0D,
> > + BD71837_BUCK1_VOLT_IDLE = 0x0E,
> > + BD71837_BUCK1_VOLT_SUSP = 0x0F,
> > + BD71837_BUCK2_VOLT_RUN = 0x10,
> > + BD71837_BUCK2_VOLT_IDLE = 0x11,
> > + BD71837_BUCK3_VOLT_RUN = 0x12,
> > + BD71837_BUCK4_VOLT_RUN = 0x13,
> > + BD71837_BUCK5_VOLT = 0x14,
> > + BD71837_BUCK6_VOLT = 0x15,
> > + BD71837_BUCK7_VOLT = 0x16,
> > + BD71837_BUCK8_VOLT = 0x17,
> > + BD71837_LDO1_VOLT = 0x18,
> > + BD71837_LDO2_VOLT = 0x19,
> > + BD71837_LDO3_VOLT = 0x1A,
> > + BD71837_LDO4_VOLT = 0x1B,
> > + BD71837_LDO5_VOLT = 0x1C,
> > + BD71837_LDO6_VOLT = 0x1D,
> > + BD71837_LDO7_VOLT = 0x1E,
> > + BD71837_TRANS_COND0 = 0x1F,
> > + BD71837_TRANS_COND1 = 0x20,
> > + BD71837_VRFAULTEN = 0x21,
> > + BD71837_MVRFLTMASK0 = 0x22,
> > + BD71837_MVRFLTMASK1 = 0x23,
> > + BD71837_MVRFLTMASK2 = 0x24,
> > + BD71837_RCVCFG = 0x25,
> > + BD71837_RCVNUM = 0x26,
> > + BD71837_PWRONCONFIG0= 0x27,
> > + BD71837_PWRONCONFIG1= 0x28,
> > + BD71837_RESETSRC= 0x29,
> > + BD71837_MIRQ= 0x2A,
> > + BD71837_IRQ = 0x2B,
> > + BD71837_IN_MON = 0x2C,
> > + BD71837_POW_STATE = 0x2D,
> > + BD71837_OUT32K = 0x2E,
> > + BD71837_REGLOCK = 0x2F,
> > + BD71837_MUXSW_EN= 0x30,
> > + BD71837_REG_NUM,
>
> Lower-case hex please.
Ok.
>
> > +};
> > +
> > +int power_bd71837_init(unsigned char bus);
>
> Should be able to drop th
Re: [U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
在 2019-04-24三的 13:44 +0800，Icenowy Zheng写道：
> The Allwinner H6 SoC has a register to set the PIO banks' voltage.
> When
> it mismatches the real voltage supplied to the VCC to the PIO supply,
> the PIO will work improperly.
>
> The PIO controller also has a register that contains the status of
> each
> VCC rail of the PIO supplies, and it has the same definition with the
> configuration register. so we can just copy the content of this
> register
> to the configuration register at startup, to ensure the configuration
> is
> correct at startup stage.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
> arch/arm/mach-sunxi/board.c| 9 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 40a3f845d0..a646ea6a3c 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
> struct sunxi_gpio_int gpio_int;
> };
>
> +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
> +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
> +
> #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
> &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
> &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank)
> - SUNXI_GPIO_L])
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-
> sunxi/board.c
> index c6dd7b8e54..bd3b5d8303 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
>
> static int gpio_init(void)
> {
> + __maybe__unused uint val;
Sorry for the extra _ here. Should be __maybe_unused.
> #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
> #if defined(CONFIG_MACH_SUN4I) || \
> defined(CONFIG_MACH_SUN7I) || \
> @@ -139,6 +140,14 @@ static int gpio_init(void)
> #error Unsupported console port number. Please fix pin mux settings
> in board.c
> #endif
>
> +#ifdef CONFIG_MACH_SUN50I_H6
> + /* Update PIO power bias configuration by copy hardware
> detected value */
> + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> +#endif
> +
> return 0;
> }
>
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Re: [U-Boot] [RFC PATCH v1 2/2] power: regulator: support ROHM BD71837 PMIC
Hello Simon,
Thanks a bunch for taking the time and reviewing this! I do appreciate!
On Tue, 2019-04-23 at 21:54 -0600, Simon Glass wrote:
> Hi Matti,
>
> On Wed, 27 Mar 2019 at 06:40, Matti Vaittinen
> wrote:
> >
> > Add regulator driver for ROHM BD71837 PMIC. BD71837 contains
> > 8 bucks and 7 LDOS. Voltages for bucks 1-4 can be adjusted
> > when regulators are enabled. For other bucks and LDOs we may
> > have over- or undershooting if voltage is adjusted when
> > regulator is enabled. Thus this is prevented by default.
> >
> > BD71837 has a quirk which may leave power output disabled
> > after reset if enable/disable state was controlled by SW.
> > Thus the SW control is only allowed for bucks3 and 4 by
> > default.
> >
> > Signed-off-by: Matti Vaittinen
> > ---
> > drivers/power/regulator/Kconfig | 15 ++
> > drivers/power/regulator/Makefile | 1 +
> > drivers/power/regulator/bd71837.c | 373
> > ++
> > include/power/bd71837.h | 20 ++
> > 4 files changed, 409 insertions(+)
> >
>
> Reviewed-by: Simon Glass
>
> But please see nits below.
I see you reviewed the RFC version. I would like to ask you to see also
the non RFC version https://patchwork.ozlabs.org/patch/1080860/ which
supports also BD71847. I see that most (maybe all) of these comments
apply to that patch too - but you might have some additional ideas
too.
I will create v2 of this non RFC patch based on these comments (and fix
your comments to patch 1/2 too) but I won't add your reviewed-by just
yet - I hope you can also check the pieces adding BD71847 support and
give me a nudge if you see there something to improve. =)
> > --- /dev/null
> > +++ b/drivers/power/regulator/bd71837.c
> > @@ -0,0 +1,373 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +//
> > +// Copyright (C) 2019 ROHM Semiconductors
> > +//
> > +// ROHM BD71837 regulator driver
>
> The SPDX line has a // comment but everything else should use C
> comments:
>
> /*
> * Copyright ...
> *
> * ROHM ...
> */
This is fine for me. But just to note that this differs from Linux
notation which accepts also the copyright block being // - comments. I
am not sure how closely u-Boot follows (or wants to follow) kernel
coding guidelines. But as I said, I don't mind changing this.
> > +
> > +static int bd71837_regulator_probe(struct udevice *dev)
> > +{
> > + struct bd71837_data *d = dev_get_platdata(dev);
> > + int i, ret;
> > + struct dm_regulator_uclass_platdata *uc_pdata;
> > +
> > + for (i = 0; i < ARRAY_SIZE(bd71837_reg_data); i++) {
> > + if (!strcmp(dev->name, bd71837_reg_data[i].name)) {
> > + *d = bd71837_reg_data[i];
> > + if (d->enablemask != HW_STATE_CONTROL) {
> > + u8 ctrl;
> > +
> > + /* Take the regulator under SW
> > control. Ensure
> > +* the initial state matches dt
> > flags and then
> > +* write the SEL bit
> > +*/
> > + uc_pdata =
> > dev_get_uclass_platdata(dev);
> > + ret = bd71837_set_enable(dev,
> > +!!(uc_pdat
> > a->boot_on ||
> > +uc_pdata-
> > >always_on));
> > + if (ret)
> > + return ret;
> > +
> > + ctrl = pmic_reg_read(dev->parent,
> > +d-
> > >enable_reg);
> > + if (ctrl < 0)
> > + return ctrl;
> > +
> > + ctrl |= d->sel_mask;
> > + return pmic_reg_write(dev->parent,
> > + d-
> > >enable_reg, ctrl);
> > + }
> > + return 0;
> > + }
> > + }
> > +
> > + pr_err("Unknown regulator '%s'\n", dev->name);
> > +
> > + return -EINVAL;
>
> -ENOENT ?
At first the -ENOENT sounded to me like a regulator/device is missing.
I thought that here we have extra (invalid/unknown) regulator in the
device-tree. Thus I used the -EINVAL. But I think you are right, we can
think that DT is correct and the driver lacks of correct regulator
entity. So -ENOENT can be appropriate. => I'll change this too.
> > --
> > Matti Vaittinen, Linux device drivers
> > ROHM Semiconductors, Finland SWDC
> > Kiviharjunlenkki 1E
> > 90220 OULU
> > FINLAND
> >
> > ~~~ "I don't think so," said Rene Descartes. Just then he vanished
> > ~~~
>
> This would be better in Latin.
Unfortunately that's far beyond my skills =) I can do Finnish though ;)
Rest of the comments seemed all like trivial fixes and I will apply
them =)
>
> R
Re: [U-Boot] [PATCH] riscv:Add Microchip MPFS Icicle Board support
Hi Bin,
On Tue, Apr 23, 2019 at 6:42 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Apr 18, 2019 at 2:21 AM Padmarao Begari
> wrote:
> >
> > This patch adds Microchip MPFS Icicle Board support.
>
> nits: Board->board. Please fix the commit message too.
>
Ok
> > For now, NS16550 serial driver is only enabled.
> > The Microchip MPFS Icicle defconfig by default builds
> > U-Boot for M-Mode with SMP support.
> >
> > Signed-off-by: Padmarao Begari
> > ---
> > arch/riscv/Kconfig| 4 ++
> > board/microchip/mpfs-icicle/Kconfig | 20 ++
> > board/microchip/mpfs-icicle/MAINTAINERS | 7
> > board/microchip/mpfs-icicle/Makefile | 7
> > board/microchip/mpfs-icicle/mpfs-icicle.c | 31 +++
> > configs/microchip-mpfs-icicle_defconfig | 16
> > include/configs/microchip-mpfs-icicle.h | 63
> +++
> > 7 files changed, 148 insertions(+)
> > create mode 100644 board/microchip/mpfs-icicle/Kconfig
> > create mode 100644 board/microchip/mpfs-icicle/MAINTAINERS
> > create mode 100644 board/microchip/mpfs-icicle/Makefile
> > create mode 100644 board/microchip/mpfs-icicle/mpfs-icicle.c
> > create mode 100644 configs/microchip-mpfs-icicle_defconfig
> > create mode 100644 include/configs/microchip-mpfs-icicle.h
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index ae8ff7b..df9b2ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -17,12 +17,16 @@ config TARGET_QEMU_VIRT
> > config TARGET_SIFIVE_FU540
> > bool "Support SiFive FU540 Board"
> >
> > +config TARGET_MICROCHIP_MPFS
>
> I assume MPFS stands for Microchip PolarFire-SoC? And the board is
> called Icicle? If yes, shouldn't this be TARGET_MICROCHIP_ICICLE?
>
yes, I will use TARGET_MICROCHIP_ICICLE
>
> nits: TARGET_MICROCHIP_xxx should come before TARGET_SIFIVE_
>
Ok
>
> > + bool "Support Microchip PolarFire-SoC Icicle Board"
> > +
> > endchoice
> >
> > # board-specific options below
> > source "board/AndesTech/ax25-ae350/Kconfig"
> > source "board/emulation/qemu-riscv/Kconfig"
> > source "board/sifive/fu540/Kconfig"
> > +source "board/microchip/mpfs-icicle/Kconfig"
>
> nits: please put it in the alphabetical order
>
Ok
>
> For naming convention, please use mpfs_icicle (_ instead of -)
>
Ok
>
> >
> > # platform-specific options below
> > source "arch/riscv/cpu/ax25/Kconfig"
> > diff --git a/board/microchip/mpfs-icicle/Kconfig
> b/board/microchip/mpfs-icicle/Kconfig
> > new file mode 100644
> > index 000..e17ba78
> > --- /dev/null
> > +++ b/board/microchip/mpfs-icicle/Kconfig
> > @@ -0,0 +1,20 @@
> > +if TARGET_MICROCHIP_MPFS
> > +
> > +config SYS_BOARD
> > + default "mpfs-icicle"
> > +
> > +config SYS_VENDOR
> > + default "microchip"
> > +
> > +config SYS_CPU
> > + default "generic"
> > +
> > +config SYS_CONFIG_NAME
> > + default "microchip-mpfs-icicle"
>
> nits: use _ instead of -
>
Ok
>
> > +
> > +config BOARD_SPECIFIC_OPTIONS # dummy
> > + def_bool y
> > + select GENERIC_RISCV
> > + imply SMP
> > +
> > +endif
> > diff --git a/board/microchip/mpfs-icicle/MAINTAINERS
> b/board/microchip/mpfs-icicle/MAINTAINERS
> > new file mode 100644
> > index 000..9987efe
> > --- /dev/null
> > +++ b/board/microchip/mpfs-icicle/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +Microchip MPFS icicle
> > +M: Padmarao Begari
> > +M: Cyril Jean
> > +S: Maintained
> > +F: board/microchip/mpfs-icicle/
> > +F: include/configs/microchip-mpfs-icicle.h
> > +F: configs/microchip-mpfs-icicle_defconfig
> > diff --git a/board/microchip/mpfs-icicle/Makefile
> b/board/microchip/mpfs-icicle/Makefile
> > new file mode 100644
> > index 000..4706586
> > --- /dev/null
> > +++ b/board/microchip/mpfs-icicle/Makefile
> > @@ -0,0 +1,7 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2019 Microchip Technology Inc.
> > +# Padmarao Begari
> > +#
> > +
> > +obj-y += mpfs-icicle.o
> > diff --git a/board/microchip/mpfs-icicle/mpfs-icicle.c
> b/board/microchip/mpfs-icicle/mpfs-icicle.c
> > new file mode 100644
> > index 000..5a23a7d
> > --- /dev/null
> > +++ b/board/microchip/mpfs-icicle/mpfs-icicle.c
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
> > +
> > +int board_init(void)
> > +{
> > + /* For now nothing to do here. */
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_BOARD_EARLY_INIT_F
>
> Can this be optionally turned off? If not, please select it in
> BOARD_SPECIFIC_OPTIONS, and remove the #ifdef here.
>
Ok
>
> > +int board_early_init_f(void)
> > +{
> > + unsigned int val;
>
> nits: should have a blank line here
>
Ok
Thanks for review.
Padmarao
>
> > + /* Reset uart peripheral
[U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/board.c| 9 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..a646ea6a3c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
+#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
+#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
+
#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) -
SUNXI_GPIO_L])
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8e54..bd3b5d8303 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
+ __maybe__unused uint val;
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
@@ -139,6 +140,14 @@ static int gpio_init(void)
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
+#ifdef CONFIG_MACH_SUN50I_H6
+ /* Update PIO power bias configuration by copy hardware detected value
*/
+ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+#endif
+
return 0;
}
--
2.18.1
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[U-Boot] [PATCH v2 1/1] common: fdt_support: Check mtdparts cell size
When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].
This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.
[1] Documentation/devicetree/bindings/mtd/partition.txt
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Use fdt_setprop_u64() and ..._u32() instead of fdt_setprop()
- Add size value using fdt_appendprop_u64() and ..._u32()
common/fdt_support.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..1c1a954829 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -724,11 +724,6 @@ int fdt_increase_size(void *fdt, int add_len)
#include
#include
-struct reg_cell {
- unsigned int r0;
- unsigned int r1;
-};
-
static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
@@ -787,15 +782,22 @@ int fdt_node_set_part_info(void *blob, int parent_offset,
{
struct list_head *pentry;
struct part_info *part;
- struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+ int sizecell;
char buf[64];
ret = fdt_del_partitions(blob, parent_offset);
if (ret < 0)
return ret;
+ /*
+* Check if size/address is 1 or 2 cells.
+* We assume #address-cells and #size-cells have same value.
+*/
+ sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+ 0, "#size-cells", 1);
+
/*
* Check if it is nand {}; subnode, adjust
* the offset in this case
@@ -844,10 +846,21 @@ add_ro:
goto err_prop;
}
- cell.r0 = cpu_to_fdt32(part->offset);
- cell.r1 = cpu_to_fdt32(part->size);
add_reg:
- ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+ if (sizecell == 2) {
+ ret = fdt_setprop_u64(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u64(blob, newoff,
+"reg", part->size);
+ } else {
+ ret = fdt_setprop_u32(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u32(blob, newoff,
+"reg", part->size);
+ }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
--
2.17.1
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Re: [U-Boot] [PATCH v4] arm: socfpga: mailbox: Fix off-by-one error on command length checking
Ley Foon Tan schrieb am Mi., 24. Apr. 2019, 07:21: > A mailbox command contains 1-u32 header + arguments. The "len" variable > only contains the length of the arguments, but not the 1-u32 header. > Include the length of header when checking the ring buffer space to > prevent off-by-one error. > > Signed-off-by: Ley Foon Tan > Signed-off-by: Chee Hong Ang > Reviewed-by: Simon Goldschmidt --- > v3->v4: > - Change DWORD to u32 in commit message > - Add note len is in u32 unit in code > > v2->v3: > - Update commit description. > --- > arch/arm/mach-socfpga/mailbox_s10.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-socfpga/mailbox_s10.c > b/arch/arm/mach-socfpga/mailbox_s10.c > index 3c33223936..4498ab55df 100644 > --- a/arch/arm/mach-socfpga/mailbox_s10.c > +++ b/arch/arm/mach-socfpga/mailbox_s10.c > @@ -55,11 +55,11 @@ static __always_inline int > mbox_fill_cmd_circular_buff(u32 header, u32 len, > cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; > > /* if command buffer is full or not enough free space > -* to fit the data > +* to fit the data. Note, len is in u32 unit. > */ > if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || > ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % > -MBOX_CMD_BUFFER_SIZE) < len) > +MBOX_CMD_BUFFER_SIZE) < (len + 1)) > return -ENOMEM; > > /* write header to circular buffer */ > -- > 2.19.0 > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4] arm: socfpga: mailbox: Fix off-by-one error on command length checking
A mailbox command contains 1-u32 header + arguments. The "len" variable only contains the length of the arguments, but not the 1-u32 header. Include the length of header when checking the ring buffer space to prevent off-by-one error. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- v3->v4: - Change DWORD to u32 in commit message - Add note len is in u32 unit in code v2->v3: - Update commit description. --- arch/arm/mach-socfpga/mailbox_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 3c33223936..4498ab55df 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -55,11 +55,11 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; /* if command buffer is full or not enough free space -* to fit the data +* to fit the data. Note, len is in u32 unit. */ if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % -MBOX_CMD_BUFFER_SIZE) < len) +MBOX_CMD_BUFFER_SIZE) < (len + 1)) return -ENOMEM; /* write header to circular buffer */ -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d
> Subject: [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d
>
> Copy device tree files from Linux directly.
Please describe which specific commit from Linux kernel upstream
Regards,
Peng.
>
> Signed-off-by: Jun Nie
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/imx7d-pico-pi.dts | 93 +++
> arch/arm/dts/imx7d-pico.dtsi | 585
> +
> 3 files changed, 679 insertions(+)
> create mode 100644 arch/arm/dts/imx7d-pico-pi.dts create mode 100644
> arch/arm/dts/imx7d-pico.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 0aee8df..e6cb1d3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -555,6 +555,7 @@ dtb-$(CONFIG_ARCH_MX6) += \
>
> dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> imx7d-sdb-qspi.dtb \
> + imx7d-pico-pi.dtb \
> imx7-colibri-emmc.dtb \
> imx7-colibri-rawnand.dtb \
> imx7s-warp.dtb
> diff --git a/arch/arm/dts/imx7d-pico-pi.dts b/arch/arm/dts/imx7d-pico-pi.dts
> new file mode 100644 index 000..70bea95
> --- /dev/null
> +++ b/arch/arm/dts/imx7d-pico-pi.dts
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // // Copyright 2017 NXP
> +
> +#include "imx7d-pico.dtsi"
> +
> +/ {
> + model = "TechNexion PICO-IMX7D Board and PI baseboard";
> + compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> + led {
> + label = "gpio-led";
> + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx7-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + simple-audio-card,cpu {
> + sound-dai = <&sai1>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + sgtl5000: codec@a {
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + compatible = "fsl,sgtl5000";
> + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_vref_1v8>;
> + };
> +};
> +
> +&i2c4 {
> + polytouch: touchscreen@38 {
> + compatible = "edt,edt-ft5x06";
> + reg = <0x38>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_touchscreen>;
> + interrupt-parent = <&gpio2>;
> + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
> + touchscreen-size-x = <800>;
> + touchscreen-size-y = <480>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
> + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
> + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
> + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
> + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
> + MX7D_PAD_EPDC_DATA12__GPIO2_IO120x14
> + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioledsgrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
> + >;
> + };
> +
> + pinctrl_touchscreen: touchscreengrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
> + MX7D_PAD_EPDC_DATA13__GPIO2_IO130x14
> + >;
> + };
> +
> +};
> diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi new
> file mode 100644 index 000..3fd595a
> --- /dev/null
> +++ b/arch/arm/dts/imx7d-pico.dtsi
> @@ -0,0 +1,585 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // // Copyright 2017 NXP
> +
> +/dts-v1/;
> +
> +#include "imx7d.dtsi"
> +
> +/ {
> + /* Will be filled by the bootloader */
> + memory@8000 {
> + device_type = "memory";
> + reg = <0x8000 0>;
> + };
> +
> + reg_wlreg_on: regulator-wlreg_on {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_wlreg_on>;
> + regulator-name = "wlreg_on";
> + regulator-min-
Re: [U-Boot] [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE
> Subject: [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE
>
> Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so
> that the OPTEE memory is not override during u-boot relocation.
>
> Note the OPTEE boot process will itself subtract the DRAM region it lives in
> from the memory map passed to Linux.
>
> Signed-off-by: Jun Nie
> ---
> board/technexion/pico-imx7d/pico-imx7d.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
> b/board/technexion/pico-imx7d/pico-imx7d.c
> index 53e1469..7c9e145 100644
> --- a/board/technexion/pico-imx7d/pico-imx7d.c
> +++ b/board/technexion/pico-imx7d/pico-imx7d.c
> @@ -60,6 +60,11 @@ int dram_init(void)
> {
> gd->ram_size = imx_ddr_size();
>
> + /* Subtract the defined OPTEE runtime firmware length */ #ifdef
> +CONFIG_OPTEE_TZDRAM_SIZE
> + gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE; #endif
> +
Better describe that OP-TEE runs at the top of DRAM. Actually the best
method should be modify dram banks, because OP-TEE not always
runs at top DRAM. Since this is pico board specific, so
Reviewed-by: Peng Fan
Regards,
Peng.
> return 0;
> }
>
> --
> 2.7.4
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Re: [U-Boot] [PATCH v3 4/9] pico-imx7d: Correct uart clock root
> Subject: [PATCH v3 4/9] pico-imx7d: Correct uart clock root
>
> Correct uart clock root ID. Incorrect ID may result the clock is gated because
> rate value 0 is returned in
> imx_get_uartclk()
Yes. hardcoding to UART1_ROOT_CLK in imx_get_uartclk is not good.
But actually init_clk_uart configures all the uart with same root clk,
so it should work as expected.
Regards,
Peng.
>
> Signed-off-by: Jun Nie
> ---
> arch/arm/include/asm/arch-mx7/clock.h | 18 ++
> arch/arm/mach-imx/Kconfig | 7 +++
> arch/arm/mach-imx/mx7/clock.c | 2 +-
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-mx7/clock.h
> b/arch/arm/include/asm/arch-mx7/clock.h
> index f56564e..dc9 100644
> --- a/arch/arm/include/asm/arch-mx7/clock.h
> +++ b/arch/arm/include/asm/arch-mx7/clock.h
> @@ -175,6 +175,24 @@ enum clk_root_index {
> CLK_ROOT_MAX,
> };
>
> +#if (CONFIG_IMX_CONSOLE_UART_ID == 1)
> +#define UART_CLK_ROOT UART1_CLK_ROOT
> +#elif (CONFIG_IMX_CONSOLE_UART_ID == 2) #define UART_CLK_ROOT
> +UART2_CLK_ROOT #elif (CONFIG_IMX_CONSOLE_UART_ID == 3) #define
> +UART_CLK_ROOT UART3_CLK_ROOT #elif
> (CONFIG_IMX_CONSOLE_UART_ID == 4)
> +#define UART_CLK_ROOT UART4_CLK_ROOT #elif
> (CONFIG_IMX_CONSOLE_UART_ID
> +== 5) #define UART_CLK_ROOT UART5_CLK_ROOT #elif
> +(CONFIG_IMX_CONSOLE_UART_ID == 6) #define UART_CLK_ROOT
> UART6_CLK_ROOT
> +#elif (CONFIG_IMX_CONSOLE_UART_ID == 7) #define UART_CLK_ROOT
> +UART7_CLK_ROOT #else #error "Invalid IMX UART ID for serial console is
> +defined"
> +#endif
> +
> struct clk_root_setting {
> enum clk_root_index root;
> u32 setting;
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index
> ec09ef2..7c5db30 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -27,6 +27,13 @@ config IMX_BOOTAUX
> help
> bootaux [addr] to boot auxiliary core.
>
> +config IMX_CONSOLE_UART_ID
> + int "UART ID for console"
> + default 1
> + depends on ARCH_MX7
> + help
> + Specify the UART ID that's for serial console.
> +
> config USE_IMXIMG_PLUGIN
> bool "Use imximage plugin code"
> depends on ARCH_MX7 || ARCH_MX6
> diff --git a/arch/arm/mach-imx/mx7/clock.c
> b/arch/arm/mach-imx/mx7/clock.c index 8cda71c..e364b16 100644
> --- a/arch/arm/mach-imx/mx7/clock.c
> +++ b/arch/arm/mach-imx/mx7/clock.c
> @@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
>
> u32 imx_get_uartclk(void)
> {
> - return get_root_clk(UART1_CLK_ROOT);
> + return get_root_clk(UART_CLK_ROOT);
> }
>
> u32 imx_get_fecclk(void)
> --
> 2.7.4
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Re: [U-Boot] [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped
Hi Jun
> Subject: [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped
>
> Add empty arch_cpu_init if low level init is skipped. So that it does not
> break
> spl compile though spl is not needed in the skipped case actually.
>
> Signed-off-by: Jun Nie
> ---
> arch/arm/mach-imx/mx7/soc.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 7cfdff0..9b04013 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -286,6 +286,11 @@ int arch_cpu_init(void)
>
> return 0;
> }
> +#else
> +int arch_cpu_init(void)
> +{
> + return 0;
> +}
> #endif
Please describe what ATF/OP-TEE initialization has done
when booting into uboot.
I think SKIP_LOWLEVEL_INIT is mostly for lowlevel_init,
not arch_cpu_init.
init_aips/init_csu/isolate_resources/init_snvs might be
done in your ATF, I am not sure, but imx_enet_mdio_fixup,
mxs_dma_init, imx_gpcv2_init, are these also done in ATF?
Regards,
Peng.
>
> #ifdef CONFIG_ARCH_MISC_INIT
> --
> 2.7.4
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[U-Boot] [PATCH v3 9/9] pico-imx7d: README: Add BL33 usage case
Add Documentation of BL33 usage case. U-boot is in non-secure world in this case. Signed-off-by: Jun Nie --- board/technexion/pico-imx7d/README.pico-imx7d_BL33 | 44 ++ 1 file changed, 44 insertions(+) create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33 diff --git a/board/technexion/pico-imx7d/README.pico-imx7d_BL33 b/board/technexion/pico-imx7d/README.pico-imx7d_BL33 new file mode 100644 index 000..40324ff --- /dev/null +++ b/board/technexion/pico-imx7d/README.pico-imx7d_BL33 @@ -0,0 +1,44 @@ +This document describes the instruction to build and flash ATF/OPTEE/U-Boot on +pico-imx7d board. U-Boot is loaded as part of FIP image by ATF in this setup. +The boot sequence is ATF -> OPTEE -> U-Boot -> Linux. U-Boot is in non-secure +world in this case. + +- Build u-boot +Set environment variable of CROSS_COMPILE for your toolchain and ARCH=arm +$ make pico-imx7d_bl33_defconfig +$ make all + +- Download and build OPTEE +$ git clone g...@github.com:OP-TEE/optee_os.git +$ make PLATFORM=imx PLATFORM_FLAVOR=mx7dpico_mbl CFG_BOOT_SECONDARY_REQUEST=y ARCH=arm + +- Download and build ATF +$ git clone https://git.linaro.org/landing-teams/working/mbl/arm-trusted-firmware.git -b linaro-imx7 +$ make DEBUG=1 PLAT=picopi ARCH=aarch32 ARM_ARCH_MAJOR=7 \ +CROSS_COMPILE=arm-linux-gnueabihf- LOG_LEVEL=50 V=1 \ +CRASH_REPORTING=1 AARCH32_SP=optee all +Save file content in this link to file pico-imx7d.cfg: + http://git.linaro.org/landing-teams/working/mbl/u-boot.git/tree/board/technexion/pico-imx7d/pico-imx7d.cfg?h=linaro-imx +$ u-boot/tools/mkimage -n pico-imx7d.cfg -T imximage -e 0x9df0 -d \ +build/picopi/debug/bl2.bin bl2.imx + +- Create FIP image +Create a fiptool_images/ folder in ATF folder, copy u-boot.bin in u-boot +folder and tee*.bin in optee out/arm-plat-imx/core/tee/ folder to +fiptool_images. Run below command in ATF folder to generate FIP image. +$ make -C tools/fiptool/ +$ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin \ + --tos-fw-extra1 fiptool_images/tee-pager_v2.bin \ + --tos-fw-extra2 fiptool_images/tee-pageable_v2.bin \ + --nt-fw fiptool_images/u-boot.bin \ + fip.bin + +- Burn the images to eMMC for test. +Run below command in atf folder: +$ dd if=build/picopi/debug/bl2.bin.imx of=/dev/disk/by-id/usb- bs=1024 seek=1;sync +$ dd if=fip.bin of=/dev/disk/by-id/usb- bs=1024 seek=1;sync + +- Test +Just boot up your board and wait for u-boot start up after ATF's log. +For booting Linux in FIT image, please reference the FIT files in +u-boot doc/uImage.FIT/ folder. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 8/9] pico-imx7d: Add bl33 config
Add default configuration to run u-boot as BL33 in the boot flow case of ATF(ARM Trusted Firmware) -> OPTEE -> U-boot. Signed-off-by: Jun Nie --- configs/pico-imx7d_bl33_defconfig | 63 +++ 1 file changed, 63 insertions(+) create mode 100644 configs/pico-imx7d_bl33_defconfig diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig new file mode 100644 index 000..a896cb3 --- /dev/null +++ b/configs/pico-imx7d_bl33_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x8780 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_CONSOLE_UART_ID=5 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x2 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PXE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DFU_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OPTEE_TZDRAM_SIZE=0x200 -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 4/9] pico-imx7d: Correct uart clock root
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()
Signed-off-by: Jun Nie
---
arch/arm/include/asm/arch-mx7/clock.h | 18 ++
arch/arm/mach-imx/Kconfig | 7 +++
arch/arm/mach-imx/mx7/clock.c | 2 +-
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx7/clock.h
b/arch/arm/include/asm/arch-mx7/clock.h
index f56564e..dc9 100644
--- a/arch/arm/include/asm/arch-mx7/clock.h
+++ b/arch/arm/include/asm/arch-mx7/clock.h
@@ -175,6 +175,24 @@ enum clk_root_index {
CLK_ROOT_MAX,
};
+#if (CONFIG_IMX_CONSOLE_UART_ID == 1)
+#define UART_CLK_ROOT UART1_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 2)
+#define UART_CLK_ROOT UART2_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 3)
+#define UART_CLK_ROOT UART3_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 4)
+#define UART_CLK_ROOT UART4_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 5)
+#define UART_CLK_ROOT UART5_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 6)
+#define UART_CLK_ROOT UART6_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 7)
+#define UART_CLK_ROOT UART7_CLK_ROOT
+#else
+#error "Invalid IMX UART ID for serial console is defined"
+#endif
+
struct clk_root_setting {
enum clk_root_index root;
u32 setting;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ec09ef2..7c5db30 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -27,6 +27,13 @@ config IMX_BOOTAUX
help
bootaux [addr] to boot auxiliary core.
+config IMX_CONSOLE_UART_ID
+ int "UART ID for console"
+ default 1
+ depends on ARCH_MX7
+ help
+ Specify the UART ID that's for serial console.
+
config USE_IMXIMG_PLUGIN
bool "Use imximage plugin code"
depends on ARCH_MX7 || ARCH_MX6
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8cda71c..e364b16 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
u32 imx_get_uartclk(void)
{
- return get_root_clk(UART1_CLK_ROOT);
+ return get_root_clk(UART_CLK_ROOT);
}
u32 imx_get_fecclk(void)
--
2.7.4
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[U-Boot] [PATCH v3 6/9] pico-imx7d: Add boot option for verified boot
Add boot option to boot from fitimage to support verified boot.
The boot script plain text file should be packed into fit blob as
image with name of bootscr.
Signed-off-by: Jun Nie
---
include/configs/pico-imx7d.h | 38 +++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 1884c58..8eb9064 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -52,11 +52,29 @@
"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
"rootfs part 0 1\0" \
-#define BOOTMENU_ENV \
+/* When booting with FIT specify the node entry containing boot.scr */
+#if defined(CONFIG_FIT)
+#define PICO_BOOT_ENV \
+ "bootscr_fitimage_name=bootscr\0" \
+ "bootscriptaddr=0x8320\0" \
+ "fdtovaddr=0x8310\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "rootwait rw;\0" \
+ "loadbootscript=" \
+ "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
+#else
+#define PICO_BOOT_ENV \
"bootmenu_0=Boot using PICO-Hobbit baseboard=" \
"setenv fdtfile imx7d-pico-hobbit.dtb\0" \
"bootmenu_1=Boot using PICO-Pi baseboard=" \
"setenv fdtfile imx7d-pico-pi.dtb\0" \
+ BOOTENV
+#endif
+
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
@@ -68,7 +86,6 @@
"fdt_high=0x\0" \
"initrd_high=0x\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- BOOTMENU_ENV \
"fdt_addr=0x8300\0" \
"fdt_addr_r=0x8300\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
@@ -88,7 +105,22 @@
"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
"fastboot_partition_alias_system=rootfs\0" \
"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
- BOOTENV
+ PICO_BOOT_ENV
+
+#if defined(CONFIG_FIT)
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "iminfo ${bootscriptaddr};" \
+ "if test $? -eq 1; then hab_failsafe; fi;" \
+ "run bootscript; " \
+ "else " \
+ "echo Fail to load fitImage with boot script;" \
+ "hab_failsafe;" \
+ "fi; " \
+ "fi"
+#endif
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
--
2.7.4
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[U-Boot] [PATCH 3/3] sound: Add codec enable to the sound bindings
For U-Boot we allow a GPIO to be specified to enable the codec. Add this to the relevant binding files. Signed-off-by: Simon Glass --- doc/device-tree-bindings/sound/intel-hda.txt | 1 + doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt | 1 + doc/device-tree-bindings/sound/snow.txt| 1 + 3 files changed, 3 insertions(+) diff --git a/doc/device-tree-bindings/sound/intel-hda.txt b/doc/device-tree-bindings/sound/intel-hda.txt index fb2ce550063..aa96be06e9b 100644 --- a/doc/device-tree-bindings/sound/intel-hda.txt +++ b/doc/device-tree-bindings/sound/intel-hda.txt @@ -12,6 +12,7 @@ Required properties: Optional properties - intel,beep-nid: Node ID to use for beep (will be detected if not provided) +- codec-enable-gpio : The GPIO used to enable the audio codec Required subnodes: - codecs: Contains a list of codec nodes diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt index c3495beba35..25c63eac628 100644 --- a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt +++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt @@ -27,6 +27,7 @@ Required properties: Optional properties: - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in - nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in +- codec-enable-gpio : The GPIO used to enable the audio codec Example: diff --git a/doc/device-tree-bindings/sound/snow.txt b/doc/device-tree-bindings/sound/snow.txt index 80fd9a87bb3..fa06956e772 100644 --- a/doc/device-tree-bindings/sound/snow.txt +++ b/doc/device-tree-bindings/sound/snow.txt @@ -19,6 +19,7 @@ Required sub-nodes: Optional: - samsung,model: The name of the sound-card +- codec-enable-gpio : The GPIO used to enable the audio codec Example: -- 2.21.0.593.g511ec345e18-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped
Add empty arch_cpu_init if low level init is skipped. So that
it does not break spl compile though spl is not needed in the
skipped case actually.
Signed-off-by: Jun Nie
---
arch/arm/mach-imx/mx7/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 7cfdff0..9b04013 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -286,6 +286,11 @@ int arch_cpu_init(void)
return 0;
}
+#else
+int arch_cpu_init(void)
+{
+ return 0;
+}
#endif
#ifdef CONFIG_ARCH_MISC_INIT
--
2.7.4
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[U-Boot] [PATCH 2/3] sound: tegra: Add the binding file for tegra-audio
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.
Signed-off-by: Simon Glass
---
.../sound/nvidia,tegra-audio-max98090.txt | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
new file mode 100644
index 000..c3495beba35
--- /dev/null
+++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -0,0 +1,53 @@
+NVIDIA Tegra audio complex, with MAX98090 CODEC
+
+Required properties:
+- compatible : "nvidia,tegra-audio-max98090"
+- clocks : Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+ - pll_a
+ - pll_a_out0
+ - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source. Valid names for sources and
+ sinks are the MAX98090's pins (as documented in its binding), and the jacks
+ on the board:
+
+ * Headphones
+ * Speakers
+ * Mic Jack
+ * Int Mic
+
+- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
+ connected to the CODEC.
+- nvidia,audio-codec : The phandle of the MAX98090 audio codec.
+
+Optional properties:
+- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
+
+Example:
+
+sound {
+ compatible = "nvidia,tegra-audio-max98090-venice2",
+"nvidia,tegra-audio-max98090";
+ nvidia,model = "NVIDIA Tegra Venice2";
+
+ nvidia,audio-routing =
+ "Headphones", "HPR",
+ "Headphones", "HPL",
+ "Speakers", "SPKR",
+ "Speakers", "SPKL",
+ "Mic Jack", "MICBIAS",
+ "IN34", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&acodec>;
+
+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+<&tegra_car TEGRA124_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+};
--
2.21.0.593.g511ec345e18-goog
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[U-Boot] [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so that
the OPTEE memory is not override during u-boot relocation.
Note the OPTEE boot process will itself subtract the DRAM region it lives
in from the memory map passed to Linux.
Signed-off-by: Jun Nie
---
board/technexion/pico-imx7d/pico-imx7d.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
b/board/technexion/pico-imx7d/pico-imx7d.c
index 53e1469..7c9e145 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -60,6 +60,11 @@ int dram_init(void)
{
gd->ram_size = imx_ddr_size();
+ /* Subtract the defined OPTEE runtime firmware length */
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+ gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
+#endif
+
return 0;
}
--
2.7.4
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[U-Boot] [PATCH v3 0/9] pico-imx7d: Add support for BL33 case
Add configuration to boot U-boot as BL33 case. The boot flow
is ATF -> OPTEE -> U-boot.
Changes vs V2:
- Revise fix to UART clock ID.
- Add documentation of build and test for BL33 usage case.
- Add device tree to store public key for FIT image verfication usage.
- Add revert patch to LCD support. Pico-pi does not boot with it.
I see it is suggested to be reverted in maillist.
Changes vs V1:
- Remove DCD file.
- Add a patch to fix uart clock root ID.
- Change file name from pico-pi-imx7d_bl33_defconfig to
pico-imx7d_bl33_defconfig
Jun Nie (9):
Revert "pico-imx7d: Add LCD support"
mx7_common: Share configs to skip low level init
imx: mx7: Add empty arch_cpu_init if skipped
pico-imx7d: Correct uart clock root
pico-imx7d: Reserve region of memory to OPTEE
pico-imx7d: Add boot option for verified boot
pico-imx7d: Add device tree for pico-imx7d
pico-imx7d: Add bl33 config
pico-imx7d: README: Add BL33 usage case
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx7d-pico-pi.dts | 93
arch/arm/dts/imx7d-pico.dtsi | 585 +
arch/arm/include/asm/arch-mx7/clock.h | 18 +
arch/arm/mach-imx/Kconfig | 7 +
arch/arm/mach-imx/mx7/clock.c | 2 +-
arch/arm/mach-imx/mx7/soc.c| 5 +
board/technexion/pico-imx7d/README.pico-imx7d_BL33 | 44 ++
board/technexion/pico-imx7d/pico-imx7d.c | 60 +--
configs/pico-hobbit-imx7d_defconfig| 1 -
...i-imx7d_defconfig => pico-imx7d_bl33_defconfig} | 40 +-
configs/pico-imx7d_defconfig | 1 -
configs/pico-pi-imx7d_defconfig| 1 -
include/configs/mx7_common.h | 11 +
include/configs/pico-imx7d.h | 50 +-
include/configs/warp7.h| 11 -
16 files changed, 826 insertions(+), 104 deletions(-)
create mode 100644 arch/arm/dts/imx7d-pico-pi.dts
create mode 100644 arch/arm/dts/imx7d-pico.dtsi
create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33
copy configs/{pico-pi-imx7d_defconfig => pico-imx7d_bl33_defconfig} (65%)
--
2.7.4
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[U-Boot] [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d
Copy device tree files from Linux directly.
Signed-off-by: Jun Nie
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx7d-pico-pi.dts | 93 +++
arch/arm/dts/imx7d-pico.dtsi | 585 +
3 files changed, 679 insertions(+)
create mode 100644 arch/arm/dts/imx7d-pico-pi.dts
create mode 100644 arch/arm/dts/imx7d-pico.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8df..e6cb1d3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -555,6 +555,7 @@ dtb-$(CONFIG_ARCH_MX6) += \
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
+ imx7d-pico-pi.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
imx7s-warp.dtb
diff --git a/arch/arm/dts/imx7d-pico-pi.dts b/arch/arm/dts/imx7d-pico-pi.dts
new file mode 100644
index 000..70bea95
--- /dev/null
+++ b/arch/arm/dts/imx7d-pico-pi.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+#include "imx7d-pico.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX7D Board and PI baseboard";
+ compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx7-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ };
+ };
+};
+
+&i2c1 {
+ sgtl5000: codec@a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_vref_1v8>;
+ };
+};
+
+&i2c4 {
+ polytouch: touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
+ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
+ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
+ MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
+ MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
+ MX7D_PAD_EPDC_DATA12__GPIO2_IO120x14
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
+ >;
+ };
+
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO130x14
+ >;
+ };
+
+};
diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi
new file mode 100644
index 000..3fd595a
--- /dev/null
+++ b/arch/arm/dts/imx7d-pico.dtsi
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+ /* Will be filled by the bootloader */
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0>;
+ };
+
+ reg_wlreg_on: regulator-wlreg_on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wlreg_on>;
+ regulator-name = "wlreg_on";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+
[U-Boot] [PATCH 1/3] sound: snow: Add the binding file for snow
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/sound/snow.txt | 31 +
1 file changed, 31 insertions(+)
create mode 100644 doc/device-tree-bindings/sound/snow.txt
diff --git a/doc/device-tree-bindings/sound/snow.txt
b/doc/device-tree-bindings/sound/snow.txt
new file mode 100644
index 000..80fd9a87bb3
--- /dev/null
+++ b/doc/device-tree-bindings/sound/snow.txt
@@ -0,0 +1,31 @@
+Audio Binding for Snow boards
+
+Required properties:
+- compatible : Can be one of the following,
+ "google,snow-audio-max98090" or
+ "google,snow-audio-max98091" or
+ "google,snow-audio-max98095"
+- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S
controller
+- samsung,audio-codec (deprecated): The phandle of the audio codec
+
+Required sub-nodes:
+
+ - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
+controller
+ - 'codec' subnode with a 'sound-dai' property containing list of phandles
+to the CODEC nodes, first entry must be the phandle of the MAX98090,
+MAX98091 or MAX98095 CODEC (exact device type is indicated by the
compatible
+string) and the second entry must be the phandle of the HDMI IP block node
+
+Optional:
+- samsung,model: The name of the sound-card
+
+Example:
+
+sound {
+ compatible = "google,snow-audio-max98095";
+
+ samsung,model = "Snow-I2S-MAX98095";
+ samsung,i2s-controller = <&i2s0>;
+ samsung,audio-codec = <&max98095>;
+};
--
2.21.0.593.g511ec345e18-goog
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[U-Boot] [PATCH v3 2/9] mx7_common: Share configs to skip low level init
Share configs in mx7 to skip low level init if we are in the case where OPTEE is loaded already (maybe by ARM Trusted Firmware) and that most of the low level initialization is already done and that we may/should skip it doing them here. Fix the definition detection with size detection to decide whether to skip it. Signed-off-by: Jun Nie --- include/configs/mx7_common.h | 11 +++ include/configs/warp7.h | 11 --- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index cc7e872..57fbec7 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -54,4 +54,15 @@ #endif #endif +/* + * If we have defined the OPTEE ram size and not OPTEE it means that we were + * launched by OPTEE, because of that we shall skip all the low level + * initialization since it was already done by ATF or OPTEE + */ +#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) +#ifndef CONFIG_OPTEE +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#endif + #endif diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 043f286..80ddd72 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -13,17 +13,6 @@ #define PHYS_SDRAM_SIZESZ_512M -/* - * If we have defined the OPTEE ram size and not OPTEE it means that we were - * launched by OPTEE, because of that we shall skip all the low level - * initialization since it was already done by ATF or OPTEE - */ -#ifdef CONFIG_OPTEE_TZDRAM_SIZE -#ifndef CONFIG_OPTEE -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#endif - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Size of malloc() pool */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] disk: efi: unify code for finding a valid gpt
On Wed, 3 Apr 2019 at 06:25, Urja Rannikko wrote: > > There were 3 copies of the same sequence, make it into a function. > > Signed-off-by: Urja Rannikko > --- > disk/part_efi.c | 73 +++-- > 1 file changed, 34 insertions(+), 39 deletions(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/10] pinctrl: rockchip: Remove redundant spaces
On Wed, 3 Apr 2019 at 21:52, David Wu wrote: > > Some files have the redundant spaces, remove them. > > Signed-off-by: David Wu > --- > > drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++-- > drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++-- > drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 - > drivers/pinctrl/rockchip/pinctrl-rk3288.c | 20 +-- > drivers/pinctrl/rockchip/pinctrl-rk3328.c | 24 +++ > drivers/pinctrl/rockchip/pinctrl-rk3368.c | 16 +++ > drivers/pinctrl/rockchip/pinctrl-rk3399.c | 24 +++ > 7 files changed, 63 insertions(+), 63 deletions(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/9] Revert "pico-imx7d: Add LCD support"
This reverts commit 9e3c0174da842dd88f5feaffbf843ba332233897.
---
board/technexion/pico-imx7d/pico-imx7d.c | 55
configs/pico-hobbit-imx7d_defconfig | 1 -
configs/pico-imx7d_defconfig | 1 -
configs/pico-pi-imx7d_defconfig | 1 -
include/configs/pico-imx7d.h | 12 ---
5 files changed, 70 deletions(-)
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
b/board/technexion/pico-imx7d/pico-imx7d.c
index 767d13d..53e1469 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -39,16 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
-#define LCD_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
-PAD_CTL_DSE_3P3V_49OHM)
-
-#define LCD_SYNC_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
- PAD_CTL_DSE_3P3V_196OHM)
-
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
/* I2C4 for PMIC */
static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
@@ -254,58 +246,11 @@ int board_early_init_f(void)
return 0;
}
-#ifdef CONFIG_VIDEO_MXS
-static iomux_v3_cfg_t const lcd_pads[] = {
- MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-void setup_lcd(void)
-{
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
- /* Set Brightness to high */
- gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
- /* Set LCD enable to high */
- gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
-}
-#endif
-
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_VIDEO_MXS
- setup_lcd();
-#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
diff --git a/configs/pico-hobbit-imx7d_defconfig
b/configs/pico-hobbit-imx7d_defconfig
index f58d517..cb4a6bf 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 7e13923..f90d757 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index c8ac2ff..8e48ba7 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa
Re: [U-Boot] [PATCH] rk8xx: implement poweroff
Hi, On Wed, 3 Apr 2019 at 06:21, Urja Rannikko wrote: > > Based on snooping around the linux kernel rk8xx driver, and > tested to work on the ASUS C201. > > Signed-off-by: Urja Rannikko > --- > This is really handy to be able to poweroff (without pressing power button > for a long time) the C201 from u-boot, so i'm sending this as is. > The thing that is bothering me is the pmic_get --- i checked that > every rk8xx is named "pmic" in the device tree so it should work, but > it just feels really weird that this seems to be the best way to access > the driver... > > drivers/power/pmic/rk8xx.c | 34 ++ > include/power/rk8xx_pmic.h | 4 > 2 files changed, 38 insertions(+) This should really use a sysreset driver. You can make the PMIC have a child sysreset driver to implement this function. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/7] tegra: sound: Add an audio hub driver
Hi Jon, On Wed, 3 Apr 2019 at 03:05, Jon Hunter wrote: > > > On 01/04/2019 21:38, Simon Glass wrote: > > Add a driver for the audio hub. This is modelled as a misc device which > > supports writing audio data from I2S. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v2: > > - Fix 'I2C' typo > > > > arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 +++ > > drivers/sound/Kconfig| 9 + > > drivers/sound/Makefile | 1 + > > drivers/sound/tegra_ahub.c | 256 ++ > > 4 files changed, 741 insertions(+) > > create mode 100644 arch/arm/include/asm/arch-tegra/tegra_ahub.h > > create mode 100644 drivers/sound/tegra_ahub.c > > > > diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h > > b/arch/arm/include/asm/arch-tegra/tegra_ahub.h > > new file mode 100644 > > index 000..96d542a91ca > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-tegra/tegra_ahub.h > > @@ -0,0 +1,475 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * tegra_ahub.h - Definitions for Tegra124 audio hub driver > > + * Taken from dc tegra_ahub.h > > + * > > + * Copyright 2018 Google LLC > > + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. > > + */ > > Looks fine to me, although you may wish to update your copyright date > now ;-) > > Acked-by: Jon Hunter Feel free to update it when applying, but I'm OK with it. It's been sitting around for a while! Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/7] sound: tegra: Add a sound driver
Hi Jon,
On Wed, 3 Apr 2019 at 03:15, Jon Hunter wrote:
>
>
> On 01/04/2019 21:38, Simon Glass wrote:
> > Add a sound driver for tegra devices. This connects the audio hub, I2S
> > controller and audio codec to allow sound output.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v2: None
> >
> > drivers/sound/Makefile | 2 +-
> > drivers/sound/tegra_sound.c | 100
> > 2 files changed, 101 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/sound/tegra_sound.c
> >
> > diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
> > index 358d5f920b2..73ed7fe53c3 100644
> > --- a/drivers/sound/Makefile
> > +++ b/drivers/sound/Makefile
> > @@ -11,7 +11,7 @@ obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o
> > obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
> > obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o
> > obj-$(CONFIG_I2S_SAMSUNG)+= samsung_sound.o
> > -obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o
> > +obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o
> > tegra_sound.o
> > obj-$(CONFIG_SOUND_WM8994) += wm8994.o
> > obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o
> > obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
> > diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c
> > new file mode 100644
> > index 000..7c2ed53f5a7
> > --- /dev/null
> > +++ b/drivers/sound/tegra_sound.c
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 Google, LLC
> > + * Written by Simon Glass
> > + */
> > +
> > +#define LOG_CATEGORY UCLASS_I2S
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "tegra_i2s_priv.h"
> > +
> > +static int tegra_sound_setup(struct udevice *dev)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > + struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s);
> > + int ret;
> > +
> > + if (uc_priv->setup_done)
> > + return -EALREADY;
> > + ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id,
> > + i2c_priv->samplingrate,
> > + i2c_priv->samplingrate * i2c_priv->rfs,
> > + i2c_priv->bitspersample,
> > + i2c_priv->channels);
> > + if (ret)
> > + return ret;
> > + uc_priv->setup_done = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int tegra_sound_play(struct udevice *dev, void *data, uint
> > data_size)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > +
> > + return i2s_tx_data(uc_priv->i2s, data, data_size);
> > +}
> > +
> > +static int tegra_sound_probe(struct udevice *dev)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > + struct gpio_desc en_gpio;
> > + struct udevice *ahub;
> > + int ret;
> > +
> > + ret = gpio_request_by_name(dev, "codec-enable-gpio", 0, &en_gpio,
> > +GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
>
>
> This looks a bit odd. I am not sure if this is supposed to be optional
> or not, but there is no checking of the return value although you store it.
Yes. If there is an error then en_gpio will not be set up. Then later
on we won't set the GPIO when enabling the codec.
>
> Is there DT binding documentation that does along with this that
> describes these properties?
Unfortunately not. The binding is actually board-specific in many
cases. I'll do a little series to in these files for all boards
including nyan.
Regards,
Simon
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Re: [U-Boot] [PATCH V2] mmc: dw_mmc: Calculate timeout from transfer length
On Mon, 1 Apr 2019 at 21:39, Marek Vasut wrote: > > The current 4-minute data transfer timeout is misleading and broken. > Instead of such a long wait, calculate the timeout duration based on > the length of the data transfer. The current formula is the transfer > length in bits, divided by a multiplication of bus frequency in Hz, > bus width, DDR mode and converted the mSec. The value is bounded from > the bottom to 1000 mSec. > > Signed-off-by: Marek Vasut > Cc: Jaehoon Chung > Cc: Simon Glass > --- > V2: Pull the timeout calculation into separate function > --- > drivers/mmc/dw_mmc.c | 24 +--- > 1 file changed, 21 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] disk: efi: ignore 'IGNOREME' GPT header found on cros eMMCs
Hi Urja, On Wed, 3 Apr 2019 at 06:25, Urja Rannikko wrote: > > Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of > the eMMC write protected and equipped with a dummy 'IGNOREME' GPT > header - instead of spewing error messages about it, just silently > try the backup GPT. > > Note: this does not touch the gpt cmd writing/verifying functions, > those will still complain. > > Signed-off-by: Urja Rannikko > --- > disk/part_efi.c| 28 +--- > include/part_efi.h | 2 ++ > 2 files changed, 23 insertions(+), 7 deletions(-) Could we add a Kconfig to control this? Other devices shouldn't have this code. Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] configs: update rk3288 veyron defconfigs
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko wrote: > > Updates jerry, mickey, minnie and speedy defconfigs to: > - fit the SPL in 32k > - boot from SPI (only) > - remove gadget support (these have no OTG port) > > Signed-off-by: Urja Rannikko > --- > configs/chromebit_mickey_defconfig | 26 -- > configs/chromebook_jerry_defconfig | 26 -- > configs/chromebook_minnie_defconfig | 26 -- > configs/chromebook_speedy_defconfig | 26 ++ > 4 files changed, 62 insertions(+), 42 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] test: env: Enable env unit tests by default
On Sun, 7 Apr 2019 at 09:58, Heinrich Schuchardt wrote: > > If CONFIG_UNIT_TEST is enabled we should enable the individual tests by > default to ensure good test coverage. > > Signed-off-by: Heinrich Schuchardt > --- > Tests ok on Travis CI: > https://travis-ci.org/xypron2/u-boot/builds/516825681 > --- > test/env/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] configs: Move CONFIG_SPI_FLASH_GIGADEVICE properly into Kconfig
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko wrote: > > Affects rk3288 veyrons and rk3036, this was mostly done by > moveconfig.py. > > Signed-off-by: Urja Rannikko > --- > configs/chromebit_mickey_defconfig | 1 + > configs/chromebook_jerry_defconfig | 1 + > configs/chromebook_minnie_defconfig | 1 + > configs/chromebook_speedy_defconfig | 1 + > configs/evb-rk3036_defconfig| 1 + > configs/kylin-rk3036_defconfig | 1 + > include/configs/rk3036_common.h | 2 -- > include/configs/veyron.h| 2 -- > 8 files changed, 6 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v1 2/2] power: regulator: support ROHM BD71837 PMIC
Hi Matti,
On Wed, 27 Mar 2019 at 06:40, Matti Vaittinen
wrote:
>
> Add regulator driver for ROHM BD71837 PMIC. BD71837 contains
> 8 bucks and 7 LDOS. Voltages for bucks 1-4 can be adjusted
> when regulators are enabled. For other bucks and LDOs we may
> have over- or undershooting if voltage is adjusted when
> regulator is enabled. Thus this is prevented by default.
>
> BD71837 has a quirk which may leave power output disabled
> after reset if enable/disable state was controlled by SW.
> Thus the SW control is only allowed for bucks3 and 4 by
> default.
>
> Signed-off-by: Matti Vaittinen
> ---
> drivers/power/regulator/Kconfig | 15 ++
> drivers/power/regulator/Makefile | 1 +
> drivers/power/regulator/bd71837.c | 373 ++
> include/power/bd71837.h | 20 ++
> 4 files changed, 409 insertions(+)
>
Reviewed-by: Simon Glass
But please see nits below.
> diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
> index 3ed0dd2264..323516587c 100644
> --- a/drivers/power/regulator/Kconfig
> +++ b/drivers/power/regulator/Kconfig
> @@ -43,6 +43,21 @@ config REGULATOR_AS3722
> but does not yet support change voltages. Currently this must be
> done using direct register writes to the PMIC.
>
> +config DM_REGULATOR_BD71837
> + bool "Enable Driver Model for REGULATOR BD71837"
> + depends on DM_REGULATOR && DM_PMIC_BD71837
> + help
> + This config enables implementation of driver-model regulator uclass
> + features for REGULATOR BD71837. The driver implements get/set api for:
> + value and enable.
> +
> +config SPL_DM_REGULATOR_BD71837
> + bool "Enable Driver Model for REGULATOR BD71837 in SPL"
> + depends on DM_REGULATOR_BD71837
> + help
> + This config enables implementation of driver-model regulator uclass
> + features for REGULATOR BD71837 in SPL.
> +
> config DM_REGULATOR_PFUZE100
> bool "Enable Driver Model for REGULATOR PFUZE100"
> depends on DM_REGULATOR && DM_PMIC_PFUZE100
> diff --git a/drivers/power/regulator/Makefile
> b/drivers/power/regulator/Makefile
> index f617ce723a..898ed5f084 100644
> --- a/drivers/power/regulator/Makefile
> +++ b/drivers/power/regulator/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
> obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
> obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
> obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
> obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
> diff --git a/drivers/power/regulator/bd71837.c
> b/drivers/power/regulator/bd71837.c
> new file mode 100644
> index 00..5b32425ba9
> --- /dev/null
> +++ b/drivers/power/regulator/bd71837.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +//
> +// Copyright (C) 2019 ROHM Semiconductors
> +//
> +// ROHM BD71837 regulator driver
The SPDX line has a // comment but everything else should use C comments:
/*
* Copyright ...
*
* ROHM ...
*/
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define HW_STATE_CONTROL 0
> +
Need struct comment.
/**
* struct bd71837_vrange - description here
*
* @min_volt: Description here
* ...
*/
> +struct bd71837_vrange {
> + unsigned intmin_volt;
> + unsigned intstep;
> + u8 min_sel;
> + u8 max_sel;
> + u8 rangeval;
> +};
> +
Need struct comment
> +struct bd71837_data {
How about bd71837_platdata?
> + const char *name;
> + u8 enable_reg;
> + u8 enablemask;
> + u8 volt_reg;
> + u8 volt_mask;
> + struct bd71837_vrange *ranges;
> + unsigned intnumranges;
> + u8 rangemask;
> + u8 sel_mask;
> + booldvs;
> +};
> +
> +#define BD_RANGE(_min, _vstep, _sel_low, _sel_hi, _range_sel) \
> +{ \
> + .min_volt = (_min), .step = (_vstep), .min_sel = (_sel_low), \
> + .max_sel = (_sel_hi), .rangeval = (_range_sel) \
> +}
> +
> +#define BD_DATA(_name, enreg, enmask, vreg, vmask, _range, rmask, _dvs, sel)
> \
> +{ \
> + .name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \
> + .volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \
> + .numranges = ARRAY_SIZE(_range), .rangemask = (rmask), .dvs = (_dvs),
> \
> + .sel_mask = (sel) \
> +}
> +
> +static struct bd71837_vrange buck1to4_vranges[] = {
> + BD_RANGE(70, 1, 0, 0x3C, 0),
Please use lower-case hex throughout.
> + BD_RANGE(130, 0, 0x3D, 0x3F, 0),
> +};
> +
> +static struct
Re: [U-Boot] [PATCH v1 1/2] regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-boot
Hi Matti,
On Mon, 8 Apr 2019 at 04:28, Matti Vaittinen
wrote:
>
> https://source.codeaurora.org/external/imx/uboot-imx
>
> cherry picked, styled and merged commits:
> - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
> - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96
>
> Signed-off-by: Ye Li
> Signed-off-by: Matti Vaittinen
> ---
>
> Based on RFC:
> https://lists.denx.de/pipermail/u-boot/2019-March/363076.html
>
> drivers/power/pmic/Kconfig| 7 +++
> drivers/power/pmic/Makefile | 2 +
> drivers/power/pmic/bd71837.c | 89 +++
> drivers/power/pmic/pmic_bd71837.c | 31 +++
> include/power/bd71837.h | 64 ++
> 5 files changed, 193 insertions(+)
> create mode 100644 drivers/power/pmic/bd71837.c
> create mode 100644 drivers/power/pmic/pmic_bd71837.c
> create mode 100644 include/power/bd71837.h
>
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index 8cf60ebcf3..e154d0a57b 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -48,6 +48,13 @@ config PMIC_AS3722
> interface and is designs to cover most of the power managementment
> required for a tablets or laptop.
>
> +config DM_PMIC_BD71837
> + bool "Enable Driver Model for PMIC BD71837"
> + depends on DM_PMIC
> + help
> + This config enables implementation of driver-model pmic uclass
> features
> + for PMIC BD71837. The driver implements read/write operations.
> +
> config DM_PMIC_FAN53555
> bool "Enable support for OnSemi FAN53555"
> depends on DM_PMIC && DM_REGULATOR && DM_I2C
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 637352ab2b..e74c6190a8 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
> obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
> obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
> obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
> obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
> obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
> @@ -30,6 +31,7 @@ obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
> obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
> obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
> obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
> +obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o
> obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
> obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
> obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
> diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
> new file mode 100644
> index 00..eadf373a18
> --- /dev/null
> +++ b/drivers/power/pmic/bd71837.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2018 NXP *
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct pmic_child_info pmic_children_info[] = {
> + /* buck */
> + { .prefix = "b", .driver = BD71837_REGULATOR_DRIVER},
> + /* ldo */
> + { .prefix = "l", .driver = BD71837_REGULATOR_DRIVER},
> + { },
> +};
> +
> +static int bd71837_reg_count(struct udevice *dev)
> +{
> + return BD71837_REG_NUM;
> +}
> +
> +static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff,
> +int len)
> +{
> + if (dm_i2c_write(dev, reg, buff, len)) {
> + pr_err("write error to device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int bd71837_read(struct udevice *dev, uint reg, uint8_t *buff, int
> len)
> +{
> + if (dm_i2c_read(dev, reg, buff, len)) {
> + pr_err("read error from device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int bd71837_bind(struct udevice *dev)
> +{
> + int children;
> + ofnode regulators_node;
> +
> + regulators_node = dev_read_subnode(dev, "regulators");
> + if (!ofnode_valid(regulators_node)) {
> + debug("%s: %s regulators subnode not found!", __func__,
> + dev->name);
> + return -ENXIO;
> + }
> +
> + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
> +
> + children = pmic_bind_children(dev, regulators_node,
> pmic_children_info);
> + if (!children)
> + debug("%s: %s - no child found\n", __func__, dev->name);
> +
> + /* Always return success for this device */
> + return 0;
> +}
> +
> +static struct dm_pmic_ops bd71837_ops = {
> + .reg_count = bd71837_reg_count,
> + .read = bd71837_read,
> + .w
Re: [U-Boot] [PATCH v4 1/2] dlmalloc: fix malloc range at end of ram
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt wrote: > > If the malloc range passed to mem_malloc_init() is at the end of address > range and 'start + size' overflows to 0, following allocations fail as > mem_malloc_end is zero (which looks like uninitialized). > > Fix this by subtracting 1 of 'start + size' overflows to zero. > > Signed-off-by: Simon Goldschmidt > --- > > Changes in v4: None > Changes in v3: None > > common/dlmalloc.c | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: Move tegra loopback disable option to be under tegra
On Mon, 1 Apr 2019 at 17:05, Trent Piepho wrote: > > This is a configuration option specific to the tegra controller. > > Doing it this way makes it show up directly under the tegra controller > option, indented one level, as "Disable external clock loopback". > > The way it is now, it shows up at the end of the controller list, not > indented, as if it's some kind of generic MMC configuration option. > > Cc: Marcel Ziswiler > Cc: Simon Glass > Cc: Jaehoon Chung > Cc: Tom Warren > Signed-off-by: Trent Piepho > --- > drivers/mmc/Kconfig | 22 +++--- > 1 file changed, 11 insertions(+), 11 deletions(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] dlmalloc: be compatible to tiny printf
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt
wrote:
>
> Convert debug output from '%#lx' to '0x%lx' to be compatible with tiny
> printf used in SPL.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v4:
> - dumped clearing BSS before SPL board_init_f, only real bugfixes remain
>
> Changes in v3:
> - fixed summary ("stack" -> "heap")
> - enable CONFIG_SPL_CLEAR_BSS_F for socfpga_arria10 using full malloc
> early in SPL
> - rebased
>
> common/dlmalloc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] Booting MX6 via Serial Download after DM conversion
Hi Fabio > -Original Message- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: 2019年4月24日 10:01 > To: Peng Fan ; Abel Vesa > Cc: Stefano Babic ; Lukasz Majewski ; > Michael Trimarchi ; dl-uboot-imx > ; Jagan Teki ; Marcel > Ziswiler ; U-Boot-Denx > ; Adam Ford ; Ye Li > ; Otavio Salvador > Subject: Re: Booting MX6 via Serial Download after DM conversion > > Hi Peng and Abel, > > On Mon, Apr 22, 2019 at 11:00 PM Peng Fan wrote: > > > Honestly I am not familiar with imx_usb, we use mfgtool previously and not > uuu tool. > > Is the UUU tool capable of loading SPL + u-boot-dtb.img generated from > mainline U-Boot for mx6sabresd? Not try this. uuu should support SPL file being loaded, then if SPL could runs into fastboot mode to interactive with uuu, then u-boot-dtb.img could be loaded I think. Regards, Peng. > > Thanks ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable
Hi Bin Bin Meng 於 2019年4月23日 週二 下午8:19寫道： > > On Tue, Apr 23, 2019 at 8:14 PM Bin Meng wrote: > > > > Hi Rick, > > > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > > > From: Rick Chen > > > > > > > typo in the commit title: seletable -> selectable OK > > > > > In smp flow this two features only can be enabled when U-Boot > > > > this->these OK > > > > > boot from ram. It shall be disabled when U-Boot boot from flash. > > > > boot->boots OK > > > > > > > > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select > > BTW: is it possible to use a single option for such feature, like > CONFIG_XIP? Basically these two options are used for the same reason. Yes. This is my initial idea. But I worry the connection seem a little weak. But if you say so, I will do it as you say. Thanks Rick > > > > this two features. Their default value will say YES for booting > > > > this->these > > > > > from ram. > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Booting MX6 via Serial Download after DM conversion
Hi Peng and Abel, On Mon, Apr 22, 2019 at 11:00 PM Peng Fan wrote: > Honestly I am not familiar with imx_usb, we use mfgtool previously and not > uuu tool. Is the UUU tool capable of loading SPL + u-boot-dtb.img generated from mainline U-Boot for mx6sabresd? Thanks ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram
Hi Bin Bin Meng 於 2019年4月23日 週二 下午8:14寫道： > > Hi Rick, > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > From: Rick Chen > > > > nits in the commit title: boot->booting OK > > > When AE350 was booting from ram, use OF_PRIOR_STAGE instead > > of OF_PRIOR_STAGE. > > This should be CONFIG_OF_BOARD OK Thanks Rick > > > > > Signed-off-by: Rick Chen > > Cc: Greentime Hu > > --- > > configs/ae350_rv32_defconfig | 2 +- > > configs/ae350_rv64_defconfig | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig > > index e13c7de..54b65f1 100644 > > --- a/configs/ae350_rv32_defconfig > > +++ b/configs/ae350_rv32_defconfig > > @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > -CONFIG_OF_BOARD=y > > +CONFIG_OF_PRIOR_STAGE=y > > CONFIG_DEFAULT_DEVICE_TREE="ae350_32" > > CONFIG_ENV_IS_IN_SPI_FLASH=y > > CONFIG_NET_RANDOM_ETHADDR=y > > diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig > > index a41f918..0ff4de8 100644 > > --- a/configs/ae350_rv64_defconfig > > +++ b/configs/ae350_rv64_defconfig > > @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y > > # CONFIG_CMD_SETEXPR is not set > > CONFIG_BOOTP_PREFER_SERVERIP=y > > CONFIG_CMD_CACHE=y > > -CONFIG_OF_BOARD=y > > +CONFIG_OF_PRIOR_STAGE=y > > CONFIG_DEFAULT_DEVICE_TREE="ae350_64" > > CONFIG_ENV_IS_IN_SPI_FLASH=y > > CONFIG_NET_RANDOM_ETHADDR=y > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable
Hi Bin Bin Meng 於 2019年4月23日 週二 下午8:14寫道： > > Hi Rick, > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > From: Rick Chen > > > > commit title should read: prior_stage_fdt_address should only be used > when OF_PRIOR_STAGE is enabled OK > > > This patch will fix prior_stage_fdt_address write failure problem, when > > AE350 was booting from flash. > > > > When AE350 was booting from falsh, prior_stage_fdt_address will be in > > flash address, we shall avoid it to be written. > > > > Signed-off-by: Rick Chen > > Cc: Greentime Hu > > --- > > arch/riscv/cpu/start.S | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > index d030d4a..0e672e0 100644 > > --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -111,7 +111,9 @@ call_board_init_f_0: > > bneztp, secondary_hart_loop > > #endif > > > > +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) > > la t0, prior_stage_fdt_address > > +#endif > > I think you should also surround the declaration of > prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE OK I will surround it. Thanks for review Rick > > > SREGs1, 0(t0) > > > > jal board_init_f_init_reserve > > -- > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow
Hi Bin Bin Meng 於 2019年4月23日 週二 下午8:14寫道： > > Hi Rick, > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > From: Rick Chen > > nits in the commit title: boot->booting OK > > > > > Add two defconfig to support AE350 SMP boot from flash > > boot->bootings OK > > > by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS. > > disable->disabling OK > > > > > Signed-off-by: Rick Chen > > Cc: Greentime Hu > > --- > > configs/ae350_rv32_xip_defconfig | 37 + > > configs/ae350_rv64_xip_defconfig | 38 > > ++ > > 2 files changed, 75 insertions(+) > > create mode 100644 configs/ae350_rv32_xip_defconfig > > create mode 100644 configs/ae350_rv64_xip_defconfig > > > > diff --git a/configs/ae350_rv32_xip_defconfig > > b/configs/ae350_rv32_xip_defconfig > > new file mode 100644 > > index 000..1639367 > > --- /dev/null > > +++ b/configs/ae350_rv32_xip_defconfig > > @@ -0,0 +1,37 @@ > > +CONFIG_RISCV=y > > +CONFIG_HART_LOTTERY=n > > +CONFIG_AVAILABLE_HARTS=n > > I think this should be: > > # CONFIG_HART_LOTTERY is not set > # CONFIG_AVAILABLE_HARTS is not set OK > > > +CONFIG_SYS_TEXT_BASE=0x8000 > > +CONFIG_TARGET_AX25_AE350=y > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_NR_DRAM_BANKS=2 > > +CONFIG_FIT=y > > +CONFIG_BOOTDELAY=3 > > +CONFIG_BOARD_EARLY_INIT_F=y > > +CONFIG_SYS_PROMPT="RISC-V # " > > +CONFIG_CMD_IMLS=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_SF=y > > +CONFIG_CMD_SF_TEST=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_BOOTP_PREFER_SERVERIP=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_OF_BOARD=y > > +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" > > +CONFIG_ENV_IS_IN_SPI_FLASH=y > > +CONFIG_NET_RANDOM_ETHADDR=y > > +CONFIG_MMC=y > > +CONFIG_FTSDC010=y > > +CONFIG_FTSDC010_SDIO=y > > +CONFIG_MTD_NOR_FLASH=y > > +CONFIG_FLASH_CFI_DRIVER=y > > +CONFIG_CFI_FLASH=y > > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y > > +CONFIG_SYS_FLASH_CFI=y > > +CONFIG_SPI_FLASH=y > > +CONFIG_SPI_FLASH_MACRONIX=y > > +CONFIG_FTMAC100=y > > +CONFIG_BAUDRATE=38400 > > +CONFIG_SYS_NS16550=y > > +CONFIG_SPI=y > > +CONFIG_ATCSPI200_SPI=y > > diff --git a/configs/ae350_rv64_xip_defconfig > > b/configs/ae350_rv64_xip_defconfig > > new file mode 100644 > > index 000..d6a502c > > --- /dev/null > > +++ b/configs/ae350_rv64_xip_defconfig > > @@ -0,0 +1,38 @@ > > +CONFIG_RISCV=y > > +CONFIG_HART_LOTTERY=n > > +CONFIG_AVAILABLE_HARTS=n > > ditto OK > > > +CONFIG_SYS_TEXT_BASE=0x8000 > > +CONFIG_TARGET_AX25_AE350=y > > +CONFIG_ARCH_RV64I=y > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_NR_DRAM_BANKS=2 > > +CONFIG_FIT=y > > +CONFIG_BOOTDELAY=3 > > +CONFIG_BOARD_EARLY_INIT_F=y > > +CONFIG_SYS_PROMPT="RISC-V # " > > +CONFIG_CMD_IMLS=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_SF=y > > +CONFIG_CMD_SF_TEST=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_BOOTP_PREFER_SERVERIP=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_OF_BOARD=y > > +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" > > +CONFIG_ENV_IS_IN_SPI_FLASH=y > > +CONFIG_NET_RANDOM_ETHADDR=y > > +CONFIG_MMC=y > > +CONFIG_FTSDC010=y > > +CONFIG_FTSDC010_SDIO=y > > +CONFIG_MTD_NOR_FLASH=y > > +CONFIG_FLASH_CFI_DRIVER=y > > +CONFIG_CFI_FLASH=y > > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y > > +CONFIG_SYS_FLASH_CFI=y > > +CONFIG_SPI_FLASH=y > > +CONFIG_SPI_FLASH_MACRONIX=y > > +CONFIG_FTMAC100=y > > +CONFIG_BAUDRATE=38400 > > +CONFIG_SYS_NS16550=y > > +CONFIG_SPI=y > > +CONFIG_ATCSPI200_SPI=y > Thanks for your review. Rick > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data section
> -Original Message-
> From: Lukasz Majewski [mailto:lu...@denx.de]
> Sent: 2019年4月23日 22:45
> To: Stefano Babic ; u-boot@lists.denx.de; Fabio Estevam
> ; Fabio Estevam ;
> dl-uboot-imx ; Jagan Teki
> ; Adam Ford
> Cc: Lukasz Majewski ; Bin Meng ;
> Simon Glass
> Subject: [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data
> section
>
> This commit is necessary to be able to re-use the pinctrl code in early SPL to
> properly configure pins.
>
> The problem is that those "static" structures (without explicit
> initialization) are placed in the SDRAM area, which corresponds to u-boot
> proper (not even SPL).
> Hence, when one wants to configure pins before relocation via DTS/DM, the
> board hangs (imx6q SoC powered one) as only OCRAM area is available
> (0x009x).
>
> This commit prevents from this issue by moving the imx6_pinctrl_soc_info
> structure to data section (from BSS).
>
> Signed-off-by: Lukasz Majewski
>
> ---
>
> Changes in v2:
> - Use __section(".data") instead of rewritting the code to use calloc()
> (less intrusive commit)
>
> drivers/pinctrl/nxp/pinctrl-imx6.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c
> b/drivers/pinctrl/nxp/pinctrl-imx6.c
> index d7c95bb738..0c1e7a9c05 100644
> --- a/drivers/pinctrl/nxp/pinctrl-imx6.c
> +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
> @@ -10,7 +10,7 @@
>
> #include "pinctrl-imx.h"
>
> -static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
> +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info
> +__section(".data");
>
> /* FIXME Before reloaction, BSS is overlapped with DT area */ static struct
> imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {
Reviewed-by: Peng Fan
> --
> 2.11.0
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Re: [U-Boot] [PATCH 0/4] AE350 support SMP boot from flash
Hi Lukas Auer, Lukas 於 2019年4月24日 週三 上午3:58寫道： > > Hi Rick, > > On Tue, 2019-04-23 at 13:42 +0800, Andes wrote: > > From: Rick Chen > > > > In current RISC-V SMP flow, AE350 will encounter the the write > > failure problem since hart_lottery and available_harts_lock was > > not in ram address but in flash address when booing from flash. > > > > This patch can help to fix the failure problem when AE350 was > > booting from flash by disable this two features. > > > > Can you describe the issue you are seeing a bit more. The write > failures are both to variables in the .data section, which should be > writable. Perhaps the write failures can be avoided by moving the .data > section or just the variable to RAM? > When I compile AE350's CONFIG_SYS_TEXT_BASE=0x8000 which is spi flash base. And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will run in XIP mode. At this time prior_stage_fdt_address will be in flash address(0x8004e9e8) So it is not writable. 8042: 16021563bneztp,81ac 8046: 0004f297auipc t0,0x4f 804a: 9a22a283lw t0,-1630(t0) # 8004e9e8 804e: 0092a023sw s1,0(t0) Rick > Thanks, > Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] EFIBootGuard for CIP and SecureBoot
Hello Francois, Jan, Christian, and all Sorry for the late reply, I was waiting for the administrator of the Boot Architecture mailing list to accept my subscription request, but it seems it will take a bit more time. I will send this reply and hope it will not be blocked. I have also added the u-boot mailing list to Cc, as Tom suggested (although I'm not a member), the CIP mailing list, Jan Kiszka (one of the main developers of Efibootguard) and Christian (an expert in software updates). Background: during the last Linaro connect in Bangkok I was told that Linaro Edge (LEDGE) were working on a secure software update mechanism based on UEFI capsules that would flash firmware updates from a UEFI application, instead of using a Linux agent such as SWUpdate. Then, I had an online meeting with Francois, director of LEDGE. I explained to Francois that in CIP we are using the Linux agent approach right now, and we are also considering the use of a UEFI application (Efibootguard) to arm a watchdog and deal with the state-machine variables (installed, testing, ok, failed..) needed for A/B software updates. Efibootguard sounds like an excellent place to collaborate with Linaro (particularly on the watchdog drivers front) because it does not strictly depend on where the firmware is flashed (UEFI capsule or Linux agent). > On Fri, Apr 19, 2019 at 12:48:51PM +0200, Francois Ozog wrote: > > Hi Daniel, > > > > We will be conducting a UEFI gap analysis to support EFIBootGuard in U-Boot. > > > > As we are working on UEFI SecureBoot implementation in U-Boot, how do > > you expect the boot process to be secured? Would U-Boot UEFI > > SecureBoot verify EFIBootGuard signature and in turn EFIBootGuard will > > check either grub or Linux signature? > > > > Please elaborate on your vision of a secured boot process. Efibootguard is composed of two parts. - A UEFI application that can arm a watchdog and decide what environment (kernel, boot args, etc.) to use next depending on a set of variables (update status, highest revision, etc.) stored in FAT16 partitions. - A Linux application that can read and set those variables from Linux (similar to u-boot's fw_setenv). This functionality is also available in the form of a library. As far as I know, there is no concept of "Secure Booting" in Efibootguard at the moment. Adding signature checks before booting into the selected kernel would be a possible solution. Thanks, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] warp7: configs: bl33: Tidy up OPTEE defines
When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the following print-out. Board: WARP7 in secure mode OPTEE DRAM 0xa000-0xa000 This is incorrect the right range is 0x9e00-0xa000. This patch fixes the defines on the warp7_bl33_defconfig file to tidy up the output. Signed-off-by: Bryan O'Donoghue Cc: Fabio Estevam --- configs/warp7_bl33_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 6eaf152bac..8cc622fe47 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -50,4 +50,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" -CONFIG_OPTEE_TZDRAM_SIZE=0x200 +CONFIG_OPTEE=y +CONFIG_OPTEE_TZDRAM_BASE=0x9e00 +CONFIG_OPTEE_TZDRAM_SIZE=0x0200 -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4] warp7: include: configs: Skip low-level init if BOOTM_OPTEE false
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") wants to skip low-level init of i.MX7 hardware in the case where
OP-TEE has already run and u-boot is being run as BL33 in normal world.
Currently we check for both #ifdef CONFIG_OPTEE_TZDRAM_SIZE and #ifndef
CONFIG_OPTEE to determine if lowlevel init should be skipped, however, in
order to ensure non-OPTEE users never see OPTEE related defines we cannot
rely on this method.
Fortunately we can use CONFIG_BOOTM_OPTEE for the same purpose.
CONFIG_BOOTM_OPTEE is only relevant if you want u-boot to load OP-TEE not
if u-boot has already been loaded by OP-TEE.
Signed-off-by: Bryan O'Donoghue
Cc: Fabio Estevam
Cc: Breno Lima
Cc: Rui Miguel Silva
---
include/configs/warp7.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 043f2861b6..458cb8fe10 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -18,11 +18,9 @@
* launched by OPTEE, because of that we shall skip all the low level
* initialization since it was already done by ATF or OPTEE
*/
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
-#ifndef CONFIG_OPTEE
+#ifndef CONFIG_BOOTM_OPTEE
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#endif
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
--
2.20.1
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[U-Boot] [PATCH 4/4] MAINTAINERS: Update lib/optee with my details
Commit 32ce6179fb99 ("optee: Add lib entries for sharing OPTEE code across
ports") adds code into lib/optee but neglects to update MAINTAINERS to make
me buggable for questions and maintenance.
Signed-off-by: Bryan O'Donoghue
Suggested-by: Jens Wiklander
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa4b3bc650..16ea180fe2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -754,6 +754,11 @@ F: drivers/tee/
F: include/tee.h
F: include/tee/
+TEE-lib
+M: Bryan O'Donoghue
+S: Maintained
+F: lib/optee
+
UBI
M: Kyungmin Park
M: Heiko Schocher
--
2.20.1
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[U-Boot] [PATCH 0/4] Tidy up some dangling OP-TEE gotchas
Rober P Day rightly pointed out that some odd OP-TEE specific defines were appearing in his defconfig, despite not having CONFIG_OPTEE=y set in his defconfig. Looking into this with a small bit of restructure we can fix this corner case. - Make sure OP-TEE CONFIG options only appear when you are compiling for OPTEE - Fix WaRP7 BL33 so that the low-level init skipping routines can tolerate the afore mentioned change. - Update MAINTAINERS with my own details so that questions pertaining to lib/optee comes my way. Bryan O'Donoghue (4): optee: Make TZDRAM config options contingent on CONFIG_OPTEE warp7: include: configs: Skip low-level init if BOOTM_OPTEE false warp7: configs: bl33: Tidy up OPTEE defines MAINTAINERS: Update lib/optee with my details MAINTAINERS | 5 + configs/warp7_bl33_defconfig | 4 +++- include/configs/warp7.h | 4 +--- lib/optee/Kconfig| 2 ++ 4 files changed, 11 insertions(+), 4 deletions(-) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] optee: Make TZDRAM config options contingent on CONFIG_OPTEE
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") makes the TZDRAM defines for OPTEE show up for all configs as a
side-effect. While not harmful its not what we really want.
This patch makes the following defines contingent on CONFIG_OPTEE=y
CONFIG_OPTEE_TZDRAM_BASE
CONFIG_OPTEE_TZDRAM_SIZE
Rightly, if you don't have CONFIG_OPTEE=y you don't care about the above
two defines.
Signed-off-by: Bryan O'Donoghue
Cc: Rui Miguel Silva
---
lib/optee/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
index 3773d89c31..c398f9b953 100644
--- a/lib/optee/Kconfig
+++ b/lib/optee/Kconfig
@@ -17,6 +17,7 @@ config OPTEE_LOAD_ADDR
config OPTEE_TZDRAM_SIZE
hex "Amount of Trust-Zone RAM for the OPTEE image"
default 0x000
+ depends on OPTEE
help
The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
runtime.
@@ -24,6 +25,7 @@ config OPTEE_TZDRAM_SIZE
config OPTEE_TZDRAM_BASE
hex "Base address of Trust-Zone RAM for the OPTEE image"
default 0x
+ depends on OPTEE
help
The base address of pre-allocated Trust Zone DRAM for
the OPTEE runtime.
--
2.20.1
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Re: [U-Boot] [PATCH] RISCV: image: Add booti support.
On 4/24/19 1:36 AM, Atish Patra wrote:
> This patch adds booti support for RISC-V Linux kernel. The existing
> bootm method will also continue to work as it is.
>
> It depends on the following kernel patch which adds the header to the
> flat Image.
>
> https://patchwork.kernel.org/patch/10913869/
>
> Tested on HiFive Unleashed and QEMU.
> Currently, compressed images such as Image.gz are not supported.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/image.c | 60 +
> cmd/Kconfig | 2 +-
> cmd/booti.c | 8 --
> 4 files changed, 68 insertions(+), 3 deletions(-)
> create mode 100644 arch/riscv/lib/image.c
>
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 1c332db436a9..6ae6ebbeafda 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -7,6 +7,7 @@
> # Rick Chen, Andes Technology Corporation
>
> obj-$(CONFIG_CMD_BOOTM) += bootm.o
> +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> obj-$(CONFIG_CMD_GO) += boot.o
> obj-y+= cache.o
> obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
> new file mode 100644
> index ..99c2e31066a3
> --- /dev/null
> +++ b/arch/riscv/lib/image.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Western Digital Corporation or its affiliates.
> + * Authors:
> + * Atish Patra
> + * Based on arm/lib/image.c
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* ASCII version of "RISCV" defined in Linux kernel */
> +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
> +
> +struct linux_image_h {
> + uint32_tcode0; /* Executable code */
> + uint32_tcode1; /* Executable code */
> + uint64_ttext_offset;/* Image load offset */
> + uint64_timage_size; /* Effective Image size */
> + uint64_tres1; /* reserved */
> + uint64_tmagic; /* Magic number */
> + uint32_tres2; /* reserved */
> + uint32_tres3; /* reserved */
> +};
> +
> +int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
> + bool force_reloc)
> +{
> + struct linux_image_h *lhdr;
> + uint64_t dst;
> + uint64_t image_size, text_offset;
> +
> + *relocated_addr = image;
You're setting this here to $image, but you're overriding this at the
end of the function again with gd->ram_base + text_offset , is that
intended?
> + lhdr = (struct linux_image_h *)map_sysmem(image, 0);
> +
> + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
> + puts("Bad Linux RISCV Image magic!\n");
> + return 1;
> + }
> +
> + if (lhdr->image_size != 0) {
> + image_size = lhdr->image_size;
> + text_offset = lhdr->text_offset;
Maybe you can use lhdr->* directly and get rid of these local variables ?
> + } else {
> + puts("Image lacks image_size field, Error!!\n");
error, lowercase . And use one exclamation mark.
> + return 1;
Use errno.h return code instead.
> + }
> + *size = image_size;
> + dst = gd->ram_base;
> + *relocated_addr = dst + text_offset;
Use gd->ram_base instead of $dst and drop $dst altogether.
> +
[...]
--
Best regards,
Marek Vasut
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[U-Boot] [PATCH] RISCV: image: Add booti support.
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image.
https://patchwork.kernel.org/patch/10913869/
Tested on HiFive Unleashed and QEMU.
Currently, compressed images such as Image.gz are not supported.
Signed-off-by: Atish Patra
---
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/image.c | 60 +
cmd/Kconfig | 2 +-
cmd/booti.c | 8 --
4 files changed, 68 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/lib/image.c
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1c332db436a9..6ae6ebbeafda 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -7,6 +7,7 @@
# Rick Chen, Andes Technology Corporation
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
new file mode 100644
index ..99c2e31066a3
--- /dev/null
+++ b/arch/riscv/lib/image.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ * Authors:
+ * Atish Patra
+ * Based on arm/lib/image.c
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ASCII version of "RISCV" defined in Linux kernel */
+#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
+
+struct linux_image_h {
+ uint32_tcode0; /* Executable code */
+ uint32_tcode1; /* Executable code */
+ uint64_ttext_offset;/* Image load offset */
+ uint64_timage_size; /* Effective Image size */
+ uint64_tres1; /* reserved */
+ uint64_tmagic; /* Magic number */
+ uint32_tres2; /* reserved */
+ uint32_tres3; /* reserved */
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+ bool force_reloc)
+{
+ struct linux_image_h *lhdr;
+ uint64_t dst;
+ uint64_t image_size, text_offset;
+
+ *relocated_addr = image;
+
+ lhdr = (struct linux_image_h *)map_sysmem(image, 0);
+
+ if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+ puts("Bad Linux RISCV Image magic!\n");
+ return 1;
+ }
+
+ if (lhdr->image_size != 0) {
+ image_size = lhdr->image_size;
+ text_offset = lhdr->text_offset;
+ } else {
+ puts("Image lacks image_size field, Error!!\n");
+ return 1;
+ }
+ *size = image_size;
+ dst = gd->ram_base;
+ *relocated_addr = dst + text_offset;
+
+ unmap_sysmem(lhdr);
+
+ return 0;
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2bdbfcb3d091..d427b66d3714 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -212,7 +212,7 @@ config CMD_BOOTZ
config CMD_BOOTI
bool "booti"
- depends on ARM64
+ depends on ARM64 || RISCV
default y
help
Boot an AArch64 Linux Kernel image from memory.
diff --git a/cmd/booti.c b/cmd/booti.c
index 04353b68eccc..c22ba9bae2e4 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
+ #ifdef CONFIG_RISCV_SMODE
+ images.os.arch = IH_ARCH_RISCV;
+ #elif CONFIG_ARM64
images.os.arch = IH_ARCH_ARM64;
+ #endif
ret = do_bootm_states(cmdtp, flag, argc, argv,
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
BOOTM_STATE_RAMDISK |
@@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
#ifdef CONFIG_SYS_LONGHELP
static char booti_help_text[] =
"[addr [initrd[:size]] [fdt]]\n"
- "- boot arm64 Linux Image stored in memory\n"
+ "- boot arm64/riscv Linux Image stored in memory\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
"\tof an initrd in memory. The optional parameter ':size' allows\n"
"\tspecifying the size of a RAW initrd.\n"
@@ -107,5 +111,5 @@ static char booti_help_text[] =
U_BOOT_CMD(
booti, CONFIG_SYS_MAXARGS, 1, do_booti,
- "boot arm64 Linux Image image from memory", booti_help_text
+ "boot arm64/riscv Linux Image image from memory", booti_help_text
);
--
2.21.0
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Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver
On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote: > Hi, > > This is V4 of the series to add a UCLASS_CACHE dm driver to handling > the configuration of cache settings. Place this new driver under > /drivers/cache. In this initial revision, the driver is only configuring > what I think are essential cache settings. The more comprehensive cache > settings can be done in the OS. > > Diffs from v4: > - Fix compile error found in sandbox_cache.c Thanks. I'd greatly appreciate it if you can throw this whole series at travis (or just do a world build locally) and report back that everything is OK now. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv5 4/6] dm: cache: add the pl310 cache controller driver
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.
This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
v4: no change
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
drivers/cache/Kconfig | 9 +
drivers/cache/Makefile | 1 +
drivers/cache/cache-l2x0.c | 76 ++
3 files changed, 86 insertions(+)
create mode 100644 drivers/cache/cache-l2x0.c
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
is usually located on the same chip. This uclass can be used for
configuring settings that be found from a device tree file.
+config L2X0_CACHE
+ tristate "PL310 cache driver"
+ select CACHE
+ depends on ARM
+ help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+#include
+#include
+#include
+
+#include
+#include
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+ u32 tag[3] = { 0, 0, 0 };
+ u32 saved_reg, prefetch;
+ struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+ /* Disable the L2 Cache */
+ clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+
+ saved_reg = readl(®s->pl310_aux_ctrl);
+ if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ }
+
+ if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+ }
+
+ saved_reg |= dev_read_bool(dev, "arm,shared-override");
+ writel(saved_reg, ®s->pl310_aux_ctrl);
+
+ saved_reg = readl(®s->pl310_tag_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_tag_latency_ctrl);
+
+ saved_reg = readl(®s->pl310_data_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_data_latency_ctrl);
+
+ /* Enable the L2 cache */
+ setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+ l2c310_of_parse_and_init(dev);
+
+ return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+ { .compatible = "arm,pl310-cache" },
+ {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+ .name = "pl310_cache",
+ .id = UCLASS_CACHE,
+ .of_match = l2x0_ids,
+ .probe = l2x0_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
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[U-Boot] [PATCHv5 6/6] configs: socfpga: add imply pl310 cache controller
Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f58f8fb235..f5132d8174 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -845,6 +845,7 @@ config ARCH_SOCFPGA imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI_SUPPORT + imply L2X0_CACHE config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv5 3/6] dm: cache: Create a uclass for cache
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
v5: fix compile error for sandbox_cache.c
v4: re-order includes and add Reviewed-by:
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/cache/Kconfig | 16 +++
drivers/cache/Makefile| 3 +++
drivers/cache/cache-uclass.c | 24 ++
drivers/cache/sandbox_cache.c | 34 +++
include/cache.h | 38 +++
include/dm/uclass-id.h| 1 +
test/dm/cache.c | 20 ++
9 files changed, 139 insertions(+)
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/cache-uclass.c
create mode 100644 drivers/cache/sandbox_cache.c
create mode 100644 include/cache.h
create mode 100644 test/dm/cache.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index e6702eced4..96ff4f566a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
+source "drivers/cache/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-y += board/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+ bool "Enable Driver Model for Cache controllers"
+ depends on DM
+ help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->get_info)
+ return -ENOSYS;
+
+ return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+ .id = UCLASS_CACHE,
+ .name = "cache",
+ .post_bind = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..14cc6b0c0a
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+ info->base = 0x11223344;
+
+ return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+ .get_info = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+ { .compatible = "sandbox,cache" },
+ { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+ .name = "cache_sandbox",
+ .id = UCLASS_CACHE,
+ .of_match = sandbox_cache_ids,
+ .ops= &sandbox_cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+ phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+ /**
+* get_info() - Get basic cache info
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @info: Place to put info
+* @
[U-Boot] [PATCHv5 5/6] ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/misc.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+ struct udevice *dev;
- /* Enable the L2 cache */
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+ pr_err("cache controller driver NOT found!\n");
}
void v7_outer_cache_disable(void)
--
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[U-Boot] [PATCHv5 2/6] ARM: pl310: Add macro's for handling tag and data latency mask
Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc..f69e9e45f8 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -18,6 +18,9 @@ #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n)((n) << 4) +#define L310_LATENCY_CTRL_WR(n)((n) << 8) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv5 1/6] Documentation: dts: Add pl310 cache controller dts documentation
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")
Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt
Copied from Linux kernel v5.0.
"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
.../devicetree/bindings/arm/l2c2x0.txt| 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+ "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+ "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+ "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+ "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3
cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells
of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
+- cache-id-part: cache id part number to be used if it is not present
+ on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
+- arm,parity-en
[U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver
Hi, This is V4 of the series to add a UCLASS_CACHE dm driver to handling the configuration of cache settings. Place this new driver under /drivers/cache. In this initial revision, the driver is only configuring what I think are essential cache settings. The more comprehensive cache settings can be done in the OS. Diffs from v4: - Fix compile error found in sandbox_cache.c Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache dm: cache: add the pl310 cache controller driver ARM: socfpga: use the pl310 driver to configure the cache configs: socfpga: add imply pl310 cache controller .../devicetree/bindings/arm/l2c2x0.txt| 114 ++ arch/arm/Kconfig | 1 + arch/arm/include/asm/pl310.h | 3 + arch/arm/mach-socfpga/misc.c | 16 +-- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 25 drivers/cache/Makefile| 4 + drivers/cache/cache-l2x0.c| 76 drivers/cache/cache-uclass.c | 24 drivers/cache/sandbox_cache.c | 34 ++ include/cache.h | 38 ++ include/dm/uclass-id.h| 1 + test/dm/cache.c | 20 +++ 14 files changed, 346 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/cache-l2x0.c create mode 100644 drivers/cache/cache-uclass.c create mode 100644 drivers/cache/sandbox_cache.c create mode 100644 include/cache.h create mode 100644 test/dm/cache.c -- 2.20.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h
On 4/23/19 10:51 PM, Simon Goldschmidt wrote: > > > Marek Vasut mailto:ma...@denx.de>> schrieb am Di., 23. > Apr. 2019, 22:43: > > On 4/23/19 9:36 PM, Simon Goldschmidt wrote: > > This series cleans up the include/configs/socfpga_common.h file a bit. > > > > It removes some defines that are used nowhere and cleans up some > > leftovers after various subsystems have been converted to use DM. > > > > Changes in v4: > > - fix DM_I2C case: don't call i2c_set_bus_num() since this is > > done in cmd/eeprom already > > > > Changes in v3: > > - changed commit message: s/defines/macros and comments/ > > > > Changes in v2: > > - added (this) patch to move socfpga_vining to DM_I2C > > - remove even more outdated things > > - added (this) patch with further cleanups to the socfpga board config > > files > > > > Simon Goldschmidt (4): > > arm: socfpga: move vining_fpga to DM_I2C > > arm: socfpga: clean up socfpga_common.h > > arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ > > arm: socfpga: clean up board config files > > > > board/samtec/vining_fpga/socfpga.c | 9 +--- > > configs/socfpga_vining_fpga_defconfig | 8 ++- > > include/configs/socfpga_arria10_socdk.h | 6 --- > > include/configs/socfpga_arria5_socdk.h | 2 - > > include/configs/socfpga_common.h | 68 > > > include/configs/socfpga_cyclone5_socdk.h | 2 - > > include/configs/socfpga_de0_nano_soc.h | 2 - > > include/configs/socfpga_de10_nano.h | 2 - > > include/configs/socfpga_de1_soc.h | 2 - > > include/configs/socfpga_is1.h | 2 - > > include/configs/socfpga_sockit.h | 2 - > > include/configs/socfpga_socrates.h | 2 - > > include/configs/socfpga_sr1500.h | 11 > > include/configs/socfpga_vining_fpga.h | 18 --- > > 14 files changed, 8 insertions(+), 128 deletions(-) > > Neither of these apply to u-boot-socfpga/master :-( > > > Sorry for the confusion, these are again meant to apply on top of other > patches in a PR. Sent to the ML for reference, mainly, as the diffs are > tiny. > > How should I mark such patches to prevent such misunderstandings in the > future? Just send an incremental patch on top of u-boot-socfpga/master please . If you want me to squash it into another patch, note it somewhere around the diffstat. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, PATCHv4, 3/6] dm: cache: Create a uclass for cache
On 4/22/19 12:48 PM, Tom Rini wrote: > On Mon, Apr 01, 2019 at 05:32:17PM -0500, Dinh Nguyen wrote: > >> The cache UCLASS will be used for configure settings that can be found >> in a CPU's L2 cache controller. >> >> Add a uclass and a test for cache. >> >> Reviewed-by: Simon Glass >> Signed-off-by: Dinh Nguyen >> --- >> v4: re-order includes and add Reviewed-by: >> v3: Add cache_get_info() to check for non-zero value >> Add comments to cache_info struct >> v2: separate out uclass patch from driver and add test > > NAK: >sandbox: + tools-only > +(tools-only) In file included from drivers/cache/sandbox_cache.c:6:0: > +(tools-only) include/cache.h:13:2: error: unknown type name 'phys_addr_t' > +(tools-only) phys_addr_t base; /* Base physical address of cache device. */ > +(tools-only) ^~~ > +(tools-only) int (*get_info)(struct udevice *dev, struct cache_info *info); > +(tools-only) ^~~ > +(tools-only) int cache_get_info(struct udevice *dev, struct cache_info > *info); > +(tools-only)^~~ > +(tools-only) .get_info = sandbox_get_info, > +(tools-only) ^~~~ > +(tools-only) drivers/cache/sandbox_cache.c:21:14: note: (near initialization > for 'sandbox_cach > e_ops.get_info') > +(tools-only) make[3]: *** [drivers/cache/sandbox_cache.o] Error 1 > +(tools-only) make[2]: *** [drivers/cache] Error 2 > +(tools-only) make[1]: *** [drivers] Error 2 > +(tools-only) make: *** [sub-make] Error 2 > w+(tools-only) include/cache.h:24:25: warning: 'struct udevice' declared > inside parameter list will not be visible outside of this definition or > declaration > w+(tools-only) include/cache.h:36:27: warning: 'struct udevice' declared > inside parameter list will not be visible outside of this definition or > declaration > w+(tools-only) drivers/cache/sandbox_cache.c:21:14: warning: initialization > from incompatible pointer type [-Wincompatible-pointer-types] > I apologize for that! V5 is enroute and should be error free. Dinh signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h
Marek Vasut schrieb am Di., 23. Apr. 2019, 22:43: > On 4/23/19 9:36 PM, Simon Goldschmidt wrote: > > This series cleans up the include/configs/socfpga_common.h file a bit. > > > > It removes some defines that are used nowhere and cleans up some > > leftovers after various subsystems have been converted to use DM. > > > > Changes in v4: > > - fix DM_I2C case: don't call i2c_set_bus_num() since this is > > done in cmd/eeprom already > > > > Changes in v3: > > - changed commit message: s/defines/macros and comments/ > > > > Changes in v2: > > - added (this) patch to move socfpga_vining to DM_I2C > > - remove even more outdated things > > - added (this) patch with further cleanups to the socfpga board config > > files > > > > Simon Goldschmidt (4): > > arm: socfpga: move vining_fpga to DM_I2C > > arm: socfpga: clean up socfpga_common.h > > arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ > > arm: socfpga: clean up board config files > > > > board/samtec/vining_fpga/socfpga.c | 9 +--- > > configs/socfpga_vining_fpga_defconfig| 8 ++- > > include/configs/socfpga_arria10_socdk.h | 6 --- > > include/configs/socfpga_arria5_socdk.h | 2 - > > include/configs/socfpga_common.h | 68 > > include/configs/socfpga_cyclone5_socdk.h | 2 - > > include/configs/socfpga_de0_nano_soc.h | 2 - > > include/configs/socfpga_de10_nano.h | 2 - > > include/configs/socfpga_de1_soc.h| 2 - > > include/configs/socfpga_is1.h| 2 - > > include/configs/socfpga_sockit.h | 2 - > > include/configs/socfpga_socrates.h | 2 - > > include/configs/socfpga_sr1500.h | 11 > > include/configs/socfpga_vining_fpga.h| 18 --- > > 14 files changed, 8 insertions(+), 128 deletions(-) > > Neither of these apply to u-boot-socfpga/master :-( > Sorry for the confusion, these are again meant to apply on top of other patches in a PR. Sent to the ML for reference, mainly, as the diffs are tiny. How should I mark such patches to prevent such misunderstandings in the future? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h
On 4/23/19 9:36 PM, Simon Goldschmidt wrote: > This series cleans up the include/configs/socfpga_common.h file a bit. > > It removes some defines that are used nowhere and cleans up some > leftovers after various subsystems have been converted to use DM. > > Changes in v4: > - fix DM_I2C case: don't call i2c_set_bus_num() since this is > done in cmd/eeprom already > > Changes in v3: > - changed commit message: s/defines/macros and comments/ > > Changes in v2: > - added (this) patch to move socfpga_vining to DM_I2C > - remove even more outdated things > - added (this) patch with further cleanups to the socfpga board config > files > > Simon Goldschmidt (4): > arm: socfpga: move vining_fpga to DM_I2C > arm: socfpga: clean up socfpga_common.h > arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ > arm: socfpga: clean up board config files > > board/samtec/vining_fpga/socfpga.c | 9 +--- > configs/socfpga_vining_fpga_defconfig| 8 ++- > include/configs/socfpga_arria10_socdk.h | 6 --- > include/configs/socfpga_arria5_socdk.h | 2 - > include/configs/socfpga_common.h | 68 > include/configs/socfpga_cyclone5_socdk.h | 2 - > include/configs/socfpga_de0_nano_soc.h | 2 - > include/configs/socfpga_de10_nano.h | 2 - > include/configs/socfpga_de1_soc.h| 2 - > include/configs/socfpga_is1.h| 2 - > include/configs/socfpga_sockit.h | 2 - > include/configs/socfpga_socrates.h | 2 - > include/configs/socfpga_sr1500.h | 11 > include/configs/socfpga_vining_fpga.h| 18 --- > 14 files changed, 8 insertions(+), 128 deletions(-) Neither of these apply to u-boot-socfpga/master :-( -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] eeprom: fix DM_I2C support without CONFIG_SYS_I2C_EEPROM_BUS
Hi Simon,
> The current device model enabled eeprom code only works if
> CONFIG_SYS_I2C_EEPROM_BUS is set.
>
> This patch makes it work without that define so that the bus
> number passed to 'eeprom_init' is used.
Reviewed-by: Lukasz Majewski
>
> Signed-off-by: Simon Goldschmidt
> Reviewed-by: Heiko Schocher
> ---
>
> Changes in v3:
> - use eeprom_init() to set CONFIG_SYS_I2C_EEPROM_BUS, not
> i2c_set_bus_num to make things work with CONFIG_DM_I2C
>
> Changes in v2: None
>
> cmd/eeprom.c | 23 +++
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/cmd/eeprom.c b/cmd/eeprom.c
> index 6c29b33ba3..7b1f81477f 100644
> --- a/cmd/eeprom.c
> +++ b/cmd/eeprom.c
> @@ -59,6 +59,10 @@
> #endif
> #endif
>
> +#if defined(CONFIG_DM_I2C)
> +int eeprom_i2c_bus;
> +#endif
> +
> __weak int eeprom_write_enable(unsigned dev_addr, int state)
> {
> return 0;
> @@ -67,7 +71,9 @@ __weak int eeprom_write_enable(unsigned dev_addr,
> int state) void eeprom_init(int bus)
> {
> /* I2C EEPROM */
> -#if defined(CONFIG_SYS_I2C)
> +#if defined(CONFIG_DM_I2C)
> + eeprom_i2c_bus = bus;
> +#elif defined(CONFIG_SYS_I2C)
> if (bus >= 0)
> i2c_set_bus_num(bus);
> i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> @@ -124,14 +130,14 @@ static int eeprom_rw_block(unsigned offset,
> uchar *addr, unsigned alen, {
> int ret = 0;
>
> -#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
> +#if defined(CONFIG_DM_I2C)
> struct udevice *dev;
>
> - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS,
> addr[0],
> + ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0],
> alen - 1, &dev);
> if (ret) {
> printf("%s: Cannot find udev for a bus %d\n",
> __func__,
> -CONFIG_SYS_I2C_EEPROM_BUS);
> +eeprom_i2c_bus);
> return CMD_RET_FAILURE;
> }
>
> @@ -141,15 +147,12 @@ static int eeprom_rw_block(unsigned offset,
> uchar *addr, unsigned alen, ret = dm_i2c_write(dev, offset, buffer,
> len);
> #else /* Non DM I2C support - will be removed */
> -#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
> - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
> -#endif
>
> if (read)
> ret = i2c_read(addr[0], offset, alen - 1, buffer,
> len); else
> ret = i2c_write(addr[0], offset, alen - 1, buffer,
> len); -#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */
> +#endif /* CONFIG_DM_I2C */
> if (ret)
> ret = CMD_RET_FAILURE;
>
> @@ -164,6 +167,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned
> offset, uchar *buffer, int rcode = 0;
> uchar addr[3];
>
> +#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
> + eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS);
> +#endif
> +
> while (offset < end) {
> alen = eeprom_addr(dev_addr, offset, addr);
>
Best regards,
Lukasz Majewski
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Re: [U-Boot] [PATCH 0/4] AE350 support SMP boot from flash
Hi Rick, On Tue, 2019-04-23 at 13:42 +0800, Andes wrote: > From: Rick Chen > > In current RISC-V SMP flow, AE350 will encounter the the write > failure problem since hart_lottery and available_harts_lock was > not in ram address but in flash address when booing from flash. > > This patch can help to fix the failure problem when AE350 was > booting from flash by disable this two features. > Can you describe the issue you are seeing a bit more. The write failures are both to variables in the .data section, which should be writable. Perhaps the write failures can be avoided by moving the .data section or just the variable to RAM? Thanks, Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/4] arm: socfpga: clean up socfpga_common.h
Remove outdated macros and comments (not used any more, outdated due to DM conversion) from socfpga_common.h. Signed-off-by: Simon Goldschmidt --- Changes in v4: None Changes in v3: - changed commit message: s/defines/macros and comments/ Changes in v2: - remove even more outdated things include/configs/socfpga_common.h | 40 1 file changed, 40 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a65fc804e3..5b5e5f5d43 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -72,29 +72,12 @@ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot argument buffer size */ -#ifndef CONFIG_SYS_HOSTNAME -#define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD -#endif - /* * Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -/* - * EPCS/EPCQx1 Serial Flash Controller - */ -#ifdef CONFIG_ALTERA_SPI -/* - * The base address is configurable in QSys, each board must specify the - * base address based on it's particular FPGA configuration. Please note - * that the address here is incremented by 0x400 from the Base address - * selected in QSys, since the SPI registers are at offset +0x400. - * #define CONFIG_SYS_SPI_BASE 0xff240400 - */ -#endif - /* * Ethernet on SoC (EMAC) */ @@ -162,15 +145,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif -/* - * Designware SPI support - */ - -/* - * Serial Driver - */ -#define CONFIG_SYS_NS16550_SERIAL - /* * USB */ @@ -206,20 +180,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_ENV_SECT_SIZE (64 * 1024) #endif -/* - * mtd partitioning for serial NOR flash - * - * device nor0 , # parts = 6 - * #: namesizeoffset mask_flags - * 0: u-boot 0x0010 0x 0 - * 1: env10x0004 0x0010 0 - * 2: env20x0004 0x0014 0 - * 3: UBI 0x03e8 0x0018 0 - * 4: boot0x00e8 0x0018 0 - * 5: rootfs 0x0100 0x0100 0 - * - */ - /* * SPL * -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 4/4] arm: socfpga: clean up board config files
Remove outdated defines (not used any more, outdated due to DM conversion) from various socfpga files in include/config. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- Changes in v4: None Changes in v3: None Changes in v2: - added (this) patch with further cleanups to the socfpga board config files include/configs/socfpga_arria10_socdk.h | 6 -- include/configs/socfpga_arria5_socdk.h | 2 -- include/configs/socfpga_cyclone5_socdk.h | 2 -- include/configs/socfpga_de0_nano_soc.h | 2 -- include/configs/socfpga_de10_nano.h | 2 -- include/configs/socfpga_de1_soc.h| 2 -- include/configs/socfpga_is1.h| 2 -- include/configs/socfpga_sockit.h | 2 -- include/configs/socfpga_socrates.h | 2 -- include/configs/socfpga_sr1500.h | 11 --- include/configs/socfpga_vining_fpga.h| 9 - 11 files changed, 42 deletions(-) diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 0f116fbf2d..92630c5e6e 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -19,12 +19,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x4000 -/* Ethernet on SoC (EMAC) */ - -/* - * U-Boot environment configurations - */ - /* * Serial / UART configurations */ diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 24fcdd8b5a..af6137aeb1 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 18da8496ef..028db2a09e 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index d3224d5bd3..21108e3447 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h index 2fcabff8af..d85f98fbd4 100644 --- a/include/configs/socfpga_de10_nano.h +++ b/include/configs/socfpga_de10_nano.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index f37099c58f..9919d292dc 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index c233c208a5..c4da5947f3 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -19,8 +19,6 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) #define CONFIG_ARP_TIMEOUT 500UL - -/* PHY */ #endif /* The rest of the configuration is shared */ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 3a7f354914..97249a 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index f0d9347891..7faea150a9 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR0x0100 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index b6a98611c0..3a8ccc3021 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -19,8 +19,6 @@ /* The PHY is autodetected, so no MII PHY address is needed here */ #define PHY_AN
[U-Boot] [PATCH v4 3/4] arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ
socfpga_common.h defines CONFIG_SYS_BOOTMAPSZ to 64 MiB. Since having this define overrides the 'bootm_size' env variable for the whole socfpga platform, let's remove this define from socfpga_common.h and instead rely on the 'bootm_size' env variable (which is initialized to 160 MiB in the same file's default env). This gives users the chance to override it in their own environment. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- Changes in v4: None Changes in v3: None Changes in v2: None include/configs/socfpga_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5b5e5f5d43..5eccb01d1d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -10,8 +10,6 @@ */ #define CONFIG_CLOCKS -#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/4] arm: socfpga: move vining_fpga to DM_I2C
All socfpga boards except for vining_fpga use DM_I2C. Enable
DM_I2C for this board and set the EEPROM defines via Kconfig
(enabling CONFIG_I2C_EEPROM from MISC).
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- fix DM_I2C case: don't call i2c_set_bus_num() since this is
done in cmd/eeprom already
Changes in v3: None
Changes in v2:
- added (this) patch to move socfpga_vining to DM_I2C
board/samtec/vining_fpga/socfpga.c| 9 +
configs/socfpga_vining_fpga_defconfig | 8 +++-
include/configs/socfpga_common.h | 26 --
include/configs/socfpga_vining_fpga.h | 9 -
4 files changed, 8 insertions(+), 44 deletions(-)
diff --git a/board/samtec/vining_fpga/socfpga.c
b/board/samtec/vining_fpga/socfpga.c
index d99aac6828..efc8ddf162 100644
--- a/board/samtec/vining_fpga/socfpga.c
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -52,14 +52,7 @@ int misc_init_r(void)
u32 serial;
int ret;
- /* EEPROM is at bus 0. */
- ret = i2c_set_bus_num(0);
- if (ret) {
- puts("Cannot select EEPROM I2C bus.\n");
- return 0;
- }
-
- /* EEPROM is at address 0x50. */
+ /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
ret = eeprom_read(0x50, 0, data, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
diff --git a/configs/socfpga_vining_fpga_defconfig
b/configs/socfpga_vining_fpga_defconfig
index 7b47b111b7..4a7f775337 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -16,8 +16,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -44,6 +44,7 @@ CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
@@ -55,6 +56,11 @@ CONFIG_LED_STATUS_BIT2=54
CONFIG_LED_STATUS3=y
CONFIG_LED_STATUS_BIT3=65
CONFIG_LED_STATUS_CMD=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a501b5209f..a65fc804e3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -149,32 +149,6 @@
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
-/*
- * I2C support
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BASESOCFPGA_I2C0_ADDRESS
-#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
-#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
-#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
-/* Using standard mode which the speed up to 100Kb/s */
-#define CONFIG_SYS_I2C_SPEED 10
-#define CONFIG_SYS_I2C_SPEED1 10
-#define CONFIG_SYS_I2C_SPEED2 10
-#define CONFIG_SYS_I2C_SPEED3 10
-/* Address of device when used as slave */
-#define CONFIG_SYS_I2C_SLAVE 0x02
-#define CONFIG_SYS_I2C_SLAVE1 0x02
-#define CONFIG_SYS_I2C_SLAVE2 0x02
-#define CONFIG_SYS_I2C_SLAVE3 0x02
-#ifndef __ASSEMBLY__
-/* Clock supplied to I2C controller in unit of MHz */
-unsigned int cm_get_l4_sp_clk_hz(void);
-#define IC_CLK (cm_get_l4_sp_clk_hz() / 100)
-#endif
-#endif /* CONFIG_DM_I2C */
-
/*
* QSPI support
*/
diff --git a/include/configs/socfpga_vining_fpga.h
b/include/configs/socfpga_vining_fpga.h
index 5517ed722d..0e547a1295 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -16,15 +16,6 @@
#define CONFIG_LOADADDR0x0100
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* I2C EEPROM */
-#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-#endif
-
/*
* Status LEDs:
* 0 ... Top Green
--
2.17.1
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[U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h
This series cleans up the include/configs/socfpga_common.h file a bit. It removes some defines that are used nowhere and cleans up some leftovers after various subsystems have been converted to use DM. Changes in v4: - fix DM_I2C case: don't call i2c_set_bus_num() since this is done in cmd/eeprom already Changes in v3: - changed commit message: s/defines/macros and comments/ Changes in v2: - added (this) patch to move socfpga_vining to DM_I2C - remove even more outdated things - added (this) patch with further cleanups to the socfpga board config files Simon Goldschmidt (4): arm: socfpga: move vining_fpga to DM_I2C arm: socfpga: clean up socfpga_common.h arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ arm: socfpga: clean up board config files board/samtec/vining_fpga/socfpga.c | 9 +--- configs/socfpga_vining_fpga_defconfig| 8 ++- include/configs/socfpga_arria10_socdk.h | 6 --- include/configs/socfpga_arria5_socdk.h | 2 - include/configs/socfpga_common.h | 68 include/configs/socfpga_cyclone5_socdk.h | 2 - include/configs/socfpga_de0_nano_soc.h | 2 - include/configs/socfpga_de10_nano.h | 2 - include/configs/socfpga_de1_soc.h| 2 - include/configs/socfpga_is1.h| 2 - include/configs/socfpga_sockit.h | 2 - include/configs/socfpga_socrates.h | 2 - include/configs/socfpga_sr1500.h | 11 include/configs/socfpga_vining_fpga.h| 18 --- 14 files changed, 8 insertions(+), 128 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/2] Revert "cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT"
This reverts commit 65a97e7fcf54feb7c4ebe1aee8a572830af4cf51.
The 'eeprom' command has been converted to work with DM_I2C in a patch
submitted around the same time as this commit:
commit 0c07a9b4078d ("eeprom: Add device model based I2C support to eeprom
command")
Signed-off-by: Simon Goldschmidt
Reviewed-by: Heiko Schocher
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- added patch to fix DM_I2C eeprom code to work without
CONFIG_SYS_I2C_EEPROM_BUS
cmd/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2bdbfcb3d0..87012670e0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -455,7 +455,6 @@ config CRC32_VERIFY
config CMD_EEPROM
bool "eeprom - EEPROM subsystem"
- depends on !DM_I2C || DM_I2C_COMPAT
help
(deprecated, needs conversion to driver model)
Provides commands to read and write EEPROM (Electrically Erasable
--
2.17.1
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