This does not need to be global across all functions in this file. Pass a
parameter instead.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Update bsp_do_flight_plan() to say 'on the BSP'
arch/x86/cpu/mp_init.c | 22
Add a way to run a function on a selection of CPUs. This supports either
a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel
terminology.
It works by writing into a mailbox and then waiting for the CPUs to notice
it, take action and indicate they are done.
When SMP is not yet
At present each CPU is given a number when it starts itself up. While this
saves a tiny amount of time by doing the device-tree read in parallel, it
is confusing that the numbering happens on the fly.
Move this code into mp_init() and do it at the start.
Signed-off-by: Simon Glass
Reviewed-by:
Fix a typo in the command help.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v1)
cmd/x86/mtrr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index 084d7315f4..5d25c5802a 100644
---
The functions used by the flight plan are declared in the header file but
are not used in any other file.
Move the flight plan steps down to just above where it is used so that we
can make these function static.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
At present the APs (non-boot CPUs) are inited once and then parked ready
for the OS to use them. However in some cases we want to send new requests
through, such as to change MTRRs and keep them consistent across CPUs.
Change the last state of the flight plan to go into a wait loop, accepting
It is convenient to iterate through the CPUs performing work on each one
and processing the result. Add a few iterator functions which handle this.
These can be used by any client code. It can call mp_run_on_cpus() on
each CPU that is returned, handling them one at a time.
Signed-off-by: Simon
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL.
For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot,
but this is somewhat more complicated. For now that is disabled too.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang
These parameters are named differently from elsewhere in this file. Switch
them to avoid confusion.
Also add comments to this function.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v2)
Changes in v2:
- Add comments to explain what
Allow keeping track of whether all CPUs have been enabled yet. This allows
us to know whether other CPUs need to be considered when updating
CPU-specific settings such as MTRRs on x86.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v3)
Changes in v3:
- Rename
Set this flag so we can track when it is safe to use CPUs other than the
main one.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Rename flag to GD_FLG_SMP_READY
arch/x86/cpu/mp_init.c | 1 +
1 file changed, 1
With the new MP features the CPUs are no-longer parked when the OS is run.
Fix this by calling a special function to park them, just before the OS is
started.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v3)
Changes in v3:
- Update the comment for
This function is misnamed since it does not actually init the BSP. Also
it is convenient to adjust it to return a little more information.
Rename and update the function, to allow it to return the BSP CPU device
and number, as well as the total number of CPUs.
Signed-off-by: Simon Glass
+Tom,
On Wed, Jul 8, 2020 at 10:23 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 29 Jun 2020 at 20:33, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass wrote:
> > >
> > > At present we can only read from a top-level binman node entry. Refactor
> > > this
Hello Yash,
Am 23.04.2020 um 13:27 schrieb Yash Shah:
DT documentation for PWM controller added from Linux v5.6
commit: daa78cc3408e
("pwm: sifive: Add DT documentation for SiFive PWM Controller")
Signed-off-by: Yash Shah
---
doc/device-tree-bindings/pwm/pwm-sifive.txt | 31
Hi Tom,
Please pull the rockchip updates:
- dts sync from kernel for rk3399 boards;
- Add Radxa Rock Pi N8, N10;
- Some feature update for Pinebook Pro;
Gitlab ci:
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip/pipelines/3907
Thanks,
- Kever
The following changes since commit
On Wed, Jul 08, 2020 at 10:12:38AM +0900, AKASHI Takahiro wrote:
> On Fri, Jul 03, 2020 at 01:00:21PM +0200, Heinrich Schuchardt wrote:
> > On 09.06.20 07:09, AKASHI Takahiro wrote:
> > > Since the size check against an entry in efi_search_siglist() is
> > > incorrect, this function will never
Hi Bin,
On Mon, 29 Jun 2020 at 23:58, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass wrote:
> >
> > Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
> > (NHLT).
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> >
Hi Bin,
On Tue, 30 Jun 2020 at 02:27, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass wrote:
> >
> > These registers need to be accesses from ACPI code, so move them to the
> > header file.
> >
>
> I don't think these are common offset to every platform.
That's
Hi Wolfgang,
On Thu, 2 Jul 2020 at 02:11, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> I dont know NHLT well enough to actually review the code, but I did compare
> the files in this patch to the version in coreboot. Most of the changes are
> obvious (coding style, spelling, ...), but some things
Hi Wolfgang,
On Wed, 1 Jul 2020 at 09:16, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
> > Betreff: [PATCH v1 37/43] x86: Store the coreboot table address in
> > global_data
> >
> > At present this information is used to locate and parse the tables but is
> > not
Hi Bin,
On Tue, 30 Jun 2020 at 01:47, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass wrote:
> >
> > Implement the method that converts a GPIO into the form used by ACPI, so
> > that GPIOs can be added to ACPI tables.
> >
> > Signed-off-by: Simon Glass
> > ---
>
On Mon, Jul 06, 2020 at 12:59:16PM +0200, Heinrich Schuchardt wrote:
> On 16.06.20 01:16, AKASHI Takahiro wrote:
> > More fixes against pylint warnings that autopep8 didn't handle
> > in the previous commit.
> >
> > Signed-off-by: AKASHI Takahiro
>
> This patch has to be rebased:
This patch
Hi Simon,
On Tue, Jul 7, 2020 at 3:58 PM Bin Meng wrote:
>
> On Tue, Jul 7, 2020 at 3:56 PM Bin Meng wrote:
> >
> > On Mon, Jul 6, 2020 at 10:16 AM Simon Glass wrote:
> > >
> > > These prevent use of compile-time checks such as:
> > >
> > > if (CONFIG_IS_ENABLED(DM_SPI))
> > >
> > > since,
Heinrich,
On Fri, Jul 03, 2020 at 12:56:55PM +0200, Heinrich Schuchardt wrote:
> On 09.06.20 07:09, AKASHI Takahiro wrote:
> > UEFI specification requires that we shall support three type of
> > certificates of authenticode in PE image:
> > WIN_CERT_TYPE_EFI_GUID with the guid,
On Thu, Jun 11, 2020 at 12:03:21PM +0100, Andre Przywara wrote:
> The ARM Juno boards (-r1 and -r2) feature a Silicon Image 3132 PCIe
> SATA controller soldered on the board, providing two SATA ports.
>
> Enable the driver and the sata command in the defconfig, to be able to
> load images from
Any comments or update on this series?
- Yash
> -Original Message-
> From: Yash Shah
> Sent: 23 April 2020 16:58
> To: martyn.we...@collabora.co.uk; h...@denx.de; u-boot@lists.denx.de;
> Sachin Ghadi
> Cc: Yash Shah
> Subject: [PATCH v2 0/2] Add support for PWM SiFive
>
> The patch
From: Heiko Stuebner
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and
Hi Wolfgang,
On Wed, 1 Jul 2020 at 09:15, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
>
> > Betreff: [PATCH v1 33/43] x86: irq: Support flags for acpi_gpe
> >
> > This binding currently has a flags cell but it is not used. Make use of it
> > to create ACPI tables
Hi Wolfgang,
On Thu, 25 Jun 2020 at 06:46, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
> > Betreff: [PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation
> >
> > Update the PCI driver to generate ACPI information so that Linux has the
> > full
Add a function to write a scope to the generated ACPI code.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Changes in v2:
- Rename parameter from 'name' to 'scope'
include/acpi/acpigen.h | 9 +
lib/acpi/acpigen.c | 7 +++
test/dm/acpi.c | 3 +--
This series is split off from the original ACPI series and renumbered to
version 1.
It includes functions for generating more ACPI constructs as well as I2C,
GPIO and sound support. There are also quite a few patches related to
getting coral to work correctly with ACPI.
Changes in v2:
- Rename
Add support for accessing an entry's contents in memory-mapped SPI flash.
Signed-off-by: Simon Glass
---
(no changes since v1)
include/binman.h | 22 ++
lib/binman.c | 23 +++
2 files changed, 45 insertions(+)
diff --git a/include/binman.h
In some cases an internal error may prevent this from working. Update the
function return value and report the error. At present the API for writing
tables does not easily support reporting errors, but once it is fully
updated to use a context pointer, this will be easier.
Signed-off-by: Simon
At present we can only read from a top-level binman node entry. Refactor
this function to produce a second local function which supports reading
from any node.
Signed-off-by: Simon Glass
---
Changes in v2:
- Rename binman_entry_find_()
lib/binman.c | 19 +--
1 file changed, 13
The start of an ACPI path typically has backslashes in it. These are not
preserved during the translation from device tree to C code, since dtc
(correctly) uses the first backslash as an escape character, and dtoc
therefore leaves it out of the C string.
Fix this with special-case handling.
Hi Bin,
On Tue, 30 Jun 2020 at 02:40, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass wrote:
> >
> > This function does not exist anymore. Drop it from the header file.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > arch/x86/include/asm/u-boot-x86.h | 2 --
>
Hi Bin,
On Tue, 30 Jun 2020 at 02:40, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass wrote:
> >
> > At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr'
> > command does not work correctly. It is not easy to make it work for all
> > CPUs, since
On x86 the SPI ROM can be memory-mapped, at least most of it. Add a way
to tell binman the offset from a ROM address to a RAM address.
Signed-off-by: Simon Glass
---
(no changes since v1)
Changes in v1:
- Add a way to set the binman ROM offset
include/binman.h | 8
lib/binman.c
Heinrich,
On Fri, Jul 03, 2020 at 01:08:55PM +0200, Heinrich Schuchardt wrote:
> On 09.06.20 07:09, AKASHI Takahiro wrote:
> > There are a couple of occurrences of hash calculations in which a new
> > efi_hash_regions will be commonly used.
>
> Please, describe the difference.
the difference of
On Thu, Jun 11, 2020 at 12:03:17PM +0100, Andre Przywara wrote:
> When compiled as a DM_ETH driver, the scm911x driver was reading the MAC
> address from the optional EEPROM storage, but failed to copy this to the
> platdata struct. Since it was also missing a definition of the
>
On Thu, Jun 11, 2020 at 12:03:16PM +0100, Andre Przywara wrote:
> Similar to patch 821fec0ceb3e ("net: remove scary warning about EEPROM
> provided MAC address") this removes the somewhat awkward "warning" on
> boards using DM_ETH:
> In many parts of the computing world having a unique MAC
On Thu, Jun 11, 2020 at 12:03:18PM +0100, Andre Przywara wrote:
> The smc911X driver is now DM enabled, so we can switch the Juno board
> over to use DM_ETH for the on-board Fast Ethernet device.
> Works out of the box by using the DT.
>
> Signed-off-by: Andre Przywara
> Reviewed-by: Linus
On Wed, May 27, 2020 at 08:04:22PM +0200, Heinrich Schuchardt wrote:
> On ARM systems gd is stored in register r9 or x18. When compiling with
> clang gd is defined as a macro calling function gd_ptr(). So we can not
> make assignments to gd.
>
> Use function set_gd() for setting the register on
On Thu, Jun 11, 2020 at 12:03:20PM +0100, Andre Przywara wrote:
> The ARM Juno boards in their -r1 and -r2 variants sport a PCIe
> controller, which we configure already in board specific code to be ECAM
> compliant. Hence we can just enable the generic ECAM driver to let
> U-Boot use PCIe
On Thu, Jun 11, 2020 at 12:03:19PM +0100, Andre Przywara wrote:
> Even though the sata_sil driver was converted over to the driver model,
> it still assumed that the PCI controller is using the legacy interface.
>
> Allow the "devno" member to be a struct udevice pointer and use
> DM_PCI_COMPAT
On Thu, Jun 11, 2020 at 12:03:15PM +0100, Andre Przywara wrote:
> The arch timer on 64-bit Arm Ltd. platforms is driven by a 24 MHz
> crystal oscillator, so the frequency is not 25165824 MHz, as the current
> code suggests.
>
> Signed-off-by: Andre Przywara
> Reviewed-by: Linus Walleij
On Wed, May 27, 2020 at 08:04:24PM +0200, Heinrich Schuchardt wrote:
> Compiling with clang on ARMv8 shows errors like:
>
> ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w"
> asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
>
On Wed, May 27, 2020 at 08:04:23PM +0200, Heinrich Schuchardt wrote:
> Clang 9 supports -ffixed-x18.
>
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Thu, Jun 04, 2020 at 05:24:00PM +0200, Heiko Schocher wrote:
> make the sleep time and the margin configurable.
>
> Signed-off-by: Heiko Schocher
> Reviewed-by: Simon Glass
> Reviewed-by: Stephen Warren
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
The comment here applies only to FSP1, so update it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
arch/x86/cpu/start.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index
This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.
Signed-off-by: Simon Glass
---
Changes in v2:
- Don't enable this for qemu
arch/Kconfig | 1 +
drivers/core/Kconfig | 2 +-
2 files changed, 2 insertions(+),
Currently U-Boot implements version 2 but reports version 4. Correct it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes in v2:
- Use ACPI_MADT_REV_ACPI_3_0 instead of the open-coded value
arch/x86/lib/acpi_table.c | 2 +-
1 file changed, 1
This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.
Rename it to reduce confusion.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
arch/x86/cpu/coreboot/coreboot.c
This function does not exist anymore. Drop it from the header file.
Signed-off-by: Simon Glass
---
Changes in v2:
- Remove the function from zimage.c also
arch/x86/include/asm/u-boot-x86.h | 2 --
arch/x86/lib/zimage.c | 10 --
2 files changed, 12 deletions(-)
diff --git
At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr'
command does not work correctly. It is not easy to make it work for all
CPUs, since coreboot has halted them and we would need to start them up
again, but it is easy enough to make them work on the boot CPU.
Update the code
Hello Alex, Arthur,
Am 06.07.2020 um 11:22 schrieb Heiko Schocher:
Hello Alex, Arthur,
Am 01.06.2020 um 21:56 schrieb Alex Nemirovsky:
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
On Fri, Jul 03, 2020 at 01:00:21PM +0200, Heinrich Schuchardt wrote:
> On 09.06.20 07:09, AKASHI Takahiro wrote:
> > Since the size check against an entry in efi_search_siglist() is
> > incorrect, this function will never find out a to-be-matched certificate
> > and its associated revocation time
Update the mtrr command to use mp_run_on_cpus() to obtain its information.
Since the selected CPU is the boot CPU this does not change the result,
but it sets the stage for supporting other CPUs.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes
This currently excludes the temporary memory used to start up the APs.
Add it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v2)
Changes in v2:
- Add new patch to add AP_DEFAULT_BASE to coral's memory map
When the boot CPU MTRRs are updated, perform the same update on all other
CPUs so they are kept in sync.
This avoids kernel warnings about mismatched MTRRs.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v2)
Changes in v2:
- Rename function to mtrr_write_all()
At present do_mtrr() does the 'list' subcommand at the top and the rest
below. Update it to do them all in the same place so we can (in a later
patch) add parsing of the CPU number for all subcommands.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no
Use the multi-CPU calls to set the MTRR values. This still supports only
the boot CPU for now.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- Drop the renamed mtrr_set_valid_() instead of mtrr_set_valid()
Add a description of how this module works and also some missing function
comments.
Reviewed-by: Wolfgang Wallner
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Remove stray asterisk from comments
- Drop mention of cpu_map which was handled in a
Add a -c option to mtrr to allow any CPU to be updated with this command.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- Mention that the CPU number is in hex
cmd/x86/mtrr.c | 18 --
1 file changed,
Update this command so it can list the MTRRs on a selected CPU. If
'-c all' is used, then all CPUs are listed.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
cmd/x86/mtrr.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff
To enable support for the 'mtrr' command, add a way to perform MTRR
operations on selected CPUs.
This works by setting up a little 'operation' structure and sending it
around the CPUs for action.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes
Drop some #ifdefs that are not needed or can be converted to compile-time
checks.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
Reviewed-by: Bin Meng
---
(no changes since v1)
arch/x86/cpu/cpu.c | 58 -
arch/x86/cpu/i386/cpu.c | 2 --
I am wondering if anyone has a copy of the PPC440EPx evaluation board
(Sequoia) schematic that was made by AMCC. The information is no longer
easily available as the amcc.com and apm.com sites are no longer running
and the schematic is not archived on the wayback machine. I figured that
U-Boot
Hi Bin,
On Mon, 6 Jul 2020 at 18:22, Bin Meng wrote:
>
> Hi Simon,
>
> On Tue, Jul 7, 2020 at 3:22 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Thu, 2 Jul 2020 at 22:33, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass wrote:
> > > >
> > > > Hi
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.
Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the
Allow writing out a generic register.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
include/acpi/acpi_device.h | 1 +
include/acpi/acpigen.h | 28 +++
lib/acpi/acpigen.c | 71
Write required information into the SSDT to describe the SD card
card-detect pin. Since the required GPIO properties are not present in
the device-tree binding, set them manually for now.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
Changes in v1:
-
This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).
Signed-off-by: Simon Glass
---
Changes in v2:
Add a comment about only x86 boards supporting NHLT
Changes in v1:
At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by:
Add information about what is returned on error.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/include/asm/intel_pinctrl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/intel_pinctrl.h
b/arch/x86/include/asm/intel_pinctrl.h
index
This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).
Signed-off-by: Simon Glass
---
Changes in v2:
Add a comment about only x86 boards supporting NHLT
Changes in v1:
Some devices such as GPIO need to override the normal path that would be
generated by driver model. Add a device-tree property for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
doc/device-tree-bindings/device.txt | 23
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.
Add core support for this, based on a structure which is built up through
calls to the driver.
Signed-off-by: Simon
At present only acpigen_write_integer() is exported for use by other code.
But in some cases it is useful to call the specific function depending on
the size of the value.
Export these functions and add a test.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
Add a Kconfig to control whether pinctrl is represented as a single ACPI
device or as multiple devices. In the latter case (the default) we should
return the pin number relative to the pinctrl device.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes
Allow writing an ACPI device to the generated ACPI code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
include/acpi/acpigen.h | 9 +
lib/acpi/acpigen.c | 7 +++
test/dm/acpigen.c | 27
Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
(NHLT).
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Changes in v2:
- Add a comment pointing to the PCI spec
include/dt-bindings/sound/nhlt.h | 24
1 file changed, 24
Allow writing named integers and strings to the generated ACPI code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
include/acpi/acpigen.h | 72 ++
lib/acpi/acpigen.c | 49
Hi Simon,
On 2020/6/14 上午10:57, Simon Glass wrote:
+ optee {
+ description = "OP-TEE";
+ type = "firmware";
+ arch = "arm";
+
Hi Bin,
On Tue, 7 Jul 2020 at 02:26, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jul 6, 2020 at 11:37 AM Simon Glass wrote:
> >
> > With the new MP features the CPUs are no-longer parked when the OS is run.
> > Fix this by calling a special function to park them, just before the OS is
> >
On Sat, May 09, 2020 at 07:55:09PM +0530, Amit Singh Tomar wrote:
> This commit adds clocks needed for ethernet operations for
> Actions OWL family of SoCs (S700 and S900).
>
> Signed-off-by: Amit Singh Tomar
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sat, Apr 25, 2020 at 07:37:21PM +0200, Robert Marko wrote:
> This patch adds support for ZSTD decompression of FIT images.
>
> Signed-off-by: Robert Marko
> Cc: Luka Perkov
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sat, May 09, 2020 at 01:45:08PM +0530, Amit Singh Tomar wrote:
> Now that, we calculate SDRAM size by reading DDR registers,
> "CONFIG_SYS_SDRAM_SIZE" is no more needed.
>
> This commit removes "CONFIG_SYS_SDRAM_SIZE" from common configuration
> file.
>
> Signed-off-by: Amit Singh Tomar
>
On Mon, Mar 30, 2020 at 05:22:58PM +0200, Niel Fourie wrote:
> Add a command to print a list of available block device drivers,
> and for each, the list of known block devices.
>
> Signed-off-by: Niel Fourie
> Cc: Simon Glass
> Cc: Stefan Roese
> Reviewed-by: Simon Glass
> Reviewed-by:
On Sat, May 09, 2020 at 01:45:07PM +0530, Amit Singh Tomar wrote:
> Calculate the SDRAM size from DDR capacity register registers instead
> of using hard-coded value. This is quite useful to get correct size
> on differnt boards based on Actions OWL family of SoCs (S700 and S900).
>
> There is
On Tue, Mar 24, 2020 at 04:17:05PM +0100, Niel Fourie wrote:
> Renamed dm "drivers" subcommand to "compat" (as it listed
> compatibility strings) and prevent it from segfaulting when
> drivers have no of_match populated.
>
> Added a new "drivers" subcommand to dump a list of all known DM
>
On Tue, Mar 24, 2020 at 04:17:04PM +0100, Niel Fourie wrote:
> Added command "fstypes" to list supported/included filesystems.
>
> Signed-off-by: Niel Fourie
> Cc: Simon Glass
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Tue, Mar 24, 2020 at 04:17:03PM +0100, Niel Fourie wrote:
> Add a subcommand "types" to the part command, which lists the supported
> partition table types.
>
> Signed-off-by: Niel Fourie
> Cc: Simon Glass
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
This confuses Linux's PCI probing so needs to be hidden when booting
Linux. Add a remove() method to handle this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
Tested-by: Wolfgang Wallner
---
(no changes since v1)
arch/x86/cpu/intel_common/p2sb.c | 13
These registers need to be accesses from ACPI code, so move them to the
header file.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
drivers/power/acpi_pmc/acpi-pmc-uclass.c | 9 -
include/power/acpi_pmc.h | 14 ++
2
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.
Fix this by
Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v2:
- Add a few blank lines
- Drop dead code behind if (0)
Changes in v1:
- Capitalise ACPI_OPS_PTR
This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
(no changes since v1)
arch/x86/cpu/acpi_gpe.c | 26 +++
Add debugging for a few more values and also use log to show return values
when something goes wrong. This makes it easier to see the root cause.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
Reviewed-by: Heiko Schocher
---
(no changes since v1)
Changes in
1 - 100 of 329 matches
Mail list logo
