Will do, thanks!
Chen-Yu Tsai 于2021年2月8日周一 下午2:50写道：
> Hi,
>
> On Mon, Feb 8, 2021 at 9:46 AM alex tian wrote:
> >
> > From 01598339be9dbeec6ba41c470b29af1c53e29c40 Mon Sep 17 00:00:00 2001
> > From: Xiaobo Tian
> > Date: Mon, 8 Feb 2021 09:40:03 +0800
> > Subject: [PATCH] arm64: rk3399: Add
From: Xiaobo Tian
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card
support,
including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0
port.
port.It also has two GPIO headers which
From: Xiaobo Tian
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card
support,
including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0
port.
port.It also has two GPIO headers which
From: Xiaobo Tian
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card
support,
including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0
port.
port.It also has two GPIO headers which
On 27.01.21 17:12, Pali Rohár wrote:
From: Konstantin Porotchkin
While the SPI controller speed is defined by DTS, the maximum
slave speed (connected devices) is limited by the pre-defined
configuration value CONFIG_SF_DEFAULT_SPEED to 1MHz
This patch increases this maximum SPI slave device
On 04.02.21 17:38, Marek Behún wrote:
On Thu, 4 Feb 2021 07:18:23 +0900
Jaehoon Chung wrote:
Commit da18c62b6e6a causes the regression. The Fixes tag, as I
understand, should link to commit with which the regression first
occured, so that if someone wanted to backport my patch to previous
Dear Tom,
Please find my pull-request for u-boot-fsl-qoriq/master
https://github.com/u-boot/u-boot/pull/52/checks
Summary
Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2
On 2/8/21 6:57 AM, Samuel Holland wrote:
Resetting an XHCI controller inside xhci_register undoes any register
setup performed by the platform driver. And at least on the Allwinner
H6, resetting the XHCI controller also resets the PHY, which prevents
the controller from working. That means the
On 25.01.21 15:27, Stefan Roese wrote:
Testing has shown, that the quality of the PCIe signals and also the
stability of correct link establishment on the 2 PCIe ports is better,
when the deemphasis bit is set in the PCIe config register.
This needs to be done very early, even before the SERDES
add support for the UUU commands ACmd and UCmd.
Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT
base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")
and ported it to current mainline. Tested this patch
on imx6ul based board.
On 25.01.21 15:27, Stefan Roese wrote:
This patch changes the board specific "pcie" U-Boot command to not only
check for PCIe device existance but also for the correct link speed
and width that has been established. This cmd can be used by U-Boot
scripts for automated testing, if the PCIe setup
On 27.01.21 11:56, Pali Rohár wrote:
Default options depends on compile time defines.
Signed-off-by: Pali Rohár
Applied to u-boot-marvell/master
Thanks,
Stefan
On Sun, Feb 07, 2021 at 07:37:55AM -0700, Simon Glass wrote:
> On Fri, 5 Feb 2021 at 13:46, Andy Shevchenko
> wrote:
> > On Fri, Feb 05, 2021 at 09:17:27PM +0200, Andy Shevchenko wrote:
> > > On Fri, Feb 05, 2021 at 08:15:25PM +0200, Andy Shevchenko wrote:
> > > > On Fri, Feb 05, 2021 at
On 02.02.21 07:43, Baruch Siach wrote:
Call mmc_of_parse() so that generic DT properties like 'non-removable'
are taken into account.
This fixes boot on Clearfog with eMMC on SOM that requires the
non-removable property.
Reported-by: Thorsten Spille
Signed-off-by: Baruch Siach
Applied to
On 25.01.21 15:25, Stefan Roese wrote:
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
and testing it with the DM PCI driver I noticed, that the PCI root
On Thu, 4 Feb 2021 21:22:03 -0700
Simon Glass wrote:
> It is convenient to be able to adjust some of the flags for a GPIO while
> leaving others alone. Add a function for this.
>
> Update dm_gpio_set_dir_flags() to make use of this.
>
> Also update dm_gpio_set_value() to use this also, since
From: Stephen Carlson
This patch adds support for more PMBus compatible devices to the NXP
drivers for its QorIQ family devices. At runtime, the voltage regulator is
queried over I2C, and the required voltage multiplier determined. This
change supports the DIRECT and LINEAR PMBus voltage
On 23.12.20 12:21, Pali Rohár wrote:
This patch series set default env values of $fdtfile and $ethNaddr for
Espressobin board at runtime.
It fixes two main issues on Espressobin board that 'env default -a'
completely erases permanent board MAC addresses and also erase $fdtfile
variable which is
Hi Tom,
please pull the 2nd batch of Marvell MVEBU related patches. Here the
summary log:
- Espressobin: Set default env values at runtime (Pali)
- Espressobin: Set the maximum slave SPI speed to 40MHz (Pali)
- theadorable: PCIe
Hi Marek,
Hi Bin,
On 15.01.21 08:52, Stefan Roese wrote:
Testing with v2021.01 on MIPS Octeon has shown, that the latest patch
for the "short packet event trb handling" did introduce a bug on
platforms with virtual address != physical address. This patch fixes
this issue by using the correct
The ESRT is initialised during efi_init_objlist after
efi_initialize_system_table().
The ESRT is initially created with size for 50 FW image entries.
The ESRT is resized when it runs out of space. Every resize adds 50
additional entries.
The ESRT is populated from information provided by FMP
The following 2 commits add the ESRT and provide a test of the
functionality.
The first commit adds the ESRT as defined in the UEFI 2.8 specification.
An empty ESRT is created during the execution of the efi_init_obj_list().
The ESRT is updated when:
1) a FMP protocol is installed in the
This commit exercises the ESRT creation -- introduced in the previous
commit.
A fake FMP, controlling TEST_ESRT_NUM_ENTRIES, is installed in the system
leading to the corresponding ESRT entries being populated.
The ESRT entries are checked against the FMP initialization input
datastructure.
Hi Simon
on tipo in title:
s/doumentation/documentation/
On 1/7/21 5:21 AM, Simon Glass wrote:
There are quite a few available version options in U-Boot. Add a list of
the available Makefile variables and #defines, along with examples.
Signed-off-by: Simon Glass
---
README | 84
On Mon, Feb 8, 2021 at 1:27 PM Roger Pau Monné wrote:
>
> Hello,
>
> I'm trying to build an u-boot image that I can flash into my SD card
> in order to boot from Odroid Go Super. I'm currently trying to use the
> odroid-go2_defconfig which should be fairly similar to the hardware
> present in the
Hello Stefan!
On Monday 08 February 2021 15:19:20 Stefan Roese wrote:
> On 08.02.21 15:00, Marek Behun wrote:
> >I would like to know why this memory controller is there and whether
> >it should be configured. The pci-mvebu driver in kernel currently
> >ignores this Memory Controller.
The optee_copy_fdt_nodes is only used to copy op-tee nodes
of U-Boot device tree (from gd->fdt_blob when OF_LIVE is not activated)
to external device tree but it is not compatible with OF_LIVE.
This patch migrates all used function fdt_ functions to read node on
old_blob to ofnode functions,
Hi Bin,
On Sun, 7 Feb 2021 at 22:17, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Feb 8, 2021 at 12:21 PM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Sun, 7 Feb 2021 at 08:11, Bin Meng wrote:
> > >
> > > At present fdt_read_prop() can only handle 1 or 2 cells. It is
> > > called by
Hi Bin,
On Sun, 7 Feb 2021 at 22:12, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Feb 8, 2021 at 12:20 PM Simon Glass wrote:
> >
> > On Sun, 7 Feb 2021 at 08:12, Bin Meng wrote:
> > >
> > > This adds a new command 'addrmap' to display the address map for
> > > non-identity virtual-physical memory
On 2/8/21 1:39 PM, Stefan Roese wrote:
Hi Marek,
Hi Bin,
On 15.01.21 08:52, Stefan Roese wrote:
Testing with v2021.01 on MIPS Octeon has shown, that the latest patch
for the "short packet event trb handling" did introduce a bug on
platforms with virtual address != physical address. This patch
On Sun, 7 Feb 2021 14:13:37 -0500
Tom Rini wrote:
Hi Tom, Marek,
> On Sun, Feb 07, 2021 at 07:20:14PM +0100, Marek Vasut wrote:
> > On 2/4/21 5:57 PM, Tom Rini wrote:
> > [...]
> >
> > > > > > > > > > +static void nvme_flush_dcache_range(void *start, unsigned
> > > > > > > > > > long size)
At the moment nvme_read_completion_status() tries to invidate a single
member of the cqes[] array, which is shady as just a single entry is
not cache line aligned.
The structure is dictated by hardware, and with 16 bytes is smaller than
any cache line we usually deal with. Also multiple entries
Hi Simon,
On 1/7/21 5:21 AM, Simon Glass wrote:
For SMBIOS we want to store the numeric version numbers in the tables. It
does not make sense to parse the strings. Instead, add new #defines with
the version and patchlevel.
Signed-off-by: Simon Glass
---
Makefile | 4
README | 8
Hi Marek,
On 08.02.21 15:00, Marek Behun wrote:
On Mon, 25 Jan 2021 15:25:31 +0100
Stefan Roese wrote:
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
Hello Igor,
On 05.02.21 16:10, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> At present if U-Boot proper uses driver model for I2C, then SPL has to
> also. While this is desirable, it places a significant barrier to moving
> to driver model in some cases. For example, with a space-constrained
Hello,
I'm trying to build an u-boot image that I can flash into my SD card
in order to boot from Odroid Go Super. I'm currently trying to use the
odroid-go2_defconfig which should be fairly similar to the hardware
present in the Go3.
I've managed to build it from 2021.01, but I'm not sure how I
My first patch so be not too hard ...
Patch to give imx8mp the chance to operate SPI and EQOS.
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -116,6 +116,29 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
Add "flags" in lmb_property to save the "no-map" property of
reserved region and a new function lmb_reserve_flags() to check
this flag.
The default allocation use flags = LMB_NONE.
The adjacent reserved memory region are merged only when they have
the same flags value.
This patch is partially
Hello Igor,
On 05.02.21 16:10, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Use CONFIG_IS_ENABLED() macro, which provides more convenient
> way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs
> for both SPL and U-Boot proper.
>
> CONFIG_IS_ENABLED(DM_I2C) expands to:
> - 1 if CONFIG_SPL_BUILD
Add basic driver support for the IMX General Purpose Timer (GPT) available
on almost all i.MX SoCs family.
Giulio Benetti (3):
timer: imx-gpt: Add timer support for i.MX SoCs family
dt-bindings: clock: imxrt1050: add PIT GPT clock
imxrt1050 dtsi gpt1 node
Jesse Taube (1):
timer: imx-gpt:
On Mon, 25 Jan 2021 15:25:31 +0100
Stefan Roese wrote:
> This patch changes the PCI config routines in the Armada XP / 38x driver
> to not allow access to the PCIe root ports.
>
> While updating the Armada XP based theadorable to the latest mainline
> and testing it with the DM PCI driver I
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
This patch fixes an issue where predictive read access on secure DDR
OP-TEE reserved area are caught by firewall.
Signed-off-by: Patrick Delaunay
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
This patch fixes potential issue when predictive access is done by ARM
core.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
Add lmb_dump_region() function, to simplify lmb_dump_all_force().
This patch is based on Linux memblock dump function.
An example of bdinfo output is:
.
fdt_size= 0x000146a0
FB base = 0xfdd0
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0xc000-0x], 0x4000
Add a test to check the management of reserved region with flags.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
test/lib/lmb.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/test/lib/lmb.c
Add a new function lmb_is_reserved_flags to check is a
address is reserved with a specific flags.
This function can be used to check if an address had be
reserved with no-map flags with:
lmb_is_reserved_flags(lmb, addr, LMB_NOMAP);
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick
Save the no-map information present in 'reserved-memory' node to allow
correct handling when the MMU is configured in board to avoid
speculative access.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
common/image-fdt.c | 23 +++
Hi,
It it the v2 serie of [1].
This v2 serie is build/can be applied on top of 2 previous series
- [2] for stm32mp parts and added dram_bank_mmu_setup
- [3] for LMB impacts
After V1 remarks, I propose this separate serie [2] for DACR support.
On STM32MP15x platform we can use OP-TEE, loaded
Maybe we should ask kernel people. It seems that Thomas Petazzoni may
be able to answer, since he is author of the following kernel patch:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f4ac99011e542d06ea2bda10063502583c6d7991
On Mon, Feb 08, 2021 at 10:07:55AM -0700, Simon Glass wrote:
> On Mon, 8 Feb 2021 at 04:34, Andy Shevchenko
> wrote:
> > On Sun, Feb 07, 2021 at 07:37:55AM -0700, Simon Glass wrote:
> > > On Fri, 5 Feb 2021 at 13:46, Andy Shevchenko
> > > wrote:
> > > > On Fri, Feb 05, 2021 at 09:17:27PM +0200,
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.
The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.
Signed-off-by: motib
Reviewed-by: Alex Leibovich
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
Hi Simon,
2 minor remarks,
On 2/5/21 5:22 AM, Simon Glass wrote:
It is convenient to be able to adjust some of the flags for a GPIO while
leaving others alone. Add a function for this.
Update dm_gpio_set_dir_flags() to make use of this.
Also update dm_gpio_set_value() to use this also, since
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.
- function mv_ddr_spd_die_capacity_user_get() has a bug,
since it insert a user memory enum to it,
instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.
WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
drivers/ddr/marvell/a38x/mv_ddr_topology.c | 3 ++-
2 files changed, 4
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.
the twin-die combined memory device should be treatened as X8
device and not as X16 one
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
The default value for twin_die_combined is set to NOT_COMBINED for all
boards, as this
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.
Import this change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/ddr3_training.c
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.
The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.
@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.
Signed-off-by: Marek Behún
---
On Mon, 8 Feb 2021 16:49:58 +0100
Marek Vasut wrote:
Hi,
> On 2/8/21 2:32 PM, Andre Przywara wrote:
> [...]
> >>> +static void nvme_flush_dcache_range(void *start, unsigned long
> >>> size)
> >>> +{
> >>> + unsigned long s, e;
> >>> +
On Mon, 8 Feb 2021 17:24:16 +0100
Stefan Roese wrote:
> Hi Marek,
>
> On 08.02.21 17:04, Marek Behún wrote:
> > This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> > of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
> > Specifically this syncs with commit
On Sun, 7 Feb 2021 at 23:03, Samuel Holland wrote:
>
> binman can fill in the default FIT configuration index as selected by
> the "default-dt" argument, which is set to CONFIG_DEFAULT_DEVICE_TREE.
> Let's respect the user's configuration by taking advantage of this
> feature, instead of always
HI Marek,
On Mon, 8 Feb 2021 at 09:10, Marek Szyprowski wrote:
>
> Hi Simon,
>
> On 06.02.2021 17:21, Simon Glass wrote:
> > On Thu, 4 Feb 2021 at 03:36, Marek Szyprowski
> > wrote:
> >> ...
> >> Could you give me a bit more hints or point where to start? I've tried
> >> to build sandbox, but
Hi Jorge,
On Sun, 7 Feb 2021 at 11:11, Jorge Ramirez-Ortiz, Foundries
wrote:
>
> On 07/02/21, Simon Glass wrote:
> > Hi Jorge,
> >
> > On Sat, 6 Feb 2021 at 16:05, Jorge Ramirez-Ortiz wrote:
> > >
> > > Enable and provision the SCP03 keys on a TEE controlled secured elemt
> > > from the U-Boot
On Sun, 7 Feb 2021 at 23:03, Samuel Holland wrote:
>
> The FIT description has access to the configuration variables. Use the
> appropriate variable instead of hardcoding the address.
>
> Signed-off-by: Samuel Holland
> ---
> arch/arm/dts/sunxi-u-boot.dtsi | 2 +-
> 1 file changed, 1
Hi,
thanks for the info, I'll have a look at this.
Regards
Stefan
On 04.02.21 03:24, Tom Rini wrote:
This platform did not ever enable CONFIG_REVISION_TAG, so the code to
set the board_rev environment variable was never enabled. This
particular symbol is also only for use with the REVISION
On 2/8/21 6:08 PM, Simon Glass wrote:
HI Marek,
On Mon, 8 Feb 2021 at 09:10, Marek Szyprowski wrote:
Hi Simon,
On 06.02.2021 17:21, Simon Glass wrote:
On Thu, 4 Feb 2021 at 03:36, Marek Szyprowski wrote:
...
Could you give me a bit more hints or point where to start? I've tried
to build
Hi Simon,
On 2/5/21 5:22 AM, Simon Glass wrote:
Using the internal vs. external pull resistors it is possible to get
27 different combinations from 3 strapping pins. Add an implementation
of this.
This involves updating the sandbox GPIO driver to model external and
(weaker) internal pull
This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There are some commits regarding DDR3 on top of version 14.0.0 in the
mv-ddr-marvell repository (from Chris Packham), but these changes
already are in U-Boot.
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich
Reviewed-by: Nadav Haklai
Reviewed-by: Kostya Porotchkin
Signed-off-by:
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.
- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern
exist at the memory
then the algorithm will fail, since it
commit a165037ec26f301be75e1fabc263643683e85255 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
On 2/8/21 4:11 PM, Bin Meng wrote:
[...]
As I said: I don't see how this patch changes anything on arm64, which
the commit messages claims to be the reason for this post.
If someone please can confirm, but invalidate_dcache_range() always
works on arm64, in fact does the very rounding already
Hi Heinrich,
On Mon, 8 Feb 2021 at 00:25, Heinrich Schuchardt wrote:
>
> On 2/8/21 5:05 AM, Simon Glass wrote:
> > Tests are supposed to be independent. With driver model tests, the
> > environment is reset before each test, which ensures that.
> >
> > With Python tests there is no reset of the
Hi Patrick,
On Mon, 8 Feb 2021 at 06:52, Patrick DELAUNAY
wrote:
>
> Hi Simon
>
> on tipo in title:
>
> s/doumentation/documentation/
>
> On 1/7/21 5:21 AM, Simon Glass wrote:
> > There are quite a few available version options in U-Boot. Add a list of
> > the available Makefile variables and
Hi Andy,
On Mon, 8 Feb 2021 at 04:34, Andy Shevchenko
wrote:
>
> On Sun, Feb 07, 2021 at 07:37:55AM -0700, Simon Glass wrote:
> > On Fri, 5 Feb 2021 at 13:46, Andy Shevchenko
> > wrote:
> > > On Fri, Feb 05, 2021 at 09:17:27PM +0200, Andy Shevchenko wrote:
> > > > On Fri, Feb 05, 2021 at
On 2/8/21 2:32 PM, Andre Przywara wrote:
[...]
+static void nvme_flush_dcache_range(void *start, unsigned long size)
+{
+ unsigned long s, e;
+ nvme_align_dcache_range(start, size, , );
+ flush_dcache_range(s, e);
There is no good reason for alignment restrictions when it
On Mon, Feb 08, 2021 at 01:55:26PM +, Peter Robinson wrote:
> On Mon, Feb 8, 2021 at 1:27 PM Roger Pau Monné wrote:
> >
> > Hello,
> >
> > I'm trying to build an u-boot image that I can flash into my SD card
> > in order to boot from Odroid Go Super. I'm currently trying to use the
> >
This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit fae3f6c98230 ("Bump mv_ddr to
release 14.0.0").
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0,
Hi Simon,
On 06.02.2021 17:21, Simon Glass wrote:
> On Thu, 4 Feb 2021 at 03:36, Marek Szyprowski
> wrote:
>> ...
>> Could you give me a bit more hints or point where to start? I've tried
>> to build sandbox, but it fails for v2021.01 release (I've did make
>> sandbox_defconfig && make all). I
Hi Marek,
On 08.02.21 17:04, Marek Behún wrote:
This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit fae3f6c98230 ("Bump mv_ddr to
release 14.0.0").
There is a new version
Hi Heiko,
On 2/8/21 12:38 PM, Heiko Schocher wrote:
add support for the UUU commands ACmd and UCmd.
Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT
base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")
and ported it to
Hi Igor,
On 1/24/21 10:39 AM, Igor Opaniuk wrote:
From: Igor Opaniuk
Add support for rpmb-dev property in optee node.
Prioritize that provided eMMC info from DT for RPMB operations over
the one provided by OP-TEE OS core in RPC calls.
Signed-off-by: Igor Opaniuk
---
Changes in v2:
- Return
Hi Andre,
On Mon, Feb 8, 2021 at 9:33 PM Andre Przywara wrote:
>
> On Sun, 7 Feb 2021 14:13:37 -0500
> Tom Rini wrote:
>
> Hi Tom, Marek,
>
> > On Sun, Feb 07, 2021 at 07:20:14PM +0100, Marek Vasut wrote:
> > > On 2/4/21 5:57 PM, Tom Rini wrote:
> > > [...]
> > >
> > > > > > > > > > > +static
Hi Tom,
On 2/4/21 3:24 AM, Tom Rini wrote:
These platforms never had to support an ATAGs-based Linux Kernel, so
remove the options.
Cc: Kamil Lulko
Cc: Patrick Delaunay
Cc: Patrice Chotard
Cc: Vikas Manocha
Cc: Marek Vasut
Signed-off-by: Tom Rini
---
I'm assuming, please correct me if
Hi
I was not able to read the last block of my sd card
(the gpt backup block) without the following
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index d0aad0252a..ea9d763072 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -147,7 +147,7 @@ static
btw tested on Turris Omnia
This patch is needed on some Turris Omnia boards with Samsung DDR chips,
otherwise DDR training fails in ~60% of cases.
Marvell send us this patch for testing, I have updated it a little.
Please test this on other A38x boards.
If it doesn't break anything on other boards, we can apply it and
Hi Marek,
On 9/02/21 7:34 am, Marek Behún wrote:
> This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
>
> There are some commits regarding DDR3 on top of version 14.0.0 in the
> mv-ddr-marvell repository (from
On Mon, 8 Feb 2021 20:14:26 +
Chris Packham wrote:
> On 9/02/21 8:15 am, Marek Behun wrote:
> > This patch is needed on some Turris Omnia boards with Samsung DDR chips,
> > otherwise DDR training fails in ~60% of cases.
> >
> > Marvell send us this patch for testing, I have updated it a
On Mon, 8 Feb 2021 20:11:06 +
Chris Packham wrote:
> Hi Marek,
>
> Do you have this in a repo I can pull from? I've got a couple of boards
> I can give this a spin on.
https://gitlab.nic.cz/turris/turris-omnia-uboot/
branch v2021.04-rc-mv-ddr-14.0.0
also please test branch
On 08/02/21, Simon Glass wrote:
> Hi Jorge,
>
> On Sun, 7 Feb 2021 at 11:11, Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
> > On 07/02/21, Simon Glass wrote:
> > > Hi Jorge,
> > >
> > > On Sat, 6 Feb 2021 at 16:05, Jorge Ramirez-Ortiz
> > > wrote:
> > > >
> > > > Enable and provision the SCP03
From: motib
In each pattern cycle the bus state can be changed.
In order to avoid it, we need to switch back to the same bus state on
each pattern cycle.
Signed-off-by: motib
Fixed code style, removed commented code, switched to use DEBUG macros
instead of printf.
Signed-off-by: Marek Behún
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