Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
From: Dirk Eibach dirk.eib...@gdsys.cc
Changes in v6:
- Add CONFIG_PCI_INDIRECT_BRIDGE to controlcenterd.h
- Add MAINTAINERS entry
- drop mpc85xx: Add CONFIG_RELEASE_CORE0_ONLY and use mp_holdoff instead
- rename CONFIG_ATMEL_TWI_TPM to CONFIG_TPM_ATMEL_TWI
- rename drivers/tpm/atmel_twi_tpm.c
From: Dirk Eibach eib...@gdsys.de
Add support for Atmel TPM devices with two wire interface.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6:
- rename CONFIG_ATMEL_TWI_TPM to
From: Reinhard Pfau p...@gdsys.de
Extend the tpm library with support for single authorized (AUTH1) commands
as specified in the TCG Main Specification 1.2. (The internally used helper
functions are implemented in a way that they could also be used for double
authorized commands if someone needs
From: Dirk Eibach eib...@gdsys.de
MAKEALL is fine for ppc4xx and mpc85xx.
Run checks were done on our controlcenterd hardware.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- consider
From: Reinhard Pfau p...@gdsys.de
if alen is 0: no longer start a write cycle before reading data.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6: None
Changes in v5:
- fix
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
Dear Tom Rini,
On Mon, Jun 10, 2013 at 09:05:48AM +0200, Wolfgang Denk wrote:
Dear Heiko Schocher,
In message 51b555d7.5010...@denx.de you wrote:
Ok, I can change this. Envvar name dfu_data_buf_size is ok?
Such long names are a paint to type. As we can't buffer anything else
but
Dear Simon Glass,
On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com wrote:
Signed-off-by: Axel Lin axel@ingics.com
Reviewed-by: Simon Glass s...@chromium.org
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
___
Hello Marek,
Am 12.06.2013 10:36, schrieb Marek Vasut:
Dear Tom Rini,
On Mon, Jun 10, 2013 at 09:05:48AM +0200, Wolfgang Denk wrote:
Dear Heiko Schocher,
In message 51b555d7.5010...@denx.de you wrote:
Ok, I can change this. Envvar name dfu_data_buf_size is ok?
Such long names are a
Hello tom,
your
commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674
Author: Tom Rini tr...@ti.com
Date: Fri May 31 12:31:59 2013 -0400
am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
introduced, that all am335x based boards must call
save_omap_boot_params() from the
Hi,
Your patch looks good to me, but the same time
I have sent some comments on v4 patch
http://patchwork.ozlabs.org/patch/249603/
I think you might respond to above thread before sending v5, may be
your missing my
earlier comments?
fyi: One one more thing the patch subject prefix should be
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes
On 06/12/2013 10:56 AM, Jagan Teki wrote:
Hi,
Your patch looks good to me, but the same time
I have sent some comments on v4 patch
http://patchwork.ozlabs.org/patch/249603/
I think you might respond to above thread before sending v5, may be
your missing my
earlier comments?
Yes, I missed
- Marek Vasut ma...@denx.de wrote:
Dear Simon Glass,
On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com
wrote:
Signed-off-by: Axel Lin axel@ingics.com
Reviewed-by: Simon Glass s...@chromium.org
Reviewed-by: Marek Vasut ma...@denx.de
Acked-by: Ajay Bhargav
On Wed, Jun 12, 2013 at 3:56 PM, Armando Visconti
armando.visco...@st.com wrote:
On 06/12/2013 10:56 AM, Jagan Teki wrote:
Hi,
Your patch looks good to me, but the same time
I have sent some comments on v4 patch
http://patchwork.ozlabs.org/patch/249603/
I think you might respond to above
On 06/10/2013 06:01 PM, Jagan Teki wrote:
Hi,
Please use the commit header as below: just to sync with remaining
drivers in tree.
spi: arm-pl022: Add support for ARM PL022 spi controller
OK,
I already did it for v5.
I'll keep it for v6 as well...
On Fri, Jun 7, 2013 at 1:14 PM, Armando
On Wed, Jun 12, 2013 at 4:40 PM, Armando Visconti
armando.visco...@st.com wrote:
On 06/10/2013 06:01 PM, Jagan Teki wrote:
Hi,
Please use the commit header as below: just to sync with remaining
drivers in tree.
spi: arm-pl022: Add support for ARM PL022 spi controller
OK,
I already did
Hello Jagan,
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022),
that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 =
On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote:
Hello tom,
your
commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674
Author: Tom Rini tr...@ti.com
Date: Fri May 31 12:31:59 2013 -0400
am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
introduced,
On Wed, Jun 12, 2013 at 5:48 PM, Armando Visconti
armando.visco...@st.com wrote:
Hello Jagan,
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022),
that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static
Hello Tom,
Am 12.06.2013 14:28, schrieb Tom Rini:
On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote:
Hello tom,
your
commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674
Author: Tom Rini tr...@ti.com
Date: Fri May 31 12:31:59 2013 -0400
am33xx/omap: Move
Please use the commit header as spi: pl022_spi:
as you haven't use the same on v5 i guess, please check.
OK, Jagan,
I'll do it!
Armando
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On Tue, Jun 11, 2013 at 11:22:30AM -0500, Dan Murphy wrote:
Update the EXTRA_ENV_SETTING for the dra7xx.
The console needs to be set to ttyO0 and the
findfdt needs to be updated to load the
dra7xx-evm.dtb file.
Signed-off-by: Dan Murphy dmur...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
On Wed, Jun 12, 2013 at 02:39:13PM +0200, Heiko Schocher wrote:
Hello Tom,
Am 12.06.2013 14:28, schrieb Tom Rini:
On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote:
Hello tom,
your
commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674
Author: Tom Rini tr...@ti.com
Date:
On Mon, 27 May 2013 14:29:20 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
These series of patches fix the location of
displaying IRQ stack infomation.
Because ARM architecture supports generic_board,
I separated my commit into 2 patches.
The first one fix arch/arm/lib/board.c
Thanks for v6 sent.
Have you tested this?
on which board, include/configs/*.h file?
--
Thanks,
Jagan.
On Wed, Jun 12, 2013 at 6:17 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has
Is there a reason why the gateway address (NetOurGatewayIP) doesn't get set
from the BOOTP header (bp_giaddr) as a default before processing the DHCP
options? Sure would help me.
Thanks,
Dean
___
U-Boot mailing list
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Is anyone considering porting/supporting uboot for ARMv8. Our initial
investigation of boot loader support for ARMv8 indicates that the only boot
loader currently being targeted is UEFI.
The decisions we need to make are:
- Do we move to UEFI on ARM?
- Can we leverage someone else's
On 06/12/2013 04:25 PM, Jagan Teki wrote:
Thanks for v6 sent.
Have you tested this?
on which board, include/configs/*.h file?
No Jagan.
I have not tested v6, as I currently don't have a spare board.
Nevertheless, Vipin tested it up to v3. And he
tested it on spear1340 evaluation board.
But if you prefer to be on safer side I think we
need to re-do some checks on a spare 1340 board...
OK, maybe it is better to re-check again.
I need to find some time and a spare board...
I'll let you know,
Arm
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On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti
armando.visco...@st.com wrote:
But if you prefer to be on safer side I think we
need to re-do some checks on a spare 1340 board...
OK, maybe it is better to re-check again.
I need to find some time and a spare board...
I'll let you know,
Hi Dirk,
On 12/06/2013 07:28, Dirk Behme wrote:
On 11.05.2013 07:25, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point
numbers.
Convert the desired divisor to the smallest number which
On Wed, Jun 12, 2013 at 9:12 PM, Stefano Babic sba...@denx.de wrote:
Hi Dirk,
On 12/06/2013 07:28, Dirk Behme wrote:
On 11.05.2013 07:25, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating
On 06/12/2013 05:29 PM, Jagan Teki wrote:
On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti
armando.visco...@st.com wrote:
But if you prefer to be on safer side I think we
need to re-do some checks on a spare 1340 board...
OK, maybe it is better to re-check again.
I need to find some time
Hi,
On 12/06/2013 17:47, Jagan Teki wrote:
Sorry, i didn't understand the conversation here, was this fix applied?
Could you please explain.
Patches are not applied and are currently assigned to me. As they
concerned the SPI subsystem (really, it is the SPI driver for iMX), they
could be
Nothing is used from asm/mipsregs.h.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips64/interrupts.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/cpu/mips64/interrupts.c
Gabor Juhos (4):
MIPS: mips32/time.c: fix checkpatch errors/warnings
MIPS: mips64/interrupt.c: remove superfluous include
MIPS: remove obsolete TODO items
MIPS: mips32/cache.S: remove superfluous register assignment
arch/mips/cpu/mips32/cache.S |3 +--
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.
Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: Gabor Juhos juh...@openwrt.org
---
Checking mips32/time.c with checkpatch.pl shows this:
arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters
arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses
are not required
total: 1 errors, 1 warnings, 0 checks, 85 lines checked
Fix the code to make
The MIPS code uses centralized u-boot.lds script already,
and dynamic relocation is supported as well.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
doc/README.mips |4
1 file changed, 4 deletions(-)
diff --git
On Wed, Jun 12, 2013 at 9:30 PM, Stefano Babic sba...@denx.de wrote:
Hi,
On 12/06/2013 17:47, Jagan Teki wrote:
Sorry, i didn't understand the conversation here, was this fix applied?
Could you please explain.
Patches are not applied and are currently assigned to me. As they
concerned
On Wed, Jun 12, 2013 at 06:05:51AM +0200, Heiko Schocher wrote:
Dfu transfer uses a buffer before writing data to the
raw storage device. Make the size (in bytes) of this buffer
configurable through environment variable dfu_bufsiz.
Defaut value is configurable through
Hello,
(cc:ing all ARM related repo custodians for PRs)
I have cleaned up my todo list for 2013.07 and am now preparing for
-rc1.
ARM related repo custodians who have PRs still pending to be
sent to me, please do now.
Any patches that their submitter feels should be in some ARM
repo by now but
On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote:
Is anyone considering porting/supporting uboot for ARMv8. ?Our initial
investigation of boot loader support for ARMv8 indicates that the only
boot loader currently being targeted is UEFI. ?
The decisions we need to make are:
Hi Simon,
On Wed, Jun 12, 2013 at 3:59 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This series is v3 for the patch series sent few weeks back with a head
sf: Update sf
Hi Tom,
On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote:
On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote:
Is anyone considering porting/supporting uboot for ARMv8. ?Our initial
investigation of boot loader support for ARMv8 indicates that the only
boot
On Wed, Jun 12, 2013 at 06:54:54PM +0200, Albert ARIBAUD wrote:
Hi Tom,
On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote:
On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote:
Is anyone considering porting/supporting uboot for ARMv8. ?Our initial
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 = A1-A5
GPIO171, GPIO101, GPIO182: 1 0 1 = A6
Panda ES:
Dear dirk.eib...@gdsys.cc,
In message 1371024486-15629-6-git-send-email-dirk.eib...@gdsys.cc you wrote:
The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On
Hi Tom,
On Wed, 12 Jun 2013 13:47:18 -0400, Tom Rini tr...@ti.com wrote:
On Wed, Jun 12, 2013 at 06:54:54PM +0200, Albert ARIBAUD wrote:
Hi Tom,
On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote:
On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote:
Hi,
Few comments, please get back your inputs.
Use commit header as spi: ftssp010_spi:
On 07-05-2013 12:04, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements
Hi,
On 03-06-2013 23:50, Jagan Teki wrote:
Hi,
Looks ok to me as per coding style after a quick look.
On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe t-ub...@infra-silbe.de wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds an SPI driver for Marvell Dove SoCs. This
Hi,
Can you please update the commit header and logic of the code
w.r.t current master tree.
also please use proper commit body.
--
Thanks,
Jagan.
On 27-09-2012 02:37, Dale Smith wrote:
The fsl spi engine is non functional when reading from a device. This
patch fixes it.
Note that none of
On 12-06-2013 15:49, Ajay Bhargav wrote:
- Marek Vasut ma...@denx.de wrote:
Dear Simon Glass,
On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com
wrote:
Signed-off-by: Axel Lin axel@ingics.com
Reviewed-by: Simon Glass s...@chromium.org
Reviewed-by: Marek Vasut
On 06/12/2013 08:58 PM, Jagan Teki wrote:
On 03-06-2013 23:50, Jagan Teki wrote:
Looks ok to me as per coding style after a quick look.
On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe
t-ub...@infra-silbe.de wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds an SPI
On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On 06/12/2013 08:58 PM, Jagan Teki wrote:
On 03-06-2013 23:50, Jagan Teki wrote:
Looks ok to me as per coding style after a quick look.
On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe
On 06/12/2013 09:30 PM, Jagan Teki wrote:
On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
Is any of you even listening? Please do _not_ name it after Dove! It is
compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the
chance to have a
Hi,
Can you separate the PMIC and SPI changes into two different patches.
Also may i know why you remove the SPI from configs, does it defined
some where or you don't want SPI at all.?
--
Thanks,
Jagan.
On 07-06-2013 17:25, Inderpal Singh wrote:
They have been defined once already. Hence
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.
Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed
On 30-05-2013 10:57, Rajeshwari Shinde wrote:
Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the
The following changes since commit 58bb8f5f6138fa56875574a709f5af98c600c2a9:
cosmetic: arm: fix comments in arch/arm/lib/crt0.S (2013-06-10 21:24:22 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-pxa.git master
for you to fetch changes up to
The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806:
MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up to
On Tue, Jun 11, 2013 at 11:25:58PM +0200, Wolfgang Denk wrote:
Dear Tom,
The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806:
MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200)
are available in the git repository at:
On Tue, Jun 11, 2013 at 11:25:57PM +0200, Wolfgang Denk wrote:
Dear Tom,
The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806:
MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200)
are available in the git repository at:
The following changes since commit 58bb8f5f6138fa56875574a709f5af98c600c2a9:
cosmetic: arm: fix comments in arch/arm/lib/crt0.S (2013-06-10 21:24:22 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-pxa.git master
for you to fetch changes up to
Acked-by: Che-Liang Chiou clch...@chromium.org
On Wed, Jun 12, 2013 at 1:08 AM, dirk.eib...@gdsys.cc wrote:
From: Reinhard Pfau p...@gdsys.de
Extend the tpm library with support for single authorized (AUTH1) commands
as specified in the TCG Main Specification 1.2. (The internally used helper
2013/6/12 Gabor Juhos juh...@openwrt.org:
Gabor Juhos (4):
MIPS: mips32/time.c: fix checkpatch errors/warnings
MIPS: mips64/interrupt.c: remove superfluous include
MIPS: remove obsolete TODO items
MIPS: mips32/cache.S: remove superfluous register assignment
Hi Jagan,
On Wed, Jun 12, 2013 at 12:51 PM, Jagan Teki jagannadh.t...@gmail.comwrote:
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.
Implement this as a delay on the first/next
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to read a flash bank address register.
reading extended/bank address register will give whether the flash
is operated on extended/bank addressing or
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to read a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only
Signed-off-by: Dale P. Smith dsm...@vtiinstruments.com
---
drivers/spi/fsl_espi.c | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 28609ee..bd9dc64 100644
--- a/drivers/spi/fsl_espi.c
+++
On 06/09/2013 12:54:43 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Due to the nand SPL on the board P1022DS has a size limit, it can not
be
more than 4K. So, the SPL cannot initialize the DDR with the SPD code.
This patch introduces TPL to enable a loader stub
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Initialized bank_sel variable to 0 to support the updated read
ops for flashes which has 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by:
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in
Hi Albert,
On Tuesday, June 11, 2013 2:17:29 PM, Albert ARIBAUD wrote:
This series optimizes relocation by ensuring ARM
binaries only use one type of relocation record,
R_ARM_RELATIVE., then optimizing relocation code
accordingly.
1. A Makefile rule is added that checks that no
other
On Wed, Jun 12, 2013 at 3:42 PM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing
Hi,
I've just found a crash in usb_stor_get_info (actually usb_inquiry
which gets auto-inlined). The cause seems to be that ss-transport is
set to the pre-relocation address of usb_stor_BBB_transport. Yet
ss-transport_reset is set to the correct relocated address of.
The difference between the
On Thu, Jun 13, 2013 at 12:02 PM, Chris Packham judge.pack...@gmail.com wrote:
Hi,
I've just found a crash in usb_stor_get_info (actually usb_inquiry
which gets auto-inlined). The cause seems to be that ss-transport is
set to the pre-relocation address of usb_stor_BBB_transport. Yet
Hi,
Thanks for sending this.
Few comments.
1. Please use subject prefix with version number this case it should
be PATH v3
2. Commit header should be stand' one as all follows.
spi: fsl_espi:
On Thu, Jun 13, 2013 at 3:24 AM, Dale P. Smith
dsm...@vtiinstruments.com wrote:
Hi Simon,
On Thu, Jun 13, 2013 at 4:09 AM, Simon Glass s...@chromium.org wrote:
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and
Hi Simon,
On Thu, Jun 13, 2013 at 3:48 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash bank address
register.
extended/bank
On Thu, Jun 13, 2013 at 3:36 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Wed, Jun 12, 2013 at 12:51 PM, Jagan Teki jagannadh.t...@gmail.com
wrote:
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add
From: Rob Herring rob.herr...@calxeda.com
interrupt_init also sets up the abort stack, but is not setup before
relocation. So any aborts during relocation will hang and not print out
any useful information. Fix this by moving the interrupt_init to after
the stack setup in board_init_f.
From: Rob Herring rob.herr...@calxeda.com
get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
arch/arm/cpu/armv7/highbank/timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Rob Herring rob.herr...@calxeda.com
The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
arch/arm/cpu/armv7/highbank/timer.c| 6 --
From: Rob Herring rob.herr...@calxeda.com
There is no reason to wait for the entire frame to start DMA on receive,
so enable rx cut-thru for better performance.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
drivers/net/calxedaxgmac.c | 2 +-
1 file changed, 1
From: Rob Herring rob.herr...@calxeda.com
The timer_init function is called before relocation and writes to bss data
were corrupting relocation data. Fix this by removing the call to
reset_timer_masked. The initial timer count should be 0 or near 0 anyway,
so initializing the variables are not
From: Rob Herring rob.herr...@calxeda.com
Various changes to highbank config:
Enable EFI partitions
Enable ext4 and FAT filesystems
Enable bootz command and raw initrd
Increase cmd and print buffer size to 1K
Change serial baudrate to 115200
Enable hush shell
Signed-off-by: Rob Herring
From: Rob Herring rob.herr...@calxeda.com
Enable resetting on command timeout. The timeout is set with environment
setting bootretry.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
include/configs/highbank.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Rob Herring rob.herr...@calxeda.com
Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2:
- Reword commit message
board/highbank/highbank.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/highbank/highbank.c
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