Re: [U-Boot] Odroid XU3 - exynos5422 - SPL - iRAM/sRAM address
Hi Suriyan, On 01/23/2015 10:46 AM, Suriyan Ramasami wrote: > On Thu, Jan 22, 2015 at 9:51 AM, Kevin Hilman wrote: >> Suriyan Ramasami writes: >> >>> Hello Kevin, >>> >>> On Wed, Jan 21, 2015 at 4:54 PM, Kevin Hilman wrote: Hi Surijan, Suriyan Ramasami writes: > Hello Sjoerd Simons, >A signed BL2 which allows unsigned BL2 chain load is already > available for experimentation. Refer this link: > http://forum.odroid.com/viewtopic.php?f=98&t=6147#p58984 > The suriyan.bl2-hkxu3.1212.5422.zip blob contains a signed BL2 which > allows the same. > > The layout of SD card is as follows: > > BL1 (1 to 30) 15K > BL2 (31 to 62) 16K > indicator block (63 to 64) 1K > uboot (65 to 2112) 1M > tzsw (2113 to 2624) 256K > unsigned BL2 (2625 to 2656) 16K > > A non zero in the first byte of the indicator block instructs the > signed BL2 to load the unsigned BL2 @ offset 2625. I took the binaries from your .zip file above and put them on the SD card for my odroid-xu3 at the offsets above. I'm using BL1 and TZSW from the u-boot-hardkernel release[1] and using u-boot-dtb.bin from my own mainline u-boot build which inclues the odroid-xu3 patches. If I leave the indicator block zero'd, everything works fine, and it boots my version of mainline u-boot without any problems. If I then write a non-zero value to the first byte of the indicator block and write your unsigned BL2 at the appropriate offset, it no longer boots. Is the unsigned BL2 supposed to boot u-boot at offset 65 when it's finished as well? >>> >>> The unsigned SPL from mainline used will be spl/u-boot-spl.bin (raw >>> jump to offset 0 in that file will be pure code without headers) >> Is it impossible the unsigned BL2(spl/smdk5422-spl.bin) file from hardkernel u-boot with your chaining signed BL2? >> OK. >> >>> Changes are needed in spl_boot.c to make it next load u-boot-dtb.bin. >>> >>> I shall try to list most of the changes here: >>> 1.arch/arm/cpu/armv7/exynos/spl_boot.c: >>>The Odroid-XU3's IROM function pointers does not have any code >>> (AFAICT). I checked the locations that are listed in the array table >>> and found all 0's there. >>>We need to replace function copy_uboot_to_ram() with something >>> similar from HK's file, so that it uses exynos_smc() calls to load the >>> bits from SD card, or we could enable MMC code in SPL (haven't tried >>> it) and use those functions instead. >>> For quick results,I just forced an SD card read. >>> >>> 2. #define CONFIG_SEC_FW_SIZE (15 << 10) /* 15 KB */ >>> somewhere, so that the start offset for U-Boot is calculated correctly. >>> >>> 3. for chain loading we define CONFIG_SPL_TEXT_BASE to be, say >>> 0x63E0 so that when its executed the static global pointers are >>> accessed correctly - static struct spl_machine_param machine_param in >>> file smdk5420_spl.c. >>> >>> 4. mem_ctrl_init() hangs in while (val != FOUTBPLL); >>> One workaround is to use HKs version of this function which again >>> uses some smc calls. >>> >>> With all these changes, SPL chainloading works. >> >> Do you have a patch against mainline u-boot for all these changes? I'd >> be happy to test. >> > > Give me some time and I shall iron out my notes and get back to > creating a patch for this against mainline U-Boot. > I'm also waiting. Thanks for your try. Thanks. How are you debugging your SPL images? I tried adding CONFIG_SPL_SERIAL_SUPPORT so I could printf from SPL, but that doesn't compile because it seems that libfdt support is needed. >>> >>> I didn't enable SERIAL SUPPORT for debugging. I did study the HK SPL >>> code vs mainline SPL code quite a bit and worked from there. >>> I can try to see if there is an easy way to enable serial printfs. >> >> Are there any GPIO LEDs to blink? >> > > It does have some LEDs. > >> Thanks, >> >> Kevin > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd_i2c: Provide option for bulk 'i2c write' in one transaction
Hello Lubomir,
Am 24.11.2014 17:00, schrieb Lubomir Popov:
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus transaction (aka atomic transfer), otherwise either the write
does not come into effect at all, or normal operation of internal circuitry
cannot be guaranteed. The current implementation of the 'i2c write' command
(transfer of multiple bytes from a memory buffer) in fact performs a separate
transaction for each byte to be written and thus cannot support such types of
I2C slave devices.
This patch provides an alternative by allowing 'i2c write' to execute the
write transfer of the given number of bytes in a single bus transaction if
CONFIG_SYS_I2C_BULK_WRITE is defined in the board header (otherwise the old
method shall compile).
Signed-off-by: Lubomir Popov
---
common/cmd_i2c.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
Could you rebase your patch against current mainline, please?
As we have now DM in i2c subsystem your patch does not apply clean
anymore ... thanks!
bye,
Heiko
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 3a75f94..7116458 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -280,10 +280,22 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
return cmd_usage(cmdtp);
/*
-* Length is the number of objects, not number of bytes.
+* Length is the number of bytes.
*/
length = simple_strtoul(argv[4], NULL, 16);
+#if defined(CONFIG_SYS_I2C_BULK_WRITE)
+ /*
+* Write all bytes in a single I2C transaction. If the target
+* device is an EEPROM, it is your responsibility to not cross
+* a page bounady.
+*/
+ if (i2c_write(chip, devaddr, alen, memaddr, length) != 0) {
+ puts("Error writing to the chip.\n");
+ return 1;
+ }
+#else
+ /* Perform separate write transactions of one byte each */
while (length-- > 0) {
if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
puts("Error writing to the chip.\n");
@@ -296,6 +308,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
udelay(11000);
#endif
}
+#endif
return 0;
}
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH v2 22/22] x86: Add support for Intel Minnowboard Max
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote: > This is a relatively low-cost x86 board in a small form factor. The main > peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 > series CPU. So far only the dual core 2GB variant is supported. > > This uses the existing FSP support. Binary blobs are required to make this > board work. The microcode update is included as a patch (all 3000 lines of > it). > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file > - Add comment about FSP setting PCIE_ECAM_BASE > - Put baytrail Kconfig in alphabetical order > - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart() > - Fix compatible string for SPI flash > - Remove commented-out DEBUG_UART_CLOCK baud rate > - Rename 'Coreboot' to 'coreboot' in README.x86 > Reviewed-by: Bin Meng [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver
Hi Simon, On Wed, Jan 28, 2015 at 1:17 PM, Simon Glass wrote: > Hi Bin, > > On 27 January 2015 at 07:00, Bin Meng wrote: >> Hi Simon, >> >> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: >>> The base address is found in a different way and the protection bit is also >>> in a different place. Otherwise it is very similar. >>> >>> Signed-off-by: Simon Glass >>> --- >>> >>> drivers/spi/ich.c | 56 >>> --- >>> drivers/spi/ich.h | 11 ++- >>> 2 files changed, 47 insertions(+), 20 deletions(-) > > Just a note on this one...for v2 I have done nothing. I think we > should move it to device tree as you say but it needs some more > thought, as we have register offsets and device types to think about. > I will try a few things and test on link also. Once I have this I will > send a v3. So this patch will have to sit here until that is done, > hopefully only a few days. > OK, I think we can just apply this patch for now along with other patches in this series. We can revisit this driver when adding DT and DM support. > Thanks for the quick reviews! > You are welcome! Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 18/22] x86: spi: Support ValleyView in ICH SPI driver
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote:
> The base address is found in a different way and the protection bit is also
> in a different place. Otherwise it is very similar.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> drivers/spi/ich.c | 56
> ---
> drivers/spi/ich.h | 11 ++-
> 2 files changed, 47 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index fdff158..da85779 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -7,6 +7,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -21,6 +22,7 @@
> struct ich_ctlr {
> pci_dev_t dev; /* PCI device number */
> int ich_version;/* Controller version, 7 or 9 */
> + bool use_sbase; /* Use SBASE instead of RCB */
> int ichspi_lock;
> int locked;
> uint8_t *opmenu;
> @@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
> unsigned int cs,
> * ICH 7 SPI controller only supports array read command
> * and byte program command for SST flash
> */
> - if (ctlr.ich_version == 7) {
> + if (ctlr.ich_version == 7 || ctlr.use_sbase) {
> ich->slave.op_mode_rx = SPI_OPM_RX_AS;
> ich->slave.op_mode_tx = SPI_OPM_TX_BP;
> }
> @@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id)
> if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
> device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
> (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
> -device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
> +device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
> + device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
> return 9;
>
> return 0;
> @@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
> return speed == 1;
> }
>
> -static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
> +static int ich_find_spi_controller(struct ich_ctlr *ich)
> {
> int last_bus = pci_last_busno();
> int bus;
>
> if (last_bus == -1) {
> debug("No PCI busses?\n");
> - return -1;
> + return -ENODEV;
> }
>
> for (bus = 0; bus <= last_bus; bus++) {
> @@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int
> *ich_versionp)
> device_id = ids >> 16;
>
> if (vendor_id == PCI_VENDOR_ID_INTEL) {
> - *devp = dev;
> - *ich_versionp = get_ich_version(device_id);
> - return 0;
> + ich->dev = dev;
> + ich->ich_version = get_ich_version(device_id);
> + if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
> + ich->use_sbase = true;
> + return ich->ich_version == 0 ? -ENODEV : 0;
> }
> }
>
> debug("ICH SPI: No ICH found.\n");
> - return -1;
> + return -ENODEV;
> }
>
> static int ich_init_controller(struct ich_ctlr *ctlr)
> {
> uint8_t *rcrb; /* Root Complex Register Block */
> uint32_t rcba; /* Root Complex Base Address */
> + uint32_t sbase_addr;
> + uint8_t *sbase;
>
> pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
> /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
> rcrb = (uint8_t *)(rcba & 0xc000);
> +
> + /* SBASE is similar */
> + pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
> + sbase = (uint8_t *)(sbase_addr & 0xfe00);
> +
> if (ctlr->ich_version == 7) {
> struct ich7_spi_regs *ich7_spi;
>
> @@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
> } else if (ctlr->ich_version == 9) {
> struct ich9_spi_regs *ich9_spi;
>
> - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
> + if (ctlr->use_sbase)
> + ich9_spi = (struct ich9_spi_regs *)sbase;
> + else
> + ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
> ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
> ctlr->opmenu = ich9_spi->opmenu;
> ctlr->menubytes = sizeof(ich9_spi->opmenu);
> @@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
> ctlr->ich_version);
> return -1;
> }
> - debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
>
> /* Work out the maximum speed we can support */
> ctlr->max_speed = 2000;
> if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
>
Re: [U-Boot] [PATCH v2 17/22] x86: Allow a UART to be set up before the FSP is ready
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote:
> Since the FSP is a black box it helps to have some sort of debugging
> available to check its inputs. If the debug UART is in use, set it up
> after CAR is available.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Remove duplicate prototype of setup_early_uart()
>
> arch/x86/include/asm/u-boot-x86.h | 3 +++
> arch/x86/lib/fsp/fsp_support.c| 4
> 2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/include/asm/u-boot-x86.h
> b/arch/x86/include/asm/u-boot-x86.h
> index b98afa8..5d7dff5 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -45,6 +45,9 @@ ulong board_get_usable_ram_top(ulong total_size);
> void dram_init_banksize(void);
> int default_print_cpuinfo(void);
>
> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
> +int setup_early_uart(void);
> +
> void setup_pcat_compatibility(void);
>
> void isa_unmap_rom(u32 addr);
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index 8b639f7..5f96da1 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void
> *nvs_buf)
> struct fsp_init_params *params_ptr;
> struct upd_region *fsp_upd;
>
> +#ifdef CONFIG_DEBUG_UART
> + setup_early_uart();
> +#endif
> +
> fsp_hdr = find_fsp_header();
> if (fsp_hdr == NULL) {
> /* No valid FSP info header was found */
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH v2 14/22] x86: mmc: Move common FSP functions into a common file
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote:
> Since these board functions seem to be the same for all boards which use
> FSP, move them into a common file. We can adjust this later if future FSPs
> need more flexibility.
>
> This creates a generic PCI MMC device.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Move MMC code into a new pci_mmc.c file
> - Remove setup_early_uart() function prototype
>
> arch/x86/cpu/queensbay/tnc.c | 27 ---
> arch/x86/cpu/queensbay/tnc_pci.c | 15 ---
> arch/x86/cpu/queensbay/topcliff.c | 33 +++
> arch/x86/lib/fsp/Makefile | 1 +
> arch/x86/lib/fsp/fsp_common.c | 55
> +++
> drivers/mmc/Makefile | 1 +
> drivers/mmc/pci_mmc.c | 42 ++
> include/mmc.h | 14 ++
> 8 files changed, 116 insertions(+), 72 deletions(-)
> create mode 100644 arch/x86/lib/fsp/fsp_common.c
> create mode 100644 drivers/mmc/pci_mmc.c
>
> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
> index f9b3bfa..30ab725 100644
> --- a/arch/x86/cpu/queensbay/tnc.c
> +++ b/arch/x86/cpu/queensbay/tnc.c
> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>
> return 0;
> }
> -
> -int print_cpuinfo(void)
> -{
> - post_code(POST_CPU_INFO);
> - return default_print_cpuinfo();
> -}
> -
> -void reset_cpu(ulong addr)
> -{
> - /* cold reset */
> - outb(0x06, PORT_RESET);
> -}
> -
> -void board_final_cleanup(void)
> -{
> - u32 status;
> -
> - /* call into FspNotify */
> - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
> - status = fsp_notify(NULL, INIT_PHASE_BOOT);
> - if (status != FSP_SUCCESS)
> - debug("fail, error code %x\n", status);
> - else
> - debug("OK\n");
> -
> - return;
> -}
> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c
> b/arch/x86/cpu/queensbay/tnc_pci.c
> index 9b0b725..6c291f9 100644
> --- a/arch/x86/cpu/queensbay/tnc_pci.c
> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>
> hose->region_count = 4;
> }
> -
> -int board_pci_post_scan(struct pci_controller *hose)
> -{
> - u32 status;
> -
> - /* call into FspNotify */
> - debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
> - status = fsp_notify(NULL, INIT_PHASE_PCI);
> - if (status != FSP_SUCCESS)
> - debug("fail, error code %x\n", status);
> - else
> - debug("OK\n");
> -
> - return 0;
> -}
> diff --git a/arch/x86/cpu/queensbay/topcliff.c
> b/arch/x86/cpu/queensbay/topcliff.c
> index b01422a..9faf1b9 100644
> --- a/arch/x86/cpu/queensbay/topcliff.c
> +++ b/arch/x86/cpu/queensbay/topcliff.c
> @@ -5,43 +5,16 @@
> */
>
> #include
> -#include
> -#include
> -#include
> +#include
> #include
> -#include
>
> static struct pci_device_id mmc_supported[] = {
> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
> - { }
> };
>
> int cpu_mmc_init(bd_t *bis)
> {
> - struct sdhci_host *mmc_host;
> - pci_dev_t devbusfn;
> - u32 iobase;
> - int ret;
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
> - devbusfn = pci_find_devices(mmc_supported, i);
> - if (devbusfn == -1)
> - return -ENODEV;
> -
> - mmc_host = (struct sdhci_host *)malloc(sizeof(struct
> sdhci_host));
> - if (!mmc_host)
> - return -ENOMEM;
> -
> - mmc_host->name = "Topcliff SDHCI";
> - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
> - mmc_host->ioaddr = (void *)iobase;
> - mmc_host->quirks = 0;
> - ret = add_sdhci(mmc_host, 0, 0);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> + return pci_mmc_init("Topcliff SDHCI", mmc_supported,
> + ARRAY_SIZE(mmc_supported));
> }
> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
> index 3a2bac0..5b12c12 100644
> --- a/arch/x86/lib/fsp/Makefile
> +++ b/arch/x86/lib/fsp/Makefile
> @@ -5,5 +5,6 @@
> #
>
> obj-y += fsp_car.o
> +obj-y += fsp_common.o
> obj-y += fsp_dram.o
> obj-y += fsp_support.o
> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
> new file mode 100644
> index 000..f668259
> --- /dev/null
> +++ b/arch/x86/lib/fsp/fsp_common.c
> @@ -0,0 +1,55 @@
> +/*
> + * Copyright (C) 2014, Bin Meng
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +int print_cpuinfo(void)
> +{
> + post_code(POST_CPU_INFO);
> +
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi Simon,
On 01/28/2015 02:15 PM, Simon Glass wrote:
> Hi Joonyoung,
>
> On 27 January 2015 at 22:12, Joonyoung Shim wrote:
>> Hi Simon,
>>
>> On 01/28/2015 02:01 PM, Simon Glass wrote:
>>> Hi Joonyoung,
>>>
>>> On 27 January 2015 at 21:46, Joonyoung Shim wrote:
Hi Simon,
On 01/28/2015 01:09 PM, Simon Glass wrote:
> Hi,
>
> On 15 January 2015 at 23:09, Joonyoung Shim
> wrote:
>> Hi,
>>
>> On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
>>> We planned to fetch peripheral rate through one generic API per
>>> peripheral. These generic peripheral functions are in turn
>>> expected to fetch apt values from a function refactored as
>>> per SoC versions. This patch adds support for fetching peripheral
>>> rates for Exynos5420 and Exynos5800.
>>>
>>> Signed-off-by: Akshay Saraswat
>>> ---
>>> Changes since v2:
>>> - Fixed enum and exynos542x_get_periph_rate switch.
>>> - Added checks for negative values in exynos542x_get_periph_rate.
>>>
>>> Changes since v1:
>>> - Changes suuport -> support in commit message.
>>> - Removed position change of exynos5420_get_pll_clk.
>>> - Removed #ifdef.
>>>
>>> arch/arm/cpu/armv7/exynos/clock.c | 151
>>> +++--
>>> arch/arm/include/asm/arch-exynos/clk.h | 3 +
>>> 2 files changed, 147 insertions(+), 7 deletions(-)
>
> What else needs to be done to get this applied, please?
>
As i said, current this patch has some problem like mask bits, so eMMC
doesn't work normally.
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>>> b/arch/arm/cpu/armv7/exynos/clock.c
>>> index 5dc9ed2..ee6c13b 100644
>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> @@ -27,7 +27,7 @@ struct clk_bit_info {
>>> };
>>>
>>> /* periph_id src_bit div_bit prediv_bit */
>>> -static struct clk_bit_info clk_bit_info[] = {
>>> +static struct clk_bit_info exynos5_bit_info[] = {
>>> {PERIPH_ID_UART0, 0, 0, -1},
>>> {PERIPH_ID_UART1, 4, 4, -1},
>>> {PERIPH_ID_UART2, 8, 8, -1},
>>> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
>>> {PERIPH_ID_NONE,-1, -1, -1},
>>> };
>>>
>>> +static struct clk_bit_info exynos542x_bit_info[] = {
>>> + {PERIPH_ID_UART0, 4, 8, -1},
>>> + {PERIPH_ID_UART1, 8, 12, -1},
>>> + {PERIPH_ID_UART2, 12, 16, -1},
>>> + {PERIPH_ID_UART3, 16, 20, -1},
>>> + {PERIPH_ID_I2C0,-1, 8, -1},
>>> + {PERIPH_ID_I2C1,-1, 8, -1},
>>> + {PERIPH_ID_I2C2,-1, 8, -1},
>>> + {PERIPH_ID_I2C3,-1, 8, -1},
>>> + {PERIPH_ID_I2C4,-1, 8, -1},
>>> + {PERIPH_ID_I2C5,-1, 8, -1},
>>> + {PERIPH_ID_I2C6,-1, 8, -1},
>>> + {PERIPH_ID_I2C7,-1, 8, -1},
>>> + {PERIPH_ID_SPI0,20, 20, 8},
>>> + {PERIPH_ID_SPI1,24, 24, 16},
>>> + {PERIPH_ID_SPI2,28, 28, 24},
>>> + {PERIPH_ID_SDMMC0, 0, 0, -1},
>>> + {PERIPH_ID_SDMMC1, 4, 10, -1},
>>> + {PERIPH_ID_SDMMC2, 8, 20, -1},
>>> + {PERIPH_ID_I2C8,-1, 8, -1},
>>> + {PERIPH_ID_I2C9,-1, 8, -1},
>>> + {PERIPH_ID_I2S0,0, 0, 4},
>>> + {PERIPH_ID_I2S1,4, 12, 16},
>>> + {PERIPH_ID_SPI3,12, 16, 0},
>>> + {PERIPH_ID_SPI4,16, 20, 8},
>>> + {PERIPH_ID_SDMMC4, 16, 0, 8},
>>> + {PERIPH_ID_PWM0,24, 28, -1},
>>> + {PERIPH_ID_PWM1,24, 28, -1},
>>> + {PERIPH_ID_PWM2,24, 28, -1},
>>> + {PERIPH_ID_PWM3,24, 28, -1},
>>> + {PERIPH_ID_PWM4,24, 28, -1},
>>> + {PERIPH_ID_I2C10, -1, 8, -1},
>>> +
>>> + {PERIPH_ID_NONE,-1, -1, -1},
>>> +};
>>> +
>>> /* Epll Clock division values to achive different frequency output */
>>> static struct set_epll_con_val exynos5_epll_div[] = {
>>> { 19200, 0, 48, 3, 1, 0 },
>>> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
>>> pllreg)
>>> static struct clk_bit_info *get_clk_bit_info(int peripheral)
>>> {
>>> int i;
>>> + struct clk_bit_info *info;
>>>
>>> - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
>>> - if (clk_bit_info[i].id == peripheral)
Re: [U-Boot] [PATCH v2 08/22] x86: Rename MMCONF_BASE_ADDRESS and make it common across x86
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote: > This setting will be used by more than just ivybridge so make it common. > > Also rename it to PCIE_ECAM_BASE which is a more descriptive name. > > Signed-off-by: Simon Glass > --- Reviewed-by: Bin Meng Please see one minor issue below. > Changes in v2: > - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE > - Adjust the Kconfig help according to Bin's comments > > arch/x86/Kconfig | 14 ++ > arch/x86/cpu/ivybridge/sdram.c| 2 +- > arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- > board/google/chromebook_link/Kconfig | 3 +-- > 4 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 90e828a..bda7a0e 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig" > > source "board/intel/crownbay/Kconfig" > > +config PCIE_ECAM_BASE > + hex > +default 0xe000 Need make 'default' aligned. Sorry I did not point it out in the v1 review. You can fix it when applying. > + help > + This is the memory-mapped address of PCI configuration space, which > + is only available through the Enhanced Configuration Access > + Mechanism (ECAM) with PCI Express. It can be set up almost > + anywhere. Before it is set up, it is possible to access PCI > + configuration space through I/O access, but memory access is more > + convenient. Using this, PCI can be scanned and configured. This > + should be set to a region that does not conflict with memory > + assigned to PCI devices - i.e. the memory and prefetch regions, as > + passed to pci_set_region(). > + > endmenu > diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c > index 4963448..766b385 100644 > --- a/arch/x86/cpu/ivybridge/sdram.c > +++ b/arch/x86/cpu/ivybridge/sdram.c > @@ -757,7 +757,7 @@ int dram_init(void) > .mchbar = DEFAULT_MCHBAR, > .dmibar = DEFAULT_DMIBAR, > .epbar = DEFAULT_EPBAR, > - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, > + .pciexbar = CONFIG_PCIE_ECAM_BASE, > .smbusbar = SMBUS_IO_BASE, > .wdbbar = 0x400, > .wdbsize = 0x1000, > diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h > b/arch/x86/include/asm/arch-ivybridge/sandybridge.h > index cf7457f..c960525 100644 > --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h > +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h > @@ -43,7 +43,7 @@ > #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ > #define DEFAULT_RCBABASE 0xfed1c000 > /* 4 KB per PCIe device */ > -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS > +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE > > /* Device 0:0.0 PCI configuration space (Host Bridge) */ > #define EPBAR 0x40 > diff --git a/board/google/chromebook_link/Kconfig > b/board/google/chromebook_link/Kconfig > index 33a31f3..ea45472 100644 > --- a/board/google/chromebook_link/Kconfig > +++ b/board/google/chromebook_link/Kconfig > @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy > select MARK_GRAPHICS_MEM_WRCOMB > select BOARD_ROMSIZE_KB_8192 > > -config MMCONF_BASE_ADDRESS > - hex > +config PCIE_ECAM_BASE > default 0xf000 > > config EARLY_POST_CROS_EC > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/22] x86: Add an option to enabling building a ROM file
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote: > Rather than requiring the Makefile to be modified, provide a build option to > enable the ROM to be built. > > We cannot do this by default since it requires binary blobs. Without these > the build will fail. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Fix README typos > > Makefile | 5 +++-- > doc/README.x86 | 10 ++ > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/Makefile b/Makefile > index a876f1f..c6e4ad1 100644 > --- a/Makefile > +++ b/Makefile > @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) > endif > ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf > > -# We can't do this yet due to the need for binary blobs > -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +ifneq ($(BUILD_ROM),) > +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +endif > > # enable combined SPL/u-boot/dtb rules for tegra > ifneq ($(CONFIG_TEGRA),) > diff --git a/doc/README.x86 b/doc/README.x86 > index 7df8cc5..ddfd75e 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as > u-boot.rom) is a > little bit tricky, as generally it requires several binary blobs which are > not > shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build > is > not turned on by default in the U-Boot source tree. Firstly, you need turn it > -on by uncommenting the following line in the main U-Boot Makefile: > +on by enabling the ROM build: > > -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +$ export BUILD_ROM=y > + > +This tells the Makefile to build u-boot.rom as a target. > > Link-specific instructions: > > @@ -126,11 +128,11 @@ Make sure 0x111 matches CONFIG_SYS_TEXT_BASE and > 0x1110015 matches the > symbol address of _start (in arch/x86/cpu/start.S). > > If you want to use ELF as the coreboot payload, change U-Boot configuration > to > -use CONFIG_OF_EMBED. > +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. > > CPU Microcode > - > -Modern CPU usually requires a special bit stream called microcode [5] to be > +Modern CPUs usually require a special bit stream called microcode [5] to be > loaded on the processor after power up in order to function properly. U-Boot > has already integrated these as hex dumps in the source tree. > > -- Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/22] pci: Add a function to find a device by class
Hi Simon,
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass wrote:
> There is an existing function prototype in the header file but it is not
> implemented. Implement something similar.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Bin Meng
One typo below and I think you can fix it before applying.
> Changes in v2:
> - Fix missing spaces (code style nit)
> - Add another comment in pci_find_class()
>
> drivers/pci/pci.c | 43 +++
> include/pci.h | 3 +--
> 2 files changed, 44 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 950a247..0210e41 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -15,6 +15,7 @@
> #include
>
> #include
> +#include
> #include
> #include
> #include
> @@ -236,6 +237,48 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids,
> int index)
> return -1;
> }
>
> +pci_dev_t pci_find_class(uint find_class, int index)
> +{
> + int bus;
> + int devnum;
> + pci_dev_t bdf;
> + uint32_t class;
> +
> + for (bus = 0; bus <= pci_last_busno(); bus++) {
> + for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
> + pci_read_config_dword(PCI_BDF(bus, devnum, 0),
> + PCI_CLASS_REVISION, &class);
> + if (class >> 16 == 0x)
> + continue;
> +
> + for (bdf = PCI_BDF(bus, devnum, 0);
> + bdf <= PCI_BDF(bus, devnum,
> + PCI_MAX_PCI_FUNCTIONS - 1);
> + bdf += PCI_BDF(0, 0, 1)) {
> + pci_read_config_dword(bdf, PCI_CLASS_REVISION,
> + &class);
> + class >>= 8;
> +
> + if (class != find_class)
> + continue;
> + /*
> +* Decrement the index. We want to return the
> +* correct device, so index is 0 for theh
> first
theh -> the
> +* matching device, 1 for the second, etc.
> +*/
> + if (index) {
> + index--;
> + continue;
> + }
> + /* Return index'th controller. */
> + return bdf;
> + }
> + }
> + }
> +
> + return -ENODEV;
> +}
> +
> pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int
> index)
> {
> struct pci_device_id ids[2] = { {}, {0, 0} };
> diff --git a/include/pci.h b/include/pci.h
> index 4fbb8f6..004a048 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller
> *hose, pci_dev_t dev);
>
> extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device,
> int index);
> extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
> -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
> - int wanted_prog_if, int index);
> +pci_dev_t pci_find_class(unsigned int find_class, int index);
>
> extern int pci_hose_config_device(struct pci_controller *hose,
> pci_dev_t dev,
> --
Regards,
Bin
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[U-Boot] [PATCH v1 6/8] avr32: add generic board support
Signed-off-by: Andreas Bießmann
---
Changes in v1:
- add timer_init in board_r
- remove extern declaration of mmu_init_r()
arch/avr32/config.mk|3 +++
arch/avr32/cpu/u-boot.lds |2 ++
arch/avr32/include/asm/config.h |1 +
arch/avr32/include/asm/u-boot.h |7 +++
arch/avr32/lib/Makefile |2 ++
arch/avr32/lib/interrupts.c |5 +
common/board_f.c| 13 ++---
common/board_r.c| 26 +++---
include/asm-generic/u-boot.h|4
9 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
index 469185e..8252f59 100644
--- a/arch/avr32/config.mk
+++ b/arch/avr32/config.mk
@@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := avr32-linux-
endif
+# avr32 has generic board support
+__HAVE_ARCH_GENERIC_BOARD := y
+
CONFIG_STANDALONE_LOAD_ADDR ?= 0x
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds
index cb29a22..b0180e3 100644
--- a/arch/avr32/cpu/u-boot.lds
+++ b/arch/avr32/cpu/u-boot.lds
@@ -48,9 +48,11 @@ SECTIONS
_edata = .;
.bss (NOLOAD) : {
+ __bss_start = .;
*(.bss)
*(.bss.*)
}
. = ALIGN(8);
__bss_end = .;
+ __init_end = .;
}
diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h
index 63056a4..529fe22 100644
--- a/arch/avr32/include/asm/config.h
+++ b/arch/avr32/include/asm/config.h
@@ -8,5 +8,6 @@
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#endif
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 2387f8a..0f7 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -6,6 +6,11 @@
#ifndef __ASM_U_BOOT_H__
#define __ASM_U_BOOT_H__ 1
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include
+#else
+
typedef struct bd_info {
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
@@ -22,6 +27,8 @@ typedef struct bd_info {
#define bi_memstart bi_dram[0].start
#define bi_memsize bi_dram[0].size
+#endif
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile
index bb45cbe..d5cb8b2 100644
--- a/arch/avr32/lib/Makefile
+++ b/arch/avr32/lib/Makefile
@@ -8,6 +8,8 @@
#
obj-y += memset.o
+ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
+endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c
index bacb2d1..5f3a49e 100644
--- a/arch/avr32/lib/interrupts.c
+++ b/arch/avr32/lib/interrupts.c
@@ -7,6 +7,11 @@
#include
+int interrupt_init(void)
+{
+ return 0;
+}
+
void enable_interrupts(void)
{
asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
diff --git a/common/board_f.c b/common/board_f.c
index 215108b..1a735ae 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -174,7 +174,7 @@ static int announce_dram_init(void)
return 0;
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_AVR32)
static int init_func_ram(void)
{
#ifdef CONFIG_BOARD_TYPES
@@ -268,6 +268,8 @@ static int setup_mon_len(void)
gd->mon_len = (ulong)&_end - (ulong)_init;
#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
+#elif defined(CONFIG_AVR32)
+ gd->mon_len = (ulong)&__bss_end - (ulong)&_text;
#else
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
@@ -581,7 +583,7 @@ static int reserve_stacks(void)
gd->irq_sp = gd->start_addr_sp;
# endif
#else
-# ifdef CONFIG_PPC
+# if defined(CONFIG_PPC) || defined(CONFIG_AVR32)
ulong *s;
# endif
@@ -611,6 +613,11 @@ static int reserve_stacks(void)
s = (ulong *) gd->start_addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
+# elif defined(CONFIG_AVR32)
+ gd->arch.stack_end = gd->start_addr_sp;
+ s = (ulong *)gd->start_addr_sp;
+ *s = 0;
+ *--s = 0;
# endif /* Architecture specific code */
return 0;
@@ -912,7 +919,7 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_ARM) || defined(CONFIG_X86)
dram_init, /* configure available RAM banks */
#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_AVR32)
init_func_ram,
#endif
#ifdef CONFIG_POST
diff --git a/common/board_r.c b/common/board_r.c
index e712902..3620438 100644
--- a/common/board_r.c
+++ b/common/boa
Re: [U-Boot] [RFC PATCH 04/21] ARM: tegra: collect SoC sources into mach-tegra
Hi Stephen, On Mon, 26 Jan 2015 10:40:57 -0700 Stephen Warren wrote: > On 01/24/2015 11:11 PM, Masahiro Yamada wrote: > > This commit moves files as follows: > > > > arch/arm/cpu/arm720t/tegra20/* -> arch/arm/mach-tegra/tegra20/* > > arch/arm/cpu/arm720t/tegra30/* -> arch/arm/mach-tegra/tegra30/* > ... > > Bikeshed: I know that this matches what the Linux kernel has for 32-bit ARM, > but I've always disliked using the word "machine" to describe an SoC. Would > just "tegra" or "soc-tegra" be better than "mach-tegra"? Feel free to > entirely ignore this though; I don't feel too strongly. In hindsight, arch/arm/soc-* would have been clearer than arch/arm/mach-*. However, we are already familiar with this directory name convention, so "machine" looks OK to me. > > Oh and one more thing: We're starting to work on 64-bit Tegra support in the > Linux kernel. A fair amount of the code moved by this patch is likely to > apply on both 32-bit and 64-bit Tegra. Will arch/arm support 64-bit within > U-Boot, or will there be a separate directory for 32- and 64-bit ARM? If so, > should this code all be moved to something more like soc/tegra/... or > drivers/tegra/... or drivers/soc/tegra/... or ... so it can be shared between > the architectures? We had a hot discussion when aarch64 support was introduced to U-Boot. Finally, the community chose arch/arm/cpu/armv8/ rather than arch/arm64/, i.e. single-arch-directory. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 0/8] avr32: add generic board
This is the first attempt to add generic board support to avr32 architecture. It has at least one relevant part for other manual reloc architectures. This series is currently runtime tested on grasshhopper and atstk1002. Andreas Bießmann Changes in v1: - new since RFC - new since RFC - add timer_init in board_r - remove extern declaration of mmu_init_r() - new since RFC Andreas Bießmann (8): avr32: use dlmalloc for DMA buffers avr32: rename cpu_init() -> arch_cpu_init() avr32: factor out cpu_mmc_init() avr32: rename mmu.h definitions common/board_r: manual relocation for cmd table avr32: add generic board support grasshopper: enable generic board atstk1002: enable generic board arch/avr32/config.mk |3 ++ arch/avr32/cpu/Makefile |1 + arch/avr32/cpu/at32ap700x/mmu.c |8 ++-- arch/avr32/cpu/cpu.c |2 +- arch/avr32/cpu/mmc.c | 16 +++ arch/avr32/cpu/u-boot.lds|2 + arch/avr32/include/asm/arch-at32ap700x/mmu.h |6 +-- arch/avr32/include/asm/config.h |1 + arch/avr32/include/asm/dma-mapping.h |7 ++- arch/avr32/include/asm/u-boot.h |9 arch/avr32/lib/Makefile |2 + arch/avr32/lib/board.c | 61 +- arch/avr32/lib/interrupts.c |5 +++ board/atmel/atngw100/atngw100.c | 12 ++--- board/atmel/atngw100mkii/atngw100mkii.c | 18 board/atmel/atstk1000/atstk1000.c| 12 ++--- board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 12 ++--- board/in-circuit/grasshopper/grasshopper.c | 12 ++--- board/mimc/mimc200/mimc200.c | 18 board/miromico/hammerhead/hammerhead.c | 12 ++--- common/board_f.c | 13 -- common/board_r.c | 38 ++-- include/asm-generic/u-boot.h |4 ++ include/configs/atngw100.h |1 - include/configs/atngw100mkii.h |1 - include/configs/atstk1002.h |5 ++- include/configs/atstk1006.h |1 - include/configs/favr-32-ezkit.h |1 - include/configs/grasshopper.h|5 ++- include/configs/hammerhead.h |1 - include/configs/mimc200.h|1 - 31 files changed, 159 insertions(+), 131 deletions(-) create mode 100644 arch/avr32/cpu/mmc.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 20/22] x86: Enable bootstage features
Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None include/configs/x86-common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ecedfc3..66d4894 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -245,6 +245,9 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTSTAGE +#define CONFIG_CMD_BOOTSTAGE + #define CONFIG_CMD_USB #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/22] x86: bootstage: Add time measurement for vesa start-up
Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
time, measure it using bootstage.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/video/vesa_fb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 9164f8d..47f824a 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -42,8 +42,10 @@ void *video_hw_init(void)
printf("no card detected\n");
return NULL;
}
+ bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
PCI_ROM_ALLOW_FALLBACK);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
return NULL;
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 13/22] x86: Make CAR and DRAM FSP code common
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/lib/fsp/Makefile | 2 ++
arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0
arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 0
4 files changed, 3 insertions(+), 1 deletion(-)
rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (100%)
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index b3e7d87..d8761fd 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
obj-y += fsp_configs.o
+obj-y += tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 1b9b0e2..3a2bac0 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -4,4 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += fsp_car.o
+obj-y += fsp_dram.o
obj-y += fsp_support.o
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S
similarity index 100%
rename from arch/x86/cpu/queensbay/tnc_car.S
rename to arch/x86/lib/fsp/fsp_car.S
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c
similarity index 100%
rename from arch/x86/cpu/queensbay/tnc_dram.c
rename to arch/x86/lib/fsp/fsp_dram.c
--
2.2.0.rc0.207.ga3a616c
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Re: [U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver
Hi Bin, On 27 January 2015 at 07:00, Bin Meng wrote: > Hi Simon, > > On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: >> The base address is found in a different way and the protection bit is also >> in a different place. Otherwise it is very similar. >> >> Signed-off-by: Simon Glass >> --- >> >> drivers/spi/ich.c | 56 >> --- >> drivers/spi/ich.h | 11 ++- >> 2 files changed, 47 insertions(+), 20 deletions(-) Just a note on this one...for v2 I have done nothing. I think we should move it to device tree as you say but it needs some more thought, as we have register offsets and device types to think about. I will try a few things and test on link also. Once I have this I will send a v3. So this patch will have to sit here until that is done, hopefully only a few days. Thanks for the quick reviews! Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/22] pci: Add a function to find a device by class
There is an existing function prototype in the header file but it is not
implemented. Implement something similar.
Signed-off-by: Simon Glass
---
Changes in v2:
- Fix missing spaces (code style nit)
- Add another comment in pci_find_class()
drivers/pci/pci.c | 43 +++
include/pci.h | 3 +--
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 950a247..0210e41 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -15,6 +15,7 @@
#include
#include
+#include
#include
#include
#include
@@ -236,6 +237,48 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int
index)
return -1;
}
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+ int bus;
+ int devnum;
+ pci_dev_t bdf;
+ uint32_t class;
+
+ for (bus = 0; bus <= pci_last_busno(); bus++) {
+ for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
+ pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+ PCI_CLASS_REVISION, &class);
+ if (class >> 16 == 0x)
+ continue;
+
+ for (bdf = PCI_BDF(bus, devnum, 0);
+ bdf <= PCI_BDF(bus, devnum,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ bdf += PCI_BDF(0, 0, 1)) {
+ pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+ &class);
+ class >>= 8;
+
+ if (class != find_class)
+ continue;
+ /*
+* Decrement the index. We want to return the
+* correct device, so index is 0 for theh first
+* matching device, 1 for the second, etc.
+*/
+ if (index) {
+ index--;
+ continue;
+ }
+ /* Return index'th controller. */
+ return bdf;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
struct pci_device_id ids[2] = { {}, {0, 0} };
diff --git a/include/pci.h b/include/pci.h
index 4fbb8f6..004a048 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller
*hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device,
int index);
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
-extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
- int wanted_prog_if, int index);
+pci_dev_t pci_find_class(unsigned int find_class, int index);
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
--
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[U-Boot] [PATCH v2 18/22] x86: spi: Support ValleyView in ICH SPI driver
The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/spi/ich.c | 56 ---
drivers/spi/ich.h | 11 ++-
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index fdff158..da85779 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -21,6 +22,7 @@
struct ich_ctlr {
pci_dev_t dev; /* PCI device number */
int ich_version;/* Controller version, 7 or 9 */
+ bool use_sbase; /* Use SBASE instead of RCB */
int ichspi_lock;
int locked;
uint8_t *opmenu;
@@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (ctlr.ich_version == 7) {
+ if (ctlr.ich_version == 7 || ctlr.use_sbase) {
ich->slave.op_mode_rx = SPI_OPM_RX_AS;
ich->slave.op_mode_tx = SPI_OPM_TX_BP;
}
@@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id)
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
(device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
-device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
+ device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
return 9;
return 0;
@@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
return speed == 1;
}
-static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
+static int ich_find_spi_controller(struct ich_ctlr *ich)
{
int last_bus = pci_last_busno();
int bus;
if (last_bus == -1) {
debug("No PCI busses?\n");
- return -1;
+ return -ENODEV;
}
for (bus = 0; bus <= last_bus; bus++) {
@@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int
*ich_versionp)
device_id = ids >> 16;
if (vendor_id == PCI_VENDOR_ID_INTEL) {
- *devp = dev;
- *ich_versionp = get_ich_version(device_id);
- return 0;
+ ich->dev = dev;
+ ich->ich_version = get_ich_version(device_id);
+ if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
+ ich->use_sbase = true;
+ return ich->ich_version == 0 ? -ENODEV : 0;
}
}
debug("ICH SPI: No ICH found.\n");
- return -1;
+ return -ENODEV;
}
static int ich_init_controller(struct ich_ctlr *ctlr)
{
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
+ uint32_t sbase_addr;
+ uint8_t *sbase;
pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xc000);
+
+ /* SBASE is similar */
+ pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
+ sbase = (uint8_t *)(sbase_addr & 0xfe00);
+
if (ctlr->ich_version == 7) {
struct ich7_spi_regs *ich7_spi;
@@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
} else if (ctlr->ich_version == 9) {
struct ich9_spi_regs *ich9_spi;
- ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
+ if (ctlr->use_sbase)
+ ich9_spi = (struct ich9_spi_regs *)sbase;
+ else
+ ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = ich9_spi->opmenu;
ctlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
ctlr->ich_version);
return -1;
}
- debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
/* Work out the maximum speed we can support */
ctlr->max_speed = 2000;
if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
ctlr->max_speed = 3300;
+ debug("ICH SPI: Version %d detected at %p, speed %ld\n",
+ ctlr->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
@@ -298,7 +314,7 @@ void spi_init(void)
{
uint8_t bios_cntl;
- if (ich_fi
[U-Boot] [PATCH v2 12/22] x86: Adjust the FSP types slightly
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v2: None
arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 --
arch/x86/include/asm/fsp/fsp_api.h| 6 --
arch/x86/include/asm/fsp/fsp_support.h| 4 +++-
arch/x86/lib/fsp/fsp_support.c| 4 ++--
4 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
index bce58b1..3c57558 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -10,8 +10,6 @@
#ifndef __VPDHEADER_H__
#define __VPDHEADER_H__
-#define UPD_TERMINATOR 0x55AA
-
struct __packed upd_region {
u64 sign; /* Offset 0x */
u64 reserved; /* Offset 0x0008 */
diff --git a/arch/x86/include/asm/fsp/fsp_api.h
b/arch/x86/include/asm/fsp/fsp_api.h
index a9d7156..2d34d13 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -8,6 +8,8 @@
#ifndef __FSP_API_H__
#define __FSP_API_H__
+#include
+
/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
@@ -47,9 +49,9 @@ struct fsp_notify_params {
};
/* FspInit API function prototype */
-typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
+typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
/* FspNotify API function prototype */
-typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
+typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
#endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h
b/arch/x86/include/asm/fsp/fsp_support.h
index 6329cfe..c6c7dc0 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -26,6 +26,8 @@ struct shared_data {
#define FSP_LOWMEM_BASE0x10UL
#define FSP_HIGHMEM_BASE 0x1ULL
+#define UPD_TERMINATOR 0x55AA
+
/**
* FSP Continuation assembly helper routine
@@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32 status,
*
* @retval: the offset of FSP header. If signature is invalid, returns 0.
*/
-u32 find_fsp_header(void);
+struct fsp_header *find_fsp_header(void);
/**
* FSP initialization wrapper function.
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index f6ae85a..bf37807 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1,
return false;
}
-u32 __attribute__((optimize("O0"))) find_fsp_header(void)
+struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
{
/*
* This function may be called before the a stack is established,
@@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
fsp = 0;
}
- return (u32)fsp;
+ return (struct fsp_header *)fsp;
}
void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
--
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[U-Boot] [PATCH v2 14/22] x86: mmc: Move common FSP functions into a common file
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass
---
Changes in v2:
- Move MMC code into a new pci_mmc.c file
- Remove setup_early_uart() function prototype
arch/x86/cpu/queensbay/tnc.c | 27 ---
arch/x86/cpu/queensbay/tnc_pci.c | 15 ---
arch/x86/cpu/queensbay/topcliff.c | 33 +++
arch/x86/lib/fsp/Makefile | 1 +
arch/x86/lib/fsp/fsp_common.c | 55 +++
drivers/mmc/Makefile | 1 +
drivers/mmc/pci_mmc.c | 42 ++
include/mmc.h | 14 ++
8 files changed, 116 insertions(+), 72 deletions(-)
create mode 100644 arch/x86/lib/fsp/fsp_common.c
create mode 100644 drivers/mmc/pci_mmc.c
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f9b3bfa..30ab725 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -43,30 +43,3 @@ int arch_cpu_init(void)
return 0;
}
-
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- outb(0x06, PORT_RESET);
-}
-
-void board_final_cleanup(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
- status = fsp_notify(NULL, INIT_PHASE_BOOT);
- if (status != FSP_SUCCESS)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return;
-}
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 9b0b725..6c291f9 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
hose->region_count = 4;
}
-
-int board_pci_post_scan(struct pci_controller *hose)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
- status = fsp_notify(NULL, INIT_PHASE_PCI);
- if (status != FSP_SUCCESS)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return 0;
-}
diff --git a/arch/x86/cpu/queensbay/topcliff.c
b/arch/x86/cpu/queensbay/topcliff.c
index b01422a..9faf1b9 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -5,43 +5,16 @@
*/
#include
-#include
-#include
-#include
+#include
#include
-#include
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
- { }
};
int cpu_mmc_init(bd_t *bis)
{
- struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
- u32 iobase;
- int ret;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
-
- mmc_host = (struct sdhci_host *)malloc(sizeof(struct
sdhci_host));
- if (!mmc_host)
- return -ENOMEM;
-
- mmc_host->name = "Topcliff SDHCI";
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
- mmc_host->ioaddr = (void *)iobase;
- mmc_host->quirks = 0;
- ret = add_sdhci(mmc_host, 0, 0);
- if (ret)
- return ret;
- }
-
- return 0;
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
}
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 3a2bac0..5b12c12 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -5,5 +5,6 @@
#
obj-y += fsp_car.o
+obj-y += fsp_common.o
obj-y += fsp_dram.o
obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
new file mode 100644
index 000..f668259
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014, Bin Meng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ outb(0x06, PORT_RESET);
+}
+
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+ status = fsp_notify(NULL, INIT_PHASE_PCI);
+ if (st
[U-Boot] [PATCH v2 17/22] x86: Allow a UART to be set up before the FSP is ready
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.
Signed-off-by: Simon Glass
---
Changes in v2:
- Remove duplicate prototype of setup_early_uart()
arch/x86/include/asm/u-boot-x86.h | 3 +++
arch/x86/lib/fsp/fsp_support.c| 4
2 files changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/u-boot-x86.h
b/arch/x86/include/asm/u-boot-x86.h
index b98afa8..5d7dff5 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -45,6 +45,9 @@ ulong board_get_usable_ram_top(ulong total_size);
void dram_init_banksize(void);
int default_print_cpuinfo(void);
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_early_uart(void);
+
void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr);
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 8b639f7..5f96da1 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
struct fsp_init_params *params_ptr;
struct upd_region *fsp_upd;
+#ifdef CONFIG_DEBUG_UART
+ setup_early_uart();
+#endif
+
fsp_hdr = find_fsp_header();
if (fsp_hdr == NULL) {
/* No valid FSP info header was found */
--
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[U-Boot] [PATCH v2 01/22] x86: Enhance the microcode tool to support header files as input
Sometimes microcode is delivered as a header file. Allow the tool to
support this as well as collecting multiple microcode blocks into a
single update.
Signed-off-by: Simon Glass
Tested-by: Bin Meng
---
Changes in v2: None
tools/microcode-tool.py | 90 ++---
1 file changed, 70 insertions(+), 20 deletions(-)
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 003716d..71c2e91 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -76,6 +76,35 @@ def ParseFile(fname):
microcodes[name] = Microcode(name, data)
return date, license_text, microcodes
+def ParseHeaderFiles(fname_list):
+"""Parse a list of header files and return the component parts
+
+Args:
+fname_list: List of files to parse
+Returns:
+date: String containing date from the file's header
+license_text: List of text lines for the license file
+microcodes: List of Microcode objects from the file
+"""
+microcodes = {}
+license_text = []
+date = ''
+name = None
+for fname in fname_list:
+name = os.path.basename(fname).lower()
+name = os.path.splitext(name)[0]
+data = []
+with open(fname) as fd:
+for line in fd:
+line = line.rstrip()
+
+# Omit anything after the last comma
+words = line.split(',')[:-1]
+data += [word + ',' for word in words]
+microcodes[name] = Microcode(name, data)
+return date, license_text, microcodes
+
+
def List(date, microcodes, model):
"""List the available microcode chunks
@@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
break
return found, tried
-def CreateFile(date, license_text, mcode, outfile):
+def CreateFile(date, license_text, mcodes, outfile):
"""Create a microcode file in U-Boot's .dtsi format
Args:
date: String containing date of original microcode file
license:List of text lines for the license file
-mcode: Microcode object to write
+mcodes: Microcode objects to write (normally only 1)
outfile:Filename to write to ('-' for stdout)
"""
out = '''/*%s
@@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
data = <%s
\t>;'''
words = ''
-for i in range(len(mcode.words)):
-if not (i & 3):
-words += '\n'
-val = mcode.words[i]
-# Change each word so it will be little-endian in the FDT
-# This data is needed before RAM is available on some platforms so we
-# cannot do an endianness swap on boot.
-val = struct.unpack("I", val))[0]
-words += '\t%#010x' % val
+add_comments = len(mcodes) > 1
+for mcode in mcodes:
+if add_comments:
+words += '\n/* %s */' % mcode.name
+for i in range(len(mcode.words)):
+if not (i & 3):
+words += '\n'
+val = mcode.words[i]
+# Change each word so it will be little-endian in the FDT
+# This data is needed before RAM is available on some platforms so
+# we cannot do an endianness swap on boot.
+val = struct.unpack("I", val))[0]
+words += '\t%#010x' % val
+
+# Use the first microcode for the headers
+mcode = mcodes[0]
# Take care to avoid adding a space before a tab
text = ''
@@ -187,8 +223,8 @@ data = <%s
print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
os.makedirs(MICROCODE_DIR)
outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
-print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
- mcode.name, outfile)
+print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
+', '.join([mcode.name for mcode in mcodes]), outfile)
with open(outfile, 'w') as fd:
print >> fd, out % tuple(args)
@@ -198,8 +234,12 @@ def MicrocodeTool():
parser = OptionParser()
parser.add_option('-d', '--mcfile', type='string', action='store',
help='Name of microcode.dat file')
+parser.add_option('-H', '--headerfile', type='string', action='append',
+help='Name of .h file containing microcode')
parser.add_option('-m', '--model', type='string', action='store',
-help='Model name to extract')
+help="Model name to extract ('all' for all)")
+parser.add_option('-M', '--multiple', type='string', action='store',
+help="Allow output of multiple models")
parser.add_option('-o', '--outfile', type='string', action='store',
help='Filename to use for output (- for stdout), default
is'
' %s/.dtsi' % MICROCODE_DIR)
@@ -224,9 +264,14 @@ def MicrocodeTool():
if cmd
[U-Boot] [PATCH v2 16/22] x86: Allow FSP Kconfig settings for all x86
While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: None arch/x86/Kconfig | 38 ++ arch/x86/cpu/queensbay/Kconfig | 38 -- 2 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index bda7a0e..1b7955b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_ADDR + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc indicates that the binary must + be located at offset 0xc from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x200 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + source "arch/x86/cpu/coreboot/Kconfig" source "arch/x86/cpu/ivybridge/Kconfig" diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index f6b5201..397e599 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -11,44 +11,6 @@ config INTEL_QUEENSBAY if INTEL_QUEENSBAY -config HAVE_FSP - bool "Add an Firmware Support Package binary" - help - Select this option to add an Firmware Support Package binary to - the resulting U-Boot image. It is a binary blob which U-Boot uses - to set up SDRAM and other chipset specific initialization. - - Note: Without this binary U-Boot will not be able to set up its - SDRAM so will not boot. - -config FSP_FILE - string "Firmware Support Package binary filename" - depends on HAVE_FSP - default "fsp.bin" - help - The filename of the file to use as Firmware Support Package binary - in the board directory. - -config FSP_ADDR - hex "Firmware Support Package binary location" - depends on HAVE_FSP - default 0xfffc - help - FSP is not Position Independent Code (PIC) and the whole FSP has to - be rebased if it is placed at a location which is different from the - perferred base address specified during the FSP build. Use Intel's - Binary Configuration Tool (BCT) to do the rebase. - - The default base address of 0xfffc indicates that the binary must - be located at offset 0xc from the beginning of a 1MB flash device. - -config FSP_TEMP_RAM_ADDR - hex - default 0x200 - help - Stack top address which is used in FspInit after DRAM is ready and - CAR is disabled. - config HAVE_CMC bool "Add a Chipset Micro Code state machine binary" help -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 21/22] x86: Add some documentation on how to port U-Boot on x86
Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: - Document how to change the SPI speed with ifdtool doc/README.x86 | 64 ++ 1 file changed, 64 insertions(+) diff --git a/doc/README.x86 b/doc/README.x86 index ddfd75e..a9105f8 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -164,6 +164,70 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to mode to use. U-Boot sets up some reasonable values but you can adjust then with this command. +Development Flow + + +These notes are for those who want to port U-Boot to a new x86 platform. + +Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. +The Dediprog em100 can be used on Linux. The em100 tool is available here: + + http://review.coreboot.org/p/em100.git + +On Minnowboard Max the following command line can be used: + + sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r + +A suitable clip for connecting over the SPI flash chip is here: + + http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 + +This allows you to override the SPI flash contents for development purposes. +Typically you can write to the em100 in around 1200ms, considerably faster +than programming the real flash device each time. The only important +limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. +This means that images must be set to boot with that speed. This is an +Intel-specific feature - e.g. tools/ifttool has an option to set the SPI +speed in the SPI descriptor region. + +If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly +easy to fit it in. You can follow the Minnowboard Max implementation, for +example. Hopefully you will just need to create new files similar to those +in arch/x86/cpu/baytrail which provide Bay Trail support. + +If you are not using an FSP you have more freedom and more responsibility. +The ivybridge support works this way, although it still uses a ROM for +graphics and still has binary blobs containing Intel code. You should aim to +support all important peripherals on your platform including video and storage. +Use the device tree for configuration where possible. + +For the microcode you can create a suitable device tree file using the +microcode tool: + + ./tools/microcode-tool -d microcode.dat create + +or if you only have header files and not the full Intel microcode.dat database: + + ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ + -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ + create all + +These are written to arch/x86/dts/microcode/ by default. + +Note that it is possible to just add the micrcode for your CPU if you know its +model. U-Boot prints this information when it starts + + CPU: x86_64, vendor Intel, device 30673h + +so here we can use the M0130673322 file. + +If you platform can display POST codes on two little 7-segment displays on +the board, then you can use post_code() calls from C or assembler to monitor +boot progress. This can be good for debugging. + +If not, you can try to get serial working as early as possible. The early +debug serial port may be useful here. See setup_early_uart() for an example. + TODO List - - Audio -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/22] usb: pci: Add XHCI driver for PCI
Add a driver which locates the available XHCI controllers on the PCI bus
and makes them available.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-pci.c | 60 +
2 files changed, 61 insertions(+)
create mode 100644 drivers/usb/host/xhci-pci.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c11b551..66d6e9a 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
new file mode 100644
index 000..361fcce
--- /dev/null
+++ b/drivers/usb/host/xhci-pci.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015, Google, Inc
+ * Written by Simon Glass
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+
+#include "xhci.h"
+
+/*
+ * Create the appropriate control structures to manage a new XHCI host
+ * controller.
+ */
+int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
+ struct xhci_hcor **ret_hcor)
+{
+ struct xhci_hccr *hccr;
+ struct xhci_hcor *hcor;
+ pci_dev_t pdev;
+ uint32_t cmd;
+ int len;
+
+ pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
+ if (pdev < 0) {
+ printf("XHCI host controller not found\n");
+ return -1;
+ }
+
+ hccr = (struct xhci_hccr *)pci_map_bar(pdev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
+ hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
+
+ debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor, len);
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ /* enable busmaster */
+ pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding * to the XHCI host
+ * controller
+ */
+void xhci_hcd_stop(int index)
+{
+}
--
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[U-Boot] [PATCH v2 19/22] scsi: bootstage: Measure time taken to scan the bus
On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
common/cmd_scsi.c | 2 ++
include/bootstage.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index cbc107e..a0a62eb 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -217,8 +217,10 @@ void scsi_init(void)
(busdevfunc >> 8) & 0x7);
}
#endif
+ bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
scsi_low_level_init(busdevfunc);
scsi_scan(1);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
}
#endif
diff --git a/include/bootstage.h b/include/bootstage.h
index df13ab2..6b7588d 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -194,6 +194,7 @@ enum bootstage_id {
BOOTSTAGE_ID_MAIN_CPU_READY,
BOOTSTAGE_ID_ACCUM_LCD,
+ BOOTSTAGE_ID_ACCUM_SCSI,
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,
--
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[U-Boot] [PATCH v2 15/22] x86: Remove unnecessary casts and fix comment typos
Tidy up the FSP support code a little.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index bf37807..8b639f7 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -124,25 +124,25 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
struct fsp_init_params *params_ptr;
struct upd_region *fsp_upd;
- fsp_hdr = (struct fsp_header *)find_fsp_header();
+ fsp_hdr = find_fsp_header();
if (fsp_hdr == NULL) {
/* No valid FSP info header was found */
panic("Invalid FSP header");
}
- fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
+ fsp_upd = &shared_data.fsp_upd;
memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
/* Reserve a gap in stack top */
rt_buf.common.stack_top = (u32 *)stack_top - 32;
rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
+ rt_buf.common.upd_data = fsp_upd;
/* Get VPD region start */
fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
- /* Verifify the VPD data region is valid */
+ /* Verify the VPD data region is valid */
assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
(fsp_vpd->sign == VPD_IMAGE_ID));
@@ -150,7 +150,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
sizeof(struct upd_region));
- /* Verifify the UPD data region is valid */
+ /* Verify the UPD data region is valid */
assert(fsp_upd->terminator == UPD_TERMINATOR);
/* Override any UPD setting if required */
--
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[U-Boot] [PATCH v2 08/22] x86: Rename MMCONF_BASE_ADDRESS and make it common across x86
This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass --- Changes in v2: - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments arch/x86/Kconfig | 14 ++ arch/x86/cpu/ivybridge/sdram.c| 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- board/google/chromebook_link/Kconfig | 3 +-- 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..bda7a0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig" source "board/intel/crownbay/Kconfig" +config PCIE_ECAM_BASE + hex +default 0xe000 + help + This is the memory-mapped address of PCI configuration space, which + is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. It can be set up almost + anywhere. Before it is set up, it is possible to access PCI + configuration space through I/O access, but memory access is more + convenient. Using this, PCI can be scanned and configured. This + should be set to a region that does not conflict with memory + assigned to PCI devices - i.e. the memory and prefetch regions, as + passed to pci_set_region(). + endmenu diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4963448..766b385 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -757,7 +757,7 @@ int dram_init(void) .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_PCIE_ECAM_BASE, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x400, .wdbsize = 0x1000, diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index cf7457f..c960525 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,7 +43,7 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f3..ea45472 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192 -config MMCONF_BASE_ADDRESS - hex +config PCIE_ECAM_BASE default 0xf000 config EARLY_POST_CROS_EC -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 07/22] x86: Add an option to enabling building a ROM file
Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built. We cannot do this by default since it requires binary blobs. Without these the build will fail. Signed-off-by: Simon Glass --- Changes in v2: - Fix README typos Makefile | 5 +++-- doc/README.x86 | 10 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index a876f1f..c6e4ad1 100644 --- a/Makefile +++ b/Makefile @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf -# We can't do this yet due to the need for binary blobs -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +ifneq ($(BUILD_ROM),) +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +endif # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) diff --git a/doc/README.x86 b/doc/README.x86 index 7df8cc5..ddfd75e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by uncommenting the following line in the main U-Boot Makefile: +on by enabling the ROM build: -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +$ export BUILD_ROM=y + +This tells the Makefile to build u-boot.rom as a target. Link-specific instructions: @@ -126,11 +128,11 @@ Make sure 0x111 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the symbol address of _start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to -use CONFIG_OF_EMBED. +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. CPU Microcode - -Modern CPU usually requires a special bit stream called microcode [5] to be +Modern CPUs usually require a special bit stream called microcode [5] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree. -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 05/22] usb: pci: Use pci_find_class() to find the device
Use the new utility function instead of local code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/usb/host/ehci-pci.c | 53 +
1 file changed, 1 insertion(+), 52 deletions(-)
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 991b199..b9eabc5 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -34,57 +34,6 @@ static struct pci_device_id ehci_pci_ids[] = {
{0, 0}
};
#else
-static pci_dev_t ehci_find_class(int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus <= pci_last_busno(); bus++) {
- for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, &class);
- if (class >> 16 == 0x)
- continue;
-
- for (bdf = PCI_BDF(bus, devnum, 0);
- bdf <= PCI_BDF(bus, devnum,
- PCI_MAX_PCI_FUNCTIONS - 1);
- bdf += PCI_BDF(0, 0, 1)) {
- pci_read_config_dword(bdf, PCI_CLASS_REVISION,
- &class);
- class >>= 8;
- /*
-* Here be dragons! In case we have multiple
-* PCI EHCI controllers, this function will
-* be called multiple times as well. This
-* function will scan the PCI busses, always
-* starting from bus 0, device 0, function 0,
-* until it finds an USB controller. The USB
-* stack gives us an 'index' of a controller
-* that is currently being registered, which
-* is a number, starting from 0 and growing
-* in ascending order as controllers are added.
-* To avoid probing the same controller in tne
-* subsequent runs of this function, we will
-* skip 'index - 1' detected controllers and
-* report the index'th controller.
-*/
- if (class != PCI_CLASS_SERIAL_USB_EHCI)
- continue;
- if (index) {
- index--;
- continue;
- }
- /* Return index'th controller. */
- return bdf;
- }
- }
- }
-
- return -ENODEV;
-}
#endif
/*
@@ -102,7 +51,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
#ifdef CONFIG_PCI_EHCI_DEVICE
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
#else
- pdev = ehci_find_class(index);
+ pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
#endif
if (pdev < 0) {
printf("EHCI host controller not found\n");
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 04/22] x86: video: Enable video for Minnowboard Max
This board uses a new PCI ID.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/video/vesa_fb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 3dacafd..3a0fea2 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -23,6 +23,7 @@ struct pci_device_id vesa_video_ids[] = {
{ .vendor = 0x1002, .device = 0x5159 },
{ .vendor = 0x1002, .device = 0x4752 },
{ .vendor = 0x1002, .device = 0x5452 },
+ { .vendor = 0x8086, .device = 0x0f31 },
{},
};
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 03/22] x86: pci: Add PCI IDs for Minnowboard Max
This board includes a few IDs we have not seen before. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: None include/pci_ids.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/pci_ids.h b/include/pci_ids.h index 26f4748..1012abe 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1346,6 +1346,7 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 @@ -2594,6 +2595,10 @@ #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO0x0f15 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA0x0f23 #define PCI_DEVICE_ID_INTEL_82541ER0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/22] x86: Move common FSP code into a common location
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/queensbay/Makefile| 2 +-
arch/x86/cpu/queensbay/fsp_configs.c | 2 +-
arch/x86/cpu/queensbay/tnc.c | 2 +-
arch/x86/cpu/queensbay/tnc_dram.c | 2 +-
arch/x86/cpu/queensbay/tnc_pci.c | 2 +-
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h| 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h| 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h| 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h | 0
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h| 2 +-
arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h | 0
arch/x86/lib/Makefile | 1 +
arch/x86/lib/cmd_hob.c | 2 +-
arch/x86/lib/fsp/Makefile | 7 +++
arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 2 +-
18 files changed, 16 insertions(+), 8 deletions(-)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (99%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
create mode 100644 arch/x86/lib/fsp/Makefile
rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (99%)
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 2c2ec01..b3e7d87 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,5 +5,5 @@
#
obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
-obj-y += fsp_configs.o fsp_support.o
+obj-y += fsp_configs.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/fsp_configs.c
b/arch/x86/cpu/queensbay/fsp_configs.c
index af28e45..78bc966 100644
--- a/arch/x86/cpu/queensbay/fsp_configs.c
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -6,7 +6,7 @@
*/
#include
-#include
+#include
void update_fsp_upd(struct upd_region *fsp_upd)
{
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8637cdc..f9b3bfa 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -9,7 +9,7 @@
#include
#include
#include
-#include
+#include
#include
static void unprotect_spi_flash(void)
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c
b/arch/x86/cpu/queensbay/tnc_dram.c
index df79a39..4c0a7c8 100644
--- a/arch/x86/cpu/queensbay/tnc_dram.c
+++ b/arch/x86/cpu/queensbay/tnc_dram.c
@@ -5,7 +5,7 @@
*/
#include
-#include
+#include
#include
#include
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 39bff49..9b0b725 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
b/arch/x86/include/asm/fsp/fsp_api.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
rename to arch/x86/include/asm/fsp/fsp_api.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
b/arch/x86/include/asm/fsp/fsp_bootmode.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
rename to arch/x86/include/asm/fsp/fsp_bootmode.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
b/arch/x86/include/asm/fsp/fsp_ffs.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
rename to arch/x86/include/asm/fsp/fsp_ffs.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
b/arch/x86/include/asm/fsp/fsp_fv.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
rename to arch/x86/include/asm/fsp/fsp_fv.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
b/arch/x86/include/asm/fsp/fsp_hob.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
rename to arch/x86/include/asm/fsp/fsp_hob.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
b/arch/x86/include/asm/fsp/fsp_infoheader.h
similarity inde
[U-Boot] [PATCH v2 09/22] x86: video: Allow video ROM execution to fall back to the other method
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Rename pci_rom_emul_t to pci_rom_emul
arch/x86/cpu/ivybridge/gma.c | 3 ++-
drivers/pci/pci_rom.c| 32 +---
drivers/video/vesa_fb.c | 6 +++---
include/pci_rom.h| 15 +--
4 files changed, 43 insertions(+), 13 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 6cf9654..821ea25 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller
*hose,
#ifdef CONFIG_VIDEO
start = get_timer(0);
- ret = pci_run_vga_bios(dev, int15_handler, false);
+ ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index eb76591..0796179 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -228,11 +228,12 @@ int vbe_get_video_info(struct graphic_device *gdev)
#endif
}
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int
exec_method)
{
struct pci_rom_header *rom, *ram;
int vesa_mode = -1;
uint16_t class;
+ bool emulate;
int ret;
/* Only execute VGA ROMs */
@@ -262,6 +263,29 @@ int pci_run_vga_bios(pci_dev_t dev, int
(*int15_handler)(void), bool emulate)
vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
#endif
debug("Selected vesa mode %#x\n", vesa_mode);
+
+ if (exec_method & PCI_ROM_USE_NATIVE) {
+#ifdef CONFIG_X86
+ emulate = false;
+#else
+ if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
+ printf("BIOS native execution is only available on
x86\n");
+ return -ENOSYS;
+ }
+ emulate = true;
+#endif
+ } else {
+#ifdef CONFIG_BIOSEMU
+ emulate = true;
+#else
+ if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
+ printf("BIOS emulation not available - see
CONFIG_BIOSEMU\n");
+ return -ENOSYS;
+ }
+ emulate = false;
+#endif
+ }
+
if (emulate) {
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
@@ -274,9 +298,6 @@ int pci_run_vga_bios(pci_dev_t dev, int
(*int15_handler)(void), bool emulate)
vesa_mode, &mode_info);
if (ret)
return ret;
-#else
- printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
- return -ENOSYS;
#endif
} else {
#ifdef CONFIG_X86
@@ -284,9 +305,6 @@ int pci_run_vga_bios(pci_dev_t dev, int
(*int15_handler)(void), bool emulate)
bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
&mode_info);
-#else
- printf("BIOS native execution is only available on x86\n");
- return -ENOSYS;
#endif
}
debug("Final vesa mode %#x\n", mode_info.video_mode);
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 3a0fea2..9164f8d 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -42,8 +42,8 @@ void *video_hw_init(void)
printf("no card detected\n");
return NULL;
}
- printf("bdf %x\n", dev);
- ret = pci_run_vga_bios(dev, NULL, true);
+ ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
return NULL;
@@ -59,7 +59,7 @@ void *video_hw_init(void)
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
- debug("Framex buffer at %x\n", gdev->pciBase);
+ debug("Frame buffer at %x\n", gdev->pciBase);
return (void *)gdev;
}
diff --git a/include/pci_rom.h b/include/pci_rom.h
index 4ba36eb..2f1665d 100644
--- a/include/pci_rom.h
+++ b/include/pci_rom.h
@@ -33,14 +33,25 @@ struct pci_rom_data {
uint16_t reserved_2;
};
+/*
+ * Determines which execution method is used and whether we allow falling back
+ * to the other if the requested method is not available.
+ */
+enum pci_rom_emul {
+ PCI_ROM_EMULATE = 0 << 0,
+ PCI_ROM_USE_NATIVE = 1 << 0,
+ PCI_ROM_ALLOW_FALLBACK = 1 << 1,
+};
+
/**
* pci_run_vga_bios() - Run the VG
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi Joonyoung,
On 27 January 2015 at 22:12, Joonyoung Shim wrote:
> Hi Simon,
>
> On 01/28/2015 02:01 PM, Simon Glass wrote:
>> Hi Joonyoung,
>>
>> On 27 January 2015 at 21:46, Joonyoung Shim wrote:
>>> Hi Simon,
>>>
>>> On 01/28/2015 01:09 PM, Simon Glass wrote:
Hi,
On 15 January 2015 at 23:09, Joonyoung Shim
wrote:
> Hi,
>
> On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
>> We planned to fetch peripheral rate through one generic API per
>> peripheral. These generic peripheral functions are in turn
>> expected to fetch apt values from a function refactored as
>> per SoC versions. This patch adds support for fetching peripheral
>> rates for Exynos5420 and Exynos5800.
>>
>> Signed-off-by: Akshay Saraswat
>> ---
>> Changes since v2:
>> - Fixed enum and exynos542x_get_periph_rate switch.
>> - Added checks for negative values in exynos542x_get_periph_rate.
>>
>> Changes since v1:
>> - Changes suuport -> support in commit message.
>> - Removed position change of exynos5420_get_pll_clk.
>> - Removed #ifdef.
>>
>> arch/arm/cpu/armv7/exynos/clock.c | 151
>> +++--
>> arch/arm/include/asm/arch-exynos/clk.h | 3 +
>> 2 files changed, 147 insertions(+), 7 deletions(-)
What else needs to be done to get this applied, please?
>>>
>>> As i said, current this patch has some problem like mask bits, so eMMC
>>> doesn't work normally.
>>>
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 5dc9ed2..ee6c13b 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -27,7 +27,7 @@ struct clk_bit_info {
>> };
>>
>> /* periph_id src_bit div_bit prediv_bit */
>> -static struct clk_bit_info clk_bit_info[] = {
>> +static struct clk_bit_info exynos5_bit_info[] = {
>> {PERIPH_ID_UART0, 0, 0, -1},
>> {PERIPH_ID_UART1, 4, 4, -1},
>> {PERIPH_ID_UART2, 8, 8, -1},
>> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
>> {PERIPH_ID_NONE,-1, -1, -1},
>> };
>>
>> +static struct clk_bit_info exynos542x_bit_info[] = {
>> + {PERIPH_ID_UART0, 4, 8, -1},
>> + {PERIPH_ID_UART1, 8, 12, -1},
>> + {PERIPH_ID_UART2, 12, 16, -1},
>> + {PERIPH_ID_UART3, 16, 20, -1},
>> + {PERIPH_ID_I2C0,-1, 8, -1},
>> + {PERIPH_ID_I2C1,-1, 8, -1},
>> + {PERIPH_ID_I2C2,-1, 8, -1},
>> + {PERIPH_ID_I2C3,-1, 8, -1},
>> + {PERIPH_ID_I2C4,-1, 8, -1},
>> + {PERIPH_ID_I2C5,-1, 8, -1},
>> + {PERIPH_ID_I2C6,-1, 8, -1},
>> + {PERIPH_ID_I2C7,-1, 8, -1},
>> + {PERIPH_ID_SPI0,20, 20, 8},
>> + {PERIPH_ID_SPI1,24, 24, 16},
>> + {PERIPH_ID_SPI2,28, 28, 24},
>> + {PERIPH_ID_SDMMC0, 0, 0, -1},
>> + {PERIPH_ID_SDMMC1, 4, 10, -1},
>> + {PERIPH_ID_SDMMC2, 8, 20, -1},
>> + {PERIPH_ID_I2C8,-1, 8, -1},
>> + {PERIPH_ID_I2C9,-1, 8, -1},
>> + {PERIPH_ID_I2S0,0, 0, 4},
>> + {PERIPH_ID_I2S1,4, 12, 16},
>> + {PERIPH_ID_SPI3,12, 16, 0},
>> + {PERIPH_ID_SPI4,16, 20, 8},
>> + {PERIPH_ID_SDMMC4, 16, 0, 8},
>> + {PERIPH_ID_PWM0,24, 28, -1},
>> + {PERIPH_ID_PWM1,24, 28, -1},
>> + {PERIPH_ID_PWM2,24, 28, -1},
>> + {PERIPH_ID_PWM3,24, 28, -1},
>> + {PERIPH_ID_PWM4,24, 28, -1},
>> + {PERIPH_ID_I2C10, -1, 8, -1},
>> +
>> + {PERIPH_ID_NONE,-1, -1, -1},
>> +};
>> +
>> /* Epll Clock division values to achive different frequency output */
>> static struct set_epll_con_val exynos5_epll_div[] = {
>> { 19200, 0, 48, 3, 1, 0 },
>> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
>> pllreg)
>> static struct clk_bit_info *get_clk_bit_info(int peripheral)
>> {
>> int i;
>> + struct clk_bit_info *info;
>>
>> - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
>> - if (clk_bit_info[i].id == peripheral)
>> + if (proid_is_exynos5420() || proid_is_exynos5800())
>> + info = exynos542x_bit_info;
>> + else
>> + info = exynos5_bit_inf
[U-Boot] [PATCH v2 0/22] x86: Add bare support for Intel Minnowboard Max
This series adds support for the Intel Minnowboard Max (called Minnowmax for short). Along the way a few refactors and additions are made: - The Intel Firmware Support Package support is moved from queensbay to a common location - PCI support for XHCI is added - A few tweaks are made to the PCI support - Support for the debug UART (early debug output) is provided - The microcode tool now also supports reading in header files This board has been lightly tested. The following seem to work: - USB2 on the blue port (not USB3), e.g. for keyboard - Ethernet - HDMI out and console - UART - uSD card - SPI SATA is detected but I have not attached a drive to try it. USB3 shows signs of life but does not detect a USB stick, and crashes when trying to use a USB Ethernet adaptor. For SPI some parts cannot be read and others cannot be written. This seems to be a feature of the Intel hardware configuration. It may be possible to fix this using the SPI registers but I cannot work out how / lost interest trying. So far, addresses from 50 to 70 can be used. I have not tried the ICH GPIO driver but it likely needs work before it will function. I2C is not supported as there is currently no U-Boot driver for this. The zboot command can be used to start a bzImage kernel. Verified boot is supported - use mkimage to sign images as described in this walk-through: doc/uImage.FIT/beaglebone_vboot.txt Boot time is grim: - 1423ms to set up display (Intel FSP) - 454ms to scan AHCI (when no devices are connected) - ~1000ms to power up and start cache-as-RAM init (Intel FSP) (this is not benchmarked, may be inaccurate) - ~950ms to set up memory and initial machine configuration (Intel FSP) (this is not benchmarked, may be inaccurate) So it takes over 4 seconds to get to booting a kernel. Implementing the Memory Reference Code (MRC) cache should improve this slightly (perhaps a reduction of 500-1000ms). This cache is implemented for ivybridge so that code needs to be moved into a generic x86 directory and plumbed into the FSP code. This has not been done in this series. Also the video and SATA/AHCI can be disabled if preferred. It is also possible to run as a coreboot payload. See the instructions in README.x86 for this. In this case video does not work since coreboot does not pass through the VESA display information. To support the single-core 1GB variant, changes would need to be made to arch/x86/cpu/baytrail/fsp_configs.c to select different values for the memory. The microcode update may need to change also. This series is available at u-boot-x86 branch minnow-working. Changes in v2: - Fix missing spaces (code style nit) - Add another comment in pci_find_class() - Fix README typos - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments - Rename pci_rom_emul_t to pci_rom_emul - Move MMC code into a new pci_mmc.c file - Remove setup_early_uart() function prototype - Remove duplicate prototype of setup_early_uart() - Document how to change the SPI speed with ifdtool - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file - Add comment about FSP setting PCIE_ECAM_BASE - Put baytrail Kconfig in alphabetical order - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart() - Fix compatible string for SPI flash - Remove commented-out DEBUG_UART_CLOCK baud rate - Rename 'Coreboot' to 'coreboot' in README.x86 Simon Glass (22): x86: Enhance the microcode tool to support header files as input pci: Add a function to find a device by class x86: pci: Add PCI IDs for Minnowboard Max x86: video: Enable video for Minnowboard Max usb: pci: Use pci_find_class() to find the device usb: pci: Add XHCI driver for PCI x86: Add an option to enabling building a ROM file x86: Rename MMCONF_BASE_ADDRESS and make it common across x86 x86: video: Allow video ROM execution to fall back to the other method x86: bootstage: Add time measurement for vesa start-up x86: Move common FSP code into a common location x86: Adjust the FSP types slightly x86: Make CAR and DRAM FSP code common x86: mmc: Move common FSP functions into a common file x86: Remove unnecessary casts and fix comment typos x86: Allow FSP Kconfig settings for all x86 x86: Allow a UART to be set up before the FSP is ready x86: spi: Support ValleyView in ICH SPI driver scsi: bootstage: Measure time taken to scan the bus x86: Enable bootstage features x86: Add some documentation on how to port U-Boot on x86 x86: Add support for Intel Minnowboard Max Makefile |5 +- arch/x86/Kconfig | 67 + arch/x86/cpu/Makefile |1 + arch/x86/cpu/baytrail/Kconfig |9 + arch/x86/cpu/baytrail/Makefile | 10 + arch/x86/cpu/baytrail/early_uart.c | 78 + arch/x86/cpu/baytrail/fsp_configs.c| 156 + ar
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi Simon,
On 01/28/2015 02:01 PM, Simon Glass wrote:
> Hi Joonyoung,
>
> On 27 January 2015 at 21:46, Joonyoung Shim wrote:
>> Hi Simon,
>>
>> On 01/28/2015 01:09 PM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 15 January 2015 at 23:09, Joonyoung Shim wrote:
Hi,
On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
> We planned to fetch peripheral rate through one generic API per
> peripheral. These generic peripheral functions are in turn
> expected to fetch apt values from a function refactored as
> per SoC versions. This patch adds support for fetching peripheral
> rates for Exynos5420 and Exynos5800.
>
> Signed-off-by: Akshay Saraswat
> ---
> Changes since v2:
> - Fixed enum and exynos542x_get_periph_rate switch.
> - Added checks for negative values in exynos542x_get_periph_rate.
>
> Changes since v1:
> - Changes suuport -> support in commit message.
> - Removed position change of exynos5420_get_pll_clk.
> - Removed #ifdef.
>
> arch/arm/cpu/armv7/exynos/clock.c | 151
> +++--
> arch/arm/include/asm/arch-exynos/clk.h | 3 +
> 2 files changed, 147 insertions(+), 7 deletions(-)
>>>
>>> What else needs to be done to get this applied, please?
>>>
>>
>> As i said, current this patch has some problem like mask bits, so eMMC
>> doesn't work normally.
>>
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 5dc9ed2..ee6c13b 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -27,7 +27,7 @@ struct clk_bit_info {
> };
>
> /* periph_id src_bit div_bit prediv_bit */
> -static struct clk_bit_info clk_bit_info[] = {
> +static struct clk_bit_info exynos5_bit_info[] = {
> {PERIPH_ID_UART0, 0, 0, -1},
> {PERIPH_ID_UART1, 4, 4, -1},
> {PERIPH_ID_UART2, 8, 8, -1},
> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
> {PERIPH_ID_NONE,-1, -1, -1},
> };
>
> +static struct clk_bit_info exynos542x_bit_info[] = {
> + {PERIPH_ID_UART0, 4, 8, -1},
> + {PERIPH_ID_UART1, 8, 12, -1},
> + {PERIPH_ID_UART2, 12, 16, -1},
> + {PERIPH_ID_UART3, 16, 20, -1},
> + {PERIPH_ID_I2C0,-1, 8, -1},
> + {PERIPH_ID_I2C1,-1, 8, -1},
> + {PERIPH_ID_I2C2,-1, 8, -1},
> + {PERIPH_ID_I2C3,-1, 8, -1},
> + {PERIPH_ID_I2C4,-1, 8, -1},
> + {PERIPH_ID_I2C5,-1, 8, -1},
> + {PERIPH_ID_I2C6,-1, 8, -1},
> + {PERIPH_ID_I2C7,-1, 8, -1},
> + {PERIPH_ID_SPI0,20, 20, 8},
> + {PERIPH_ID_SPI1,24, 24, 16},
> + {PERIPH_ID_SPI2,28, 28, 24},
> + {PERIPH_ID_SDMMC0, 0, 0, -1},
> + {PERIPH_ID_SDMMC1, 4, 10, -1},
> + {PERIPH_ID_SDMMC2, 8, 20, -1},
> + {PERIPH_ID_I2C8,-1, 8, -1},
> + {PERIPH_ID_I2C9,-1, 8, -1},
> + {PERIPH_ID_I2S0,0, 0, 4},
> + {PERIPH_ID_I2S1,4, 12, 16},
> + {PERIPH_ID_SPI3,12, 16, 0},
> + {PERIPH_ID_SPI4,16, 20, 8},
> + {PERIPH_ID_SDMMC4, 16, 0, 8},
> + {PERIPH_ID_PWM0,24, 28, -1},
> + {PERIPH_ID_PWM1,24, 28, -1},
> + {PERIPH_ID_PWM2,24, 28, -1},
> + {PERIPH_ID_PWM3,24, 28, -1},
> + {PERIPH_ID_PWM4,24, 28, -1},
> + {PERIPH_ID_I2C10, -1, 8, -1},
> +
> + {PERIPH_ID_NONE,-1, -1, -1},
> +};
> +
> /* Epll Clock division values to achive different frequency output */
> static struct set_epll_con_val exynos5_epll_div[] = {
> { 19200, 0, 48, 3, 1, 0 },
> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
> pllreg)
> static struct clk_bit_info *get_clk_bit_info(int peripheral)
> {
> int i;
> + struct clk_bit_info *info;
>
> - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
> - if (clk_bit_info[i].id == peripheral)
> + if (proid_is_exynos5420() || proid_is_exynos5800())
> + info = exynos542x_bit_info;
> + else
> + info = exynos5_bit_info;
> +
> + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
> + if (info[i].id == peripheral)
> break;
> }
>
> -
Re: [U-Boot] [PATCH] patman: Make dry-run output match real functionality
On 27 January 2015 at 08:40, Peter Tyser wrote: > > On Mon, 2015-01-26 at 22:21 -0700, Simon Glass wrote: >> Hi Peter, >> >> On 26 January 2015 at 10:42, Peter Tyser wrote: >> > When run with the --dry-run argument patman prints out information >> > showing what it would do. This information currently doesn't line up >> > with what patman/git send-email really do. Some basic examples: >> > - If an email address is addressed via "Series-cc" and "Patch-cc" patman >> > shows that email address would be CC-ed two times. >> > - If an email address is addressed via "Series-to" and "Patch-cc" patman >> > shows that email address would be sent TO and CC-ed. >> > - If an email address is addressed from a combination of tag aliases, >> > get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows >> > that the email address would be CC-ed multiple times. >> > >> > Patman currently does try to send duplicate emails like the --dry-run >> > output shows, but "git send-email" intelligently removes duplicate >> > addresses so this patch shouldn't change the non-dry-run functionality. >> > >> > Change patman's output and email addressing to line up with the >> > "git send-email" logic. This trims down patman's dry-run output and >> > prevents confusion about what patman will do when emails are actually >> > sent. >> >> Thanks for the patch, it's good to match up with git send-email. >> >> Are the rules that git send-email follows documented or obtained by >> trial and error? > > Trial and error initially. The git source code lined up with what I > saw (see the send_message function in git-send-email.perl). I didn't > see the policy documented officially, but what git does makes sense > to me: > - remove any duplicate addresses in the to: field > - remove all the to: addresses from the cc: addresses > - remove any duplicate cc: addresses > > This makes sure each email is only sent to an address one time, > with the to: field taking precedence over the cc: field. > > > For a recent NAND patch series it looked like I was going to send Scott > 2-4 emails per patch which is why I looked into it. Thanks. Acked-by: Simon Glass Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus
Hi, On 27 January 2015 at 18:20, Bin Meng wrote: > Hi Rob, > > On Wed, Jan 28, 2015 at 1:38 AM, Rob Herring wrote: >> On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass wrote: >>> On some hardware this time can be significant. Add bootstage support for >>> measuring this. The result can be obtained using 'bootstage report' or >>> passed on to the Linux via the device tree. >>> >>> Signed-off-by: Simon Glass >>> --- >>> >>> common/cmd_scsi.c | 2 ++ >>> include/bootstage.h | 1 + >>> 2 files changed, 3 insertions(+) >>> >>> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c >>> index cbc107e..a0a62eb 100644 >>> --- a/common/cmd_scsi.c >>> +++ b/common/cmd_scsi.c >>> @@ -217,8 +217,10 @@ void scsi_init(void) >>>(busdevfunc >> 8) & 0x7); >>> } >>> #endif >>> + bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); >>> scsi_low_level_init(busdevfunc); >>> scsi_scan(1); >>> + bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); >> >> This does not cover the case if the platform calls scsi_scan at boot. >> The first time is the important one as that will include disk spin-up >> time. >> >> Perhaps they shouldn't be and "scsi scan" should always be in boot scripts. >> > > scsi_init() is called in common/board_r.c, which already covers the > boot scan case. I think platform data is missing. Rob if you are able to test this I could send an updated patch? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi Joonyoung,
On 27 January 2015 at 21:46, Joonyoung Shim wrote:
> Hi Simon,
>
> On 01/28/2015 01:09 PM, Simon Glass wrote:
>> Hi,
>>
>> On 15 January 2015 at 23:09, Joonyoung Shim wrote:
>>> Hi,
>>>
>>> On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat
---
Changes since v2:
- Fixed enum and exynos542x_get_periph_rate switch.
- Added checks for negative values in exynos542x_get_periph_rate.
Changes since v1:
- Changes suuport -> support in commit message.
- Removed position change of exynos5420_get_pll_clk.
- Removed #ifdef.
arch/arm/cpu/armv7/exynos/clock.c | 151
+++--
arch/arm/include/asm/arch-exynos/clk.h | 3 +
2 files changed, 147 insertions(+), 7 deletions(-)
>>
>> What else needs to be done to get this applied, please?
>>
>
> As i said, current this patch has some problem like mask bits, so eMMC
> doesn't work normally.
>
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 5dc9ed2..ee6c13b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,7 +27,7 @@ struct clk_bit_info {
};
/* periph_id src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
+static struct clk_bit_info exynos5_bit_info[] = {
{PERIPH_ID_UART0, 0, 0, -1},
{PERIPH_ID_UART1, 4, 4, -1},
{PERIPH_ID_UART2, 8, 8, -1},
@@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
{PERIPH_ID_NONE,-1, -1, -1},
};
+static struct clk_bit_info exynos542x_bit_info[] = {
+ {PERIPH_ID_UART0, 4, 8, -1},
+ {PERIPH_ID_UART1, 8, 12, -1},
+ {PERIPH_ID_UART2, 12, 16, -1},
+ {PERIPH_ID_UART3, 16, 20, -1},
+ {PERIPH_ID_I2C0,-1, 8, -1},
+ {PERIPH_ID_I2C1,-1, 8, -1},
+ {PERIPH_ID_I2C2,-1, 8, -1},
+ {PERIPH_ID_I2C3,-1, 8, -1},
+ {PERIPH_ID_I2C4,-1, 8, -1},
+ {PERIPH_ID_I2C5,-1, 8, -1},
+ {PERIPH_ID_I2C6,-1, 8, -1},
+ {PERIPH_ID_I2C7,-1, 8, -1},
+ {PERIPH_ID_SPI0,20, 20, 8},
+ {PERIPH_ID_SPI1,24, 24, 16},
+ {PERIPH_ID_SPI2,28, 28, 24},
+ {PERIPH_ID_SDMMC0, 0, 0, -1},
+ {PERIPH_ID_SDMMC1, 4, 10, -1},
+ {PERIPH_ID_SDMMC2, 8, 20, -1},
+ {PERIPH_ID_I2C8,-1, 8, -1},
+ {PERIPH_ID_I2C9,-1, 8, -1},
+ {PERIPH_ID_I2S0,0, 0, 4},
+ {PERIPH_ID_I2S1,4, 12, 16},
+ {PERIPH_ID_SPI3,12, 16, 0},
+ {PERIPH_ID_SPI4,16, 20, 8},
+ {PERIPH_ID_SDMMC4, 16, 0, 8},
+ {PERIPH_ID_PWM0,24, 28, -1},
+ {PERIPH_ID_PWM1,24, 28, -1},
+ {PERIPH_ID_PWM2,24, 28, -1},
+ {PERIPH_ID_PWM3,24, 28, -1},
+ {PERIPH_ID_PWM4,24, 28, -1},
+ {PERIPH_ID_I2C10, -1, 8, -1},
+
+ {PERIPH_ID_NONE,-1, -1, -1},
+};
+
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
{ 19200, 0, 48, 3, 1, 0 },
@@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
pllreg)
static struct clk_bit_info *get_clk_bit_info(int peripheral)
{
int i;
+ struct clk_bit_info *info;
- for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
- if (clk_bit_info[i].id == peripheral)
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ info = exynos542x_bit_info;
+ else
+ info = exynos5_bit_info;
+
+ for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+ if (info[i].id == peripheral)
break;
}
- if (clk_bit_info[i].id == PERIPH_ID_NONE)
+ if (info[i].id == PERIPH_ID_NONE)
debug("ERROR: Peripheral ID %d not found\n", peripheral);
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi Simon,
On 01/28/2015 01:09 PM, Simon Glass wrote:
> Hi,
>
> On 15 January 2015 at 23:09, Joonyoung Shim wrote:
>> Hi,
>>
>> On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
>>> We planned to fetch peripheral rate through one generic API per
>>> peripheral. These generic peripheral functions are in turn
>>> expected to fetch apt values from a function refactored as
>>> per SoC versions. This patch adds support for fetching peripheral
>>> rates for Exynos5420 and Exynos5800.
>>>
>>> Signed-off-by: Akshay Saraswat
>>> ---
>>> Changes since v2:
>>> - Fixed enum and exynos542x_get_periph_rate switch.
>>> - Added checks for negative values in exynos542x_get_periph_rate.
>>>
>>> Changes since v1:
>>> - Changes suuport -> support in commit message.
>>> - Removed position change of exynos5420_get_pll_clk.
>>> - Removed #ifdef.
>>>
>>> arch/arm/cpu/armv7/exynos/clock.c | 151
>>> +++--
>>> arch/arm/include/asm/arch-exynos/clk.h | 3 +
>>> 2 files changed, 147 insertions(+), 7 deletions(-)
>
> What else needs to be done to get this applied, please?
>
As i said, current this patch has some problem like mask bits, so eMMC
doesn't work normally.
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>>> b/arch/arm/cpu/armv7/exynos/clock.c
>>> index 5dc9ed2..ee6c13b 100644
>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> @@ -27,7 +27,7 @@ struct clk_bit_info {
>>> };
>>>
>>> /* periph_id src_bit div_bit prediv_bit */
>>> -static struct clk_bit_info clk_bit_info[] = {
>>> +static struct clk_bit_info exynos5_bit_info[] = {
>>> {PERIPH_ID_UART0, 0, 0, -1},
>>> {PERIPH_ID_UART1, 4, 4, -1},
>>> {PERIPH_ID_UART2, 8, 8, -1},
>>> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
>>> {PERIPH_ID_NONE,-1, -1, -1},
>>> };
>>>
>>> +static struct clk_bit_info exynos542x_bit_info[] = {
>>> + {PERIPH_ID_UART0, 4, 8, -1},
>>> + {PERIPH_ID_UART1, 8, 12, -1},
>>> + {PERIPH_ID_UART2, 12, 16, -1},
>>> + {PERIPH_ID_UART3, 16, 20, -1},
>>> + {PERIPH_ID_I2C0,-1, 8, -1},
>>> + {PERIPH_ID_I2C1,-1, 8, -1},
>>> + {PERIPH_ID_I2C2,-1, 8, -1},
>>> + {PERIPH_ID_I2C3,-1, 8, -1},
>>> + {PERIPH_ID_I2C4,-1, 8, -1},
>>> + {PERIPH_ID_I2C5,-1, 8, -1},
>>> + {PERIPH_ID_I2C6,-1, 8, -1},
>>> + {PERIPH_ID_I2C7,-1, 8, -1},
>>> + {PERIPH_ID_SPI0,20, 20, 8},
>>> + {PERIPH_ID_SPI1,24, 24, 16},
>>> + {PERIPH_ID_SPI2,28, 28, 24},
>>> + {PERIPH_ID_SDMMC0, 0, 0, -1},
>>> + {PERIPH_ID_SDMMC1, 4, 10, -1},
>>> + {PERIPH_ID_SDMMC2, 8, 20, -1},
>>> + {PERIPH_ID_I2C8,-1, 8, -1},
>>> + {PERIPH_ID_I2C9,-1, 8, -1},
>>> + {PERIPH_ID_I2S0,0, 0, 4},
>>> + {PERIPH_ID_I2S1,4, 12, 16},
>>> + {PERIPH_ID_SPI3,12, 16, 0},
>>> + {PERIPH_ID_SPI4,16, 20, 8},
>>> + {PERIPH_ID_SDMMC4, 16, 0, 8},
>>> + {PERIPH_ID_PWM0,24, 28, -1},
>>> + {PERIPH_ID_PWM1,24, 28, -1},
>>> + {PERIPH_ID_PWM2,24, 28, -1},
>>> + {PERIPH_ID_PWM3,24, 28, -1},
>>> + {PERIPH_ID_PWM4,24, 28, -1},
>>> + {PERIPH_ID_I2C10, -1, 8, -1},
>>> +
>>> + {PERIPH_ID_NONE,-1, -1, -1},
>>> +};
>>> +
>>> /* Epll Clock division values to achive different frequency output */
>>> static struct set_epll_con_val exynos5_epll_div[] = {
>>> { 19200, 0, 48, 3, 1, 0 },
>>> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
>>> pllreg)
>>> static struct clk_bit_info *get_clk_bit_info(int peripheral)
>>> {
>>> int i;
>>> + struct clk_bit_info *info;
>>>
>>> - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
>>> - if (clk_bit_info[i].id == peripheral)
>>> + if (proid_is_exynos5420() || proid_is_exynos5800())
>>> + info = exynos542x_bit_info;
>>> + else
>>> + info = exynos5_bit_info;
>>> +
>>> + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
>>> + if (info[i].id == peripheral)
>>> break;
>>> }
>>>
>>> - if (clk_bit_info[i].id == PERIPH_ID_NONE)
>>> + if (info[i].id == PERIPH_ID_NONE)
>>> debug("ERROR: Peripheral ID %d not found\n", peripheral);
>>>
>>> - return &clk_bit_info[i];
>>> + return &info[i];
>>> }
>>>
>>> static unsigned long exynos5_get_periph_rate(int peripheral)
>>> @@ -414,12 +456,107 @@ static unsigned long exyn
Re: [U-Boot] [PATCH 11/11] Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800
Hi Akshay,
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> From: Doug Anderson
>
> It was found that the L2 cache timings that we had before could cause
> freezes and hangs. We should make things more robust with better
> timings. Currently the production ChromeOS kernel applies these
> timings, but it's nice to fixup firmware too (and upstream probably
> won't take our kernel hacks).
>
> This also provides a big cleanup of the L2 cache init code avoiding
> some duplication. The way things used to work:
> * low_power_start() was installed by the SPL (both at boot and resume
> time) and left resident in iRAM for the kernel to use when bringing
> up additional CPUs. It used configure_l2_ctlr() and
> configure_l2_actlr() when it detected it was on an A15. This was
> needed (despite the L2 cache registers being shared among all A15s)
> because we might have been the first man in after the whole A15
> cluster was shutdown.
> * secondary_cores_configure() was called on at boot time and at resume
> time. Strangely this called configure_l2_ctlr() but not
> configure_l2_actlr() which was almost certainly wrong. Given that
> we'll call both (see next bullet) later in the boot process it
> didn't matter for normal boot, but I guess this is how L2 cache
> settings got set on 5420/5800 (but not 5250?) at resume time.
> * exynos5_set_l2cache_params() was called as part of cache enablement.
> This should happen at boot time (normally in the SPL except for USB
> boot where it happens in main U-Boot).
>
> Note that the old code wasn't setting ECC/parity in the cache
> enablement code but we happened to get it anyway because we'd call
> secondary_cores_configure() at boot time. For resume time we'd get it
> anyway when the 2nd A15 core came up.
>
> Let's make this a whole lot simpler. Now we always set these
> parameters in the same place for all boots and use the same code for
> setting up secondary CPUs.
>
> Intended net effects of this change (other than cleanup):
> * Timings go from before:
> data: 0 cycle setup, 3 cycles (0x2) latency
> tag: 0 cycle setup, 3 cycles (0x2) latency
> after:
> data: 1 cycle setup, 4 cycles (0x3) latency
> tag: 1 cycle setup, 4 cycles (0x3) latency
> * L2ACTLR is properly initted on 5420/5800 in all cases.
>
> One note is that we're still relying on luck to keep low_power_start()
> working. The compiler is being nice and not storing anything on the
> stack.
>
> Another note is that on its own this patch won't help to fix cache
> settings in an RW U-Boot update where we still have the RO SPL. The
> plan for that is:
> * Have RW U-Boot re-init the cache right before calling the kernel
> (after it has turned the L2 cache off). This is why the functions
> are in a header file instead of lowlevel_init.c.
>
> * Have the kernel save the L2 cache settings of the boot CPU and apply
> them to all other CPUs. We get a little lucky here because the old
> code was using "|=" to modify the registers and all of the bits that
> it's setting are also present in the new settings (!). That means
> that when the 2nd CPU in the A15 cluster comes up it doesn't
> actually mess up the settings of the 1st CPU in the A15 cluster. An
> alternative option is to have the kernel write its own
> low_power_start() code.
>
> Signed-off-by: Doug Anderson
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/common_setup.h | 55
> +++
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 55
> +--
> arch/arm/cpu/armv7/exynos/soc.c | 51
> 3 files changed, 70 insertions(+), 91 deletions(-)
This causes a compilation error on snow, so needs to be adjusted.
Tested on pit, pi
Tested-by: Simon Glass
>
> diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h
> b/arch/arm/cpu/armv7/exynos/common_setup.h
> index e6318c0..7fa9683 100644
> --- a/arch/arm/cpu/armv7/exynos/common_setup.h
> +++ b/arch/arm/cpu/armv7/exynos/common_setup.h
> @@ -23,6 +23,8 @@
> * MA 02111-1307 USA
> */
>
> +#include
> +
> #define DMC_OFFSET 0x1
>
> /*
> @@ -43,3 +45,56 @@ void system_clock_init(void);
> int do_lowlevel_init(void);
>
> void sdelay(unsigned long);
> +
> +enum l2_cache_params {
> + CACHE_ECC_AND_PARITY = (1 << 21),
> + CACHE_TAG_RAM_SETUP = (1 << 9),
> + CACHE_DATA_RAM_SETUP = (1 << 5),
> +#ifndef CONFIG_EXYNOS5420
> + CACHE_TAG_RAM_LATENCY = (2 << 6), /* 5250 */
> + CACHE_DATA_RAM_LATENCY = (2 << 0),
> +#else
> + CACHE_TAG_RAM_LATENCY = (3 << 6), /* 5420 and 5422 */
> + CACHE_DATA_RAM_LATENCY = (3 << 0),
> +#endif
> +};
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +/*
> + * Configure L2CTLR to get timings that keep us from hanging/crashing.
> + *
> + * Must be inline here since low_power_start() is called without a
> + * stack (!).
> + */
> +static inline void configure_l2_ctlr(void)
> +{
> +
Re: [U-Boot] [PATCH 10/11] Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> On warm reset, all cores jump to the low_power_start function because iRAM
> data is retained and because while executing iROM code all cores find
> the jump flag 0x02020028 set. In low_power_start, cores check the reset
> status and if true they clear the jump flag and jump back to 0x0.
>
> The A7 cores do jump to 0x0 but consider following instructions as a Thumb
> instructions which in turn makes them loop inside the iROM code instead of
> jumping to power_down_core.
>
> This issue is fixed by replacing the "mov pc" instruction with a "bx"
> instruction which switches state along with the jump to make the execution
> unit consider the branch target as an ARM instruction.
>
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index d9f3f4b..a459432 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -124,7 +124,7 @@ static void low_power_start(void)
> reg_val = readl(RST_FLAG_REG);
> if (reg_val != RST_FLAG_VAL) {
> writel(0x0, CONFIG_LOWPOWER_FLAG);
> - set_pc(0x0);
> + branch_bx(0x0);
> }
>
> reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
> --
> 1.9.1
>
Reviewed-by: Simon Glass
Tested on snow, pit, pi
Tested-by: Simon Glass
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Re: [U-Boot] [PATCH 04/11] Exynos542x: Add workaround for ARM errata 799270
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> This patch adds workaround for the ARM errata 799270 which says
> "If the L2 cache logic clock is stopped because of L2 inactivity,
> setting or clearing the ACTLR.SMP bit might not be effective. The bit is
> modified in the ACTLR, meaning a read of the register returns the
> updated value. However the logic that uses that bit retains the previous
> value."
>
> Signed-off-by: Kimoon Kim
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index 7073c5c..3097382 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -45,6 +45,28 @@ enum {
>
> #ifdef CONFIG_EXYNOS5420
> /*
> + * Ensure that the L2 logic has been used within the previous 256 cycles
> + * before modifying the ACTLR.SMP bit. This is required during boot before
> + * MMU has been enabled, or during a specified reset or power down sequence.
> + */
> +void enable_smp(void)
> +{
> + uint32_t temp, val;
> +
> + /* Enable SMP mode */
> + mrc_auxr(temp);
> + temp |= (1 << 6);
> +
> + /* Dummy read to assure L2 access */
> + val = readl(INF_REG_BASE);
> + val &= 0;
> + temp |= val;
> + mcr_auxr(temp);
> + dsb();
> + isb();
> +}
> +
> +/*
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> * stalled for 1024 cycles to verify that its hazard condition still exists.
> */
> --
> 1.9.1
>
Reviewed-by: Simon Glass
Tested on snow, pit, pi
Tested-by: Simon Glass
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Re: [U-Boot] [PATCH 09/11] Exynos542x: Fix secondary core booting for thumb
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> When compiled SPL for Thumb secondary cores failed to boot
> at the kernel boot up. Only one core came up out of 4.
> This was happening because the code relocated to the
> address 0x02073000 by the primary core was an ARM asm
> code which was executed by the secondary cores as if it
> was a thumb code.
> This patch fixes the issue of secondary cores considering
> relocated code as Thumb instructions and not ARM instructions
> by jumping to the relocated with the help of "bx" ARM instruction.
> "bx" instruction changes the 5th bit of CPSR which allows
> execution unit to consider the following instructions as ARM
> instructions.
>
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
> arch/arm/include/asm/arch-exynos/system.h | 3 +++
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index 57b4c66..d9f3f4b 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -110,7 +110,7 @@ static void secondary_cpu_start(void)
> {
> enable_smp();
> svc32_mode_en();
> - set_pc(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
> + branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
> }
>
> /*
> diff --git a/arch/arm/include/asm/arch-exynos/system.h
> b/arch/arm/include/asm/arch-exynos/system.h
> index 86903c3..a9fd5e6 100644
> --- a/arch/arm/include/asm/arch-exynos/system.h
> +++ b/arch/arm/include/asm/arch-exynos/system.h
> @@ -75,6 +75,9 @@ struct exynos5_sysreg {
> /* Set program counter with the given value */
> #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
>
> +/* Branch to the given location */
> +#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
> +
> /* Read Main Id register */
> #define mrc_midr(x) __asm__ __volatile__ \
> ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
> --
> 1.9.1
>
Reviewed-by: Simon Glass
Tested on snow, pit, pi
Tested-by: Simon Glass
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Re: [U-Boot] [PATCH 01/11] Exynos542x: Config: Add various configs
On 15 January 2015 at 06:33, Akshay Saraswat wrote: > This patch adds "iRAM, CPU state and low power" configs > which are the addresses acting as flag registers. > > iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal > to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4). > This is a part of iROM logic. Rest other flags are being used at > various places during kernel switching and reset. > They are nowhere documented because they are part programming. > These configs are serving as flags for us because they are > representing the addresses in iRAM which we are using for > storing and extracting CPU Status and GIC status. > > Signed-off-by: Akshay Saraswat > --- > include/configs/exynos5-common.h | 28 > 1 file changed, 28 insertions(+) Reviewed-by: Simon Glass Tested on snow, pit, pi Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/11] Exynos542x: cache: Disable clean/evict push to external
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> L2 Auxiliary Control Register provides configuration
> and control options for the L2 memory system. Bit 3
> of L2ACTLR stands for clean/evict push to external.
> Setting bit 3 disables clean/evict which is what
> this patch intends to do.
>
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/soc.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
> index 8c7d7d8..7268b9b 100644
> --- a/arch/arm/cpu/armv7/exynos/soc.c
> +++ b/arch/arm/cpu/armv7/exynos/soc.c
> @@ -45,6 +45,15 @@ static void exynos5_set_l2cache_params(void)
> CACHE_DATA_RAM_LATENCY;
>
> asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
> +
> +#ifdef CONFIG_EXYNOS5420
> + /* Read CP15 L2ACTLR value */
> + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
> + /* Disable clean/evict push to external */
> + val |= (0x1 << 3);
> + /* Write new vlaue to L2ACTLR */
> + asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));
> +#endif
> }
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCH 08/11] Exynos542x: add L2 control register configuration
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> This patch does 3 things:
> 1. Enables ECC by setting 21st bit of L2CTLR.
> 2. Restore data and tag RAM latencies to 3 cycles because iROM sets
>0x3000400 L2CTLR value during switching.
> 3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
>We need to restore this here due to switching.
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 53
> +++
> arch/arm/cpu/armv7/exynos/soc.c | 7
> 2 files changed, 46 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index 688972b..57b4c66 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -67,24 +67,40 @@ static void enable_smp(void)
> }
>
> /*
> + * Enable ECC by setting L2CTLR[21].
> + * Set L2CTLR[7] to make tag ram latency 3 cycles and
> + * set L2CTLR[1] to make data ram latency 3 cycles.
> + * We need to make RAM latency of 3 cycles here because cores
> + * power ON and OFF while switching. And everytime a core powers
> + * ON, iROM provides it a default L2CTLR value 0x400 which stands
> + * for TAG RAM setup of 1 cycle. Hence, we face a need of
> + * restoring data and tag latency values.
> + */
> +static void configure_l2_ctlr(void)
> +{
> + uint32_t val;
> +
> + mrc_l2_ctlr(val);
> + val |= (1 << 21);
> + val |= (1 << 7);
> + val |= (1 << 1);
> + mcr_l2_ctlr(val);
> +}
> +
> +/*
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> * stalled for 1024 cycles to verify that its hazard condition still exists.
> + * Disable clean/evict push to external by setting L2ACTLR[3].
> */
> -static void configure_l2actlr(void)
> +static void configure_l2_actlr(void)
> {
> uint32_t val;
>
> - /* Read MIDR for Primary Part Number*/
> - mrc_midr(val);
> - val = (val >> 4);
> - val &= 0xf;
> -
> - /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
> - if (val == 0xf) {
> - mrc_l2_aux_ctlr(val);
> - val |= (1 << 7);
> - mcr_l2_aux_ctlr(val);
> - }
> + mrc_l2_aux_ctlr(val);
> + val |= (1 << 27);
> + val |= (1 << 7);
> + val |= (1 << 3);
> + mcr_l2_aux_ctlr(val);
> }
>
> /*
> @@ -121,7 +137,16 @@ static void low_power_start(void)
>
> /* Set the CPU to SVC32 mode */
> svc32_mode_en();
> - configure_l2actlr();
> +
> + /* Read MIDR for Primary Part Number*/
> + mrc_midr(val);
> + val = (val >> 4);
> + val &= 0xf;
> +
> + if (val == 0xf) {
> + configure_l2_ctlr();
> + configure_l2_actlr();
> + }
>
> /* Invalidate L1 & TLB */
> val = 0x0;
> @@ -174,7 +199,7 @@ static void power_down_core(void)
> static void secondary_cores_configure(void)
> {
> /* Setup L2 cache */
> - configure_l2actlr();
> + configure_l2_ctlr();
>
> /* Clear secondary boot iRAM base */
> writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
> diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
> index 7268b9b..ea201e7 100644
> --- a/arch/arm/cpu/armv7/exynos/soc.c
> +++ b/arch/arm/cpu/armv7/exynos/soc.c
> @@ -10,8 +10,10 @@
> #include
>
> enum l2_cache_params {
> +#ifndef CONFIG_EXYNOS5420
> CACHE_TAG_RAM_SETUP = (1 << 9),
> CACHE_DATA_RAM_SETUP = (1 << 5),
> +#endif
> CACHE_TAG_RAM_LATENCY = (2 << 6),
> CACHE_DATA_RAM_LATENCY = (2 << 0)
> };
> @@ -39,10 +41,15 @@ static void exynos5_set_l2cache_params(void)
>
> asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
>
> +#ifndef CONFIG_EXYNOS5420
> val |= CACHE_TAG_RAM_SETUP |
> CACHE_DATA_RAM_SETUP |
> CACHE_TAG_RAM_LATENCY |
> CACHE_DATA_RAM_LATENCY;
> +#else
> + val |= CACHE_TAG_RAM_LATENCY |
> + CACHE_DATA_RAM_LATENCY;
> +#endif
>
> asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
>
> --
> 1.9.1
>
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCH 05/11] Exynos542x: Add workaround for exynos iROM errata
Hi Akshay,
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> iROM logic provides undesired jump address for CPU2.
> This patch adds a programmable susbstitute for a part of
> iROM logic which wakes up cores and provides jump addresses.
> This patch creates a logic to make all secondary cores jump
> to a particular address which evades the possibility of CPU2
> jumping to wrong address and create undesired results.
>
> Logic of the workaround:
>
> Step-1: iROM code checks value at address 0x2020028.
> Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
> else, it continues executing normally.
> Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
> 0x2020028 and jump address (pointer to function low_power_start)
> in (0x202000+CPUid*4).
> Step-4: When secondary cores recieve event signal they jump to this address
> and continue execution.
>
> Signed-off-by: Kimoon Kim
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/Makefile| 2 +
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 90 +++
> arch/arm/cpu/armv7/exynos/sec_boot.S | 145
> ++
> 3 files changed, 219 insertions(+), 18 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S
>
> diff --git a/arch/arm/cpu/armv7/exynos/Makefile
> b/arch/arm/cpu/armv7/exynos/Makefile
> index e207bd6..8542f89 100644
> --- a/arch/arm/cpu/armv7/exynos/Makefile
> +++ b/arch/arm/cpu/armv7/exynos/Makefile
> @@ -7,6 +7,8 @@
>
> obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
>
> +obj-$(CONFIG_EXYNOS5420) += sec_boot.o
> +
> ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
> obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index 3097382..d3c466e 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -49,7 +49,7 @@ enum {
> * before modifying the ACTLR.SMP bit. This is required during boot before
> * MMU has been enabled, or during a specified reset or power down sequence.
> */
> -void enable_smp(void)
> +static void enable_smp(void)
> {
> uint32_t temp, val;
>
> @@ -70,7 +70,7 @@ void enable_smp(void)
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> * stalled for 1024 cycles to verify that its hazard condition still exists.
> */
> -void set_l2cache(void)
> +static void set_l2cache(void)
> {
> uint32_t val;
>
> @@ -89,6 +89,62 @@ void set_l2cache(void)
> }
>
> /*
> + * Power up secondary CPUs.
> + */
> +static void secondary_cpu_start(void)
> +{
> + enable_smp();
> + svc32_mode_en();
> + set_pc(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
> +}
> +
> +/*
> + * This is the entry point of hotplug-in and
> + * cluster switching.
> + */
> +static void low_power_start(void)
> +{
> + uint32_t val, reg_val;
> +
> + reg_val = readl(RST_FLAG_REG);
> + if (reg_val != RST_FLAG_VAL) {
> + writel(0x0, CONFIG_LOWPOWER_FLAG);
> + set_pc(0x0);
> + }
> +
> + reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
> + if (reg_val != (uint32_t)&low_power_start) {
> + /* Store jump address as low_power_start if not present */
> + writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE +
> 0x4);
> + dsb();
> + sev();
> + }
> +
> + /* Set the CPU to SVC32 mode */
> + svc32_mode_en();
> + set_l2cache();
> +
> + /* Invalidate L1 & TLB */
> + val = 0x0;
> + mcr_tlb(val);
> + mcr_icache(val);
> +
> + /* Disable MMU stuff and caches */
> + mrc_sctlr(val);
> +
> + val &= ~((0x2 << 12) | 0x7);
> + val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
> + mcr_sctlr(val);
> +
> + /* CPU state is hotplug or reset */
> + secondary_cpu_start();
> +
> + /* Core should not enter into WFI here */
> + wfi();
> +
> +}
> +
> +/*
> * Pointer to this function is stored in iRam which is used
> * for jump and power down of a specific core.
> */
> @@ -118,29 +174,25 @@ static void power_down_core(void)
> */
> static void secondary_cores_configure(void)
> {
> - uint32_t core_id;
> + /* Setup L2 cache */
> + set_l2cache();
> +
> + /* Clear secondary boot iRAM base */
> + writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
>
> - /* Store jump address for power down of secondary cores */
> + /* set lowpower flag and address */
> + writel(RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
> + writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
> + writel(RST_FLAG_VAL, RST_FLAG_REG);
> + /* Store jump address for power down */
> writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
>
> /*
Re: [U-Boot] [PATCH 03/11] Exynos542x: Add workaround for ARM errata 798870
Hi Akshay,
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> This patch adds workaround for ARM errata 798870 which says
> "If back-to-back speculative cache line fills (fill A and fill B) are
> issued from the L1 data cache of a CPU to the L2 cache, the second
> request (fill B) is then cancelled, and the second request would have
> detected a hazard against a recent write or eviction (write B) to the
> same cache line as fill B then the L2 logic might deadlock."
>
> Signed-off-by: Kimoon Kim
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index 43c957b..7073c5c 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -45,6 +45,28 @@ enum {
>
> #ifdef CONFIG_EXYNOS5420
> /*
> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> + * stalled for 1024 cycles to verify that its hazard condition still exists.
> + */
> +void set_l2cache(void)
> +{
> + uint32_t val;
> +
> + /* Read MIDR for Primary Part Number*/
Nit: Space before */
> + mrc_midr(val);
> + val = (val >> 4);
> + val &= 0xf;
> +
> + /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
> + if (val == 0xf) {
> + mrc_l2_aux_ctlr(val);
> + val |= (1 << 7);
> + mcr_l2_aux_ctlr(val);
> + mrc_l2_ctlr(val);
> + }
> +}
> +
> +/*
> * Pointer to this function is stored in iRam which is used
> * for jump and power down of a specific core.
> */
> --
> 1.9.1
>
Reviewed-by: Simon Glass
Tested on snow, pit, pi
Tested-by: Simon Glass
Regards,
Simon
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Re: [U-Boot] [PATCH 06/11] Exynos542x: Change ambiguous function name set_l2cache
On 15 January 2015 at 06:42, Akshay Saraswat wrote:
> 1. Renaming set_l2cache to configure_l2actlr in order to avoid
>misleading comprehensions. Apparently this name suggests
>that L2 cache is being set or initialized which is incorrect
>as per the code in this function.
> 2. Cleaning missed mrc for L2 control register.
>
> Signed-off-by: Akshay Saraswat
> ---
> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> index d3c466e..688972b 100644
> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
> @@ -70,7 +70,7 @@ static void enable_smp(void)
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> * stalled for 1024 cycles to verify that its hazard condition still exists.
> */
> -static void set_l2cache(void)
> +static void configure_l2actlr(void)
> {
> uint32_t val;
>
> @@ -84,7 +84,6 @@ static void set_l2cache(void)
> mrc_l2_aux_ctlr(val);
> val |= (1 << 7);
> mcr_l2_aux_ctlr(val);
> - mrc_l2_ctlr(val);
> }
> }
>
> @@ -122,7 +121,7 @@ static void low_power_start(void)
>
> /* Set the CPU to SVC32 mode */
> svc32_mode_en();
> - set_l2cache();
> + configure_l2actlr();
>
> /* Invalidate L1 & TLB */
> val = 0x0;
> @@ -175,7 +174,7 @@ static void power_down_core(void)
> static void secondary_cores_configure(void)
> {
> /* Setup L2 cache */
> - set_l2cache();
> + configure_l2actlr();
>
> /* Clear secondary boot iRAM base */
> writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
> --
> 1.9.1
>
Reviewed-by: Simon Glass
Tested on snow, pit, pi
Tested-by: Simon Glass
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Re: [U-Boot] [PATCH v3 5/6] Exynos5: Use clock_get_periph_rate generic API
Hi Akshay, On 15 January 2015 at 22:48, Akshay Saraswat wrote: > Replacing SoC and peripheral specific function calls with generic > clock_get_periph_rate calls to get the peripheral clocks. > > Signed-off-by: Akshay Saraswat > --- > Changes since v2: > - No change. > > Changes since v1: > - Separated exynos5_get_periph_rate fixes into another patch. > > arch/arm/cpu/armv7/exynos/clock.c | 52 > --- > 1 file changed, 43 insertions(+), 9 deletions(-) This commit needs to merge with the next, otherwise you create a build error. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 6/6] Exynos5: Remove dead code for fetching clocks
Hi Akshay, On 15 January 2015 at 22:48, Akshay Saraswat wrote: > Removing dead code of peripheral and SoC specific function > implementations which was used for fetching peripheral clocks. > This code is not being used anymore because of the introduction > of generic clock_get_periph_rate function. > > Signed-off-by: Akshay Saraswat > --- > Changes since v2: > - No change. > > Changes since v1: > - No change. > > arch/arm/cpu/armv7/exynos/clock.c | 226 > -- > 1 file changed, 226 deletions(-) > This commit needs to merge with the previous, otherwise you create a build error. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/11] Exynos542x: CPU: Power down all secondary cores
Hi,
On 15 January 2015 at 23:35, Minkyu Kang wrote:
> On 15/01/15 22:41, Akshay Saraswat wrote:
>> This patch adds code to shutdown secondary cores.
>> When U-boot comes up, all secondary cores appear powered on,
>> which is undesirable and causes side effects while
>> initializing these cores in kernel.
>>
>> Secondary core power down happens in following steps:
>>
>> Step-1: After Exynos power-on, primary core starts executing first.
>> Step-2: In iROM code every core has to check 2 flags i.e.
>> addresses 0x02020028 & 0x02020004.
>> Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
>> jump address for primary core and 0 for all secondary cores.
>> Step-4: Therefore, primary core follows normal iROM execution and jumps
>> to BL1 eventually, whereas all secondary cores enter WFE.
>> Step-5: When primary core comes into function secondary_cores_configure,
>> it puts pointer to function power_down_core into 0x02020004
>> and provides DSB and SEV for all cores so that they may come out
>> of WFE and jump to power_down_core function.
>> Step-6: And ultimately because of power_down_core all
>> secondary cores shut-down.
>>
>> Signed-off-by: Kimoon Kim
>> Signed-off-by: Akshay Saraswat
>> ---
>> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 62 ++
>> arch/arm/include/asm/arch-exynos/cpu.h| 30 +++
>> arch/arm/include/asm/arch-exynos/system.h | 87
>> +++
>> 3 files changed, 179 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> index 83e1dcf..43c957b 100644
>> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> @@ -31,6 +31,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include "common_setup.h"
>>
>> /* These are the things we can do during low-level init */
>> @@ -42,6 +43,62 @@ enum {
>> DO_POWER= 1 << 4,
>> };
>>
>> +#ifdef CONFIG_EXYNOS5420
>> +/*
>> + * Pointer to this function is stored in iRam which is used
>> + * for jump and power down of a specific core.
>> + */
>> +static void power_down_core(void)
>> +{
>> + uint32_t tmp, core_id, core_config;
>> +
>> + /* Get the core id */
>> + mrc_mpafr(core_id);
>> + tmp = core_id & 0x3;
>> + core_id = (core_id >> 6) & ~3;
>
> Please explain what means each bits.
>
>> + core_id |= tmp;
>> +
>> + /* Set the status of the core to low */
>> + core_config = (core_id * CORE_CONFIG_OFFSET);
>> + core_config += ARM_CORE0_CONFIG;
>> + writel(0x0, core_config);
>> +
>> + /* Core enter WFI */
>> + wfi();
>> +}
>> +
>> +/*
>> + * Configurations for secondary cores are inapt at this stage.
>> + * Reconfigure secondary cores. Shutdown and change the status
>> + * of all cores except the primary core.
>> + */
>> +static void secondary_cores_configure(void)
>> +{
>> + uint32_t core_id;
>> +
>> + /* Store jump address for power down of secondary cores */
>> + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
>> +
>> + /* Need all core power down check */
>> + dsb();
>> + sev();
>> +
>> + /*
>> + * Power down all cores(secondary) while primary core must
>> + * wait for all cores to go down.
>> + */
>> + for (core_id = 1; core_id != CORE_COUNT; core_id++) {
>> + while ((readl(ARM_CORE0_STATUS
>> + + (core_id * CORE_CONFIG_OFFSET))
>> + & 0xff) != 0x0) {
>> + isb();
>> + sev();
>> + }
>> + isb();
>> + }
>> +}
>> +#endif
>> +
>> int do_lowlevel_init(void)
>> {
>> uint32_t reset_status;
>> @@ -49,6 +106,11 @@ int do_lowlevel_init(void)
>>
>> arch_cpu_init();
>>
>> +#ifdef CONFIG_EXYNOS5420
>> + /* Reconfigure secondary cores */
>> + secondary_cores_configure();
>> +#endif
>> +
>> reset_status = get_reset_status();
>>
>> switch (reset_status) {
>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
>> b/arch/arm/include/asm/arch-exynos/cpu.h
>> index 29674ad..f1f9994 100644
>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>> @@ -177,6 +177,7 @@
>> #define EXYNOS5420_GPIO_PART1_BASE 0x1401
>> #define EXYNOS5420_MIPI_DSIM_BASE0x1450
>> #define EXYNOS5420_DP_BASE 0x145B
>> +#define EXYNOS5420_INF_REG_BASE 0x10040800
>>
>> #define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
>> #define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
>> @@ -186,6 +187,35 @@
>> #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
>> #define EXYNOS5420_USB_HOST_XHCI_BASEDEVICE_NOT_AVAILABLE
>>
>> +#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000)
>> +#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0
Re: [U-Boot] [PATCH v3 4/6] Exynos5: Fix exynos5_get_periph_rate calculations
On 15 January 2015 at 22:48, Akshay Saraswat wrote: > exynos5_get_periph_rate function reads incorrect div for > SDMMC2 & 3. It also reads prediv and does division only for > SDMMC0 & 2 when actually various other peripherals need that. > Adding changes to fix these mistakes in periph rate calculation. > > Signed-off-by: Akshay Saraswat > --- > Changes since v2: > - Added checks for negative values in exynos5_get_periph_rate. > > Changes since v1: > - New patch. > > arch/arm/cpu/armv7/exynos/clock.c | 21 + > 1 file changed, 13 insertions(+), 8 deletions(-) Reviewed-by: Simon Glass Tested on snow, pit, pi Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi,
On 15 January 2015 at 23:09, Joonyoung Shim wrote:
> Hi,
>
> On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
>> We planned to fetch peripheral rate through one generic API per
>> peripheral. These generic peripheral functions are in turn
>> expected to fetch apt values from a function refactored as
>> per SoC versions. This patch adds support for fetching peripheral
>> rates for Exynos5420 and Exynos5800.
>>
>> Signed-off-by: Akshay Saraswat
>> ---
>> Changes since v2:
>> - Fixed enum and exynos542x_get_periph_rate switch.
>> - Added checks for negative values in exynos542x_get_periph_rate.
>>
>> Changes since v1:
>> - Changes suuport -> support in commit message.
>> - Removed position change of exynos5420_get_pll_clk.
>> - Removed #ifdef.
>>
>> arch/arm/cpu/armv7/exynos/clock.c | 151
>> +++--
>> arch/arm/include/asm/arch-exynos/clk.h | 3 +
>> 2 files changed, 147 insertions(+), 7 deletions(-)
What else needs to be done to get this applied, please?
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 5dc9ed2..ee6c13b 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -27,7 +27,7 @@ struct clk_bit_info {
>> };
>>
>> /* periph_id src_bit div_bit prediv_bit */
>> -static struct clk_bit_info clk_bit_info[] = {
>> +static struct clk_bit_info exynos5_bit_info[] = {
>> {PERIPH_ID_UART0, 0, 0, -1},
>> {PERIPH_ID_UART1, 4, 4, -1},
>> {PERIPH_ID_UART2, 8, 8, -1},
>> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
>> {PERIPH_ID_NONE,-1, -1, -1},
>> };
>>
>> +static struct clk_bit_info exynos542x_bit_info[] = {
>> + {PERIPH_ID_UART0, 4, 8, -1},
>> + {PERIPH_ID_UART1, 8, 12, -1},
>> + {PERIPH_ID_UART2, 12, 16, -1},
>> + {PERIPH_ID_UART3, 16, 20, -1},
>> + {PERIPH_ID_I2C0,-1, 8, -1},
>> + {PERIPH_ID_I2C1,-1, 8, -1},
>> + {PERIPH_ID_I2C2,-1, 8, -1},
>> + {PERIPH_ID_I2C3,-1, 8, -1},
>> + {PERIPH_ID_I2C4,-1, 8, -1},
>> + {PERIPH_ID_I2C5,-1, 8, -1},
>> + {PERIPH_ID_I2C6,-1, 8, -1},
>> + {PERIPH_ID_I2C7,-1, 8, -1},
>> + {PERIPH_ID_SPI0,20, 20, 8},
>> + {PERIPH_ID_SPI1,24, 24, 16},
>> + {PERIPH_ID_SPI2,28, 28, 24},
>> + {PERIPH_ID_SDMMC0, 0, 0, -1},
>> + {PERIPH_ID_SDMMC1, 4, 10, -1},
>> + {PERIPH_ID_SDMMC2, 8, 20, -1},
>> + {PERIPH_ID_I2C8,-1, 8, -1},
>> + {PERIPH_ID_I2C9,-1, 8, -1},
>> + {PERIPH_ID_I2S0,0, 0, 4},
>> + {PERIPH_ID_I2S1,4, 12, 16},
>> + {PERIPH_ID_SPI3,12, 16, 0},
>> + {PERIPH_ID_SPI4,16, 20, 8},
>> + {PERIPH_ID_SDMMC4, 16, 0, 8},
>> + {PERIPH_ID_PWM0,24, 28, -1},
>> + {PERIPH_ID_PWM1,24, 28, -1},
>> + {PERIPH_ID_PWM2,24, 28, -1},
>> + {PERIPH_ID_PWM3,24, 28, -1},
>> + {PERIPH_ID_PWM4,24, 28, -1},
>> + {PERIPH_ID_I2C10, -1, 8, -1},
>> +
>> + {PERIPH_ID_NONE,-1, -1, -1},
>> +};
>> +
>> /* Epll Clock division values to achive different frequency output */
>> static struct set_epll_con_val exynos5_epll_div[] = {
>> { 19200, 0, 48, 3, 1, 0 },
>> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int pllreg)
>> static struct clk_bit_info *get_clk_bit_info(int peripheral)
>> {
>> int i;
>> + struct clk_bit_info *info;
>>
>> - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
>> - if (clk_bit_info[i].id == peripheral)
>> + if (proid_is_exynos5420() || proid_is_exynos5800())
>> + info = exynos542x_bit_info;
>> + else
>> + info = exynos5_bit_info;
>> +
>> + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
>> + if (info[i].id == peripheral)
>> break;
>> }
>>
>> - if (clk_bit_info[i].id == PERIPH_ID_NONE)
>> + if (info[i].id == PERIPH_ID_NONE)
>> debug("ERROR: Peripheral ID %d not found\n", peripheral);
>>
>> - return &clk_bit_info[i];
>> + return &info[i];
>> }
>>
>> static unsigned long exynos5_get_periph_rate(int peripheral)
>> @@ -414,12 +456,107 @@ static unsigned long exynos5_get_periph_rate(int
>> peripheral)
>> return sub_clk;
>> }
>>
>> +static unsigned long exynos542x_get_periph_rate(int peripheral)
>> +{
>> + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
>> + unsigned long sclk, sub_clk = 0;
>> + unsigne
Re: [U-Boot] [PATCH v3 2/6] Exynos542x: Move exynos5420_get_pll_clk up and rename
On 15 January 2015 at 22:48, Akshay Saraswat wrote: > Moving exynos5420_get_pll_clk function definition up in the > code to keep it together with rest of SoC_get_pll_clk functions. > This makes code more legible and also removes the need of > declaration when called before the position of definition in > code. Also, renaming exynos5420_get_pll_clk to > exynos542x_get_pll_clk because it is being used for both Exynos > 5420 and 5800. > > Signed-off-by: Akshay Saraswat > --- > Changes since v2: > - Changed exynos5420 -> exynos542x in line 33. > > Changes since v1: > - New patch. > > arch/arm/cpu/armv7/exynos/clock.c | 82 > +++ > 1 file changed, 41 insertions(+), 41 deletions(-) Reviewed-by: Simon Glass Tested on snow, pit, pi Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/6] Exynos5: Fix compiler warnings due to clock_get_periph_rate
On 15 January 2015 at 22:48, Akshay Saraswat wrote: > Apparently, members of clk_bit_info array do not map correctly > to the members of enum periph_id. This mapping got broken after > we changed periph_id(s) to reflect interrupt number instead of > their position in a sequence. This patch intends to fix above > mentioned issue. > > Signed-off-by: Akshay Saraswat > --- > Changes since v2: > - Added debug message for unknown periph IDs. > > Changes since v1: > - Removed exynos5_bit_info array name. > > arch/arm/cpu/armv7/exynos/clock.c | 80 > --- > 1 file changed, 49 insertions(+), 31 deletions(-) Reviewed-by: Simon Glass Tested on snow, pit, pi Tested-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v2] Exynos5800: The Peach-Pi board does not have a Parade video bridge
Hi, On 5 December 2014 at 07:24, Ajay kumar wrote: > Hi All, > > On Tue, Dec 2, 2014 at 2:00 AM, Simon Glass wrote: >> Hi Sjoerd, >> >> On 1 December 2014 at 13:25, Sjoerd Simons >> wrote: >>> On Mon, 2014-12-01 at 13:09 -0700, Simon Glass wrote: +Akshay Hi Sjoerd, On 1 December 2014 at 03:03, Sjoerd Simons wrote: > Hey Simon, > > On Sun, 2014-11-30 at 11:56 -0700, Simon Glass wrote: >> On 27 November 2014 at 08:08, Sjoerd Simons >> wrote: >> > Unlike the Peach-Pit board, there is no parade edp to lvds bridge on >> > the >> > Pi. So drop it from device-tree >> > >> > Signed-off-by: Sjoerd Simons >> > --- >> > Changes since v1: Only modify the DTB >> > >> > arch/arm/dts/exynos5800-peach-pi.dts | 5 - >> > 1 file changed, 5 deletions(-) >> >> Acked-by: Simon Glass >> >> Tested on snow, pit, pi (display does not yet work on Pi). > > Just to be clear, in your testing does the display not work on Pi? It > seems to be ok here (with u-boot starting chainloaded from one of the > KERN partitions) That's right, not in U-Boot. I think this is because some GPIOs need to be enabled to turn on the backlight etc. Maybe you have an EC which turns these on automatically? If current mainline is supposed to make the display work on Pi then I need to do some debugging. Please let me know. >>> >>> It does work on my machine, so i was wondering if it's a setup >>> difference. I'm using the chained u-boot method (iotw the standard >>> chromeos u-boot in flash starts main-line u-boot from mmc/SD), which >>> might well mean that the GPIOs you're referring to are still turned on >>> by the first u-boot (which it has to do to show me the unverified boot >>> warning screen)? >> >> Yes that's right. Maybe Akshay / Ajay have ideas, or otherwise I can >> add this. I think it is two GPIOs, but it might be TPSCHROME also. > Now, I have added support for peach_pi display in u-boot. > Kindly check the patches. It seems that these have not been applied. So Pi is not in a working state in mainline. When can these be applied please? There is also the rpll_sdiv patch. I found this when testing later patches. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: configure DWMAC DMA by default AXI burst length
Hi Joe, On Wed, Jan 28, 2015 at 4:43 AM, Joe Hershberger wrote: > On Mon, Jan 26, 2015 at 8:54 PM, wrote: >> >> From: Sonic Zhang >> >> Board can define its own AXI burst length to improve DWMAC DMA >> performance. >> >> Signed-off-by: Sonic Zhang >> --- >> >> drivers/net/designware.c |2 ++ >> drivers/net/designware.h |5 + >> 2 files changed, 7 insertions(+) >> >> diff --git a/drivers/net/designware.c b/drivers/net/designware.c >> index 9ded895..d8d6792 100644 >> --- a/drivers/net/designware.c >> +++ b/drivers/net/designware.c >> @@ -256,6 +256,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t >> *bis) >> >> writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); >> > This should probably include: > +#if CONFIG_DW_AXI_BURST_LEN > so that this register is only accessed if configured. CONFIG_DW_AXI_BURST_LEN is always defined in designware.h in the same patch. +/* Default AXI BUS Burst length */ +#ifndef CONFIG_DW_AXI_BURST_LEN +#define CONFIG_DW_AXI_BURST_LEN 0 +#endif + Regards, Sonic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 6/8] avr32: add generic board support
Hi,
On 27 January 2015 at 17:16, Andreas Bießmann
wrote:
> Signed-off-by: Andreas Bießmann
> ---
>
> Changes in v1:
> - add timer_init in board_r
> - remove extern declaration of mmu_init_r()
>
> arch/avr32/config.mk|3 +++
> arch/avr32/cpu/u-boot.lds |2 ++
> arch/avr32/include/asm/config.h |1 +
> arch/avr32/include/asm/u-boot.h |7 +++
> arch/avr32/lib/Makefile |2 ++
> arch/avr32/lib/interrupts.c |5 +
> common/board_f.c| 13 ++---
> common/board_r.c| 26 +++---
> include/asm-generic/u-boot.h|4
> 9 files changed, 57 insertions(+), 6 deletions(-)
>
> diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
> index 469185e..8252f59 100644
> --- a/arch/avr32/config.mk
> +++ b/arch/avr32/config.mk
> @@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),)
> CROSS_COMPILE := avr32-linux-
> endif
>
> +# avr32 has generic board support
> +__HAVE_ARCH_GENERIC_BOARD := y
> +
> CONFIG_STANDALONE_LOAD_ADDR ?= 0x
>
> PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
> diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds
> index cb29a22..b0180e3 100644
> --- a/arch/avr32/cpu/u-boot.lds
> +++ b/arch/avr32/cpu/u-boot.lds
> @@ -48,9 +48,11 @@ SECTIONS
> _edata = .;
>
> .bss (NOLOAD) : {
> + __bss_start = .;
> *(.bss)
> *(.bss.*)
> }
> . = ALIGN(8);
> __bss_end = .;
> + __init_end = .;
> }
> diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h
> index 63056a4..529fe22 100644
> --- a/arch/avr32/include/asm/config.h
> +++ b/arch/avr32/include/asm/config.h
> @@ -8,5 +8,6 @@
> #define _ASM_CONFIG_H_
>
> #define CONFIG_NEEDS_MANUAL_RELOC
> +#define CONFIG_SYS_GENERIC_GLOBAL_DATA
>
> #endif
> diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
> index 2387f8a..0f7 100644
> --- a/arch/avr32/include/asm/u-boot.h
> +++ b/arch/avr32/include/asm/u-boot.h
> @@ -6,6 +6,11 @@
> #ifndef __ASM_U_BOOT_H__
> #define __ASM_U_BOOT_H__ 1
>
> +#ifdef CONFIG_SYS_GENERIC_BOARD
> +/* Use the generic board which requires a unified bd_info */
> +#include
> +#else
> +
> typedef struct bd_info {
> unsigned char bi_phy_id[4];
> unsigned long bi_board_number;
> @@ -22,6 +27,8 @@ typedef struct bd_info {
> #define bi_memstart bi_dram[0].start
> #define bi_memsize bi_dram[0].size
>
> +#endif
> +
> /* For image.h:image_check_target_arch() */
> #define IH_ARCH_DEFAULT IH_ARCH_AVR32
>
> diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile
> index bb45cbe..d5cb8b2 100644
> --- a/arch/avr32/lib/Makefile
> +++ b/arch/avr32/lib/Makefile
> @@ -8,6 +8,8 @@
> #
>
> obj-y += memset.o
> +ifndef CONFIG_SYS_GENERIC_BOARD
> obj-y += board.o
> +endif
> obj-$(CONFIG_CMD_BOOTM) += bootm.o
> obj-y += interrupts.o
> diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c
> index bacb2d1..5f3a49e 100644
> --- a/arch/avr32/lib/interrupts.c
> +++ b/arch/avr32/lib/interrupts.c
> @@ -7,6 +7,11 @@
>
> #include
>
> +int interrupt_init(void)
> +{
> + return 0;
> +}
> +
> void enable_interrupts(void)
> {
> asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
> diff --git a/common/board_f.c b/common/board_f.c
> index 215108b..1a735ae 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -174,7 +174,7 @@ static int announce_dram_init(void)
> return 0;
> }
>
> -#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
> +#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_AVR32)
> static int init_func_ram(void)
> {
> #ifdef CONFIG_BOARD_TYPES
> @@ -268,6 +268,8 @@ static int setup_mon_len(void)
> gd->mon_len = (ulong)&_end - (ulong)_init;
> #elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2)
> gd->mon_len = CONFIG_SYS_MONITOR_LEN;
> +#elif defined(CONFIG_AVR32)
> + gd->mon_len = (ulong)&__bss_end - (ulong)&_text;
Would we be able to unify the symbols here rather than having a
special case for AVR32?
> #else
> /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
> gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
> @@ -581,7 +583,7 @@ static int reserve_stacks(void)
> gd->irq_sp = gd->start_addr_sp;
> # endif
> #else
> -# ifdef CONFIG_PPC
> +# if defined(CONFIG_PPC) || defined(CONFIG_AVR32)
> ulong *s;
> # endif
>
> @@ -611,6 +613,11 @@ static int reserve_stacks(void)
> s = (ulong *) gd->start_addr_sp;
> *s = 0; /* Terminate back chain */
> *++s = 0; /* NULL return address */
> +# elif defined(CONFIG_AVR32)
> + gd->arch.stack_end = gd->start_addr_sp;
> + s = (ulong *)gd->start_addr_sp;
> + *s = 0;
> + *--s = 0;
Can we create an arch_reserve_stacks() function to handle this, and
put it in the AVR32 code?
> # endif /* Ar
Re: [U-Boot] [RFC PATCH 7/7] net: Add ARP and PING response to sandbox driver
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger wrote:
> The sandbox driver will now generate response traffic to exercise the
> ping command even when no network exists. This allows the basic data
> pathways of the DM to be tested.
>
> Signed-off-by: Joe Hershberger
> ---
Looks like this can support ping. Very nice.
>
> drivers/net/sandbox.c | 75
> +++
> 1 file changed, 75 insertions(+)
>
> diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
> index e1ee69b..49413f2 100644
> --- a/drivers/net/sandbox.c
> +++ b/drivers/net/sandbox.c
> @@ -20,6 +20,11 @@ struct eth_sandbox_priv {
> int sd;
> };
>
> +static uchar fake_host_hwaddr[ARP_HLEN] = {0x00, 0x00, 0x66, 0x44, 0x22,
> 0x00};
> +static IPaddr_t fake_host_ipaddr;
> +static uchar recv_packet_buffer[PKTSIZE];
> +static int recv_packet_length;
This could go in the driver's priv area (then we could support
multiple sandbox devices).
> +
> int sb_eth_init(struct udevice *dev, bd_t *bis)
> {
> printf("eth_sandbox: Init\n");
> @@ -31,12 +36,82 @@ int sb_eth_send(struct udevice *dev, void *packet, int
> length)
> {
> printf("eth_sandbox: Send packet %d\n", length);
>
> + struct ethernet_hdr *eth = packet;
> + if (ntohs(eth->et_protlen) == PROT_ARP) {
> + struct arp_hdr *arp = packet + ETHER_HDR_SIZE;
> + if (ntohs(arp->ar_op) == ARPOP_REQUEST) {
> + /* store this as the assumed IP of the fake host */
> + fake_host_ipaddr = NetReadIP(&arp->ar_tpa);
> + /* Formulate a fake response */
> + struct ethernet_hdr *eth_recv =
> + (void *)recv_packet_buffer;
> + memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
> + memcpy(eth_recv->et_src, fake_host_hwaddr, ARP_HLEN);
> + eth_recv->et_protlen = htons(PROT_ARP);
> +
> + struct arp_hdr *arp_recv = (void *)recv_packet_buffer
> +
> + ETHER_HDR_SIZE;
> + arp_recv->ar_hrd = htons(ARP_ETHER);
> + arp_recv->ar_pro = htons(PROT_IP);
> + arp_recv->ar_hln = ARP_HLEN;
> + arp_recv->ar_pln = ARP_PLEN;
> + arp_recv->ar_op = htons(ARPOP_REPLY);
> + memcpy(&arp_recv->ar_sha, fake_host_hwaddr, ARP_HLEN);
> + NetWriteIP(&arp_recv->ar_spa, fake_host_ipaddr);
> + memcpy(&arp_recv->ar_tha, &arp->ar_sha, ARP_HLEN);
> + NetCopyIP(&arp_recv->ar_tpa, &arp->ar_spa);
> +
> + recv_packet_length = ETHER_HDR_SIZE + ARP_HDR_SIZE;
> + }
> + } else if (ntohs(eth->et_protlen) == PROT_IP) {
> + struct ip_udp_hdr *ip = packet + ETHER_HDR_SIZE;
> + if (ip->ip_p == IPPROTO_ICMP) {
> + struct icmp_hdr *icmp = (struct icmp_hdr
> *)&ip->udp_src;
> + if (icmp->type == ICMP_ECHO_REQUEST) {
> + /* reply to the ping */
> + memcpy(recv_packet_buffer, packet, length);
> + struct ethernet_hdr *eth_recv =
> + (void *)recv_packet_buffer;
> + struct ip_udp_hdr *ipr =
> + (void *)recv_packet_buffer +
> + ETHER_HDR_SIZE;
> + struct icmp_hdr *icmpr =
> + (struct icmp_hdr *)&ipr->udp_src;
> + memcpy(eth_recv->et_dest, eth->et_src,
> + ARP_HLEN);
> + memcpy(eth_recv->et_src, fake_host_hwaddr,
> + ARP_HLEN);
> + ipr->ip_sum = 0;
> + ipr->ip_off = 0;
> + NetCopyIP((void *)&ipr->ip_dst, &ip->ip_src);
> + NetWriteIP((void *)&ipr->ip_src,
> + fake_host_ipaddr);
> + ipr->ip_sum = ~NetCksum((uchar *)ipr,
> + IP_HDR_SIZE >> 1);
> +
> + icmpr->type = ICMP_ECHO_REPLY;
> + icmpr->checksum = 0;
> + icmpr->checksum = ~NetCksum((uchar *)icmpr,
> + (length - ETHER_HDR_SIZE -
> + IP_HDR_SIZE) >> 1);
> +
> + recv_packet_length = length;
> + }
> + }
> + }
> +
> return 0;
> #endif
> }
>
> int sb_eth_recv(struct u
Re: [U-Boot] [RFC PATCH 2/7] net: Rename helper function to be more clear
On 27 January 2015 at 16:27, Joe Hershberger wrote:
> Make it clear that the helper is checking the addr, not setting it.
>
> Signed-off-by: Joe Hershberger
> ---
>
> net/eth.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass
>
> diff --git a/net/eth.c b/net/eth.c
> index eac4f7b..65e8c77 100644
> --- a/net/eth.c
> +++ b/net/eth.c
> @@ -153,11 +153,6 @@ static void eth_current_changed(void)
> setenv("ethact", NULL);
> }
>
> -static int eth_address_set(unsigned char *addr)
> -{
> - return memcmp(addr, "\0\0\0\0\0\0", 6);
> -}
> -
> int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
>int eth_number)
> {
> @@ -166,9 +161,9 @@ int eth_write_hwaddr(struct eth_device *dev, const char
> *base_name,
>
> eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr);
>
> - if (eth_address_set(env_enetaddr)) {
> - if (eth_address_set(dev->enetaddr) &&
> - memcmp(dev->enetaddr, env_enetaddr, 6)) {
> + if (!is_zero_ether_addr(env_enetaddr)) {
> + if (!is_zero_ether_addr(dev->enetaddr) &&
> + memcmp(dev->enetaddr, env_enetaddr, 6)) {
> printf("\nWarning: %s MAC addresses don't match:\n",
> dev->name);
> printf("Address in SROM is %pM\n",
> @@ -183,7 +178,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char
> *base_name,
> dev->enetaddr);
> printf("\nWarning: %s using MAC address from net device\n",
> dev->name);
> - } else if (!(eth_address_set(dev->enetaddr))) {
> + } else if (is_zero_ether_addr(dev->enetaddr)) {
> printf("\nError: %s address not set.\n",
>dev->name);
> return -EINVAL;
> --
> 1.7.11.5
>
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Re: [U-Boot] [RFC PATCH 4/7] net: Refactor in preparation for driver model
On 27 January 2015 at 16:27, Joe Hershberger wrote: > Move some things around and organize things so that the driver model > implementation will fit in more easily. > > Signed-off-by: Joe Hershberger > --- > > include/net.h | 63 + > net/eth.c | 75 > +++ > 2 files changed, 73 insertions(+), 65 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 1/7] net: Provide a function to get the current MAC address
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger wrote:
> The current implementation exposes the eth_device struct to code that
> needs to access the MAC address. Add a wrapper function for this to
> abstract away the pointer for this operation.
>
> Signed-off-by: Joe Hershberger
> ---
>
> arch/mips/cpu/mips32/au1x00/au1x00_eth.c | 2 +-
> arch/powerpc/cpu/mpc8260/ether_fcc.c | 2 +-
> arch/powerpc/cpu/mpc85xx/ether_fcc.c | 2 +-
> arch/powerpc/cpu/mpc8xx/scc.c| 2 +-
> include/net.h| 8
> net/net.c| 2 +-
> 6 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
> b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
> index 4770f56..535d713 100644
> --- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
> +++ b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
> @@ -238,7 +238,7 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
> }
>
> /* Put mac addr in little endian */
> -#define ea eth_get_dev()->enetaddr
> +#define ea eth_get_ethaddr()
> *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
> *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
I know this is existing code, but (perhaps separately) it might be
nice to remove the #define and assign it it to a local variable, i.e.:
unsigned char *ea = eth_get_ethaddr();
> (ea[1] << 8) | (ea[0] ) ;
> diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c
> b/arch/powerpc/cpu/mpc8260/ether_fcc.c
> index f9f15b5..f777ba1 100644
> --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
> +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
> @@ -299,7 +299,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
> * it unique by setting a few bits in the upper byte of the
> * non-static part of the address.
> */
> -#define ea eth_get_dev()->enetaddr
> +#define ea eth_get_ethaddr()
> pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
> pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
> pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
> diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
> b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
> index 166dc9e..58d4bfb 100644
> --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
> +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
> @@ -338,7 +338,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
> * it unique by setting a few bits in the upper byte of the
> * non-static part of the address.
> */
> -#define ea eth_get_dev()->enetaddr
> +#define ea eth_get_ethaddr()
> pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
> pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
> pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
> diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
> index 251966b..66e4014 100644
> --- a/arch/powerpc/cpu/mpc8xx/scc.c
> +++ b/arch/powerpc/cpu/mpc8xx/scc.c
> @@ -339,7 +339,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
> pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
> pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
>
> -#define ea eth_get_dev()->enetaddr
> +#define ea eth_get_ethaddr()
> pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
> pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
> pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
> diff --git a/include/net.h b/include/net.h
> index 73ea88b..a9579ee 100644
> --- a/include/net.h
> +++ b/include/net.h
> @@ -111,6 +111,14 @@ struct eth_device *eth_get_dev(void)
> {
> return eth_current;
> }
> +
> +static inline unsigned char *eth_get_ethaddr(void)
> +{
> + if (eth_current)
> + return eth_current->enetaddr;
> + return NULL;
> +}
> +
> extern struct eth_device *eth_get_dev_by_name(const char *devname);
> extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @
> index */
> extern int eth_get_dev_index(void);/* get the device index */
> diff --git a/net/net.c b/net/net.c
> index 2bea07b..ddd630c 100644
> --- a/net/net.c
> +++ b/net/net.c
> @@ -275,7 +275,7 @@ static void NetInitLoop(void)
> env_changed_id = env_id;
> }
> if (eth_get_dev())
> - memcpy(NetOurEther, eth_get_dev()->enetaddr, 6);
> + memcpy(NetOurEther, eth_get_ethaddr(), 6);
>
> return;
> }
> --
> 1.7.11.5
>
Regards,
Simon
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Re: [U-Boot] [RFC PATCH 3/7] net: Remove unneeded "extern" in net.h
On 27 January 2015 at 16:27, Joe Hershberger wrote: > Many of the functions in net.h were preceded extern needlessly. Removing > them to limit the number of checkpatch.pl complaints. > > Signed-off-by: Joe Hershberger > --- > > include/net.h | 96 > +-- > 1 file changed, 48 insertions(+), 48 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 6/7] net: Add network support to sandbox
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger wrote:
> Add basic network support to sandbox which includes a network driver.
>
> Signed-off-by: Joe Hershberger
> ---
>
> arch/sandbox/dts/sandbox.dts | 4 ++
> drivers/net/Makefile | 2 +
> drivers/net/sandbox.c| 91
>
> include/configs/sandbox.h| 14 ---
> 4 files changed, 106 insertions(+), 5 deletions(-)
> create mode 100644 drivers/net/sandbox.c
>
> diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
> index 11748ae..a1d3199 100644
> --- a/arch/sandbox/dts/sandbox.dts
> +++ b/arch/sandbox/dts/sandbox.dts
> @@ -174,4 +174,8 @@
> };
> };
>
> + eth@10002000 {
> + compatible = "sandbox,eth";
> + reg = <0x10002000 0x1000>;
> + };
> };
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 46c4ac6..2659a8a 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -50,6 +50,8 @@ obj-$(CONFIG_NS8382X) += ns8382x.o
> obj-$(CONFIG_PCNET) += pcnet.o
> obj-$(CONFIG_RTL8139) += rtl8139.o
> obj-$(CONFIG_RTL8169) += rtl8169.o
> +obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
> +obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
> obj-$(CONFIG_SH_ETHER) += sh_eth.o
> obj-$(CONFIG_SMC9) += smc9.o
> obj-$(CONFIG_SMC911X) += smc911x.o
> diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
> new file mode 100644
> index 000..e1ee69b
> --- /dev/null
> +++ b/drivers/net/sandbox.c
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (c) 2015 National Instruments
> + *
> + * (C) Copyright 2015
> + * Joe Hershberger
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct eth_sandbox_priv {
> + void *device;
> + int sd;
I'm not sure what these are for.
> +};
> +
> +int sb_eth_init(struct udevice *dev, bd_t *bis)
> +{
> + printf("eth_sandbox: Init\n");
debug()?
> +
> + return 0;
> +}
> +
> +int sb_eth_send(struct udevice *dev, void *packet, int length)
> +{
> + printf("eth_sandbox: Send packet %d\n", length);
> +
> + return 0;
> +#endif
> +}
> +
> +int sb_eth_recv(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +void sb_eth_halt(struct udevice *dev)
> +{
> + printf("eth_sandbox: Halt\n");
> +}
> +
> +int sb_eth_write_hwaddr(struct udevice *dev)
> +{
> + printf("eth_sandbox: Write HW ADDR\n");
> + return 0;
> +}
> +
> +static const struct eth_ops eth_sandbox_ops = {
> + .init = sb_eth_init,
> + .send = sb_eth_send,
> + .recv = sb_eth_recv,
> + .halt = sb_eth_halt,
> + .write_hwaddr = sb_eth_write_hwaddr,
> +};
> +
> +static int eth_sandbox_remove(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +#ifdef CONFIG_OF_CONTROL
> +static int sandbox_eth_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev->platdata;
> +
> + pdata->iobase = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
> + return 0;
> +}
> +
> +static const struct udevice_id sandbox_eth_ids[] = {
> + { .compatible = "sandbox,eth" },
> + { }
> +};
> +#endif
> +
> +U_BOOT_DRIVER(eth_sandbox) = {
> + .name = "eth_sandbox",
> + .id = UCLASS_ETH,
> + .of_match = of_match_ptr(sandbox_eth_ids),
> + .ofdata_to_platdata = of_match_ptr(sandbox_eth_ofdata_to_platdata),
> + .remove = eth_sandbox_remove,
> + .ops= ð_sandbox_ops,
> + .priv_auto_alloc_size = sizeof(struct eth_sandbox_priv),
> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
> +};
> diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
> index 657f751..67bfc52 100644
> --- a/include/configs/sandbox.h
> +++ b/include/configs/sandbox.h
> @@ -143,9 +143,9 @@
> /* include default commands */
> #include
>
> -/* We don't have networking support yet */
> -#undef CONFIG_CMD_NET
> -#undef CONFIG_CMD_NFS
> +#define CONFIG_DM_ETH
> +#define CONFIG_ETH_SANDBOX
> +#define CONFIG_CMD_PING
>
> #define CONFIG_CMD_HASH
> #define CONFIG_HASH_VERIFY
> @@ -188,12 +188,16 @@
>
> #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
> "stdout=serial,lcd\0" \
> - "stderr=serial,lcd\0"
> + "stderr=serial,lcd\0" \
> + "ethaddr=00:00:11:22:33:44\0" \
> + "ipaddr=1.2.3.4\0"
> #else
>
> #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
> "stdout=serial,lcd\0" \
> - "stderr=serial,lcd\0"
> + "stderr=serial,lcd\0" \
> +
Re: [U-Boot] [RFC PATCH 5/7] net: Add basic driver model support to Ethernet stack
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger wrote:
> First just add support for MAC drivers.
>
I don't fully understand this partly because my knowledge of the
network stack is limited. So I'll make a few comments and we can go
from there.
> Signed-off-by: Joe Hershberger
> ---
>
> common/board_r.c | 4 +-
> common/cmd_bdinfo.c| 2 +
> include/dm/uclass-id.h | 1 +
> include/net.h | 23
> net/eth.c | 320
> -
> 5 files changed, 346 insertions(+), 4 deletions(-)
>
> diff --git a/common/board_r.c b/common/board_r.c
> index a301cc2..9a41cae 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -572,7 +572,7 @@ static int initr_bbmii(void)
> }
> #endif
>
> -#ifdef CONFIG_CMD_NET
> +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
> static int initr_net(void)
> {
> puts("Net: ");
> @@ -841,7 +841,7 @@ init_fnc_t init_sequence_r[] = {
> #ifdef CONFIG_BITBANGMII
> initr_bbmii,
> #endif
> -#ifdef CONFIG_CMD_NET
> +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
> INIT_FUNC_WATCHDOG_RESET
> initr_net,
> #endif
> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
> index e6d8a7a..8688cf9 100644
> --- a/common/cmd_bdinfo.c
> +++ b/common/cmd_bdinfo.c
> @@ -34,6 +34,7 @@ static void print_eth(int idx)
> printf("%-12s= %s\n", name, val);
> }
>
> +#ifndef CONFIG_DM_ETH
> __maybe_unused
> static void print_eths(void)
> {
> @@ -52,6 +53,7 @@ static void print_eths(void)
> printf("current eth = %s\n", eth_get_name());
> printf("ip_addr = %s\n", getenv("ipaddr"));
> }
> +#endif
>
> __maybe_unused
> static void print_lnum(const char *name, unsigned long long value)
> diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
> index f17c3c2..b04cbc9 100644
> --- a/include/dm/uclass-id.h
> +++ b/include/dm/uclass-id.h
> @@ -33,6 +33,7 @@ enum uclass_id {
> UCLASS_I2C, /* I2C bus */
> UCLASS_I2C_GENERIC, /* Generic I2C device */
> UCLASS_I2C_EEPROM, /* I2C EEPROM device */
> + UCLASS_ETH, /* Network device */
Ethernet device?
>
> UCLASS_COUNT,
> UCLASS_INVALID = -1,
> diff --git a/include/net.h b/include/net.h
> index 7eef9cc..25636e2 100644
> --- a/include/net.h
> +++ b/include/net.h
> @@ -78,6 +78,29 @@ enum eth_state_t {
> ETH_STATE_ACTIVE
> };
>
> +#ifdef CONFIG_DM_ETH
> +struct eth_pdata {
> + phys_addr_t iobase;
> +};
> +
> +struct eth_ops {
> + int (*init)(struct udevice *dev, bd_t *bis);
> + int (*send)(struct udevice *dev, void *packet, int length);
> + int (*recv)(struct udevice *dev);
> + void (*halt)(struct udevice *dev);
> +#ifdef CONFIG_MCAST_TFTP
> + int (*mcast)(struct udevice *dev, const u8 *enetaddr, u8 set);
> +#endif
> + int (*write_hwaddr)(struct udevice *dev);
> +};
> +
> +struct udevice *eth_get_dev(void); /* get the current device */
> +unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
> +int eth_init_state_only(bd_t *bis); /* Set active state */
> +void eth_halt_state_only(void); /* Set passive state */
> +#endif
> +
> +#ifndef CONFIG_DM_ETH
> struct eth_device {
> char name[16];
> unsigned char enetaddr[6];
> diff --git a/net/eth.c b/net/eth.c
> index c02548c..d245b65 100644
> --- a/net/eth.c
> +++ b/net/eth.c
> @@ -72,6 +72,321 @@ static int eth_mac_skip(int index)
> return ((skip_state = getenv(enetvar)) != NULL);
> }
>
> +static void eth_current_changed(void);
> +
> +#ifdef CONFIG_DM_ETH
> +#include
> +
> +struct eth_device_priv {
> + unsigned char enetaddr[6];
> + int state;
> + int index;
> + void *priv;
Suggestion: you could have per-child platform data as well as
per-child private data. See u-boot-dm/master for this. It is used for
I2C and SPI to hold the address of the child on the bus.
You could use it to hold the MAC address. I think this *might* be
better because the MAC address can then be set and retained even when
the device is probed/removed.
> +};
> +
> +struct eth_uclass_priv {
> + struct udevice *current;
> + int max_index;
> +};
> +
> +static void eth_set_current_to_next(void)
> +{
> + struct uclass *uc;
> + struct eth_uclass_priv *priv;
> +
> + uclass_get(UCLASS_ETH, &uc);
> + priv = uc->priv;
> + uclass_next_device(&(priv->current));
Note that this will probe the device. I think you are storing the
current ethernet device in the uclass, but you could just as well have
a static variable in this file if that is easier.
(Also remove internal brackets)
If priv->current is NULL, this will die.
Also to avoid confusion I think you should use uc_priv for the uclass
priv local variable, to distinguish it from priv.
> + if (!priv->current)
> + uclass_first_device(UCLASS_ETH, &(priv->current));
If I understand this
Re: [U-Boot] [RFC PATCH 0/7] Add Driver Model support to network stack
Hi Joe, On 27 January 2015 at 16:27, Joe Hershberger wrote: > For now this simply addresses the MAC part of the network hardware. > The next part to implement is the PHY children. I wanted to get early > feedback on what I have so far to make sure I'm going in the direction > that Simon envisioned. > It's great to see this! My comments are against each patch. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus
Hi Rob, On Wed, Jan 28, 2015 at 1:38 AM, Rob Herring wrote: > On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass wrote: >> On some hardware this time can be significant. Add bootstage support for >> measuring this. The result can be obtained using 'bootstage report' or >> passed on to the Linux via the device tree. >> >> Signed-off-by: Simon Glass >> --- >> >> common/cmd_scsi.c | 2 ++ >> include/bootstage.h | 1 + >> 2 files changed, 3 insertions(+) >> >> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c >> index cbc107e..a0a62eb 100644 >> --- a/common/cmd_scsi.c >> +++ b/common/cmd_scsi.c >> @@ -217,8 +217,10 @@ void scsi_init(void) >>(busdevfunc >> 8) & 0x7); >> } >> #endif >> + bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); >> scsi_low_level_init(busdevfunc); >> scsi_scan(1); >> + bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); > > This does not cover the case if the platform calls scsi_scan at boot. > The first time is the important one as that will include disk spin-up > time. > > Perhaps they shouldn't be and "scsi scan" should always be in boot scripts. > scsi_init() is called in common/board_r.c, which already covers the boot scan case. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: clean boot.bin
On 01/23/2015 03:44 PM, Masahiro Yamada wrote: On Fri, 23 Jan 2015 15:34:08 +0800 Bo Shen wrote: + Tom, Masahiro, On 01/15/2015 10:03 AM, Bo Shen wrote: When build for Atmel related boards which support SPL, it will generate boot.bin, also clean when it when do "make clean" operation. Signed-off-by: Bo Shen Hi Tom, Can this patch be applied? Thanks. Acked-by: Masahiro Yamada Hi Masahiro, Thanks. I think this patch should be applied by Tom, because I am a contributer of the build system but am not the custodian. Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] lcd: fix console address is not initialized
This commit 904672e (lcd: refactor lcd console stuff into its own file), which cause lcd console address is not initialized. This patch initialize the lcd console use the default value, will be update when splash screen is enabled. Signed-off-by: Bo Shen --- Hi Tom, If no objection of this patch, can you apply it as soon as possible. Or else most Atmel SoC based boards (which enable lcd info) will be broken. Thanks. common/lcd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/lcd.c b/common/lcd.c index cc34b8a..1195a54 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -268,6 +268,7 @@ void lcd_clear(void) console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT; #endif console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH; + lcd_init_console(lcd_base, console_rows, console_cols); lcd_init_console(lcd_logo(), console_rows, console_cols); lcd_sync(); } -- 2.3.0.rc0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file
Hi Simon,
On Tue, Jan 27, 2015 at 11:15 PM, Simon Glass wrote:
> Hi Bin,
>
> On 27 January 2015 at 05:20, Bin Meng wrote:
>> Hi Simon,
>>
>> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
>>> Since these board functions seem to be the same for all boards which use
>>> FSP, move them into a common file. We can adjust this later if future FSPs
>>> need more flexibility.
>>>
>>> Signed-off-by: Simon Glass
>>> ---
>>>
>>> arch/x86/cpu/queensbay/tnc.c | 27
>>> arch/x86/cpu/queensbay/tnc_pci.c | 15 ---
>>> arch/x86/cpu/queensbay/topcliff.c | 32 +-
>>> arch/x86/include/asm/u-boot-x86.h | 17
>>> arch/x86/lib/fsp/Makefile | 1 +
>>> arch/x86/lib/fsp/fsp_common.c | 88
>>> +++
>>> 6 files changed, 108 insertions(+), 72 deletions(-)
>>> create mode 100644 arch/x86/lib/fsp/fsp_common.c
>>>
>>> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
>>> index f9b3bfa..30ab725 100644
>>> --- a/arch/x86/cpu/queensbay/tnc.c
>>> +++ b/arch/x86/cpu/queensbay/tnc.c
>>> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>>>
>>> return 0;
>>> }
>>> -
>>> -int print_cpuinfo(void)
>>> -{
>>> - post_code(POST_CPU_INFO);
>>> - return default_print_cpuinfo();
>>> -}
>>> -
>>> -void reset_cpu(ulong addr)
>>> -{
>>> - /* cold reset */
>>> - outb(0x06, PORT_RESET);
>>> -}
>>> -
>>> -void board_final_cleanup(void)
>>> -{
>>> - u32 status;
>>> -
>>> - /* call into FspNotify */
>>> - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
>>> - status = fsp_notify(NULL, INIT_PHASE_BOOT);
>>> - if (status != FSP_SUCCESS)
>>> - debug("fail, error code %x\n", status);
>>> - else
>>> - debug("OK\n");
>>> -
>>> - return;
>>> -}
>>> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c
>>> b/arch/x86/cpu/queensbay/tnc_pci.c
>>> index 9b0b725..6c291f9 100644
>>> --- a/arch/x86/cpu/queensbay/tnc_pci.c
>>> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
>>> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>>>
>>> hose->region_count = 4;
>>> }
>>> -
>>> -int board_pci_post_scan(struct pci_controller *hose)
>>> -{
>>> - u32 status;
>>> -
>>> - /* call into FspNotify */
>>> - debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
>>> - status = fsp_notify(NULL, INIT_PHASE_PCI);
>>> - if (status != FSP_SUCCESS)
>>> - debug("fail, error code %x\n", status);
>>> - else
>>> - debug("OK\n");
>>> -
>>> - return 0;
>>> -}
>>> diff --git a/arch/x86/cpu/queensbay/topcliff.c
>>> b/arch/x86/cpu/queensbay/topcliff.c
>>> index b01422a..25032cc 100644
>>> --- a/arch/x86/cpu/queensbay/topcliff.c
>>> +++ b/arch/x86/cpu/queensbay/topcliff.c
>>> @@ -5,43 +5,15 @@
>>> */
>>>
>>> #include
>>> -#include
>>> -#include
>>> -#include
>>> #include
>>> -#include
>>>
>>> static struct pci_device_id mmc_supported[] = {
>>> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
>>> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
>>> - { }
>>> };
>>>
>>> int cpu_mmc_init(bd_t *bis)
>>> {
>>> - struct sdhci_host *mmc_host;
>>> - pci_dev_t devbusfn;
>>> - u32 iobase;
>>> - int ret;
>>> - int i;
>>> -
>>> - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
>>> - devbusfn = pci_find_devices(mmc_supported, i);
>>> - if (devbusfn == -1)
>>> - return -ENODEV;
>>> -
>>> - mmc_host = (struct sdhci_host *)malloc(sizeof(struct
>>> sdhci_host));
>>> - if (!mmc_host)
>>> - return -ENOMEM;
>>> -
>>> - mmc_host->name = "Topcliff SDHCI";
>>> - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
>>> &iobase);
>>> - mmc_host->ioaddr = (void *)iobase;
>>> - mmc_host->quirks = 0;
>>> - ret = add_sdhci(mmc_host, 0, 0);
>>> - if (ret)
>>> - return ret;
>>> - }
>>> -
>>> - return 0;
>>> + return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
>>> + ARRAY_SIZE(mmc_supported));
>>> }
>>
>> I don't think this function should be moved to fsp_common.c as it has
>> nothing related to FSP. We can move this whole function to
>> drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.
>
> How about pci_mmc.c if it is generic to PCI?
>
Sounds good.
[snip]
Regards,
Bin
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Re: [U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input
Hi Simon,
On Tue, Jan 27, 2015 at 11:12 PM, Simon Glass wrote:
> Hi Bin,
>
> On 27 January 2015 at 01:59, Bin Meng wrote:
>> Hi Simon,
>>
>> On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass wrote:
>>> Sometimes microcode is delivered as a header file. Allow the tool to
>>> support this as well as collecting multiple microcode blocks into a
>>> single update.
>>>
>>> Signed-off-by: Simon Glass
>>> ---
>>
>> Tested-by: Bin Meng
>>
>> But please see my comments below.
>>
>>> tools/microcode-tool.py | 90
>>> ++---
>>> 1 file changed, 70 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
>>> index 003716d..71c2e91 100755
>>> --- a/tools/microcode-tool.py
>>> +++ b/tools/microcode-tool.py
>>> @@ -76,6 +76,35 @@ def ParseFile(fname):
>>> microcodes[name] = Microcode(name, data)
>>> return date, license_text, microcodes
>>>
>>> +def ParseHeaderFiles(fname_list):
>>> +"""Parse a list of header files and return the component parts
>>> +
>>> +Args:
>>> +fname_list: List of files to parse
>>> +Returns:
>>> +date: String containing date from the file's header
>>> +license_text: List of text lines for the license file
>>> +microcodes: List of Microcode objects from the file
>>> +"""
>>> +microcodes = {}
>>> +license_text = []
>>> +date = ''
>>> +name = None
>>> +for fname in fname_list:
>>> +name = os.path.basename(fname).lower()
>>> +name = os.path.splitext(name)[0]
>>> +data = []
>>> +with open(fname) as fd:
>>> +for line in fd:
>>> +line = line.rstrip()
>>> +
>>> +# Omit anything after the last comma
>>> +words = line.split(',')[:-1]
>>> +data += [word + ',' for word in words]
>>> +microcodes[name] = Microcode(name, data)
>>> +return date, license_text, microcodes
>>> +
>>> +
>>> def List(date, microcodes, model):
>>> """List the available microcode chunks
>>>
>>> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
>>> break
>>> return found, tried
>>>
>>> -def CreateFile(date, license_text, mcode, outfile):
>>> +def CreateFile(date, license_text, mcodes, outfile):
>>> """Create a microcode file in U-Boot's .dtsi format
>>>
>>> Args:
>>> date: String containing date of original microcode file
>>> license:List of text lines for the license file
>>> -mcode: Microcode object to write
>>> +mcodes: Microcode objects to write (normally only 1)
>>> outfile:Filename to write to ('-' for stdout)
>>> """
>>> out = '''/*%s
>>> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
>>> data = <%s
>>> \t>;'''
>>> words = ''
>>> -for i in range(len(mcode.words)):
>>> -if not (i & 3):
>>> -words += '\n'
>>> -val = mcode.words[i]
>>> -# Change each word so it will be little-endian in the FDT
>>> -# This data is needed before RAM is available on some platforms so
>>> we
>>> -# cannot do an endianness swap on boot.
>>> -val = struct.unpack("I", val))[0]
>>> -words += '\t%#010x' % val
>>> +add_comments = len(mcodes) > 1
>>> +for mcode in mcodes:
>>> +if add_comments:
>>> +words += '\n/* %s */' % mcode.name
>>> +for i in range(len(mcode.words)):
>>> +if not (i & 3):
>>> +words += '\n'
>>> +val = mcode.words[i]
>>> +# Change each word so it will be little-endian in the FDT
>>> +# This data is needed before RAM is available on some
>>> platforms so
>>> +# we cannot do an endianness swap on boot.
>>> +val = struct.unpack("I", val))[0]
>>> +words += '\t%#010x' % val
>>> +
>>> +# Use the first microcode for the headers
>>> +mcode = mcodes[0]
>>>
>>> # Take care to avoid adding a space before a tab
>>> text = ''
>>> @@ -187,8 +223,8 @@ data = <%s
>>> print >> sys.stderr, "Creating directory '%s'" %
>>> MICROCODE_DIR
>>> os.makedirs(MICROCODE_DIR)
>>> outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
>>> -print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>>> - mcode.name, outfile)
>>> +print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>>> +', '.join([mcode.name for mcode in mcodes]), outfile)
>>> with open(outfile, 'w') as fd:
>>> print >> fd, out % tuple(args)
>>>
>>> @@ -198,8 +234,12 @@ def MicrocodeTool():
>>> parser = OptionParser()
>>> parser.add_option('-d', '--mcfile', type='string', action='store',
>>> help='Name of microcode.dat file')
>>> +parser.add_option('-H', '--headerfile',
Re: [U-Boot] [PATCH] lcd: fix console address is not initialized
Hi Nikita Kiryanov, On 01/27/2015 10:45 PM, Nikita Kiryanov wrote: Can we use the following patch to fix this issue? --->8--- diff --git a/common/lcd.c b/common/lcd.c index cc34b8a..1195a54 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -268,6 +268,7 @@ void lcd_clear(void) console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT; #endif console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH; + lcd_init_console(lcd_base, console_rows, console_cols); lcd_init_console(lcd_logo(), console_rows, console_cols); lcd_sync(); } ---8<--- It first initializes the lcd console with LCD base, if the splash screen is used, new address is updated. I think this is the best approach. I am very close to posting the next Thanks for review. I think send this fix patch first, and then you can based on this patch for your next step, or else, we can not know how long it will break most Atmel SoC related boards on master branch. So, I will send this patch and try to get it applied as soon as possible. Thanks again. step in my refactor of lcd.c, and I can incorporate it in the series. I will greatly appreciate your help in testing this series, since it involves Atmel related changes. I need this kind of fix to be applied as soon as possible, or else, most Atmel related board are broken on u-boot master branch. Best Regards, Bo Shen -- Regards, Nikita Kiryanov Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 6/7] net: Add network support to sandbox
Add basic network support to sandbox which includes a network driver.
Signed-off-by: Joe Hershberger
---
arch/sandbox/dts/sandbox.dts | 4 ++
drivers/net/Makefile | 2 +
drivers/net/sandbox.c| 91
include/configs/sandbox.h| 14 ---
4 files changed, 106 insertions(+), 5 deletions(-)
create mode 100644 drivers/net/sandbox.c
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 11748ae..a1d3199 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -174,4 +174,8 @@
};
};
+ eth@10002000 {
+ compatible = "sandbox,eth";
+ reg = <0x10002000 0x1000>;
+ };
};
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46c4ac6..2659a8a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -50,6 +50,8 @@ obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_PCNET) += pcnet.o
obj-$(CONFIG_RTL8139) += rtl8139.o
obj-$(CONFIG_RTL8169) += rtl8169.o
+obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
+obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SMC9) += smc9.o
obj-$(CONFIG_SMC911X) += smc911x.o
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
new file mode 100644
index 000..e1ee69b
--- /dev/null
+++ b/drivers/net/sandbox.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct eth_sandbox_priv {
+ void *device;
+ int sd;
+};
+
+int sb_eth_init(struct udevice *dev, bd_t *bis)
+{
+ printf("eth_sandbox: Init\n");
+
+ return 0;
+}
+
+int sb_eth_send(struct udevice *dev, void *packet, int length)
+{
+ printf("eth_sandbox: Send packet %d\n", length);
+
+ return 0;
+#endif
+}
+
+int sb_eth_recv(struct udevice *dev)
+{
+ return 0;
+}
+
+void sb_eth_halt(struct udevice *dev)
+{
+ printf("eth_sandbox: Halt\n");
+}
+
+int sb_eth_write_hwaddr(struct udevice *dev)
+{
+ printf("eth_sandbox: Write HW ADDR\n");
+ return 0;
+}
+
+static const struct eth_ops eth_sandbox_ops = {
+ .init = sb_eth_init,
+ .send = sb_eth_send,
+ .recv = sb_eth_recv,
+ .halt = sb_eth_halt,
+ .write_hwaddr = sb_eth_write_hwaddr,
+};
+
+static int eth_sandbox_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+static int sandbox_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev->platdata;
+
+ pdata->iobase = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ return 0;
+}
+
+static const struct udevice_id sandbox_eth_ids[] = {
+ { .compatible = "sandbox,eth" },
+ { }
+};
+#endif
+
+U_BOOT_DRIVER(eth_sandbox) = {
+ .name = "eth_sandbox",
+ .id = UCLASS_ETH,
+ .of_match = of_match_ptr(sandbox_eth_ids),
+ .ofdata_to_platdata = of_match_ptr(sandbox_eth_ofdata_to_platdata),
+ .remove = eth_sandbox_remove,
+ .ops= ð_sandbox_ops,
+ .priv_auto_alloc_size = sizeof(struct eth_sandbox_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 657f751..67bfc52 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -143,9 +143,9 @@
/* include default commands */
#include
-/* We don't have networking support yet */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+#define CONFIG_DM_ETH
+#define CONFIG_ETH_SANDBOX
+#define CONFIG_CMD_PING
#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
@@ -188,12 +188,16 @@
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
"stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
+ "stderr=serial,lcd\0" \
+ "ethaddr=00:00:11:22:33:44\0" \
+ "ipaddr=1.2.3.4\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
"stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
+ "stderr=serial,lcd\0" \
+ "ethaddr=00:00:11:22:33:44\0" \
+ "ipaddr=1.2.3.4\0"
#endif
#define CONFIG_GZIP_COMPRESSED
--
1.7.11.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 5/7] net: Add basic driver model support to Ethernet stack
First just add support for MAC drivers.
Signed-off-by: Joe Hershberger
---
common/board_r.c | 4 +-
common/cmd_bdinfo.c| 2 +
include/dm/uclass-id.h | 1 +
include/net.h | 23
net/eth.c | 320 -
5 files changed, 346 insertions(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index a301cc2..9a41cae 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -572,7 +572,7 @@ static int initr_bbmii(void)
}
#endif
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
static int initr_net(void)
{
puts("Net: ");
@@ -841,7 +841,7 @@ init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_BITBANGMII
initr_bbmii,
#endif
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
INIT_FUNC_WATCHDOG_RESET
initr_net,
#endif
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index e6d8a7a..8688cf9 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -34,6 +34,7 @@ static void print_eth(int idx)
printf("%-12s= %s\n", name, val);
}
+#ifndef CONFIG_DM_ETH
__maybe_unused
static void print_eths(void)
{
@@ -52,6 +53,7 @@ static void print_eths(void)
printf("current eth = %s\n", eth_get_name());
printf("ip_addr = %s\n", getenv("ipaddr"));
}
+#endif
__maybe_unused
static void print_lnum(const char *name, unsigned long long value)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f17c3c2..b04cbc9 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -33,6 +33,7 @@ enum uclass_id {
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
+ UCLASS_ETH, /* Network device */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/net.h b/include/net.h
index 7eef9cc..25636e2 100644
--- a/include/net.h
+++ b/include/net.h
@@ -78,6 +78,29 @@ enum eth_state_t {
ETH_STATE_ACTIVE
};
+#ifdef CONFIG_DM_ETH
+struct eth_pdata {
+ phys_addr_t iobase;
+};
+
+struct eth_ops {
+ int (*init)(struct udevice *dev, bd_t *bis);
+ int (*send)(struct udevice *dev, void *packet, int length);
+ int (*recv)(struct udevice *dev);
+ void (*halt)(struct udevice *dev);
+#ifdef CONFIG_MCAST_TFTP
+ int (*mcast)(struct udevice *dev, const u8 *enetaddr, u8 set);
+#endif
+ int (*write_hwaddr)(struct udevice *dev);
+};
+
+struct udevice *eth_get_dev(void); /* get the current device */
+unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
+int eth_init_state_only(bd_t *bis); /* Set active state */
+void eth_halt_state_only(void); /* Set passive state */
+#endif
+
+#ifndef CONFIG_DM_ETH
struct eth_device {
char name[16];
unsigned char enetaddr[6];
diff --git a/net/eth.c b/net/eth.c
index c02548c..d245b65 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -72,6 +72,321 @@ static int eth_mac_skip(int index)
return ((skip_state = getenv(enetvar)) != NULL);
}
+static void eth_current_changed(void);
+
+#ifdef CONFIG_DM_ETH
+#include
+
+struct eth_device_priv {
+ unsigned char enetaddr[6];
+ int state;
+ int index;
+ void *priv;
+};
+
+struct eth_uclass_priv {
+ struct udevice *current;
+ int max_index;
+};
+
+static void eth_set_current_to_next(void)
+{
+ struct uclass *uc;
+ struct eth_uclass_priv *priv;
+
+ uclass_get(UCLASS_ETH, &uc);
+ priv = uc->priv;
+ uclass_next_device(&(priv->current));
+ if (!priv->current)
+ uclass_first_device(UCLASS_ETH, &(priv->current));
+}
+
+struct udevice *eth_get_dev(void)
+{
+ struct uclass *uc;
+ uclass_get(UCLASS_ETH, &uc);
+
+ struct eth_uclass_priv *priv = uc->priv;
+ return priv->current;
+}
+
+static void eth_set_dev(struct udevice *dev)
+{
+ struct uclass *uc;
+ uclass_get(UCLASS_ETH, &uc);
+
+ struct eth_uclass_priv *priv = uc->priv;
+ priv->current = dev;
+}
+
+unsigned char *eth_get_ethaddr(void)
+{
+ struct eth_device_priv *priv;
+ if (eth_get_dev()) {
+ priv = eth_get_dev()->uclass_priv;
+ if (priv)
+ return priv->enetaddr;
+ }
+ return NULL;
+}
+
+/* Set active state */
+int eth_init_state_only(bd_t *bis)
+{
+ struct eth_device_priv *priv;
+ if (eth_get_dev()) {
+ priv = eth_get_dev()->uclass_priv;
+ if (priv)
+ priv->state = ETH_STATE_ACTIVE;
+ }
+
+ return 0;
+}
+/* Set passive state */
+void eth_halt_state_only(void)
+{
+ struct eth_device_priv *priv;
+ if (eth_get_dev()) {
+ priv = eth_get_dev()->uclass_priv;
+ if (priv)
+ priv->state = ETH_STATE_PASSIVE;
+ }
+}
+
+int eth_get_dev_in
[U-Boot] [RFC PATCH 3/7] net: Remove unneeded "extern" in net.h
Many of the functions in net.h were preceded extern needlessly. Removing
them to limit the number of checkpatch.pl complaints.
Signed-off-by: Joe Hershberger
---
include/net.h | 96 +--
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/include/net.h b/include/net.h
index a9579ee..ff8b7af 100644
--- a/include/net.h
+++ b/include/net.h
@@ -97,11 +97,11 @@ struct eth_device {
void *priv;
};
-extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */
-extern int eth_register(struct eth_device* dev);/* Register network device */
-extern int eth_unregister(struct eth_device *dev);/* Remove network device */
-extern void eth_try_another(int first_restart);/* Change the device */
-extern void eth_set_current(void); /* set nterface to ethcur var */
+int eth_initialize(bd_t *bis); /* Initialize network subsystem */
+int eth_register(struct eth_device *dev);/* Register network device */
+int eth_unregister(struct eth_device *dev);/* Remove network device */
+void eth_try_another(int first_restart); /* Change the device */
+void eth_set_current(void);/* set nterface to ethcur var */
/* get the current device MAC */
extern struct eth_device *eth_current;
@@ -119,12 +119,12 @@ static inline unsigned char *eth_get_ethaddr(void)
return NULL;
}
-extern struct eth_device *eth_get_dev_by_name(const char *devname);
-extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index
*/
-extern int eth_get_dev_index(void);/* get the device index */
-extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
-extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
-extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
+struct eth_device *eth_get_dev_by_name(const char *devname);
+struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+int eth_get_dev_index(void); /* get the device index */
+void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
+int eth_getenv_enetaddr(char *name, uchar *enetaddr);
+int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
/*
* Get the hardware address for an ethernet interface .
@@ -135,20 +135,20 @@ extern int eth_setenv_enetaddr(char *name, const uchar
*enetaddr);
* Returns:
* Return true if the address is valid.
*/
-extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
- uchar *enetaddr);
+int eth_getenv_enetaddr_by_index(const char *base_name, int index,
+uchar *enetaddr);
-extern int usb_eth_initialize(bd_t *bi);
-extern int eth_init(bd_t *bis);/* Initialize the
device */
-extern int eth_send(void *packet, int length);/* Send a packet */
+int usb_eth_initialize(bd_t *bi);
+int eth_init(bd_t *bis); /* Initialize the device */
+int eth_send(void *packet, int length); /* Send a packet */
#ifdef CONFIG_API
-extern int eth_receive(void *packet, int length); /* Receive a packet*/
-extern void (*push_packet)(void *packet, int length);
+int eth_receive(void *packet, int length); /* Receive a packet*/
+void (*push_packet)(void *packet, int length);
#endif
-extern int eth_rx(void); /* Check for received packets */
-extern void eth_halt(void);/* stop SCC */
-extern char *eth_get_name(void); /* get name of current device */
+int eth_rx(void); /* Check for received packets */
+void eth_halt(void); /* stop SCC */
+char *eth_get_name(void); /* get name of current device */
/* Set active state */
static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis)
@@ -469,25 +469,25 @@ extern IPaddr_t Mcast_addr;
#endif
/* Initialize the network adapter */
-extern void net_init(void);
-extern int NetLoop(enum proto_t);
+void net_init(void);
+int NetLoop(enum proto_t);
/* Shutdown adapters and cleanup */
-extern voidNetStop(void);
+void NetStop(void);
/* Load failed. Start again. */
-extern voidNetStartAgain(void);
+void NetStartAgain(void);
/* Get size of the ethernet header when we send */
-extern int NetEthHdrSize(void);
+intNetEthHdrSize(void);
/* Set ethernet header; returns the size of the header */
-extern int NetSetEther(uchar *, uchar *, uint);
-extern int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
+int NetSetEther(uchar *, uchar *, uint);
+int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
/* Set IP header */
-extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source);
-extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport,
+void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source);
+void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport,
[U-Boot] [PATCH v1 4/8] avr32: rename mmu.h definitions
Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.
Signed-off-by: Andreas Bießmann
---
Changes in v1:
- new since RFC
arch/avr32/cpu/at32ap700x/mmu.c |8
arch/avr32/include/asm/arch-at32ap700x/mmu.h |6 +++---
board/atmel/atngw100/atngw100.c | 12 ++--
board/atmel/atngw100mkii/atngw100mkii.c | 18 +-
board/atmel/atstk1000/atstk1000.c| 12 ++--
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 12 ++--
board/in-circuit/grasshopper/grasshopper.c | 12 ++--
board/mimc/mimc200/mimc200.c | 18 +-
board/miromico/hammerhead/hammerhead.c | 12 ++--
9 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c
index 0e28b21..f5e62f2 100644
--- a/arch/avr32/cpu/at32ap700x/mmu.c
+++ b/arch/avr32/cpu/at32ap700x/mmu.c
@@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr)
uintptr_t vmr_table_addr;
/* Round monitor address down to the nearest page boundary */
- dest_addr &= PAGE_ADDR_MASK;
+ dest_addr &= MMU_PAGE_ADDR_MASK;
/* Initialize TLB entry 0 to cover the monitor, and lock it */
sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
@@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void)
unsigned int fault_pgno;
int first, last;
- fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT;
+ fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
/* Do a binary search through the VM ranges */
@@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void)
/* Got it; let's slam it into the TLB */
uint32_t tlbelo;
- tlbelo = vmr->phys & ~PAGE_ADDR_MASK;
- tlbelo |= fault_pgno << PAGE_SHIFT;
+ tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
+ tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
sysreg_write(TLBELO, tlbelo);
__builtin_tlbw();
diff --git a/arch/avr32/include/asm/arch-at32ap700x/mmu.h
b/arch/avr32/include/asm/arch-at32ap700x/mmu.h
index fcd9a05..4736312 100644
--- a/arch/avr32/include/asm/arch-at32ap700x/mmu.h
+++ b/arch/avr32/include/asm/arch-at32ap700x/mmu.h
@@ -13,9 +13,9 @@
#include
-#define PAGE_SHIFT 20
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
+#define MMU_PAGE_SHIFT 20
+#define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT)
+#define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1))
#define MMU_VMR_CACHE_NONE \
(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index 03d767a..ed09c8c 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
- .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
- .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
- .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
- .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
- .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
- .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c
b/board/atmel/atngw100mkii/atngw100mkii.c
index 72d19e4..912ea10 100644
--- a/board/atmel/atngw100mkii/atngw100mkii.c
+++ b/board/atmel/atngw100mkii/atngw100mkii.c
@@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
- .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
- .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
- .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_
[U-Boot] [PATCH v1 8/8] atstk1002: enable generic board
Signed-off-by: Andreas Bießmann --- Changes in v1: - new since RFC include/configs/atstk1002.h |4 1 file changed, 4 insertions(+) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 9e58238..a9c064a 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -104,6 +104,10 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_GATEWAY +/* generic board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* * Command line configuration. -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 7/8] grasshopper: enable generic board
Signed-off-by: Andreas Bießmann --- Changes in v1: None include/configs/grasshopper.h |4 1 file changed, 4 insertions(+) diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 83f0ed2..54eb977 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -62,6 +62,10 @@ #define CONFIG_USART_BASE ATMEL_BASE_USART1 #define CONFIG_USART_ID1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* User serviceable stuff */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/8] avr32: factor out cpu_mmc_init()
cpu_mmc_init() is required by the init sequence to have a working MMC interface
on avr32. This will not be included in the binary if we omit the avr32 board.c
when building the generic board.
Signed-off-by: Andreas Bießmann
---
Changes in v1:
- new since RFC
arch/avr32/cpu/Makefile |1 +
arch/avr32/cpu/mmc.c| 16
arch/avr32/lib/board.c |8
3 files changed, 17 insertions(+), 8 deletions(-)
create mode 100644 arch/avr32/cpu/mmc.c
diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile
index 00cede3..e111db3 100644
--- a/arch/avr32/cpu/Makefile
+++ b/arch/avr32/cpu/Makefile
@@ -16,5 +16,6 @@ obj-y += cache.o
obj-y += interrupts.o
obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
+obj-y += mmc.o
obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/
diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c
new file mode 100644
index 000..b7213e4
--- /dev/null
+++ b/arch/avr32/cpu/mmc.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ * Copyright (C) 2015 Andreas Bießmann
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+
+/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
+int cpu_mmc_init(bd_t *bd)
+{
+ /* This calls the atmel_mci_init in gen_atmel_mci.c */
+ return atmel_mci_init((void *)ATMEL_BASE_MMCI);
+}
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 95f9526..e86530f 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -9,7 +9,6 @@
#include
#include
#include
-#include
#ifdef CONFIG_BITBANGMII
#include
@@ -38,13 +37,6 @@ static int __do_nothing(void)
int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
-/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
-int cpu_mmc_init(bd_t *bd)
-{
- /* This calls the atmel_mci_init in gen_atmel_mci.c */
- return atmel_mci_init((void *)ATMEL_BASE_MMCI);
-}
-
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
--
1.7.10.4
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[U-Boot] [PATCH v1 5/8] common/board_r: manual relocation for cmd table
This is required for architectures still need manual relocation like avr32, m68k
microblaze and maybe others.
Signed-off-by: Andreas Bießmann
Reviewed-by: Simon Glass
Tested-by: Michal Simek
---
Changes in v1: None
common/board_r.c | 12
1 file changed, 12 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index a301cc2..e712902 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -294,6 +294,15 @@ static int initr_announce(void)
return 0;
}
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+static int initr_manual_reloc_cmdtable(void)
+{
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
+ return 0;
+}
+#endif
+
#if !defined(CONFIG_SYS_NO_FLASH)
static int initr_flash(void)
{
@@ -718,6 +727,9 @@ init_fnc_t init_sequence_r[] = {
initr_serial,
initr_announce,
INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ initr_manual_reloc_cmdtable,
+#endif
#ifdef CONFIG_PPC
initr_trap,
#endif
--
1.7.10.4
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[U-Boot] [PATCH v1 2/8] avr32: rename cpu_init() -> arch_cpu_init()
Signed-off-by: Andreas Bießmann
---
Changes in v1: None
arch/avr32/cpu/cpu.c|2 +-
arch/avr32/include/asm/u-boot.h |2 ++
arch/avr32/lib/board.c |2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c
index cef630e..cd226a6 100644
--- a/arch/avr32/cpu/cpu.c
+++ b/arch/avr32/cpu/cpu.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int cpu_init(void)
+int arch_cpu_init(void)
{
extern void _evba(void);
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 6aef808..2387f8a 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -25,4 +25,6 @@ typedef struct bd_info {
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
+int arch_cpu_init(void);
+
#endif /* __ASM_U_BOOT_H__ */
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 7d13ac5..95f9526 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -98,7 +98,7 @@ void board_init_f(ulong board_type)
/* Perform initialization sequence */
board_early_init_f();
- cpu_init();
+ arch_cpu_init();
board_postclk_init();
env_init();
init_baudrate();
--
1.7.10.4
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[U-Boot] [PATCH v1 1/8] avr32: use dlmalloc for DMA buffers
Signed-off-by: Andreas Bießmann
---
Changes in v1: None
arch/avr32/include/asm/dma-mapping.h |7 -
arch/avr32/lib/board.c | 51 --
include/configs/atngw100.h |1 -
include/configs/atngw100mkii.h |1 -
include/configs/atstk1002.h |1 -
include/configs/atstk1006.h |1 -
include/configs/favr-32-ezkit.h |1 -
include/configs/grasshopper.h|1 -
include/configs/hammerhead.h |1 -
include/configs/mimc200.h|1 -
10 files changed, 6 insertions(+), 60 deletions(-)
diff --git a/arch/avr32/include/asm/dma-mapping.h
b/arch/avr32/include/asm/dma-mapping.h
index dbdd2fe..1cde827 100644
--- a/arch/avr32/include/asm/dma-mapping.h
+++ b/arch/avr32/include/asm/dma-mapping.h
@@ -14,7 +14,12 @@ enum dma_data_direction {
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
};
-extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
enum dma_data_direction dir)
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index bf0997f..7d13ac5 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -45,50 +45,6 @@ int cpu_mmc_init(bd_t *bd)
return atmel_mci_init((void *)ATMEL_BASE_MMCI);
}
-#ifdef CONFIG_SYS_DMA_ALLOC_LEN
-#include
-#include
-
-static unsigned long dma_alloc_start;
-static unsigned long dma_alloc_end;
-static unsigned long dma_alloc_brk;
-
-static void dma_alloc_init(void)
-{
- unsigned long monitor_addr;
-
- monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
- dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN;
- dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN;
- dma_alloc_brk = dma_alloc_start;
-
- printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
- dma_alloc_start, dma_alloc_end);
-
- invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
- dma_alloc_end);
-}
-
-void *dma_alloc_coherent(size_t len, unsigned long *handle)
-{
- unsigned long paddr = dma_alloc_brk;
-
- if (dma_alloc_brk + len > dma_alloc_end)
- return NULL;
-
- dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1)
-& ~(CONFIG_SYS_DCACHE_LINESZ - 1));
-
- *handle = paddr;
- return uncached(paddr);
-}
-#else
-static inline void dma_alloc_init(void)
-{
-
-}
-#endif
-
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
@@ -180,12 +136,6 @@ void board_init_f(ulong board_type)
/* Reserve memory for malloc() */
addr -= CONFIG_SYS_MALLOC_LEN;
-#ifdef CONFIG_SYS_DMA_ALLOC_LEN
- /* Reserve DMA memory (must be cache aligned) */
- addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1);
- addr -= CONFIG_SYS_DMA_ALLOC_LEN;
-#endif
-
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
@@ -264,7 +214,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
- dma_alloc_init();
enable_interrupts();
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 9c81e31..540e86a 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -143,7 +143,6 @@
#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INTRAM_BASE +
CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
-#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x0040)
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 7b4f9cf..35eae76 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -164,7 +164,6 @@
#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INTRAM_BASE +
CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
-#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x0040)
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 8f3fd0b..9e58238 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -158,7 +158,6 @@
#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INTRAM_BASE +
CONFIG_SYS_INTRAM_SIZE)
#def
[U-Boot] [RFC PATCH 4/7] net: Refactor in preparation for driver model
Move some things around and organize things so that the driver model
implementation will fit in more easily.
Signed-off-by: Joe Hershberger
---
include/net.h | 63 +
net/eth.c | 75 +++
2 files changed, 73 insertions(+), 65 deletions(-)
diff --git a/include/net.h b/include/net.h
index ff8b7af..7eef9cc 100644
--- a/include/net.h
+++ b/include/net.h
@@ -100,10 +100,7 @@ struct eth_device {
int eth_initialize(bd_t *bis); /* Initialize network subsystem */
int eth_register(struct eth_device *dev);/* Register network device */
int eth_unregister(struct eth_device *dev);/* Remove network device */
-void eth_try_another(int first_restart); /* Change the device */
-void eth_set_current(void);/* set nterface to ethcur var */
-/* get the current device MAC */
extern struct eth_device *eth_current;
static inline __attribute__((always_inline))
@@ -112,6 +109,7 @@ struct eth_device *eth_get_dev(void)
return eth_current;
}
+/* get the current device MAC */
static inline unsigned char *eth_get_ethaddr(void)
{
if (eth_current)
@@ -119,6 +117,37 @@ static inline unsigned char *eth_get_ethaddr(void)
return NULL;
}
+/* Set active state */
+static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis)
+{
+ eth_get_dev()->state = ETH_STATE_ACTIVE;
+
+ return 0;
+}
+/* Set passive state */
+static inline __attribute__((always_inline)) void eth_halt_state_only(void)
+{
+ eth_get_dev()->state = ETH_STATE_PASSIVE;
+}
+
+/*
+ * Set the hardware address for an ethernet interface based on 'eth%daddr'
+ * environment variable (or just 'ethaddr' if eth_number is 0).
+ * Args:
+ * base_name - base name for device (normally "eth")
+ * eth_number - value of %d (0 for first device of this type)
+ * Returns:
+ * 0 is success, non-zero is error status from driver.
+ */
+int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
+int eth_number);
+
+int usb_eth_initialize(bd_t *bi);
+#endif
+
+void eth_try_another(int first_restart); /* Change the device */
+void eth_set_current(void);/* set nterface to ethcur var */
+
struct eth_device *eth_get_dev_by_name(const char *devname);
struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
int eth_get_dev_index(void); /* get the device index */
@@ -138,7 +167,6 @@ int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
-int usb_eth_initialize(bd_t *bi);
int eth_init(bd_t *bis); /* Initialize the device */
int eth_send(void *packet, int length); /* Send a packet */
@@ -148,32 +176,7 @@ void (*push_packet)(void *packet, int length);
#endif
int eth_rx(void); /* Check for received packets */
void eth_halt(void); /* stop SCC */
-char *eth_get_name(void); /* get name of current device */
-
-/* Set active state */
-static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis)
-{
- eth_get_dev()->state = ETH_STATE_ACTIVE;
-
- return 0;
-}
-/* Set passive state */
-static inline __attribute__((always_inline)) void eth_halt_state_only(void)
-{
- eth_get_dev()->state = ETH_STATE_PASSIVE;
-}
-
-/*
- * Set the hardware address for an ethernet interface based on 'eth%daddr'
- * environment variable (or just 'ethaddr' if eth_number is 0).
- * Args:
- * base_name - base name for device (normally "eth")
- * eth_number - value of %d (0 for first device of this type)
- * Returns:
- * 0 is success, non-zero is error status from driver.
- */
-int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
-int eth_number);
+const char *eth_get_name(void);/* get name of current device */
#ifdef CONFIG_MCAST_TFTP
int eth_mcast_join(IPaddr_t mcast_addr, u8 join);
diff --git a/net/eth.c b/net/eth.c
index 65e8c77..c02548c 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -55,6 +55,14 @@ static inline int eth_setenv_enetaddr_by_index(const char
*base_name, int index,
return eth_setenv_enetaddr(enetvar, enetaddr);
}
+static void eth_env_init(void)
+{
+ const char *s;
+
+ s = getenv("bootfile");
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
+}
static int eth_mac_skip(int index)
{
@@ -87,6 +95,11 @@ static unsigned int eth_rcv_current, eth_rcv_last;
static struct eth_device *eth_devices;
struct eth_device *eth_current;
+static void eth_set_current_to_next(void)
+{
+ eth_current = eth_current->next;
+}
+
struct eth_device *eth_get_dev_by_name(const char *devname)
{
struct eth_device *dev, *target_dev;
@@ -137,22 +150,6 @@ int eth_get_dev_index(void)
[U-Boot] [RFC PATCH 1/7] net: Provide a function to get the current MAC address
The current implementation exposes the eth_device struct to code that
needs to access the MAC address. Add a wrapper function for this to
abstract away the pointer for this operation.
Signed-off-by: Joe Hershberger
---
arch/mips/cpu/mips32/au1x00/au1x00_eth.c | 2 +-
arch/powerpc/cpu/mpc8260/ether_fcc.c | 2 +-
arch/powerpc/cpu/mpc85xx/ether_fcc.c | 2 +-
arch/powerpc/cpu/mpc8xx/scc.c| 2 +-
include/net.h| 8
net/net.c| 2 +-
6 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
index 4770f56..535d713 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
@@ -238,7 +238,7 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
}
/* Put mac addr in little endian */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
(ea[1] << 8) | (ea[0] ) ;
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c
b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index f9f15b5..f777ba1 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -299,7 +299,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
* it unique by setting a few bits in the upper byte of the
* non-static part of the address.
*/
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 166dc9e..58d4bfb 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -338,7 +338,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
* it unique by setting a few bits in the upper byte of the
* non-static part of the address.
*/
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 251966b..66e4014 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -339,7 +339,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/include/net.h b/include/net.h
index 73ea88b..a9579ee 100644
--- a/include/net.h
+++ b/include/net.h
@@ -111,6 +111,14 @@ struct eth_device *eth_get_dev(void)
{
return eth_current;
}
+
+static inline unsigned char *eth_get_ethaddr(void)
+{
+ if (eth_current)
+ return eth_current->enetaddr;
+ return NULL;
+}
+
extern struct eth_device *eth_get_dev_by_name(const char *devname);
extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index
*/
extern int eth_get_dev_index(void);/* get the device index */
diff --git a/net/net.c b/net/net.c
index 2bea07b..ddd630c 100644
--- a/net/net.c
+++ b/net/net.c
@@ -275,7 +275,7 @@ static void NetInitLoop(void)
env_changed_id = env_id;
}
if (eth_get_dev())
- memcpy(NetOurEther, eth_get_dev()->enetaddr, 6);
+ memcpy(NetOurEther, eth_get_ethaddr(), 6);
return;
}
--
1.7.11.5
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[U-Boot] [RFC PATCH 7/7] net: Add ARP and PING response to sandbox driver
The sandbox driver will now generate response traffic to exercise the
ping command even when no network exists. This allows the basic data
pathways of the DM to be tested.
Signed-off-by: Joe Hershberger
---
drivers/net/sandbox.c | 75 +++
1 file changed, 75 insertions(+)
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
index e1ee69b..49413f2 100644
--- a/drivers/net/sandbox.c
+++ b/drivers/net/sandbox.c
@@ -20,6 +20,11 @@ struct eth_sandbox_priv {
int sd;
};
+static uchar fake_host_hwaddr[ARP_HLEN] = {0x00, 0x00, 0x66, 0x44, 0x22, 0x00};
+static IPaddr_t fake_host_ipaddr;
+static uchar recv_packet_buffer[PKTSIZE];
+static int recv_packet_length;
+
int sb_eth_init(struct udevice *dev, bd_t *bis)
{
printf("eth_sandbox: Init\n");
@@ -31,12 +36,82 @@ int sb_eth_send(struct udevice *dev, void *packet, int
length)
{
printf("eth_sandbox: Send packet %d\n", length);
+ struct ethernet_hdr *eth = packet;
+ if (ntohs(eth->et_protlen) == PROT_ARP) {
+ struct arp_hdr *arp = packet + ETHER_HDR_SIZE;
+ if (ntohs(arp->ar_op) == ARPOP_REQUEST) {
+ /* store this as the assumed IP of the fake host */
+ fake_host_ipaddr = NetReadIP(&arp->ar_tpa);
+ /* Formulate a fake response */
+ struct ethernet_hdr *eth_recv =
+ (void *)recv_packet_buffer;
+ memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN);
+ memcpy(eth_recv->et_src, fake_host_hwaddr, ARP_HLEN);
+ eth_recv->et_protlen = htons(PROT_ARP);
+
+ struct arp_hdr *arp_recv = (void *)recv_packet_buffer +
+ ETHER_HDR_SIZE;
+ arp_recv->ar_hrd = htons(ARP_ETHER);
+ arp_recv->ar_pro = htons(PROT_IP);
+ arp_recv->ar_hln = ARP_HLEN;
+ arp_recv->ar_pln = ARP_PLEN;
+ arp_recv->ar_op = htons(ARPOP_REPLY);
+ memcpy(&arp_recv->ar_sha, fake_host_hwaddr, ARP_HLEN);
+ NetWriteIP(&arp_recv->ar_spa, fake_host_ipaddr);
+ memcpy(&arp_recv->ar_tha, &arp->ar_sha, ARP_HLEN);
+ NetCopyIP(&arp_recv->ar_tpa, &arp->ar_spa);
+
+ recv_packet_length = ETHER_HDR_SIZE + ARP_HDR_SIZE;
+ }
+ } else if (ntohs(eth->et_protlen) == PROT_IP) {
+ struct ip_udp_hdr *ip = packet + ETHER_HDR_SIZE;
+ if (ip->ip_p == IPPROTO_ICMP) {
+ struct icmp_hdr *icmp = (struct icmp_hdr *)&ip->udp_src;
+ if (icmp->type == ICMP_ECHO_REQUEST) {
+ /* reply to the ping */
+ memcpy(recv_packet_buffer, packet, length);
+ struct ethernet_hdr *eth_recv =
+ (void *)recv_packet_buffer;
+ struct ip_udp_hdr *ipr =
+ (void *)recv_packet_buffer +
+ ETHER_HDR_SIZE;
+ struct icmp_hdr *icmpr =
+ (struct icmp_hdr *)&ipr->udp_src;
+ memcpy(eth_recv->et_dest, eth->et_src,
+ ARP_HLEN);
+ memcpy(eth_recv->et_src, fake_host_hwaddr,
+ ARP_HLEN);
+ ipr->ip_sum = 0;
+ ipr->ip_off = 0;
+ NetCopyIP((void *)&ipr->ip_dst, &ip->ip_src);
+ NetWriteIP((void *)&ipr->ip_src,
+ fake_host_ipaddr);
+ ipr->ip_sum = ~NetCksum((uchar *)ipr,
+ IP_HDR_SIZE >> 1);
+
+ icmpr->type = ICMP_ECHO_REPLY;
+ icmpr->checksum = 0;
+ icmpr->checksum = ~NetCksum((uchar *)icmpr,
+ (length - ETHER_HDR_SIZE -
+ IP_HDR_SIZE) >> 1);
+
+ recv_packet_length = length;
+ }
+ }
+ }
+
return 0;
#endif
}
int sb_eth_recv(struct udevice *dev)
{
+ if (recv_packet_length) {
+ int lcl_recv_packet_length = recv_packet_length;
+ printf("eth_sandbox: received packet %d\n", recv_packet_length);
+ recv_packet_length = 0;
+ NetReceive((void *)recv_packet_buffer, lcl_recv_packet_length);
+ }
return 0;
}
--
1.7.11.5
_
[U-Boot] [RFC PATCH 0/7] Add Driver Model support to network stack
For now this simply addresses the MAC part of the network hardware. The next part to implement is the PHY children. I wanted to get early feedback on what I have so far to make sure I'm going in the direction that Simon envisioned. Joe Hershberger (7): net: Provide a function to get the current MAC address net: Rename helper function to be more clear net: Remove unneeded "extern" in net.h net: Refactor in preparation for driver model net: Add basic driver model support to Ethernet stack net: Add network support to sandbox net: Add ARP and PING response to sandbox driver arch/mips/cpu/mips32/au1x00/au1x00_eth.c | 2 +- arch/powerpc/cpu/mpc8260/ether_fcc.c | 2 +- arch/powerpc/cpu/mpc85xx/ether_fcc.c | 2 +- arch/powerpc/cpu/mpc8xx/scc.c| 2 +- arch/sandbox/dts/sandbox.dts | 4 + common/board_r.c | 4 +- common/cmd_bdinfo.c | 2 + drivers/net/Makefile | 2 + drivers/net/sandbox.c| 166 + include/configs/sandbox.h| 14 +- include/dm/uclass-id.h | 1 + include/net.h| 158 +++- net/eth.c| 408 +++ net/net.c| 2 +- 14 files changed, 649 insertions(+), 120 deletions(-) create mode 100644 drivers/net/sandbox.c -- 1.7.11.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 2/7] net: Rename helper function to be more clear
Make it clear that the helper is checking the addr, not setting it.
Signed-off-by: Joe Hershberger
---
net/eth.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/net/eth.c b/net/eth.c
index eac4f7b..65e8c77 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -153,11 +153,6 @@ static void eth_current_changed(void)
setenv("ethact", NULL);
}
-static int eth_address_set(unsigned char *addr)
-{
- return memcmp(addr, "\0\0\0\0\0\0", 6);
-}
-
int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
int eth_number)
{
@@ -166,9 +161,9 @@ int eth_write_hwaddr(struct eth_device *dev, const char
*base_name,
eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr);
- if (eth_address_set(env_enetaddr)) {
- if (eth_address_set(dev->enetaddr) &&
- memcmp(dev->enetaddr, env_enetaddr, 6)) {
+ if (!is_zero_ether_addr(env_enetaddr)) {
+ if (!is_zero_ether_addr(dev->enetaddr) &&
+ memcmp(dev->enetaddr, env_enetaddr, 6)) {
printf("\nWarning: %s MAC addresses don't match:\n",
dev->name);
printf("Address in SROM is %pM\n",
@@ -183,7 +178,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char
*base_name,
dev->enetaddr);
printf("\nWarning: %s using MAC address from net device\n",
dev->name);
- } else if (!(eth_address_set(dev->enetaddr))) {
+ } else if (is_zero_ether_addr(dev->enetaddr)) {
printf("\nError: %s address not set.\n",
dev->name);
return -EINVAL;
--
1.7.11.5
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Re: [U-Boot] [PATCH 1/5] nand: Use common read function instead of verify_buf()
Hi Scott, > > I waffled about removing it, but leaned towards leaving it in because: > > - I didn't want to change the existing U-Boot behavior for other > > users. A google of 'u-boot "nand write"' shows a lot of examples that > > don't include verification of writes, and they should if we remove > > auto-verification. > > How many configs actually enable this option? I don't see many beyond > the FSL PPC boards (which are so full of copy-and-paste that it probably > wasn't deliberate). Yeah, the majority are FSL 83xx and 85xx, with 2 or so random ARM boards. > > - The reason it was removed in Linux was "Both UBI and JFFS2 are able > > to read verify what they wrote already. There are also MTD tests > > which do this verification." I thought U-Boot was more likely than > > Linux to use raw NAND writes without a filesystem, so leaving it in U- > > Boot made sense since the UBI/JFFS2 logic didn't apply as much here. > > Right, though raw writes ought to be limited to blocks that aren't > written often enough to fail. > > > - I didn't think a lot of people would know they have to explicitly > > verify NAND contents after a write, since they'd assume it was like > > other memories that aren't as lossy. > > > > - The penalty of slightly different code from Linux and a small > > performance hit was worth the gain of auto-verification to me. I > > viewed consolidating it into one small chunk of code as a happy medium. > > The davinci patches show that there can still be driver dependencies > depending on what the driver overrides. I'm not hugely opposed, but it > seems like it would be better to do it at a higher level (e.g. in > nand_util.c with a flag to enable, and either make support mandatory, or > if you try to use that command variant without support it fails rather > than silently not verifying). That seems like a good idea. How about: - Remove all CONFIG_MTD_NAND_VERIFY_WRITE references - Add a new flag WITH_WR_VERIFY and have nand_write_skip_bad() in nand_util.c verify writes only when it is set. - Update the calls to nand_write_skip_bad() in cmd_nand.c to include the new WITH_WR_VERIFY flag. I'd vote to enable it for all boards, but let me know if you disagree. That would make all "nand write" commands verify writes, with the exception of "nand write.raw". Any opinion on if this should also be verified? I only use it for development/testing, so don't have a strong opinion. Regards, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] RFC: dm: Kconfig: Move all driver model CONFIGs to Kconfig
On Tue, Dec 9, 2014 at 7:21 AM, Simon Glass wrote: > > Kconfig has been available for a while but there are still driver model > CONFIG options. Move all of these to Kconfig. > > This patch isn't final - I need to wait until the SPL series can be fully > applied, which is in turn waiting on some ARM SPL problems. So for now it > is just a placeholder. But it needs to be sent out otherwise we will never > move over. > > Signed-off-by: Simon Glass > --- > diff --git a/common/Kconfig b/common/Kconfig > index fd84fa0..174bf4f 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -153,6 +153,29 @@ endmenu > > menu "Device access commands" > > +config CMD_DM > + bool "dm - Access to driver model information" > + depends on DM > + default y > + help > + Provides access to driver model data structures and information, > + such as a list of devices, list of uclasses and the state of each > + device (e.g. activated). This is not required for operation, but > + can be useful to see the state of driver model for debugging or > + interest. > + > +config CMD_DEMO > + bool "demo - Demonstration commands for driver model" > + depends on DM > + help > + Procides a 'demo' command which can be used to play around with Provides > + driver model. To use this properly you will need to enable one or > + both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE). > + Otherwise you will always get an empty list of devices. The demo > + devices are defined in the sandbox device tree, so the easiest > + option is to use sandbox and pass the -d point to sandbox's > + u-boot.dtb file. > + > config CMD_LOADB > bool "loadb" > help ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] checkstack.pl
Masahiro, Do you mind to add aarch64 support for checkstack.pl? $ make checkstack /opt/linaro/gcc-linaro-aarch64-linux-gnu-4.8-2013.12_linux/bin/aarch64-linux-gnu-objdump -d u-boot $(find . -name u-boot-spl) | \ perl ./scripts/checkstack.pl aarch64 wrong or unknown architecture "aarch64" York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mtd:mxs:nand calculate ecc strength dynamically
On Fr, 2014-12-19 at 12:39 +0800, Peng Fan wrote:
> Calculate ecc strength according oobsize, but not hardcoded
> which is not aligned with kernel driver
>
> Signed-off-by: Peng Fan
> Signed-off-by: Ye.Li
> ---
> drivers/mtd/nand/mxs_nand.c | 22 --
> 1 file changed, 4 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
> index 7a064ab..a45fcf9 100644
> --- a/drivers/mtd/nand/mxs_nand.c
> +++ b/drivers/mtd/nand/mxs_nand.c
> @@ -146,26 +146,12 @@ static uint32_t mxs_nand_aux_status_offset(void)
> static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
> uint32_t page_oob_size)
> {
> - if (page_data_size == 2048) {
> - if (page_oob_size == 64)
> - return 8;
> + int ecc_strength;
>
> - if (page_oob_size == 112)
> - return 14;
> - }
> -
> - if (page_data_size == 4096) {
> - if (page_oob_size == 128)
> - return 8;
> -
> - if (page_oob_size == 218)
> - return 16;
> + ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
> + / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
>
> - if (page_oob_size == 224)
> - return 16;
> - }
> -
> - return 0;
> + return round_down(ecc_strength, 2);
> }
>
> static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
Many thanks for the patch! But this patch affects mxsboot which is no
not aligned with the U-Boot mxs nand driver.
I was able to fix mxsboot, but I had difficulties with round_down, which
is a macro definition in linux/kernel.h. I've copied the macro
definition to mxsboot. I will submit the patch in a seperate mail.
I would like to see a comment or a macro for the magic number 13, which
is the value for the Galois Field, just for clarification
With fixing mxsboot, I was able to test the patch on a custom
i.MX28-based board assembled with a 1Gbit NAND flash (page size = 2048
bytes, oob size = 128 bytes).
U-Boot correctly reads the NAND info
=> nand info
Device 0: nand0, sector size 128 KiB
Page size 2048 b
OOB size128 b
Erase size 131072 b
Before the patch linux failed to read from the UBI device with an ECC
error:
UBI error: ubi_io_read: error -74 (ECC error)
This patch resolves the error. Linux can read the UBI device now. This
is kernel message:
nand: device found, Manufacturer ID: 0x98, Chip ID: 0xf1
[1.327810] nand: Toshiba NAND 128MiB 3,3V 8-bit
[1.332482] nand: 128MiB, SLC, page size: 2048, OOB size: 128
BCH Geometry :
[1.594658] GF length : 13
[1.594658] ECC Strength : 18
[1.594658] Page Size in Bytes : 2176
[1.594658] Metadata Size in Bytes : 10
[1.594658] ECC Chunk Size in Bytes: 512
[1.594658] ECC Chunk Count: 4
[1.594658] Payload Size in Bytes : 2048
[1.594658] Auxiliary Size in Bytes: 16
[1.594658] Auxiliary Status Offset: 12
[1.594658] Block Mark Byte Offset : 1950
[1.594658] Block Mark Bit Offset : 2
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Re: [U-Boot] [PATCH 2/4] usb: add 'bcm_udc_otg' support
On Monday, January 26, 2015 at 06:44:14 PM, Steve Rae wrote: [...] > > No, unless there's a convincing technical argument that the currently > > mainline DWC2 gadget driver (the s3c one) can absolutelly not be used > > for the broadcom SoC, I want to avoid having two drivers for the same > > IP core in mainline, sorry. > > > > [...] > > > > Sorry, at this point I have to push back a little. > > OK -- Thanks for this information Hi! do you plan to rework the series on top of the dwc2 (s3c) driver by any chance please ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI
On Tuesday, January 27, 2015 at 09:52:14 PM, Simon Glass wrote: > Hi Marek, Hi! > On 27 January 2015 at 10:57, Marek Vasut wrote: > > On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote: > >> Add a driver which locates the available XHCI controllers on the PCI bus > >> and makes them available. > >> > >> Signed-off-by: Simon Glass > > > > Hi! > > > > Which xhci controllers did you test with this patch and on which platform > > please? Is it just the minnow max + the integrated usb 3.0 controller on > > it? I recall I tried this, but had trouble getting the xhci-pci going on > > MX6 with a PCIe card with renesas controller. > > > > Thanks for working on this ! > > I tested it on an Intel controller (MinnowMax board). As mentioned in > the cover letter it doesn't actually work, but I suspect that could be > an XHCI stack issue. Not 100% sure though. At least this is a starting > point. Ah, I must have missed that, sorry. Good luck with this USB3 stuff! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
On Tuesday, January 27, 2015 at 09:53:01 PM, Simon Glass wrote: > Hi Marek, Hi Simon, > On 27 January 2015 at 10:50, Marek Vasut wrote: > > On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote: > >> Use the new utility function instead of local code. > >> > >> Signed-off-by: Simon Glass > >> --- > >> > >> drivers/usb/host/ehci-pci.c | 53 > >> > >> + 1 file changed, 1 > >> insertion(+), 52 deletions(-) > > > > Nice! > > > > Acked-by: Marek Vasut > > > > Do you want to pick it through the x86 tree or shall I pick it through > > USB ? > > I think x86 is better since it is part of a series. I agree, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
Hi Marek, On 27 January 2015 at 10:50, Marek Vasut wrote: > On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote: >> Use the new utility function instead of local code. >> >> Signed-off-by: Simon Glass >> --- >> >> drivers/usb/host/ehci-pci.c | 53 >> + 1 file changed, 1 >> insertion(+), 52 deletions(-) > > Nice! > > Acked-by: Marek Vasut > > Do you want to pick it through the x86 tree or shall I pick it through USB ? > I think x86 is better since it is part of a series. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
