[U-Boot] [PATCH] stm32f4: fix serial output
Signed-off-by: kunhuahuang huangkun...@gmail.com
---
drivers/serial/serial_stm32.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..693a7fa 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -81,6 +81,10 @@ static int stm32_serial_getc(void)
static void stm32_serial_putc(const char c)
{
struct stm32_serial *usart = (struct stm32_serial *)USART_BASE;
+
+ if(c == '\n')
+ stm32_serial_putc('\r');
+
while ((readl(usart-sr) USART_SR_FLAG_TXE) == 0)
;
writel(c, usart-dr);
--
1.9.1
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[U-Boot] installing u-boot on a virtual x86 machine
I'm Francesco Lucconi from Italy, and I'm involved into a x86 project where my issue is to compile a u-boot (I'm currently using uboot-2015.01) and to install it into a VID (virtual image disk) of virtualbox. I've already tuned the MBR, registering two FAT16 partitions, one for u-boot and the other one for future kernel uImage and firmware development. In this moment I figured out that I've installed correctly the MBR cause I can see on the display strings I've applied on the MBR source code but it seems that u-boot.bin code doesn't run correctly, the system hangs out Could you give me any tips I didn't notice before? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/21] sunxi: usbc: Fix vbus gpio handling to work with the device-model
On Fri, Apr 24, 2015 at 10:48 AM, Hans de Goede hdego...@redhat.com wrote:
sunxi_usbc-gpio_vbus = get_vbus_gpio(index);
- if (sunxi_usbc-gpio_vbus != -1) {
+ if (sunxi_usbc-gpio_vbus = 0) {
What about using dm_gpio_is_valid() instead?
Regards,
Fabio Estevam
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Re: [U-Boot] [PATCH 1/2] dm: sf: Make SST flash write op work again
On 24 April 2015 at 14:12, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Fri, Apr 24, 2015 at 4:07 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Bin,
On 23 April 2015 at 14:30, Bin Meng bmeng...@gmail.com wrote:
With SPI flash moving to driver model, commit fbb0991 dm: Convert
spi_flash_probe() and 'sf probe' to use driver model ignored the
SST flash-specific write op (byte program word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
a new SST flash-specific driver to handle the different write op
from the standard one.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_probe.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d19138d..47438d2 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -511,4 +511,35 @@ U_BOOT_DRIVER(spi_flash_std) = {
.ops= spi_flash_std_ops,
};
+int spi_flash_sst_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ return sst_write_bp(flash, offset, len, buf);
+ else
+ return sst_write_wp(flash, offset, len, buf);
+}
+
+static const struct dm_spi_flash_ops spi_flash_sst_ops = {
+ .read = spi_flash_std_read,
+ .write = spi_flash_sst_write,
+ .erase = spi_flash_std_erase,
+};
+
+static const struct udevice_id spi_flash_sst_ids[] = {
+ { .compatible = spi-flash-sst },
+ { }
+};
+
+U_BOOT_DRIVER(spi_flash_sst) = {
+ .name = spi_flash_sst,
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_flash_sst_ids,
+ .probe = spi_flash_std_probe,
+ .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .ops= spi_flash_sst_ops,
+};
+
#endif /* CONFIG_DM_SPI_FLASH */
--
1.8.2.1
I'm just curiosity to see different approach of being code duplicate
with just for sst write call.
What about this-
int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
const void *buf)
{
struct spi_flash *flash = dev_get_uclass_priv(dev);
if defined(CONFIG_SPI_FLASH_SST)
if (flash-flags SST_WR) {
if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
}
#endif
return spi_flash_cmd_write_ops(flash, offset, len, buf);
}
Of course this requires extra flags member in spi_flash, any other thoughts?
Yep, this way works too. Let me know which way you prefer and I can respin a
v2.
I preferred second.
thanks!
--
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Re: [U-Boot] [PATCH 03/21] sunxi: usbc: Fix vbus gpio handling to work with the device-model
Hi,
On 24-04-15 20:10, Fabio Estevam wrote:
On Fri, Apr 24, 2015 at 10:48 AM, Hans de Goede hdego...@redhat.com wrote:
sunxi_usbc-gpio_vbus = get_vbus_gpio(index);
- if (sunxi_usbc-gpio_vbus != -1) {
+ if (sunxi_usbc-gpio_vbus = 0) {
What about using dm_gpio_is_valid() instead?
dm_gpio_is_valid takes a struct gpio_desc *, where as this code is using
good old gpio indexes (int). We will likely want to convert this to getting
the gpio from devicetree directly in the future, but first we need this
patch-set to convert all sunxi boards to the device-model, so that we can
make such changes without the need to introduce a whole lot of #ifdef-s
Regards,
Hans
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Re: [U-Boot] [PATCH v4 07/16] dm: regulator: add regulator command
Hello Simon,
On 04/24/2015 06:51 AM, Simon Glass wrote:
Hi Przemyslaw,
On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello Simon,
On 04/22/2015 06:30 PM, Simon Glass wrote:
Hi Przemyslaw,
On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com
wrote:
This command is based on driver model regulator's API.
The user interface provides:
- list UCLASS regulator devices
- show or [set] operating regulator device
- print constraints info
- print operating status
- print/[set] voltage value [uV] (force)
- print/[set] current value [uA]
- print/[set] operating mode id
- enable the regulator output
- disable the regulator output
The 'force' option can be used for setting the value which exceeds
the constraints min/max limits.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v3:
- new file
- Kconfig entry
Changes V4:
- cmd regulator: move platdata to uc pdata
- cmd_regulator: includes cleanup
- cmd_regulator: add get_curr_dev_and_pl() check type
- move config name: CONFIG_DM_REGULATOR_CMD to CONFIG_CMD_REGULATOR
- common/Kconfig - cleanup
---
common/Kconfig | 22 +++
common/Makefile| 1 +
common/cmd_regulator.c | 403
+
3 files changed, 426 insertions(+)
create mode 100644 common/cmd_regulator.c
Acked-by: Simon Glass s...@chromium.org
I have a few nits that could be dealt with by a follow-on patch.
Ok.
diff --git a/common/Kconfig b/common/Kconfig
index 4666f8e..52f8bb1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -470,5 +470,27 @@ config CMD_PMIC
- pmic read address - read byte of register at address
- pmic write address - write byte to register at address
The only one change for this command is 'dev' subcommand.
+
+config CMD_REGULATOR
+ bool Enable Driver Model REGULATOR command
+ depends on DM_REGULATOR
+ help
+ This command is based on driver model regulator's API.
+ User interface features:
+ - list - list regulator devices
+ - regulator dev id - show or [set] operating regulator device
+ - regulator info - print constraints info
+ - regulator status - print operating status
+ - regulator value val] -f - print/[set] voltage value [uV]
+ - regulator current val- print/[set] current value [uA]
+ - regulator mode id- print/[set] operating mode id
+ - regulator enable - enable the regulator output
+ - regulator disable - disable the regulator output
+
+ The '-f' (force) option can be used for set the value which
exceeds
+ the limits, which are found in device-tree and are kept in
regulator's
+ uclass platdata structure.
+
endmenu
+
endmenu
diff --git a/common/Makefile b/common/Makefile
index 87a3efe..93bded3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -212,6 +212,7 @@ obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
# Power
obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o
+obj-$(CONFIG_CMD_REGULATOR) += cmd_regulator.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c
new file mode 100644
index 000..b1b9e87
--- /dev/null
+++ b/common/cmd_regulator.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2014-2015 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include errno.h
+#include dm.h
+#include dm/uclass-internal.h
+#include power/regulator.h
+
+#define LIMIT_SEQ 3
+#define LIMIT_DEVNAME 20
+#define LIMIT_OFNAME 20
+#define LIMIT_INFO 16
+
+static struct udevice *currdev;
+
+static int failed(const char *getset, const char *thing,
+ const char *for_dev, int ret)
+{
+ printf(Can't %s %s %s.\nError: %d (%s)\n, getset, thing,
for_dev,
+ ret, errno_str(ret));
blank line here.
I don't see the blank line here in the patch, which I send.
Odd, there seem to be two blank lines there, and we only need one.
Ah, sorry. You mean, that there should be added a blank line.
Ok, will add one.
I worry that if someone gets one of these messages they will not be
able to find it in the source code. How about passing in the full
printf() string in each case, or just using printf() in situ? I don't
think the code space saving is significant.
It's not a debug message. And each one is different, and easy to grep
failed. The code is a little cleaner with this. Also the command code is
not complicated.
git grep -i failed |wc -l
2089
Is there some way to know it is a PMIC error message, and find it that way?
Ok, I assumed that you know which command you called, and where to find
it, so you could use:
grep -i failed common/cmd_regulator.c | wc -l
15
But this was only the function name, not a useful text for grep.
Now I see
Re: [U-Boot] [PATCH v4 00/16] Power(full) framework based on Driver Model
Hello Simon, On 04/24/2015 06:48 AM, Simon Glass wrote: Hi Przemyslaw, On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello Simon, On 04/22/2015 06:29 PM, Simon Glass wrote: Hi Przemyslaw, On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello, Again the next version. The changes are described below each commit message. This is rebased on last u-boot-dm/master after apply this patchset: https://patchwork.ozlabs.org/patch/462775/ https://patchwork.ozlabs.org/patch/462777/ https://patchwork.ozlabs.org/patch/462776/ This all can be found in here: https://github.com/bobenstein/u-boot/tree/dm-pmic-v4 Best regards, Przemyslaw Marczak (16): exynos5: fix build break by adding CONFIG_POWER exynos4-common: remove the unsued CONFIG_CMD_PMIC lib: Kconfig: add entry for errno_str() function dm: pmic: add implementation of driver model pmic uclass dm: regulator: add implementation of driver model regulator uclass dm: pmic: add pmic command dm: regulator: add regulator command pmic: max77686 set the same compatible as in the kernel dm: pmic: add max77686 pmic driver dm: regulator: add max77686 regulator driver dm: regulator: add fixed voltage regulator driver doc: driver-model: pmic and regulator uclass documentation dm: board:samsung: power_init_board: add requirement of CONFIG_DM_PMIC odroid: board: add support to dm pmic api odroid: dts: add 'voltage-regulators' description to max77686 node odroid: config: enable dm pmic, dm regulator and max77686 driver Makefile | 3 +- arch/arm/dts/exynos4412-odroid.dts | 255 ++- arch/arm/dts/exynos4412-trats2.dts | 2 +- arch/arm/dts/exynos5250-smdk5250.dts | 2 +- arch/arm/dts/exynos5250-snow.dts | 2 +- board/samsung/common/board.c | 4 +- board/samsung/common/misc.c | 1 + board/samsung/odroid/odroid.c| 77 ++- common/Kconfig | 36 + common/Makefile | 4 + common/cmd_pmic.c| 231 +++ common/cmd_regulator.c | 403 +++ configs/odroid_defconfig | 8 +- doc/device-tree-bindings/pmic/max77686.txt | 36 + doc/device-tree-bindings/regulator/fixed.txt | 38 ++ doc/device-tree-bindings/regulator/max77686.txt | 70 ++ doc/device-tree-bindings/regulator/regulator.txt | 55 ++ doc/driver-model/pmic-framework.txt | 142 drivers/power/Kconfig| 8 + drivers/power/Makefile | 1 - drivers/power/pmic/Kconfig | 18 + drivers/power/pmic/Makefile | 2 + drivers/power/pmic/max77686.c| 87 +++ drivers/power/pmic/pmic-uclass.c | 158 + drivers/power/pmic/pmic_max77686.c | 2 +- drivers/power/regulator/Kconfig | 33 + drivers/power/regulator/Makefile | 10 + drivers/power/regulator/fixed.c | 126 drivers/power/regulator/max77686.c | 825 +++ drivers/power/regulator/regulator-uclass.c | 300 + include/configs/exynos4-common.h | 1 - include/configs/exynos5-common.h | 4 + include/configs/odroid.h | 5 - include/dm/uclass-id.h | 4 + include/power/max77686_pmic.h| 29 +- include/power/pmic.h | 189 ++ include/power/regulator.h| 384 +++ lib/Kconfig | 8 + lib/fdtdec.c | 2 +- 39 files changed, 3512 insertions(+), 53 deletions(-) create mode 100644 common/cmd_pmic.c create mode 100644 common/cmd_regulator.c create mode 100644 doc/device-tree-bindings/pmic/max77686.txt create mode 100644 doc/device-tree-bindings/regulator/fixed.txt create mode 100644 doc/device-tree-bindings/regulator/max77686.txt create mode 100644 doc/device-tree-bindings/regulator/regulator.txt create mode 100644 doc/driver-model/pmic-framework.txt create mode 100644 drivers/power/pmic/Kconfig create mode 100644 drivers/power/pmic/max77686.c create mode 100644 drivers/power/pmic/pmic-uclass.c create mode 100644 drivers/power/regulator/Kconfig create mode 100644 drivers/power/regulator/Makefile create mode 100644 drivers/power/regulator/fixed.c create mode 100644 drivers/power/regulator/max77686.c create mode 100644 drivers/power/regulator/regulator-uclass.c create mode 100644 include/power/regulator.h
[U-Boot] [PATCH 18/21] sunxi: dts: Add minimal dts files for board which lack a dts sofar
u-boot has support for a number of boards for which a dts file still needs to be written, add minimal dts files for these boards so that we can switch them over to device-model / fdt. Signed-off-by: Hans de Goede hdego...@redhat.com --- arch/arm/dts/Makefile | 20 +++- arch/arm/dts/sun4i-a10-inet-3f.dts | 29 +++ arch/arm/dts/sun4i-a10-inet-3w.dts | 29 +++ arch/arm/dts/sun5i-a13-ampe-a76.dts| 29 +++ arch/arm/dts/sun5i-a13-forfun-q88db.dts| 29 +++ arch/arm/dts/sun5i-a13-inet-86vs.dts | 29 +++ arch/arm/dts/sun5i-a13-tzx-q8-713b7.dts| 29 +++ arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 57 ++ arch/arm/dts/sun6i-a31s-primo81.dts| 29 +++ arch/arm/dts/sun7i-a20-ainol-aw1.dts | 29 +++ arch/arm/dts/sun7i-a20-m5.dts | 57 ++ arch/arm/dts/sun7i-a20-mk808c.dts | 45 + arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts| 57 ++ arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts| 29 +++ arch/arm/dts/sun8i-a33-astar-mid756.dts| 29 +++ .../dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts| 29 +++ 16 files changed, 553 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/sun4i-a10-inet-3f.dts create mode 100644 arch/arm/dts/sun4i-a10-inet-3w.dts create mode 100644 arch/arm/dts/sun5i-a13-ampe-a76.dts create mode 100644 arch/arm/dts/sun5i-a13-forfun-q88db.dts create mode 100644 arch/arm/dts/sun5i-a13-inet-86vs.dts create mode 100644 arch/arm/dts/sun5i-a13-tzx-q8-713b7.dts create mode 100644 arch/arm/dts/sun6i-a31-mixtile-loftq.dts create mode 100644 arch/arm/dts/sun6i-a31s-primo81.dts create mode 100644 arch/arm/dts/sun7i-a20-ainol-aw1.dts create mode 100644 arch/arm/dts/sun7i-a20-m5.dts create mode 100644 arch/arm/dts/sun7i-a20-mk808c.dts create mode 100644 arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts create mode 100644 arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts create mode 100644 arch/arm/dts/sun8i-a33-astar-mid756.dts create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a18c565..190844b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -64,6 +64,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-gemei-g9.dtb \ sun4i-a10-hackberry.dtb \ sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet-3f.dtb \ + sun4i-a10-inet-3w.dtb \ sun4i-a10-inet97fv2.dtb \ sun4i-a10-jesurun-q5.dtb \ sun4i-a10-marsboard.dtb \ @@ -77,9 +79,13 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-mk802.dtb \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a13-ampe-a76.dtb \ + sun5i-a13-forfun-q88db.dtb \ sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-86vs.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-tzx-q8-713b7.dtb \ sun5i-a13-utoo-p66.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ @@ -87,8 +93,11 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-hummingbird.dtb \ sun6i-a31-i7.dtb \ sun6i-a31-m9.dtb \ - sun6i-a31s-cs908.dtb + sun6i-a31-mixtile-loftq.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-primo81.dtb dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-ainol-aw1.dtb \ sun7i-a20-bananapi.dtb \ sun7i-a20-bananapro.dtb \ sun7i-a20-cubieboard2.dtb \ @@ -96,6 +105,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ sun7i-a20-m3.dtb \ + sun7i-a20-m5.dtb \ + sun7i-a20-mk808c.dtb \ sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-micro.dtb \ @@ -104,10 +115,15 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-pcduino3.dtb \ sun7i-a20-pcduino3-nano.dtb \ sun7i-a20-primo73.dtb \ - sun7i-a20-wexler-tab7200.dtb + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb \ + sun7i-a20-yones-toptech-bd1078.dtb dtb-$(CONFIG_MACH_SUN8I_A23) += \ sun8i-a23-ippo-q8h-v5.dtb \ sun8i-a23-ippo-q8h-v1.2.dtb +dtb-$(CONFIG_MACH_SUN8I_A33) += \ + sun8i-a33-astar-mid756.dtb \ + sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/sun4i-a10-inet-3f.dts b/arch/arm/dts/sun4i-a10-inet-3f.dts new file mode 100644 index 000..d2805c5 --- /dev/null +++ b/arch/arm/dts/sun4i-a10-inet-3f.dts @@ -0,0 +1,29 @@ +/* + * Copyright 2015 Hans de Goede hdego...@redhat.com + * + * Minimal dts file for the iNet 3F for u-boot only
Re: [U-Boot] [PATCH 07/10] sunxi: Fix end of kernel memory alignment for A33
Hi Mark, On 17-04-15 12:20, Mark Rutland wrote: On Thu, Apr 16, 2015 at 08:12:31PM +0100, Hans de Goede wrote: Hi, On 16-04-15 19:35, Mark Rutland wrote: On Thu, Apr 16, 2015 at 08:32:03AM +0100, Hans de Goede wrote: Hi, On 15-04-15 21:57, Ian Campbell wrote: On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote: For unknown reasons the A33 needs the end of the memory we report to the kernel to be aligned to a multiple of 4 MiB. Do you really mean the A33 needs (as in the processor itself) or do you actually mean the A33 kernel port? If the latter than can't that be investigated/fixed instead of hacked here? That would be far more preferable. I mean the former, it seems that the SoC itself cannot handle dram ranges with different cache policies which are not aligned to 4 MiB, at least that is my WAG what is going on here. That sounds incredibly suspicious. What do you mean w.r.t. different cache policies -- what does that have to do with the end of DRAM? We carve out a framebuffer at the end of DRAM, and then report less DRAM then we actually have to the kernel. This framebuffer then gets picked up by the kernel through simplefb, which will map it with a different cache policy then the normal part of the DRAM has. I see. Thanks for the clarification. What problem do you see? Depending on the framebuffer-size the kernel either boots or does not boot, when it does not boot it does nothing (I've a serial console) earlyprintk does not help, I was looking into setting up an early console (should be a matter of just putting in the right parameters) when I found out that if I modify the framebuffer size that fixes things. Ok. So we don't know if the kernel is stuck somewhere or everything is completely hosed, then? I take it you can't get JTAG worknig via the SD card slot? After experimenting more it seems that keeping the last pixel of the framebuffer at the very end of DRAM is not a problem (so this does not seem to be a display engine problem), things start to work when I make the carve out at the end bigger. On the very similar A23 giving the kernel all of the DRAM except for the framebuffer (aligned to a multiple of 4k) works just fine. Sometimes I can get away with just making the carve-out bigger without aligning it to a multiple of 4 MiB, but an alignment to 4 MiB seems to always work independent of the framebuffer size. It would be worth reporting this on lakml. If you still think that after the above explanation I'll start a new thread on lakml with contents more targeted at kernel devs. I think it would be worthwhile. This could be one instance of an issue in the memory system that we might hit elsewhere. Even if we don't come to another solution, it'll at least make it visible to others. So it seems that I'm not the only one seeing this, and I've been wrongly blaming it on the A33, instead it seems to be a kernel bug, triggered on my A33 due to the display resolution it has. For details see: http://www.spinics.net/lists/arm-kernel/msg413811.html Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sunxi: display: Align end of memory to work around a linux-4.0 bug
Linux-4.0 as shipped has a bug causing it to not boot if the end of memory
is not aligned to a multiple of 2 MiB. For details see the linux-arm
mailing list post titled:
Memory size unaligned to section boundary
http://www.spinics.net/lists/arm-kernel/msg413811.html
This is something which specifically hits the sunxi display driver because
we carve out the exact needed framebuffer size at the top of mem, this
commit works around this issue by aligning the carve out.
Cc: Stefan Agner ste...@agner.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/sunxi_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 95cfe94..4607269 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -1278,6 +1278,19 @@ int sunxi_simplefb_setup(void *blob)
*/
start = gd-bd-bi_dram[0].start;
size = gd-bd-bi_dram[0].size - sunxi_display.fb_size;
+
+ /*
+* Linux-4.0 as shipped has a bug causing it not boot if the end
+* of memory is not aligned to a multiple of 2 MiB. For details
+* see the linux-arm mailing list post titled:
+* Memory size unaligned to section boundary
+* http://www.spinics.net/lists/arm-kernel/msg413811.html
+*
+* This workaround should be removed once the bug has been fixed
+* and we no longer care about the Linux versions with the bug.
+*/
+ size = ~(2 * 1024 * 1024 - 1);
+
ret = fdt_fixup_memory_banks(blob, start, size, 1);
if (ret) {
eprintf(Cannot setup simplefb: Error reserving memory\n);
--
2.3.5
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Re: [U-Boot] [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
Hi Gabriel, On 23 April 2015 at 19:40, Bin Meng bmeng...@gmail.com wrote: On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr Can you please add a commit message? --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- Reviewed-by: Bin Meng bmeng...@gmail.com Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Fat filesystem format support in u-boot
Hi All, I just want to know whether we have FAT file system formatting support in u-boot? I would like to format my SD card from u-boot. Regards, Siva ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd_mem: Store last address/size/etc as ulong
On 03/19/2015 10:50 AM, Simon Glass wrote: On 19 March 2015 at 10:43, York Sun york...@freescale.com wrote: From: Scott Wood scottw...@freescale.com Otherwise the high 32 bits get truncated on 64-bit U-boot. Signed-off-by: Scott Wood scottw...@freescale.com CC: Simon Glass s...@chromium.org --- common/cmd_mem.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index bcb3ee3..62a0404 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -35,9 +35,9 @@ static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. * Memory modify remembered values are different from display memory. */ -static uintdp_last_addr, dp_last_size; -static uintdp_last_length = 0x40; -static uintmm_last_addr, mm_last_size; +static ulong dp_last_addr, dp_last_size; +static ulong dp_last_length = 0x40; +static ulong mm_last_addr, mm_last_size; static ulong base_address = 0; Reviewed-by: Simon Glass s...@chromium.org Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum A004477
On 04/09/2015 08:29 PM, nikhil.bad...@freescale.com wrote:
-Original Message-
From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
Sent: Friday, November 21, 2014 6:00 PM
To: Badola Nikhil-B46172
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum
A004477
Hello Nikhil,
On Fri, 21 Nov 2014 17:25:21 +0530, Nikhil Badola
nikhil.bad...@freescale.com wrote:
Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power mode
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/404879/
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/include/asm/config_mpc85xx.h | 6 ++
drivers/usb/host/ehci-fsl.c | 10 ++
include/fsl_usb.h | 29
+
4 files changed, 49 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index fe3eb06..bc59352 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -298,6 +298,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
if (has_erratum_a007798())
puts(Work-around for Erratum A007798 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
+ if (has_erratum_a004477())
+ puts(Work-around for Erratum A004477 enabled\n); #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git
a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 7860b40..fe9e9c1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -161,6 +161,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508 #define
CONFIG_SYS_FSL_ERRATUM_A007075 #define
CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -292,6 +293,7 @@
#define CONFIG_FSL_SATA_ERRATUM_A001
#define CONFIG_SYS_FSL_ERRATUM_A004508 #define
CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_P1023)
#define CONFIG_MAX_CPUS2
@@ -372,6 +374,7 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_ERRATUM_A004508 #define
CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT1
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ @@ -589,6
+592,7 @@ #define CONFIG_NAND_FSL_IFC #define
CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define
CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
@@ -613,6 +617,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2
#define CONFIG_SYS_FSL_ERRATUM_A005125 #define
CONFIG_SYS_FSL_ERRATUM_A005434
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -712,6 +717,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006475 #define
CONFIG_SYS_FSL_ERRATUM_A006384 #define
CONFIG_SYS_FSL_ERRATUM_A007212
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#define CONFIG_SYS_FSL_SFP_VER_3_0
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5d4288d..41ff1a7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type
init,
if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
+ if (has_erratum_a004477()) {
+ /*
+* When reset is issued while any ULPI transaction is ongoing
+* then it may result to corruption of ULPI Function Control
+* Register which eventually causes phy clock to enter low
+* power mode which stops the clock. Thus delay is required
+* before reset to let ongoing ULPI transaction complete.
Actually the erratum suggests checking transaction status before issuing a
soft reset. Here, could the code do this check and wait for the transation to
finish, rather than wait for an arbitrary duration?
There have been discussions with IP team for changing the suggested
workaround.
The erratum talks about the ULPI transactions i.e from controller to ULPI phy
and not
the USB schedule transactions .Hence halting the controller before soft reset
isn't the
correct workaround.
In addition, as per the
Re: [U-Boot] [PATCH 0/4] x86: support of pin-muxing from device tree
Hi Gabriel, On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- Thanks for these patches! Just a general comment, you don't need send emails to u-boot-patc...@bugs.denx.de, and always include a simple sentence in the commit message :) Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- Reviewed-by: Bin Meng bmeng...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] drivers:usb: Check if USB Erratum A005697 is applicable on BSC913x
On 03/17/2015 05:46 AM, Nikhil Badola wrote: Check if USB Erratum A005697 is applicable on BSC913x and add corresponding property in the device tree via device tree fixup which is used by linux driver Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com --- Depends on drivers:usb:fsl: Add affected SOCs for USB Erratum A007792 http://patchwork.ozlabs.org/patch/448965/ Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/11] env: Fix return values in env_attr_lookup()
On 21 April 2015 at 16:02, Joe Hershberger joe.hershber...@ni.com wrote: This function returned numbers for error codes. Change them to error codes. Signed-off-by: Joe Hershberger joe.hershber...@ni.com --- common/env_attr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/11] net: Apply default format rules to all ethaddr
On 21 April 2015 at 16:02, Joe Hershberger joe.hershber...@ni.com wrote:
Use a regular expression to apply the default formatting flags for all
ethaddr env vars.
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
include/env_flags.h | 11 ---
test/dm/eth.c | 1 +
2 files changed, 9 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass s...@chromium.org
Q below.
diff --git a/include/env_flags.h b/include/env_flags.h
index 3ef6311..fc6d0d8 100644
--- a/include/env_flags.h
+++ b/include/env_flags.h
@@ -38,13 +38,18 @@ enum env_flags_varaccess {
#endif
#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_REGEX
+#define ETHADDR_WILDCARD \\d?
+#else
+#define ETHADDR_WILDCARD
+#endif
#ifdef CONFIG_ENV_OVERWRITE
-#define ETHADDR_FLAGS ethaddr:ma,
+#define ETHADDR_FLAGS eth ETHADDR_WILDCARD addr:ma,
#else
#ifdef CONFIG_OVERWRITE_ETHADDR_ONCE
-#define ETHADDR_FLAGS ethaddr:mc,
+#define ETHADDR_FLAGS eth ETHADDR_WILDCARD addr:mc,
#else
-#define ETHADDR_FLAGS ethaddr:mo,
+#define ETHADDR_FLAGS eth ETHADDR_WILDCARD addr:mo,
#endif
#endif
#else
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 4891f3a..9b714a1 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -89,6 +89,7 @@ static int dm_test_eth_rotate(struct dm_test_state *dms)
/* Invalidate eth1's MAC address */
net_ping_ip = string_to_ip(1.1.2.2);
strcpy(ethaddr, getenv(eth1addr));
Can you explain this next line, please?
+ setenv(.flags, eth1addr);
setenv(eth1addr, NULL);
/* Make sure that the default is to rotate to the next interface */
--
1.7.11.5
Regards,
Simon
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Re: [U-Boot] [PATCH 07/11] env: Add regex support to env_attrs
On 21 April 2015 at 16:02, Joe Hershberger joe.hershber...@ni.com wrote: Allow the features that use env_attrs to specify regexs for the name Signed-off-by: Joe Hershberger joe.hershber...@ni.com --- common/env_attr.c | 85 ++ include/env_callback.h | 10 -- 2 files changed, 93 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] sandbox: eth: Add a function to skip ping timeouts
On 21 April 2015 at 12:57, Joe Hershberger joe.hershber...@ni.com wrote: When called, the next call to receive will trigger a 10-second leap forward in time to avoid waiting for time to pass when tests are evaluating timeout behavior. Signed-off-by: Joe Hershberger joe.hershber...@ni.com --- arch/sandbox/include/asm/eth.h | 2 ++ drivers/net/sandbox.c | 17 + 2 files changed, 19 insertions(+) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Hi Grabriel,
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote:
commit message here
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include asm/gpio.h
This should go up one line I think, for ordering.
#include netdev.h
#include smsc_lpc47m.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
Regards,
Simon
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Re: [U-Boot] [PATCH 02/10] board_init_f_mem(): Don't require memset()
Hi Masahiro, On 20 April 2015 at 22:30, Masahiro Yamada yamada.masah...@socionext.com wrote: 2015-04-21 12:47 GMT+09:00 Simon Glass s...@chromium.org: Hi Masahiro, On 20 April 2015 at 21:42, Masahiro Yamada yamada.masah...@socionext.com wrote: Hi Simon, 2015-04-16 10:14 GMT+09:00 Simon Glass s...@chromium.org: Unfortunately memset() is not always available, so provide a substitute when needed. Signed-off-by: Simon Glass s...@chromium.org --- common/init/global_data.c | 8 1 file changed, 8 insertions(+) diff --git a/common/init/global_data.c b/common/init/global_data.c index 2633f0d..ef055c4 100644 --- a/common/init/global_data.c +++ b/common/init/global_data.c @@ -21,7 +21,15 @@ ulong board_init_f_mem(ulong top) top -= sizeof(struct global_data); top = ALIGN(top, 16); gd = (struct global_data *)top; +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBGENERIC_SUPPORT) memset((void *)gd, '\0', sizeof(*gd)); +#else + int *ptr = (int *)gd; + int *end = (int *)(gd + 1); + + while (ptr end) + *ptr++ = 0; +#endif #ifdef CONFIG_SYS_MALLOC_F_LEN top -= CONFIG_SYS_MALLOC_F_LEN; This patch implies that all the SPLs should have memset(). Is it better to build lib/ unconditionally? I posted a patch to do so. Please consider to use it as a prerequisite for cleaning up 01/10 and 02/10. That would be better I think - how did you manage it? I cannot see the patch you are referring to. It is under moderation because of too many recipients. (I think you have already received it because you were listed in CC.) Please wait until it is approved. Although what about if SPL is very close to the maximum size and adding memset() makes it too large? I suppose in that case we would get a build error and notice the problem? Buildman-test passed, but I am not sure about run-test. For those boards that define CONFIG_SPL_MAX_SIZE, CONFIG_SPL_MAX_FOOTPRINT etc., we should notice the problem at the build time. (and it did not occur.) I'd like to encourage the board maintainers to do run-test just in case. (and also to support such CONFIG options for boards with the limited memory footprint) OK, I tried it out for code size and it looked fine. I will see if I can test it on some boards, but I imagine it would be fine. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] x86: Install a default e820 table in the __weak install_e820_map()
Hi Bin,
On 21 April 2015 at 19:01, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Apr 21, 2015 at 9:52 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 20 April 2015 at 22:21, Bin Meng bmeng...@gmail.com wrote:
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/lib/zimage.c | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 566b048..c3f8a73 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -25,6 +25,8 @@
#endif
#include linux/compiler.h
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Memory lay-out:
*
@@ -40,16 +42,29 @@
#define COMMAND_LINE_SIZE 2048
-unsigned generic_install_e820_map(unsigned max_entries,
- struct e820entry *entries)
+/*
+ * Install a default e820 table with 3 entries as follows:
+ *
+ * 0x00-0x0a Useable RAM
+ * 0x0a-0x10 Reserved for ISA
+ * 0x10-gd-ram_size Useable RAM
+ */
+__weak unsigned install_e820_map(unsigned max_entries,
+struct e820entry *entries)
{
- return 0;
+ entries[0].addr = 0;
+ entries[0].size = ISA_START_ADDRESS;
+ entries[0].type = E820_RAM;
+ entries[1].addr = ISA_START_ADDRESS;
+ entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+ entries[1].type = E820_RESERVED;
+ entries[2].addr = ISA_END_ADDRESS;
+ entries[2].size = gd-ram_size - ISA_END_ADDRESS;
+ entries[2].type = E820_RAM;
+
+ return 3;
}
-unsigned install_e820_map(unsigned max_entries,
- struct e820entry *entries)
- __attribute__((weak, alias(generic_install_e820_map)));
-
static void build_command_line(char *command_line, int auto_boot)
{
char *env_command_line;
--
1.8.2.1
Why is this code sitting in zimage.c? Should it be used with bootm also?
Sorry I am not sure I understand your point. setup_zimage() is called
by boot_prep_linux() in bootm.c.
I mean that install_e820_map() seems to be unrelated to zimage, and is
perhaps better kept in a more generic place, perhaps
arch/x86/lib/bootm.c or even arch/x86/lib/e820. Anyway let's apply
this and we can figure that out later.
Acked-by: Simon Glass s...@chromium.org
Regards,
Simon
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Re: [U-Boot] [PATCH 1/3] sandbox: Add test function to advance time
On 21 April 2015 at 12:57, Joe Hershberger joe.hershber...@ni.com wrote: Add a function that maintains an offset to include in the system timer values returned from the lib/time.c APIs. This will allow timeouts to be skipped instantly in tests Signed-off-by: Joe Hershberger joe.hershber...@ni.com --- arch/sandbox/cpu/cpu.c | 5 - arch/sandbox/include/asm/test.h | 8 board/sandbox/sandbox.c | 11 ++- 3 files changed, 18 insertions(+), 6 deletions(-) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/145: Re: [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Hi Grabriel,
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote:
commit message here
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include asm/gpio.h
This should go up one line I think, for ordering.
#include netdev.h
#include smsc_lpc47m.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
Regards,
Simon
---
Added to GNATS database as unassigned-patches/145
Responsible:patch-coord
Message-Id:
CAPnjgZ1djEV3BHjoLysmc-O+KSsvN7rrn=S=qxeyuywperw...@mail.gmail.com
In-Reply-To:1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr
References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr
Patch-Date: Fri Apr 24 05:37:28 +0200 2015
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Re: [U-Boot] [PATCH v4 00/16] Power(full) framework based on Driver Model
Hi Przemyslaw, On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello Simon, On 04/22/2015 06:29 PM, Simon Glass wrote: Hi Przemyslaw, On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello, Again the next version. The changes are described below each commit message. This is rebased on last u-boot-dm/master after apply this patchset: https://patchwork.ozlabs.org/patch/462775/ https://patchwork.ozlabs.org/patch/462777/ https://patchwork.ozlabs.org/patch/462776/ This all can be found in here: https://github.com/bobenstein/u-boot/tree/dm-pmic-v4 Best regards, Przemyslaw Marczak (16): exynos5: fix build break by adding CONFIG_POWER exynos4-common: remove the unsued CONFIG_CMD_PMIC lib: Kconfig: add entry for errno_str() function dm: pmic: add implementation of driver model pmic uclass dm: regulator: add implementation of driver model regulator uclass dm: pmic: add pmic command dm: regulator: add regulator command pmic: max77686 set the same compatible as in the kernel dm: pmic: add max77686 pmic driver dm: regulator: add max77686 regulator driver dm: regulator: add fixed voltage regulator driver doc: driver-model: pmic and regulator uclass documentation dm: board:samsung: power_init_board: add requirement of CONFIG_DM_PMIC odroid: board: add support to dm pmic api odroid: dts: add 'voltage-regulators' description to max77686 node odroid: config: enable dm pmic, dm regulator and max77686 driver Makefile | 3 +- arch/arm/dts/exynos4412-odroid.dts | 255 ++- arch/arm/dts/exynos4412-trats2.dts | 2 +- arch/arm/dts/exynos5250-smdk5250.dts | 2 +- arch/arm/dts/exynos5250-snow.dts | 2 +- board/samsung/common/board.c | 4 +- board/samsung/common/misc.c | 1 + board/samsung/odroid/odroid.c| 77 ++- common/Kconfig | 36 + common/Makefile | 4 + common/cmd_pmic.c| 231 +++ common/cmd_regulator.c | 403 +++ configs/odroid_defconfig | 8 +- doc/device-tree-bindings/pmic/max77686.txt | 36 + doc/device-tree-bindings/regulator/fixed.txt | 38 ++ doc/device-tree-bindings/regulator/max77686.txt | 70 ++ doc/device-tree-bindings/regulator/regulator.txt | 55 ++ doc/driver-model/pmic-framework.txt | 142 drivers/power/Kconfig| 8 + drivers/power/Makefile | 1 - drivers/power/pmic/Kconfig | 18 + drivers/power/pmic/Makefile | 2 + drivers/power/pmic/max77686.c| 87 +++ drivers/power/pmic/pmic-uclass.c | 158 + drivers/power/pmic/pmic_max77686.c | 2 +- drivers/power/regulator/Kconfig | 33 + drivers/power/regulator/Makefile | 10 + drivers/power/regulator/fixed.c | 126 drivers/power/regulator/max77686.c | 825 +++ drivers/power/regulator/regulator-uclass.c | 300 + include/configs/exynos4-common.h | 1 - include/configs/exynos5-common.h | 4 + include/configs/odroid.h | 5 - include/dm/uclass-id.h | 4 + include/power/max77686_pmic.h| 29 +- include/power/pmic.h | 189 ++ include/power/regulator.h| 384 +++ lib/Kconfig | 8 + lib/fdtdec.c | 2 +- 39 files changed, 3512 insertions(+), 53 deletions(-) create mode 100644 common/cmd_pmic.c create mode 100644 common/cmd_regulator.c create mode 100644 doc/device-tree-bindings/pmic/max77686.txt create mode 100644 doc/device-tree-bindings/regulator/fixed.txt create mode 100644 doc/device-tree-bindings/regulator/max77686.txt create mode 100644 doc/device-tree-bindings/regulator/regulator.txt create mode 100644 doc/driver-model/pmic-framework.txt create mode 100644 drivers/power/pmic/Kconfig create mode 100644 drivers/power/pmic/max77686.c create mode 100644 drivers/power/pmic/pmic-uclass.c create mode 100644 drivers/power/regulator/Kconfig create mode 100644 drivers/power/regulator/Makefile create mode 100644 drivers/power/regulator/fixed.c create mode 100644 drivers/power/regulator/max77686.c create mode 100644 drivers/power/regulator/regulator-uclass.c create mode 100644 include/power/regulator.h -- 1.9.1 I'm going to test this and apply
Re: [U-Boot] [PATCH 4/4] x86: queensbay: Implement PIRQ routing
Hi Simon,
On Fri, Apr 24, 2015 at 11:39 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 23 April 2015 at 21:36, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Apr 24, 2015 at 11:02 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 21 April 2015 at 19:56, Bin Meng bmeng...@gmail.com wrote:
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_mist_init().
arch_misc_init()?
Will fix.
Also how can this be used on other boards? Should part of this code be
moved to a generic place?
Generally Intel interrupt router should be compatible, but the offsets
of these interrupt routing registers might be different from platform
to platform. The platform-specific part is the internal PCI devices'
interrupt pin to PIRQ map.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/irq.c | 236
+++
arch/x86/cpu/queensbay/tnc.c | 10 +-
arch/x86/include/asm/arch-queensbay/device.h | 94 +++
arch/x86/include/asm/arch-queensbay/irq.h| 55 +++
arch/x86/include/asm/arch-queensbay/tnc.h| 26 ++-
arch/x86/include/asm/u-boot-x86.h| 2 +
configs/crownbay_defconfig | 1 +
include/configs/crownbay.h | 1 +
9 files changed, 423 insertions(+), 4 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/irq.c
create mode 100644 arch/x86/include/asm/arch-queensbay/device.h
create mode 100644 arch/x86/include/asm/arch-queensbay/irq.h
[snip]
+ writew(PIRQE, rcba + D02IR);
+ writew(PIRQF, rcba + D03IR);
+ writew(PIRQG, rcba + D27IR);
+ writew(PIRQH, rcba + D31IR);
+ writew(PIRQE, rcba + D23IR);
+ writew(PIRQF, rcba + D24IR);
+ writew(PIRQG, rcba + D25IR);
+ writew(PIRQH, rcba + D26IR);
+
+ if (!create_pirq_routing_table()) {
Can you add a comment here as to why you do this next bit if
create_pirq_routing_table() fails?
I am not sure if you misread the codes? If create_pirq_routing_table()
fails, it returns non-zero value and the following pirq_route_irqs()
will not be called.
Yes I misread it. So should this function return the error code it
gets? Or maybe add debug()?
Yep, adding one debug() is nice. Will do that in v2.
+ /* Route PIRQ */
+ pirq_route_irqs(pirq_routing_table-slots,
+ get_irq_slot_count(pirq_routing_table));
+ }
+}
+
Regards,
Bin
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Re: [U-Boot] [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
There is 6 banks:
There are
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = 0;
};
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x20;
+ bank-name = C;
+ };
+
+ gpiod {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x60 0x20;
+ bank-name = D;
+ };
+
+ gpioe {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x80 0x20;
+ bank-name = E;
+ };
+
+ gpiof {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0xA0 0x20;
+ bank-name = F;
+ };
+
chosen {
stdout-path = /serial;
};
--
Reviewed-by: Bin Meng bmeng...@gmail.com
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Re: [U-Boot] [PATCH v4 11/16] dm: regulator: add fixed voltage regulator driver
Hi Przemyslaw, On 23 April 2015 at 06:31, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello Simon, On 04/20/2015 08:07 PM, Przemyslaw Marczak wrote: This driver implements regulator operations for fixed Voltage/Current value regulators. beside the standard regulator constraints, which are put into the uclass platform data, a typical fixed regulator node provides few additional properties like: - gpio - gpio-open-drain - enable-active-high - startup-delay-us The only 'gpio' is used by this driver and is kept in structure of type 'fixed_regulator_platdata', as a device platform data (dev-platdata). The driver implements: - get_value - get_current - get_enable - set_enable The regulator calls and commands can be used for fixed-regulator devices, and the proper error will be returned for prohibited. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com I missed the separation (---) here and I see that you add ACK below the changes. Could you remove them from the tree? OK, done. You could try patman which handles this automatically. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 04/16] dm: pmic: add implementation of driver model pmic uclass
Hi Przemyslaw, On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello Simon, On 04/22/2015 06:30 PM, Simon Glass wrote: Hi Przemyslaw, On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com wrote: This commit introduces the PMIC uclass implementation. It allows providing the basic I/O interface for PMIC devices. For the multi-function PMIC devices, this can be used as I/O parent device, for each IC's interface. Then, each PMIC particular function can be provided by the child device's operations, and the child devices will use its parent for read/write by the common API. Core files: - 'include/power/pmic.h' - 'drivers/power/pmic/pmic-uclass.c' The old pmic framework is still kept and is independent. For more detailed informations, please look into the header file. Changes: - new uclass-id: UCLASS_PMIC - new config: CONFIG_DM_PMIC Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com --- Changes V2: - pmic uclass: adjust uclass code to the mainline changes - pmic uclass: remove pmic_i2c and pmic_spi - pmic uclass: modify pmic_platdata - pmic uclass: add pmic_if_* functions - pmic uclass: remove pmic_init_dm() - pmic uclass: cleanup - pmic.h: define pmic ops structure (read/write operations) - pmic.h: add comments to functions Changes V3: - pmic-uclass.c and pmic.h: -- remove pmic_if_* functions -- add new function pmic_child_node_scan() - add Kconfig entry Changes V4: - move drivers/power/pmic-uclass.c to drivers/power/pmic/pmic-uclass.c - move DM_PMIC Kconfig entry: drivers/power/Kconfig to drivers/power/pmic/Kconfig - drivers/power/Kconfig: Add menu Power and include pmic Kconfig - Kconfig: provide only the general information about the PMIC - pmic-uclass.c: add pmic_bind_childs() - pmic-uclass.c: add debug - pmic-uclass.c: cleanup includes - pmic-uclass.c: remove pmic_get_uclass_ops() and use of dev_get_driver_ops() - pmic-uclass.c: use of uclass_get_device_by_name() - pmic-uclass.c: add str_get_num() - for get number from string - include/power/pmic.h - start comments rewording - power/pmic.h: comments update --- drivers/power/Kconfig| 6 ++ drivers/power/pmic/Kconfig | 11 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic-uclass.c | 158 include/dm/uclass-id.h | 3 + include/power/pmic.h | 189 +++ 6 files changed, 368 insertions(+) create mode 100644 drivers/power/pmic/Kconfig create mode 100644 drivers/power/pmic/pmic-uclass.c Acked-by: Simon Glass s...@chromium.org I have a few nits below - perhaps they can be targeted in a follow-up patch or two? I'd like to merge this soon and it is not worth holding up the series for nits. That's good information. I will fix it all and resend ASAP. diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index f8f0239..d03626e 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,3 +1,7 @@ +menu Power + +source drivers/power/pmic/Kconfig + config AXP221_POWER boolean axp221 / axp223 pmic support depends on MACH_SUN6I || MACH_SUN8I @@ -73,3 +77,5 @@ config AXP221_ELDO3_VOLT disable eldo3. On some A31(s) tablets it might be used to supply 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). + +endmenu diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig new file mode 100644 index 000..d06d632 --- /dev/null +++ b/drivers/power/pmic/Kconfig @@ -0,0 +1,11 @@ +config DM_PMIC + bool Enable Driver Model for PMIC drivers (UCLASS_PMIC) + depends on DM + ---help--- + This config enables the driver-model PMIC support. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 985cfdb..594f620 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c new file mode 100644 index 000..d82d3da --- /dev/null +++ b/drivers/power/pmic/pmic-uclass.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak p.marc...@samsung.com + * + *
Re: [U-Boot] [PATCH v4 07/16] dm: regulator: add regulator command
Hi Przemyslaw,
On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello Simon,
On 04/22/2015 06:30 PM, Simon Glass wrote:
Hi Przemyslaw,
On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com
wrote:
This command is based on driver model regulator's API.
The user interface provides:
- list UCLASS regulator devices
- show or [set] operating regulator device
- print constraints info
- print operating status
- print/[set] voltage value [uV] (force)
- print/[set] current value [uA]
- print/[set] operating mode id
- enable the regulator output
- disable the regulator output
The 'force' option can be used for setting the value which exceeds
the constraints min/max limits.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v3:
- new file
- Kconfig entry
Changes V4:
- cmd regulator: move platdata to uc pdata
- cmd_regulator: includes cleanup
- cmd_regulator: add get_curr_dev_and_pl() check type
- move config name: CONFIG_DM_REGULATOR_CMD to CONFIG_CMD_REGULATOR
- common/Kconfig - cleanup
---
common/Kconfig | 22 +++
common/Makefile| 1 +
common/cmd_regulator.c | 403
+
3 files changed, 426 insertions(+)
create mode 100644 common/cmd_regulator.c
Acked-by: Simon Glass s...@chromium.org
I have a few nits that could be dealt with by a follow-on patch.
Ok.
diff --git a/common/Kconfig b/common/Kconfig
index 4666f8e..52f8bb1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -470,5 +470,27 @@ config CMD_PMIC
- pmic read address - read byte of register at address
- pmic write address - write byte to register at address
The only one change for this command is 'dev' subcommand.
+
+config CMD_REGULATOR
+ bool Enable Driver Model REGULATOR command
+ depends on DM_REGULATOR
+ help
+ This command is based on driver model regulator's API.
+ User interface features:
+ - list - list regulator devices
+ - regulator dev id - show or [set] operating regulator device
+ - regulator info - print constraints info
+ - regulator status - print operating status
+ - regulator value val] -f - print/[set] voltage value [uV]
+ - regulator current val- print/[set] current value [uA]
+ - regulator mode id- print/[set] operating mode id
+ - regulator enable - enable the regulator output
+ - regulator disable - disable the regulator output
+
+ The '-f' (force) option can be used for set the value which
exceeds
+ the limits, which are found in device-tree and are kept in
regulator's
+ uclass platdata structure.
+
endmenu
+
endmenu
diff --git a/common/Makefile b/common/Makefile
index 87a3efe..93bded3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -212,6 +212,7 @@ obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
# Power
obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o
+obj-$(CONFIG_CMD_REGULATOR) += cmd_regulator.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c
new file mode 100644
index 000..b1b9e87
--- /dev/null
+++ b/common/cmd_regulator.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2014-2015 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include errno.h
+#include dm.h
+#include dm/uclass-internal.h
+#include power/regulator.h
+
+#define LIMIT_SEQ 3
+#define LIMIT_DEVNAME 20
+#define LIMIT_OFNAME 20
+#define LIMIT_INFO 16
+
+static struct udevice *currdev;
+
+static int failed(const char *getset, const char *thing,
+ const char *for_dev, int ret)
+{
+ printf(Can't %s %s %s.\nError: %d (%s)\n, getset, thing,
for_dev,
+ ret, errno_str(ret));
blank line here.
I don't see the blank line here in the patch, which I send.
Odd, there seem to be two blank lines there, and we only need one.
I worry that if someone gets one of these messages they will not be
able to find it in the source code. How about passing in the full
printf() string in each case, or just using printf() in situ? I don't
think the code space saving is significant.
It's not a debug message. And each one is different, and easy to grep
failed. The code is a little cleaner with this. Also the command code is
not complicated.
git grep -i failed |wc -l
2089
Is there some way to know it is a PMIC error message, and find it that way?
+ return CMD_RET_FAILURE;
+}
+
+static int regulator_get(bool list_only, int get_seq, struct udevice
**devp)
This function seems to do multiple things (find and list). Should we
split it into two?
+{
+ struct dm_regulator_uclass_platdata
Re: [U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222
++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
I guess the prefix 'ich6' is debatable.
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers?
*/
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int
dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int
func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
return -ENODEV;
}
@@ -135,7 +146,138 @@ static int
Re: [U-Boot] [PATCH 4/4] x86: queensbay: Implement PIRQ routing
Hi Bin,
On 21 April 2015 at 19:56, Bin Meng bmeng...@gmail.com wrote:
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_mist_init().
arch_misc_init()?
Also how can this be used on other boards? Should part of this code be
moved to a generic place?
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/irq.c | 236
+++
arch/x86/cpu/queensbay/tnc.c | 10 +-
arch/x86/include/asm/arch-queensbay/device.h | 94 +++
arch/x86/include/asm/arch-queensbay/irq.h| 55 +++
arch/x86/include/asm/arch-queensbay/tnc.h| 26 ++-
arch/x86/include/asm/u-boot-x86.h| 2 +
configs/crownbay_defconfig | 1 +
include/configs/crownbay.h | 1 +
9 files changed, 423 insertions(+), 4 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/irq.c
create mode 100644 arch/x86/include/asm/arch-queensbay/device.h
create mode 100644 arch/x86/include/asm/arch-queensbay/irq.h
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index d8761fd..4599a48 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,5 +5,5 @@
#
obj-y += fsp_configs.o
-obj-y += tnc.o topcliff.o
+obj-y += irq.o tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644
index 000..cf433d3
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2015, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include malloc.h
+#include asm/io.h
+#include asm/pci.h
+#include asm/post.h
+#include asm/processor.h
+#include asm/pirq_routing.h
+#include asm/arch/device.h
+#include asm/arch/tnc.h
+#include asm/arch/irq.h
+
+static struct irq_routing_table *pirq_routing_table;
+
+bool pirq_check_irq_routed(int link, u8 irq)
+{
+ u8 pirq;
+
+ pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
+ pirq = 0xf;
+
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (pirq 3 || pirq == 8 || pirq == 13)
+ return false;
+
+ return pirq == irq ? true : false;
+}
+
+int pirq_translate_link(int link)
+{
+ return LINK_V2N(link);
+}
+
+void pirq_assign_irq(int link, u8 irq)
+{
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (irq 3 || irq == 8 || irq == 13)
+ return;
+
+ x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
+}
+
+static inline void fill_irq_info(struct irq_info **slot, int *entries, u8
bus,
+u8 device, u8 func, u8 pin, u8 pirq)
+{
Please declare a local variable
struct irq_info *slot = *slotp;
and rename the param to slotp, to avoid the first four (*slot).
+ (*slot)-bus = bus;
+ (*slot)-devfn = (device 3) | func;
+ (*slot)-irq[pin - 1].link = LINK_N2V(pirq);
+ (*slot)-irq[pin - 1].bitmap = PIRQ_BITMAP;
+ (*entries)++;
+ (*slot)++;
+}
+
+/* PCIe port downstream INTx swizzle */
+static inline u8 pin_swizzle(u8 pin, int port)
+{
+ return (pin + port) % 4;
+}
+
+__weak int board_fill_irq_info(struct irq_info *slot)
+{
+ return 0;
+}
+
+static int create_pirq_routing_table(void)
+{
+ struct irq_routing_table *rt;
+ struct irq_info *slot;
+ int irq_entries = 0;
+ pci_dev_t tcf_bdf;
+ u8 tcf_bus, bus;
+ int i;
+
+ rt = malloc(sizeof(struct irq_routing_table));
+ if (!rt)
+ return -ENOMEM;
+ memset((char *)rt, 0, sizeof(struct irq_routing_table));
+
+ /* Populate the PIRQ table fields */
+ rt-signature = PIRQ_SIGNATURE;
+ rt-version = PIRQ_VERSION;
+ rt-rtr_bus = 0;
+ rt-rtr_devfn = (TNC_LPC_DEV 3) | TNC_LPC_FUNC;
+ rt-rtr_vendor = PCI_VENDOR_ID_INTEL;
+ rt-rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
+
+ slot = rt-slots;
+
+ /*
+* Now fill in the irq_info entries in the PIRQ table
+*
+* We start from internal TunnelCreek PCI devices first, then
+* followed by all the 4 PCIe ports downstream devices, including
+* the Queensbay platform Topcliff chipset devices.
+*/
+ fill_irq_info(slot, irq_entries, 0, TNC_IGD_DEV,
+ TNC_IGD_FUNC, INTA, PIRQE);
+ fill_irq_info(slot, irq_entries, 0, TNC_SDVO_DEV,
+ TNC_SDVO_FUNC, INTA, PIRQF);
+ fill_irq_info(slot, irq_entries, 0, TNC_HDA_DEV,
+ TNC_HDA_FUNC, INTA, PIRQG);
+ fill_irq_info(slot, irq_entries, 0, TNC_PCIE0_DEV,
+ TNC_PCIE0_FUNC, INTA, PIRQE);
+
Re: [U-Boot] [PATCH 1/4] x86: Add a function to assign IRQ numbers to PCI device
On 21 April 2015 at 19:56, Bin Meng bmeng...@gmail.com wrote: Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/pci.c | 21 + arch/x86/include/asm/pci.h | 14 ++ 2 files changed, 35 insertions(+) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
I think you need also update minnowmax.dts file to change the compatible string.
Regards,
Bin
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Re: [U-Boot] [PATCH v3 0/7] Add support for Colibri Vybrid Modules
On Thursday, April 23, 2015 at 03:13:51 PM, Tom Rini wrote:
On Thu, Apr 23, 2015 at 06:08:43PM +0530, maitysancha...@gmail.com wrote:
Hello,
On 15-04-15 16:24:21, Sanchayan Maity wrote:
Hello,
This is the third version of the patchset which adds support for the
Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
using the serial loader over UART. Compile tested for
vf610twr_defconfig and vf610twr_nand_defconfig as well.
First patch in the series refactors the DDR related code for use by
both the tower board and colibri modules. It also introduces a DDR3
based JEDEC timing structure.
Second third and fourth patch in this series are improvement patches
related to RTC, SoC/CPU detection and caches.
Fifth patch introduces USB support for Vybrid modules. Much of the code
is similar to the ehci-mx6 driver. Both host and client modes are
working and DFU has also been tested with client. Currently, we
restrict the ports to be in one of host and client mode.
Sixth patch adds the actual support for the Colibri modules.
Comments and feedback are most welcome. Thanks for the feedback till
now.
The patchset is based and tested on the latest master branch as of
this writing.
Discussion on the version 2 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168727.html
Discussion on the version 1 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168136.html
Changes since v2:
- Rework the USB driver to use register + offset method in light of
discussion which Fabio Estevam pointed out instead of the regular
struct{} method which v2 used. The discussion is at the below link:
https://www.marc.info/?l=u-bootm=142609602127309w=2
- Reorder the patchset, putting the USB support in the end and add an
additional patch for adding USB support to Colibri modules. By chance
if more discussions happen on the USB support, this allows picking up
of atleast the first patches on which no issues have been reported so
far.
- The register definitions have been moved under arch/arm/include/asm/
imx-common in the regs-usbphy.h file. This was agreed on after
discussion with Marek and some input from Peter Chen. Since it is not
clear if SoC's other than Freescale's use the Sigmatel Phy's which seem
to be use in iMX/VF/MXS, put the USH PHY register definitions in
imx-common rather than include/usb in a chipidea specific file.
- Remove setting of a PLL divisor select which was added for USB but is
actually not required considering default value. It also seems to break
USB after my latest rebase. The file in question concerning the change
is colibri_vf.c. PLL divisor selects the PLL Multiplication factor
which by default is 0, setting Fout = Fref * 20 giving 480MHz. The
earlier patch set this to 1 giving Fout = Fref * 22 where Fref =
24MHz.
- Rebased on the latest master branch.
Changes since v1:
- Rework the USB driver to use register offsets using the regular
struct {} method
- Some cleanups and fixes in the sixth patch for the colibri_vf.h file
which takes care of environment variables in uboot
- Purge some useless defines in the fifth and sixth patch which were
related to USB.
Ping!?
Anything preventing this patch from getting applied?
I'll pick this up soon, thanks!
This should go through u-boot-imx though ;-)
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[U-Boot] unassigned-patches/147: Re: [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote: There is 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/dts/minnowmax.dts | 42 ++ 1 file changed, 42 insertions(+) Acked-by: Simon Glass s...@chromium.org --- Added to GNATS database as unassigned-patches/147 Responsible:patch-coord Message-Id: CAPnjgZ2nJnkhFvLuxW01YX1B1u8HKTGPA=dLwOHhpDjv9iDs=a...@mail.gmail.com In-Reply-To:1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr 1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr Patch-Date: Fri Apr 24 05:26:17 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/148: Re: [PATCH 0/4] x86: support of pin-muxing from device tree
Hi Gabriel, On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- Thanks for these patches! Just a general comment, you don't need send emails to u-boot-patc...@bugs.denx.de, and always include a simple sentence in the commit message :) Regards, Bin --- Added to GNATS database as unassigned-patches/148 Responsible:patch-coord Message-Id: caeuhbmvtxf6nkx62o0jwxatyydbsqduv7syyew7jc-xqujj...@mail.gmail.com In-Reply-To:1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr Patch-Date: Fri Apr 24 05:23:35 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/20] dm: i2c: sandbox: Add debugging to the speed limit
Hello Simon,
Am 23.04.2015 17:12, schrieb Simon Glass:
Hi Heiko,
On 20 April 2015 at 23:04, Heiko Schocher h...@denx.de wrote:
Hello Simon,
Am 20.04.2015 20:37, schrieb Simon Glass:
Print a debug() message with the I2C speed is exceeded.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/sandbox_i2c.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c
index d6adc0f..621caec 100644
--- a/drivers/i2c/sandbox_i2c.c
+++ b/drivers/i2c/sandbox_i2c.c
@@ -73,8 +73,10 @@ static int sandbox_i2c_xfer(struct udevice *bus, struct
i2c_msg *msg,
* 400KHz for reads
*/
is_read = nmsgs 1;
- if (i2c-speed_hz (is_read ? 40 : 10))
+ if (i2c-speed_hz (is_read ? 40 : 10)) {
+ debug(%s: Max speed exceeded\n, __func__);
return -EINVAL;
+ }
Why different speeds for reading/writing?
This is just test code - in fact a later patch adds a flag to enable
it only when running tests. See test/dm/i2c.c.
Ah, thanks for the clarification, so:
Acked-by: Heiko Schocher h...@denx.de
bye,
Heiko
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Re: [U-Boot] [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote: There is 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/dts/minnowmax.dts | 42 ++ 1 file changed, 42 insertions(+) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4][v2]drivers:usb:fsl: Add XHCI driver support
On Thursday, April 23, 2015 at 07:02:54 PM, Ramneek Mehresh wrote:
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Next time, please follow
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-fsl.c | 107
++ include/linux/usb/xhci-fsl.h |
54 +++ 4 files changed, 168 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..9c1f1ce
100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -538,4 +538,10 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
This file looks like a dumpster . Maybe it's about time for someone
in Freescale to clean that mess up. I don't want you to fix it before
this patchset is applied, but certainly this could use some fixing.
[...]
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /* Currently fsl socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
Multiline comment ;-)
+ return 0;
+}
[...]
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERON BIT(14)
+#define USB3_PHY_TX_POWERON BIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON |
USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
How much of this is actually DWC3 stuff please ? Or are all
these bits really FSL-specific ?
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Re: [U-Boot] [PATCH] socfpga: implement socdk SPI flash config in dts
On Thursday, April 23, 2015 at 09:14:01 AM, Pavel Machek wrote: SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek pa...@denx.de Applied, thanks. Can you please cook one for Arria V too while at it, so we're consistent ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Test
Hi all, since midnight i didn't receive anything from the mailinglist ... is there something wrong with it ? or is my mail-provider defective? best regards, HAnnes ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] dm: sf: Make SST flash write op work again
Hi Jagan,
On Fri, Apr 24, 2015 at 4:07 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Bin,
On 23 April 2015 at 14:30, Bin Meng bmeng...@gmail.com wrote:
With SPI flash moving to driver model, commit fbb0991 dm: Convert
spi_flash_probe() and 'sf probe' to use driver model ignored the
SST flash-specific write op (byte program word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
a new SST flash-specific driver to handle the different write op
from the standard one.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_probe.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d19138d..47438d2 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -511,4 +511,35 @@ U_BOOT_DRIVER(spi_flash_std) = {
.ops= spi_flash_std_ops,
};
+int spi_flash_sst_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ return sst_write_bp(flash, offset, len, buf);
+ else
+ return sst_write_wp(flash, offset, len, buf);
+}
+
+static const struct dm_spi_flash_ops spi_flash_sst_ops = {
+ .read = spi_flash_std_read,
+ .write = spi_flash_sst_write,
+ .erase = spi_flash_std_erase,
+};
+
+static const struct udevice_id spi_flash_sst_ids[] = {
+ { .compatible = spi-flash-sst },
+ { }
+};
+
+U_BOOT_DRIVER(spi_flash_sst) = {
+ .name = spi_flash_sst,
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_flash_sst_ids,
+ .probe = spi_flash_std_probe,
+ .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .ops= spi_flash_sst_ops,
+};
+
#endif /* CONFIG_DM_SPI_FLASH */
--
1.8.2.1
I'm just curiosity to see different approach of being code duplicate
with just for sst write call.
What about this-
int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
const void *buf)
{
struct spi_flash *flash = dev_get_uclass_priv(dev);
if defined(CONFIG_SPI_FLASH_SST)
if (flash-flags SST_WR) {
if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
}
#endif
return spi_flash_cmd_write_ops(flash, offset, len, buf);
}
Of course this requires extra flags member in spi_flash, any other thoughts?
Yep, this way works too. Let me know which way you prefer and I can respin a v2.
Regards,
Bin
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[U-Boot] [PATCH v2] board/p2020rdb: fix the FDT_ERR_NOTFOUND issue
From: Ying Zhang b40...@freescale.com
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.
In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v1:
- To define the parameter err to eliminate the compiling error.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 3f47cfb..61b7a91 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -428,8 +428,13 @@ int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
const char *soc_usb_compat = fsl-usb2-dr;
- int err, usb1_off, usb2_off;
+ int usb_err, usb1_off, usb2_off;
+#endif
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ int err;
+#endif
ft_cpu_setup(blob, bd);
@@ -473,6 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
@@ -488,11 +494,12 @@ int ft_board_setup(void *blob, bd_t *bd)
soc_usb_compat);
return usb2_off;
}
- err = fdt_del_node(blob, usb2_off);
- if (err 0) {
+ usb_err = fdt_del_node(blob, usb2_off);
+ if (usb_err 0) {
printf(WARNING: could not remove %s\n, soc_usb_compat);
- return err;
+ return usb_err;
}
+#endif
return 0;
}
--
1.8.4.1
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Re: [U-Boot] [PATCH 3/3] biosemu: Do not free vga_info-BIOSImage when it is 0xc0000
On 24 April 2015 at 01:48, Bin Meng bmeng...@gmail.com wrote: For x86, vga_info-BIOSImage points to 0xc which cannot be freed. Signed-off-by: Bin Meng bmeng...@gmail.com --- drivers/bios_emulator/atibios.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] net/phy: refactor RTL8211F initialization
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
cc: Joe Hershberger joe.hershber...@gmail.com
---
v2: add default page and use macro instead of magic number.
drivers/net/phy/realtek.c | 33 +
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 3917c82..7e1c316 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -32,6 +32,7 @@
#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
#define MIIM_RTL8211F_PAGE_SELECT 0x1f
+#define MIIM_RTL8211F_TX_DELAY 0x100
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
@@ -43,6 +44,29 @@ static int rtl8211x_config(struct phy_device *phydev)
return 0;
}
+static int rtl8211f_config(struct phy_device *phydev)
+{
+ u16 reg;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+
+ if (phydev-interface == PHY_INTERFACE_MODE_RGMII) {
+ /* enable TXDLY */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT, 0xd08);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
+ reg |= MIIM_RTL8211F_TX_DELAY;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
+ /* restore to default page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT, 0x0);
+ }
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static int rtl8211x_parse_status(struct phy_device *phydev)
{
unsigned int speed;
@@ -142,13 +166,6 @@ static int rtl8211f_parse_status(struct phy_device *phydev)
phydev-speed = SPEED_10;
}
- if (phydev-interface == PHY_INTERFACE_MODE_RGMII) {
- /* enable TXDLY */
- phy_write(phydev, MDIO_DEVAD_NONE,
- MIIM_RTL8211F_PAGE_SELECT, 0xd08);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 0x109);
- }
-
return 0;
}
@@ -209,7 +226,7 @@ static struct phy_driver RTL8211F_driver = {
.uid = 0x1cc916,
.mask = 0xff,
.features = PHY_GBIT_FEATURES,
- .config = rtl8211x_config,
+ .config = rtl8211f_config,
.startup = rtl8211f_startup,
.shutdown = genphy_shutdown,
};
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH v4 07/16] dm: regulator: add regulator command
Hi Przemyslaw,
On 24 April 2015 at 06:53, Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello Simon,
On 04/24/2015 02:34 PM, Simon Glass wrote:
Hi Przemyslaw,
On 24 April 2015 at 06:18, Przemyslaw Marczak p.marc...@samsung.com
wrote:
Hello Simon,
On 04/24/2015 06:51 AM, Simon Glass wrote:
Hi Przemyslaw,
On 23 April 2015 at 05:33, Przemyslaw Marczak p.marc...@samsung.com
wrote:
Hello Simon,
On 04/22/2015 06:30 PM, Simon Glass wrote:
Hi Przemyslaw,
On 20 April 2015 at 12:07, Przemyslaw Marczak p.marc...@samsung.com
wrote:
This command is based on driver model regulator's API.
The user interface provides:
- list UCLASS regulator devices
- show or [set] operating regulator device
- print constraints info
- print operating status
- print/[set] voltage value [uV] (force)
- print/[set] current value [uA]
- print/[set] operating mode id
- enable the regulator output
- disable the regulator output
The 'force' option can be used for setting the value which exceeds
the constraints min/max limits.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v3:
- new file
- Kconfig entry
Changes V4:
- cmd regulator: move platdata to uc pdata
- cmd_regulator: includes cleanup
- cmd_regulator: add get_curr_dev_and_pl() check type
- move config name: CONFIG_DM_REGULATOR_CMD to CONFIG_CMD_REGULATOR
- common/Kconfig - cleanup
---
common/Kconfig | 22 +++
common/Makefile| 1 +
common/cmd_regulator.c | 403
+
3 files changed, 426 insertions(+)
create mode 100644 common/cmd_regulator.c
Acked-by: Simon Glass s...@chromium.org
I have a few nits that could be dealt with by a follow-on patch.
Ok.
diff --git a/common/Kconfig b/common/Kconfig
index 4666f8e..52f8bb1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -470,5 +470,27 @@ config CMD_PMIC
- pmic read address - read byte of register at address
- pmic write address - write byte to register at address
The only one change for this command is 'dev'
subcommand.
+
+config CMD_REGULATOR
+ bool Enable Driver Model REGULATOR command
+ depends on DM_REGULATOR
+ help
+ This command is based on driver model regulator's API.
+ User interface features:
+ - list - list regulator devices
+ - regulator dev id - show or [set] operating regulator
device
+ - regulator info - print constraints info
+ - regulator status - print operating status
+ - regulator value val] -f - print/[set] voltage value
[uV]
+ - regulator current val- print/[set] current value
[uA]
+ - regulator mode id- print/[set] operating mode
id
+ - regulator enable - enable the regulator output
+ - regulator disable - disable the regulator output
+
+ The '-f' (force) option can be used for set the value which
exceeds
+ the limits, which are found in device-tree and are kept in
regulator's
+ uclass platdata structure.
+
endmenu
+
endmenu
diff --git a/common/Makefile b/common/Makefile
index 87a3efe..93bded3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -212,6 +212,7 @@ obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
# Power
obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o
+obj-$(CONFIG_CMD_REGULATOR) += cmd_regulator.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c
new file mode 100644
index 000..b1b9e87
--- /dev/null
+++ b/common/cmd_regulator.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2014-2015 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include errno.h
+#include dm.h
+#include dm/uclass-internal.h
+#include power/regulator.h
+
+#define LIMIT_SEQ 3
+#define LIMIT_DEVNAME 20
+#define LIMIT_OFNAME 20
+#define LIMIT_INFO 16
+
+static struct udevice *currdev;
+
+static int failed(const char *getset, const char *thing,
+ const char *for_dev, int ret)
+{
+ printf(Can't %s %s %s.\nError: %d (%s)\n, getset, thing,
for_dev,
+ ret,
errno_str(ret));
blank line here.
I don't see the blank line here in the patch, which I send.
Odd, there seem to be two blank lines there, and we only need one.
Ah, sorry. You mean, that there should be added a blank line.
Ok, will add one.
I worry that if someone gets one of these messages they will not be
able to find it in the source code. How about passing in the full
printf() string in each case, or just using printf() in situ? I don't
think the code space saving is significant.
It's not a debug message. And each one is different, and easy to grep
failed. The code is a little
[U-Boot] unassigned-patches/149: [PATCH] stm32f4: fix serial output bug
Signed-off-by: kunhuahuang huangkun...@gmail.com
---
Added to GNATS database as unassigned-patches/149
Responsible:patch-coord
Message-Id: 1429868904-4779-1-git-send-email-huangkun...@gmail.com
In-Reply-To:
References:
Patch-Date: Fri Apr 24 11:48:24 +0200 2015
---
drivers/serial/serial_stm32.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..693a7fa 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -81,6 +81,10 @@ static int stm32_serial_getc(void)
static void stm32_serial_putc(const char c)
{
struct stm32_serial *usart = (struct stm32_serial *)USART_BASE;
+
+ if(c == '\n')
+ stm32_serial_putc('\r');
+
while ((readl(usart-sr) USART_SR_FLAG_TXE) == 0)
;
writel(c, usart-dr);
--
1.9.1
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[U-Boot] [PATCH 09/21] sunxi: gpio: Build sunxi_name_to_gpio_bank for device-model code too
When doing a device-model enabled build we still need sunxi_name_to_gpio_bank
(for now) for the mmc pinmux code in board/sunxi/board.c, so build it for
device-model enabled builds too.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/gpio/sunxi_gpio.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index e6a90b9..91af1a5 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -118,20 +118,6 @@ int gpio_set_value(unsigned gpio, int value)
return sunxi_gpio_output(gpio, value);
}
-int sunxi_name_to_gpio_bank(const char *name)
-{
- int group = 0;
-
- if (*name == 'P' || *name == 'p')
- name++;
- if (*name = 'A') {
- group = *name - (*name 'a' ? 'a' : 'A');
- return group;
- }
-
- return -1;
-}
-
int sunxi_name_to_gpio(const char *name)
{
int group = 0;
@@ -171,6 +157,20 @@ int sunxi_name_to_gpio(const char *name)
}
#endif
+int sunxi_name_to_gpio_bank(const char *name)
+{
+ int group = 0;
+
+ if (*name == 'P' || *name == 'p')
+ name++;
+ if (*name = 'A') {
+ group = *name - (*name 'a' ? 'a' : 'A');
+ return group;
+ }
+
+ return -1;
+}
+
#ifdef CONFIG_DM_GPIO
/* TODO(s...@chromium.org): Remove this function and use device tree */
int sunxi_name_to_gpio(const char *name)
--
2.3.5
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[U-Boot] [PATCH 07/21] sunxi: gpio: Add temporary implementation of name_to_gpio()
From: Simon Glass s...@chromium.org
Until sunxi moves to device tree (e.g. for USB) we need to convert named
GPIOs to numbers. Add a function to do this.
This fixes the USB / EHCI support not working on the LinkSprite pcDuino3
(which uses devicemodel).
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/gpio/sunxi_gpio.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 29301c4..89209df 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -172,6 +172,17 @@ int sunxi_name_to_gpio(const char *name)
#endif
#ifdef CONFIG_DM_GPIO
+/* TODO(s...@chromium.org): Remove this function and use device tree */
+int sunxi_name_to_gpio(const char *name)
+{
+ unsigned int gpio;
+ int ret;
+
+ ret = gpio_lookup_name(name, NULL, NULL, gpio);
+
+ return ret ? ret : gpio;
+}
+
static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
--
2.3.5
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Re: [U-Boot] [PATCH 1/2] dm: sf: Make SST flash write op work again
Hi Jagan,
On Fri, Apr 24, 2015 at 5:25 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 24 April 2015 at 14:12, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Fri, Apr 24, 2015 at 4:07 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Bin,
On 23 April 2015 at 14:30, Bin Meng bmeng...@gmail.com wrote:
With SPI flash moving to driver model, commit fbb0991 dm: Convert
spi_flash_probe() and 'sf probe' to use driver model ignored the
SST flash-specific write op (byte program word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
a new SST flash-specific driver to handle the different write op
from the standard one.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_probe.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d19138d..47438d2 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -511,4 +511,35 @@ U_BOOT_DRIVER(spi_flash_std) = {
.ops= spi_flash_std_ops,
};
+int spi_flash_sst_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ return sst_write_bp(flash, offset, len, buf);
+ else
+ return sst_write_wp(flash, offset, len, buf);
+}
+
+static const struct dm_spi_flash_ops spi_flash_sst_ops = {
+ .read = spi_flash_std_read,
+ .write = spi_flash_sst_write,
+ .erase = spi_flash_std_erase,
+};
+
+static const struct udevice_id spi_flash_sst_ids[] = {
+ { .compatible = spi-flash-sst },
+ { }
+};
+
+U_BOOT_DRIVER(spi_flash_sst) = {
+ .name = spi_flash_sst,
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_flash_sst_ids,
+ .probe = spi_flash_std_probe,
+ .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .ops= spi_flash_sst_ops,
+};
+
#endif /* CONFIG_DM_SPI_FLASH */
--
1.8.2.1
I'm just curiosity to see different approach of being code duplicate
with just for sst write call.
What about this-
int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
const void *buf)
{
struct spi_flash *flash = dev_get_uclass_priv(dev);
if defined(CONFIG_SPI_FLASH_SST)
if (flash-flags SST_WR) {
if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
}
#endif
return spi_flash_cmd_write_ops(flash, offset, len, buf);
}
Of course this requires extra flags member in spi_flash, any other thoughts?
Yep, this way works too. Let me know which way you prefer and I can respin a
v2.
I preferred second.
OK, will respin a v2 soon. Thanks,
Regards,
Bin
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[U-Boot] [PATCH] image: android: handle default kernel address
The two tools that create android boot images, mkbootimg and the fastboot
client, set the kernel address by default to 0x10008000.
U-boot always honors this field, and will try to relocate the kernel to
whatever value is set in the header, which won't be mapped to the actual RAM on
most platforms, resulting in the kernel obviously not booting.
All the targets in U-Boot right now will download the android boot image to
CONFIG_SYS_LOAD_ADDR, which means that it will already have been downloaded to
some location that is suitable for execution.
In order to have the kernel booting even with the default boot image kernel
address, if that address is used, just execute the kernel where it is.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
common/image-android.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/common/image-android.c b/common/image-android.c
index 59079fc32b51..d946c2f814c1 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -10,8 +10,29 @@
#include malloc.h
#include errno.h
+#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
+
static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
+static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
+{
+ /*
+* All the Android tools that generate a boot.img use this
+* address as the default.
+*
+* Even though it doesn't really make a lot of sense, and it
+* might be valid on some platforms, we treat that adress as
+* the default value for this field, and try to execute the
+* kernel in place in such a case.
+*
+* Otherwise, we will return the actual value set by the user.
+*/
+ if (hdr-kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR)
+ return (ulong)hdr + hdr-page_size;
+
+ return hdr-kernel_addr;
+}
+
/**
* android_image_get_kernel() - processes kernel part of Android boot images
* @hdr: Pointer to image header, which is at the start
@@ -30,6 +51,8 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
ulong *os_data, ulong *os_len)
{
+ u32 kernel_addr = android_image_get_kernel_addr(hdr);
+
/*
* Not all Android tools use the id field for signing the image with
* sha1 (or anything) so we don't check it. It is not obvious that the
@@ -41,7 +64,7 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr,
int verify,
printf(Android's image name: %s\n, andr_tmp_str);
printf(Kernel load addr 0x%08x size %u KiB\n,
- hdr-kernel_addr, DIV_ROUND_UP(hdr-kernel_size, 1024));
+ kernel_addr, DIV_ROUND_UP(hdr-kernel_size, 1024));
int len = 0;
if (*hdr-cmdline) {
@@ -101,7 +124,7 @@ ulong android_image_get_end(const struct andr_img_hdr *hdr)
ulong android_image_get_kload(const struct andr_img_hdr *hdr)
{
- return hdr-kernel_addr;
+ return android_image_get_kernel_addr(hdr);
}
int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
--
2.3.5
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[U-Boot] [PATCH v3 1/5] mx6cuboxi: Fix the defconfig name
From: Fabio Estevam fabio.este...@freescale.com The correct name of the defconfig file is 'mx6cuboxi_defconfig'. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Changes since v2: - None Changes since v1: - None board/solidrun/mx6cuboxi/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS index 3d468ed..a3506c2 100644 --- a/board/solidrun/mx6cuboxi/MAINTAINERS +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -3,4 +3,4 @@ M: Fabio Estevam fabio.este...@freescale.com S: Maintained F: board/solidrun/mx6cuboxi/ F: include/configs/mx6cuboxi.h -F: configs/mx6cuboxi_spl_defconfig +F: configs/mx6cuboxi_defconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 17/21] sunxi: dts: Add dts files which have been submitted but not yet merged upstream
We need dts files for all boards we support, so bring in a few unmerged ones,
these will be replaced with the upstream merged versions the next time we
sync dts files.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun4i-a10-jesurun-q5.dts | 194 ++
arch/arm/dts/sun7i-a20-primo73.dts| 102 ++
3 files changed, 298 insertions(+)
create mode 100644 arch/arm/dts/sun4i-a10-jesurun-q5.dts
create mode 100644 arch/arm/dts/sun7i-a20-primo73.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ff55dd..a18c565 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -65,6 +65,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet97fv2.dtb \
+ sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-mk802.dtb \
@@ -102,6 +103,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-orangepi-mini.dtb \
sun7i-a20-pcduino3.dtb \
sun7i-a20-pcduino3-nano.dtb \
+ sun7i-a20-primo73.dtb \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-ippo-q8h-v5.dtb \
diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts
b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
new file mode 100644
index 000..1b0452f
--- /dev/null
+++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2015 Gábor Nyers
+ *
+ * Gábor Nyers gabor.ny...@gmail.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun4i-a10.dtsi
+#include sunxi-common-regulators.dtsi
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pinctrl/sun4i-a10.h
+
+/ {
+ model = Jesurun Q5;
+ compatible = jesurun,q5, allwinner,sun4i-a10;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ stdout-path = serial0:115200n8;
+ };
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_q5;
+
+ green {
+ label = q5:green:usr;
+ gpios = pio 7 20 GPIO_ACTIVE_HIGH; /* PH20 */
+ };
+
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = regulator-fixed;
+ pinctrl-names = default;
+ pinctrl-0 = emac_power_pin_q5;
+ regulator-name = emac-3v3;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ enable-active-high;
+ gpio = pio 7 19 GPIO_ACTIVE_HIGH; /* PH19 */
+ };
+};
+
+ahci {
+ status = okay;
+};
+
+ehci0 {
+ status = okay;
+};
+
+ehci1 {
+
Re: [U-Boot] [PATCH] socfpga: implement socdk SPI flash config in dts
On Fri 2015-04-24 05:22:55, Marek Vasut wrote: On Thursday, April 23, 2015 at 09:14:01 AM, Pavel Machek wrote: SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek pa...@denx.de Applied, thanks. Can you please cook one for Arria V too while at it, so we're consistent ? Ok (if you are sure it has same hardware?). Should something like socfpga_devel_board.dtsi be created so we don't have to copy same piece of dts 3 times? Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/21] sunxi: Move ALL boards to the device-model
Hi Simon, Ian, As promised here is my patch-set to move all sunxi boards to the device-model, it was slightly more work then I expected, and as such the patch-set is also somewhat larger then expected, but it is done :) Please review, since this all only touches sunxi specific files the intention is to merge this through the sunxi tree as soon as all the patches are acked. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dm: sf: Add Atmel DataFlash spi flash driver
Hi Haikun,
On 24 April 2015 at 07:22, Haikun Wang haikun.w...@freescale.com wrote:
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B.
Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write
- 5. Replace spi_flash_read with spi_flash_cmd_read
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 5 6
Changes in v1: None
drivers/mtd/spi/Makefile| 1 +
drivers/mtd/spi/spi_dataflash.c | 704
2 files changed, 705 insertions(+)
create mode 100644 drivers/mtd/spi/spi_dataflash.c
Reviewed-by: Simon Glass s...@chromium.org
See a small questoin below.
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..42acd24 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
#ifndef CONFIG_DM_SPI
obj-$(CONFIG_SPI_FLASH) += sf_probe.o
#endif
+obj-$(CONFIG_DM_SPI_DATAFLASH) += spi_dataflash.o
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/spi_dataflash.c b/drivers/mtd/spi/spi_dataflash.c
new file mode 100644
index 000..c68cf2e
--- /dev/null
+++ b/drivers/mtd/spi/spi_dataflash.c
@@ -0,0 +1,704 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE 0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1 0x84/* group B */
+#define OP_WRITE_BUFFER2 0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE 0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1 0x53
+#define OP_TRANSFER_BUF2 0x55
+#define OP_MREAD_BUFFER1 0xD4
+#define OP_MREAD_BUFFER2 0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1 0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2 0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY 0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY 0x9B/* revision D */
+
+
+struct dataflash {
+ uint8_t command[16];
+ unsigned short page_offset;/* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+ int ret;
+ u8 status;
+ /*
+* NOTE: at45db321c over 25 MHz wants to write
+* a dummy byte after the opcode...
+*/
+ ret = spi_flash_cmd(spi, OP_READ_STATUS, status, 1);
+ return ret ? -EIO : status;
+}
+
+/*
[U-Boot] [PATCH v2] dm: sf: Add Atmel DataFlash spi flash driver
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
Verified with AT45DB021B.
Changes in v2:
- 1. Correct comment style
- 2. Use get_timer in dataflash_waitready to check whether timeout
- 3. Remove struct spi_flash * in struct dataflash, and get it from
udevice-uclass_priv
- 4. Replace spi_flash_write_common with spi_flash_cmd_write
- 5. Replace spi_flash_read with spi_flash_cmd_read
- 6. Change type of varible status form char to u8 in dataflash_status
- 7. Change add_dataflash's argument type due to change 3
- 8. Add claim_bus and release_bus in erase/write/read due to change 5 6
Changes in v1: None
drivers/mtd/spi/Makefile| 1 +
drivers/mtd/spi/spi_dataflash.c | 704
2 files changed, 705 insertions(+)
create mode 100644 drivers/mtd/spi/spi_dataflash.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784..42acd24 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,6 +15,7 @@ endif
#ifndef CONFIG_DM_SPI
obj-$(CONFIG_SPI_FLASH) += sf_probe.o
#endif
+obj-$(CONFIG_DM_SPI_DATAFLASH) += spi_dataflash.o
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/spi_dataflash.c b/drivers/mtd/spi/spi_dataflash.c
new file mode 100644
index 000..c68cf2e
--- /dev/null
+++ b/drivers/mtd/spi/spi_dataflash.c
@@ -0,0 +1,704 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.w...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include div64.h
+#include linux/err.h
+#include linux/math64.h
+
+#include sf_internal.h
+
+/*
+ * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE 0xD2
+
+/* group B requests can run even while status reports busy */
+#define OP_READ_STATUS 0xD7/* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER10xD4/* group B */
+#define OP_READ_BUFFER20xD6/* group B */
+#define OP_WRITE_BUFFER1 0x84/* group B */
+#define OP_WRITE_BUFFER2 0x87/* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE 0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1 0x53
+#define OP_TRANSFER_BUF2 0x55
+#define OP_MREAD_BUFFER1 0xD4
+#define OP_MREAD_BUFFER2 0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1 0x88/* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2 0x89/* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF10x82
+#define OP_PROGRAM_VIA_BUF20x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF10x60
+#define OP_COMPARE_BUF20x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF10x58
+#define OP_REWRITE_VIA_BUF20x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY 0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY 0x9B/* revision D */
+
+
+struct dataflash {
+ uint8_t command[16];
+ unsigned short page_offset;/* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+ int ret;
+ u8 status;
+ /*
+* NOTE: at45db321c over 25 MHz wants to write
+* a dummy byte after the opcode...
+*/
+ ret = spi_flash_cmd(spi, OP_READ_STATUS, status, 1);
+ return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return 0
+ */
+static int dataflash_waitready(struct spi_slave *spi)
+{
+ int status;
+ int timeout = 2 * CONFIG_SYS_HZ;
+ int timebase;
+
+ timebase =
[U-Boot] [PATCH v3 2/5] mx6cuboxi: Prepare for multi SoC support
From: Fabio Estevam fabio.este...@freescale.com
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v2:
- None
Changes since v1:
- None
board/solidrun/mx6cuboxi/mx6cuboxi.c | 60 ++--
configs/mx6cuboxi_defconfig | 2 +-
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index b696dcb..0377dc4 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -28,7 +28,6 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
-#include asm/arch/mx6-ddr.h
#include spl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -59,22 +58,22 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
@@ -88,7 +87,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
@@ -97,33 +96,33 @@ int board_mmc_init(bd_t *bis)
}
static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 reset */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
/* AR8035 interrupt */
- MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPIO16 - AR8035 25MHz */
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 CLK_25M -- ENET_REF_CLK (V22) */
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD1__RGMII_RD1 |
[U-Boot] [PATCH 20/21] sunxi: Move all boards to the device-model
Now that we've everything prepared for it remove the DM settings from the defconfig(s) and simply always set them for sunxi, so that all sunxi boards will allways use dm now. Signed-off-by: Hans de Goede hdego...@redhat.com --- arch/arm/Kconfig | 5 + board/sunxi/Kconfig| 12 configs/A20-OLinuXino-Lime2_defconfig | 2 -- configs/A20-OLinuXino-Lime_defconfig | 2 -- configs/A20-OLinuXino_MICRO_defconfig | 2 -- configs/Bananapi_defconfig | 2 -- configs/Bananapro_defconfig| 2 -- configs/CSQ_CS908_defconfig| 2 -- configs/Colombus_defconfig | 2 -- configs/Cubieboard2_defconfig | 2 -- configs/Cubietruck_defconfig | 2 -- configs/Hummingbird_A31_defconfig | 2 -- configs/Linksprite_pcDuino3_Nano_defconfig | 2 -- configs/Linksprite_pcDuino3_defconfig | 9 - configs/Mele_I7_defconfig | 2 -- configs/Mele_M3_defconfig | 2 -- configs/Mele_M5_defconfig | 2 -- configs/Mele_M9_defconfig | 2 -- configs/Orangepi_defconfig | 2 -- configs/Orangepi_mini_defconfig| 2 -- configs/UTOO_P66_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 2 -- configs/i12-tvbox_defconfig| 2 -- configs/mixtile_loftq_defconfig| 2 -- include/configs/sunxi-common.h | 2 +- 25 files changed, 19 insertions(+), 50 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b39bb4f..d681fcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -627,6 +627,11 @@ config TARGET_SOCFPGA_CYCLONE5 config ARCH_SUNXI bool Support sunxi (Allwinner) SoCs + select DM + select DM_GPIO + select OF_CONTROL + select OF_SEPARATE + select SPL_DISABLE_OF_CONTROL config TARGET_SNOWBALL bool Support snowball diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 3831d3b..3997637 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -529,4 +529,16 @@ config GMAC_TX_DELAY ---help--- Set the GMAC Transmit Clock Delay Chain value. +config NET + default y + +config NETDEVICES + default y + +config DM_ETH + default y + +config DM_SERIAL + default y + endif diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 7c1490e..59e7473 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,5 +11,3 @@ CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 879b939..2ba70f7 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -8,5 +8,3 @@ CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index a530d13..7d2e810 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,5 +12,3 @@ CONFIG_DRAM_CLK=384 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 0e1d7b5..8dcf4a7 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,5 +9,3 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index b68333f..d3e015c 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,5 +11,3 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 4d9e1e9..817cd6d 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -14,5 +14,3 @@ CONFIG_AXP221_ALDO1_VOLT=3300 CONFIG_USB1_VBUS_PIN= CONFIG_USB2_VBUS_PIN= CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 96b55ba..c7efabc 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -11,5 +11,3 @@ CONFIG_AXP221_ALDO1_VOLT=3300 # No Vbus gpio for usb1 CONFIG_USB1_VBUS_PIN= CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index ca0be1f..092d6b0 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -9,5 +9,3 @@ CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4
Re: [U-Boot] [PATCH v2] f_thor: Dont perform reset at the end of thor
Hi Michal,
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases and hence
provided an option to do so.
The case would be to download the images to DDR instead
of flash device.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Update commit message with additional description
drivers/usb/gadget/f_thor.c | 7 +++
drivers/usb/gadget/f_thor.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index e9a690eff5f1..5c8f6768519c 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -123,6 +123,9 @@ static int process_rqt_cmd(const struct rqt_box
*rqt) send_rsp(rsp);
g_dnl_unregister();
dfu_free_entities();
+#ifdef CONFIG_THOR_RESET_OFF
+ return RESET_DONE;
+#endif
run_command(reset, 0);
break;
case RQT_CMD_POWEROFF:
@@ -728,6 +731,10 @@ int thor_handle(void)
if (ret 0) {
ret = process_data();
+#ifdef CONFIG_THOR_RESET_OFF
+ if (ret == RESET_DONE)
+ break;
+#endif
if (ret 0)
return ret;
} else {
diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h
index 833a9d24ae7e..83412851dd17 100644
--- a/drivers/usb/gadget/f_thor.h
+++ b/drivers/usb/gadget/f_thor.h
@@ -121,4 +121,7 @@ struct f_thor {
#define F_NAME_BUF_SIZE 32
#define THOR_PACKET_SIZE SZ_1M /* 1 MiB */
#define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */
+#ifdef CONFIG_THOR_RESET_OFF
+#define RESET_DONE 0x
+#endif
#endif /* _USB_THOR_H_ */
Applied to u-boot-dfu. Thanks
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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[U-Boot] [PATCH v3 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
From: Fabio Estevam fabio.este...@freescale.com
Instead of hardcoding the 'fdt_file' variable, let's detect the SoC and
board variant on the fly and change the dtb name.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Rabeeh Khoury rab...@solid-run.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v2:
- Add Rabeeh's Signed-off-by
Changes since v1:
- Attribute the credit to Rabeeh
- Create a U-boot command for checking if the board is hummingboard
board/solidrun/mx6cuboxi/mx6cuboxi.c | 30 ++
include/configs/mx6cuboxi.h | 12 ++--
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 83410b2..4ea6081 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -212,6 +212,36 @@ int checkboard(void)
return 0;
}
+static const char *build_dts_prefix(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return imx6q;
+ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ return imx6dl;
+
+ return unknown;
+}
+
+static int do_is_hummingboard(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
+{
+ if (is_hummingboard())
+ return CMD_RET_SUCCESS;
+ else
+ return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+ is_hummingboard, 1, 1, do_is_hummingboard,
+ detect if it is a Hummingboard or Cubox-i,
+
+);
+
+int misc_init_r(void)
+{
+ setenv(dts_prefix, build_dts_prefix());
+ return 0;
+}
+
#ifdef CONFIG_SPL_BUILD
#include asm/arch/mx6-ddr.h
static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 5d58b16..c3cf633 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -29,6 +29,7 @@
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
@@ -81,14 +82,19 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV ttymxc0
#define CONFIG_MMCROOT /dev/mmcblk0p2
-#define CONFIG_DEFAULT_FDT_FILEimx6q-hummingboard.dtb
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
#define CONFIG_EXTRA_ENV_SETTINGS \
script=boot.scr\0 \
image=zImage\0 \
- fdt_file= CONFIG_DEFAULT_FDT_FILE \0 \
+ check_suffix= \
+ if is_hummingboard; then \
+ setenv dts_suffix -hummingboard.dtb; \
+ else \
+ setenv dts_suffix -cubox-i.dtb; \
+ fi; \
+ setenv fdt_file ${dts_prefix}${dts_suffix}; \
fdt_addr=0x1800\0 \
boot_fdt=try\0 \
ip_dyn=yes\0 \
@@ -119,6 +125,7 @@
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0 \
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0 \
mmcboot=echo Booting from mmc ...; \
+ run check_suffix; \
run mmcargs; \
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \
if run loadfdt; then \
@@ -137,6 +144,7 @@
root=/dev/nfs \
ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0 \
netboot=echo Booting from net ...; \
+ run check_suffix; \
run netargs; \
if test ${ip_dyn} = yes; then \
setenv get_cmd dhcp; \
--
1.9.1
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[U-Boot] [PATCH 13/21] sunxi: emac: port to phylib
This is a preparation-patch for adding device-model support to the emac
driver.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/net/sunxi_emac.c | 111 +
include/configs/sunxi-common.h | 2 +
2 files changed, 71 insertions(+), 42 deletions(-)
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 7b31f8c..b9fd1b8 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -156,9 +156,9 @@ struct sunxi_sramc_regs {
#define DMA_CPU_TRRESHOLD 2000
struct emac_eth_dev {
- u32 speed;
- u32 duplex;
- u32 phy_configured;
+ struct emac_regs *regs;
+ struct mii_dev *bus;
+ struct phy_device *phydev;
int link_printed;
};
@@ -195,11 +195,10 @@ static void emac_outblk_32bit(void *reg, void *data, int
count)
}
/* Read a word from phyxcer */
-static int emac_phy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct emac_regs *regs = (struct emac_regs *)dev-iobase;
+ struct emac_eth_dev *priv = bus-priv;
+ struct emac_regs *regs = priv-regs;
/* issue the phy address and reg */
writel(addr 8 | reg, regs-mac_madr);
@@ -213,18 +212,16 @@ static int emac_phy_read(const char *devname, unsigned
char addr,
/* push down the phy io line */
writel(0x0, regs-mac_mcmd);
- /* and write data */
- *value = readl(regs-mac_mrdd);
-
- return 0;
+ /* And read data */
+ return readl(regs-mac_mrdd);
}
/* Write a word to phyxcer */
-static int emac_phy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct emac_regs *regs = (struct emac_regs *)dev-iobase;
+ struct emac_eth_dev *priv = bus-priv;
+ struct emac_regs *regs = priv-regs;
/* issue the phy address and reg */
writel(addr 8 | reg, regs-mac_madr);
@@ -244,12 +241,44 @@ static int emac_phy_write(const char *devname, unsigned
char addr,
return 0;
}
-static void emac_setup(struct eth_device *dev)
+static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
{
- struct emac_regs *regs = (struct emac_regs *)dev-iobase;
+ int ret, mask = 0x;
+
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 CONFIG_PHY_ADDR;
+#endif
+
+ priv-bus = mdio_alloc();
+ if (!priv-bus) {
+ printf(Failed to allocate MDIO bus\n);
+ return -ENOMEM;
+ }
+
+ priv-bus-read = emac_mdio_read;
+ priv-bus-write = emac_mdio_write;
+ priv-bus-priv = priv;
+ strcpy(priv-bus-name, emac);
+
+ ret = mdio_register(priv-bus);
+ if (ret)
+ return ret;
+
+ priv-phydev = phy_find_by_mask(priv-bus, mask,
+ PHY_INTERFACE_MODE_MII);
+ if (!priv-phydev)
+ return -ENODEV;
+
+ phy_connect_dev(priv-phydev, dev);
+ phy_config(priv-phydev);
+
+ return 0;
+}
+
+static void emac_setup(struct emac_eth_dev *priv)
+{
+ struct emac_regs *regs = priv-regs;
u32 reg_val;
- u16 phy_val;
- u32 duplex_flag;
/* Set up TX */
writel(EMAC_TX_SETUP, regs-tx_mode);
@@ -262,12 +291,8 @@ static void emac_setup(struct eth_device *dev)
writel(EMAC_MAC_CTL0_SETUP, regs-mac_ctl0);
/* Set MAC CTL1 */
- emac_phy_read(dev-name, 1, 0, phy_val);
- debug(PHY SETUP, reg 0 value: %x\n, phy_val);
- duplex_flag = !!(phy_val (1 8));
-
reg_val = 0;
- if (duplex_flag)
+ if (priv-phydev-duplex == DUPLEX_FULL)
reg_val = (0x1 0);
writel(EMAC_MAC_CTL1_SETUP | reg_val, regs-mac_ctl1);
@@ -302,7 +327,7 @@ static int sunxi_emac_eth_init(struct eth_device *dev, bd_t
*bd)
{
struct emac_regs *regs = (struct emac_regs *)dev-iobase;
struct emac_eth_dev *priv = dev-priv;
- u16 phy_reg;
+ int ret;
/* Init EMAC */
@@ -320,7 +345,7 @@ static int sunxi_emac_eth_init(struct eth_device *dev, bd_t
*bd)
udelay(1);
/* Set up EMAC */
- emac_setup(dev);
+ emac_setup(priv);
writel(dev-enetaddr[0] 16 | dev-enetaddr[1] 8 |
dev-enetaddr[2], regs-mac_a1);
@@ -332,29 +357,32 @@ static int sunxi_emac_eth_init(struct eth_device *dev,
bd_t *bd)
emac_reset(dev);
/* PHY POWER UP */
- emac_phy_read(dev-name, 1, 0, phy_reg);
- emac_phy_write(dev-name, 1, 0, phy_reg (~(0x1 11)));
- mdelay(1);
-
-
Re: [U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
Hi Bin,
On 04/23/2015 08:20 PM, Bin Meng wrote:
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
I think you need also update minnowmax.dts file to change the compatible string.
Regards,
Bin
Well ... I didn't see that as the NOR was still working on the board, I
didn't find any reference except in the device tree for this compatible
string, do you know if this is really used or not?
I'll do the modification anyway, it's always better to put the correct
information.
Regards,
Gabriel
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[U-Boot] [PATCH v2 1/4] x86: Add a function to assign IRQ numbers to PCI device
Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/pci.c | 21 +
arch/x86/include/asm/pci.h | 14 ++
2 files changed, 35 insertions(+)
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e23b233..c209f15 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -151,3 +151,24 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t
bdf, uint offset,
return 0;
}
+
+void pci_assign_irqs(int bus, int device, int func, u8 irq[4])
+{
+ pci_dev_t bdf;
+ u8 pin, line;
+
+ bdf = PCI_BDF(bus, device, func);
+
+ pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+
+ /* PCI spec says all values except 1..4 are reserved */
+ if ((pin 1) || (pin 4))
+ return;
+
+ line = irq[pin - 1];
+
+ debug(Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n,
+ line, bus, device, func, 'A' + pin - 1);
+
+ x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+}
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index a1969ed..56eaa25 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -64,6 +64,20 @@ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf,
uint offset,
int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong value, enum pci_size_t size);
+/**
+ * Assign IRQ number to a PCI device
+ *
+ * This function assigns IRQ for a PCI device. If the device does not exist
+ * or does not require interrupts then this function has no effect.
+ *
+ * @bus: PCI bus number
+ * @device:PCI device number
+ * @func: PCI function number
+ * @irq: An array of IRQ numbers that are assigned to INTA through
+ * INTD of this PCI device.
+ */
+void pci_assign_irqs(int bus, int device, int func, u8 irq[4]);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_I386_H_ */
--
1.8.2.1
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[U-Boot] Please pull u-boot-fdt
Hi Tom, The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71: Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23 14:56:47 -0400) are available in the git repository at: http://git.denx.de/u-boot-fdt.git for you to fetch changes up to 77d7fff8cec2652be8c2494b6b66d14a398ec860: fdt: Fix handling of paths with options in them (2015-04-23 22:54:32 -0600) Hans de Goede (1): fdt: Fix handling of paths with options in them lib/libfdt/fdt_ro.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/11] net: Use env callbacks for net variables
Hi Joe,
On 21 April 2015 at 16:02, Joe Hershberger joe.hershber...@ni.com wrote:
Instead of checking for changes to the env each time we enter the
net_loop, use the env callbacks to update the values of the variables.
Don't update the variables when the source was programmatic, since the
variables were the source of the new value.
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
include/env_callback.h | 22 ++-
net/net.c | 105
+
2 files changed, 110 insertions(+), 17 deletions(-)
Reviewed-by: Simon Glass s...@chromium.org
Q below.
diff --git a/include/env_callback.h b/include/env_callback.h
index 3de1093..91f3cc0 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -37,6 +37,26 @@
#define ENV_DOT_ESCAPE
#endif
+#ifdef CONFIG_CMD_DNS
+#define DNS_CALLBACK dnsip:dnsip,
+#else
+#define DNS_CALLBACK
+#endif
+
+#ifdef CONFIG_NET
+#define NET_CALLBACKS \
+ bootfile:bootfile, \
+ ipaddr:ipaddr, \
+ gatewayip:gatewayip, \
+ netmask:netmask, \
+ serverip:serverip, \
+ nvlan:nvlan, \
+ vlan:vlan, \
+ DNS_CALLBACK
+#else
+#define NET_CALLBACKS
+#endif
+
/*
* This list of callback bindings is static, but may be overridden by
defining
* a new association in the .callbacks environment variable.
@@ -44,7 +64,7 @@
#define ENV_CALLBACK_LIST_STATIC ENV_DOT_ESCAPE ENV_CALLBACK_VAR
:callbacks, \
ENV_DOT_ESCAPE ENV_FLAGS_VAR :flags, \
baudrate:baudrate, \
- bootfile:bootfile, \
+ NET_CALLBACKS \
loadaddr:loadaddr, \
SILENT_CALLBACK \
SPLASHIMAGE_CALLBACK \
diff --git a/net/net.c b/net/net.c
index a365df0..57111ad 100644
--- a/net/net.c
+++ b/net/net.c
@@ -208,6 +208,9 @@ int __maybe_unused net_busy_flag;
static int on_bootfile(const char *name, const char *value, enum env_op op,
int flags)
{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
switch (op) {
case env_op_create:
case env_op_overwrite:
@@ -222,6 +225,92 @@ static int on_bootfile(const char *name, const char
*value, enum env_op op,
}
U_BOOT_ENV_CALLBACK(bootfile, on_bootfile);
+static int on_ipaddr(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
Can you just do this?
if (flags H_PROGRAMMATIC)
+ return 0;
+
+ net_ip = string_to_ip(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(ipaddr, on_ipaddr);
+
+static int on_gatewayip(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_gateway = string_to_ip(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(gatewayip, on_gatewayip);
+
+static int on_netmask(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_netmask = string_to_ip(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(netmask, on_netmask);
+
+static int on_serverip(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_server_ip = string_to_ip(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(serverip, on_serverip);
+
+static int on_nvlan(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_native_vlan = string_to_vlan(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(nvlan, on_nvlan);
+
+static int on_vlan(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_our_vlan = string_to_vlan(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(vlan, on_vlan);
+
+#if defined(CONFIG_CMD_DNS)
+static int on_dnsip(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ if ((flags H_ORIGIN_FLAGS) == H_PROGRAMMATIC)
+ return 0;
+
+ net_dns_server = string_to_ip(value);
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(dnsip, on_dnsip);
+#endif
+
/*
* Check if autoload is enabled. If so, use either NFS or TFTP to download
* the boot file.
@@ -252,22 +341,6 @@ void net_auto_load(void)
static void net_init_loop(void)
{
- static int env_changed_id;
- int env_id = get_env_id();
-
- /* update only when the environment has changed */
- if (env_changed_id != env_id) {
- net_ip = getenv_ip(ipaddr);
- net_gateway = getenv_ip(gatewayip);
-
Re: [U-Boot] [PATCH 1/8] armv8/fsl-lsch3: Add Freescale Debug Server driver
On 03/19/2015 09:20 AM, York Sun wrote: From: Bhupesh Sharma bhupesh.sha...@freescale.com The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com --- This set is to fsl-qoriq master, awaiting upstream. [U-Boot,1/8] armv8/fsl-lsch3: Add Freescale Debug Server driver [U-Boot,2/8] fsl-ch3/README: Add description for NOR flash layout (firmware images) [U-Boot,3/8] driver/fsl-mc: Add support of MC Flibs [U-Boot,4/8] driver/ldpaa_eth: Add LDPAA Ethernet driver [U-Boot,5/8] board/ls2085_common: Increase malloc length [U-Boot,6/8] driver/fsl_ifc: Add support to finalize CS1, CS3 address binding [U-Boot,7/8] nand/fsl_ifc: Increase eccstat[] for IFC 2.0 [U-Boot,v2,8/8] driver/i2c/mxc: Enable I2C bus 3 and 4 York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-fsl-qoriq master
Tom, I am having trouble cloning git repositories. I hope this pull request was generated correctly. I saw fatal: read error: Connection reset by peer when creating this pull request. The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to ab10d73d2fc13bd5baf5024e54ad92641d238bdb: armv8/fsl-lsch3: Implement workaround for I2C erratum A009203 (2015-04-23 16:46:51 -0700) Alison Wang (2): arm/ls102xa:Add support of conditional workaround implementation as per SoC ver ls102xa: ddr4: Use LPUART as console output to verify DCU driver Bhupesh Sharma (3): armv8/fsl-lsch3: Add Freescale Debug Server driver fsl-ch3/README: Add description for NOR flash layout (firmware images) armv8/fsl-ch3: Add support to print RCW configuration J. German Rivera (1): drivers/fsl-mc: Changed MC firmware loading for new boot architecture Jaiprakash Singh (1): driver/ifc: Add 64KB page support Minghuan Lian (4): pci/layerscape: remove unnecessary pcie_layerscape.h pci/layerscape: fix link and class issues to support ls2085a drivers/net/e1000.c: Cleanup whitespace armv8: Add SerDes framework for Layerscape Architecture Nikhil Badola (3): drivers:usb: Add device-tree fixup to identify socs having dual phy drivers:usb:fsl: Add affected SOCs for USB Erratum A007792 drivers:usb: Check if USB Erratum A005697 is applicable on BSC913x Prabhakar Kushwaha (8): driver/fsl-mc: Add support of MC Flibs driver/ldpaa_eth: Add LDPAA Ethernet driver board/ls2085_common: Increase malloc length driver/fsl_ifc: Add support to finalize CS1, CS3 address binding armv8/ls2085a: Update common header file driver/ldpaa_eth: Update ldpaa ethernet driver driver/ldpaa: Add support of WRIOP static data structure board/ls2085qds: Add support ethernet Scott Wood (9): nand/fsl_ifc: Increase eccstat[] for IFC 2.0 cmd_mem: Store last address/size/etc as ulong armv8/fsl-lsch3: Set nodes in DVM domain fsl-lsch3: Introduce place for common early SoC init armv8/ls2085a: Add workaround for USB erratum A-008751 armv8/fsl-lsch3: Use correct compatible for serial clock fixup armv8/ls2085aqds: NAND boot support freescale/qixis: Add support for booting from NAND armv8/ls2085ardb: Enable NAND SPL support Shaohui Xie (1): net/memac_phy: reuse driver for little endian SoCs Yangbo Lu (1): ls2085a: esdhc: Add esdhc support for ls2085a Yao Yuan (1): ls1021atwr: add hwconfig setting to do pin mux York Sun (12): driver/i2c/mxc: Enable I2C bus 3 and 4 drivers/ddr/fsl: Update DDR driver for DDR4 driver/ddr/fsl: Fix driver to support empty first slot driver/ddr/fsl: Add built-in memory test for DDR4 driver driver/ddr/fsl: Add workaround for DDR erratum A008511 armv8/fsl-lsch3: Implement workaround for erratum A008585 armv8/fsl-lsch3: Fix platform clock calculation armv8/ls2085a: Fix generic timer clock source armv8/fsl-lsch3: Update early MMU table armv8/ls2085aqds: Add support of LS2085AQDS platform armv8/ls2085ardb: Add support of LS2085ARDB platform armv8/fsl-lsch3: Implement workaround for I2C erratum A009203 Zhao Qiang (2): QE/DeepSleep: add QE deepsleep support for mpc85xx QE/DeepSleep: add QE deepsleep support for arm gaurav rana (1): Add bootscript support to esbc_validate. pankaj chauhan (2): armv8/ls2085a: Add support for reset request net/phy/cortina: Fix compilation warning README| 13 + arch/arm/Kconfig | 24 + arch/arm/cpu/armv7/ls102xa/clock.c|4 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 + arch/arm/cpu/armv8/fsl-lsch3/README | 138 +++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 123 ++- arch/arm/cpu/armv8/fsl-lsch3/fdt.c|9 +- arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 115 +++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 15 + arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 +++ arch/arm/cpu/armv8/fsl-lsch3/mp.c |7 + arch/arm/cpu/armv8/fsl-lsch3/mp.h |1 + arch/arm/cpu/armv8/fsl-lsch3/soc.c| 107 ++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 11 +- arch/arm/cpu/armv8/generic_timer.c| 11 + arch/arm/cpu/armv8/u-boot-spl.lds | 77 ++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 60 +- arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 ++
Re: [U-Boot] [PATCH 05/11] env: Simplify the reverse_strstr() interface
Hi Joe,
On 21 April 2015 at 16:02, Joe Hershberger joe.hershber...@ni.com wrote:
The logic to find the whole matching name was split needlessly between
the reverse_strstr function and its caller. Fully contain it to make the
interface for calling it more consistent.
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
common/env_attr.c | 79
+--
1 file changed, 41 insertions(+), 38 deletions(-)
You could perhaps add some environment tests in test/ for this
function, or access it through getenv(), etc.
diff --git a/common/env_attr.c b/common/env_attr.c
index e791f44..d266142 100644
--- a/common/env_attr.c
+++ b/common/env_attr.c
@@ -109,33 +109,55 @@ int env_attr_walk(const char *attr_list,
}
/*
- * Search for the last matching string in another string with the option to
- * start looking at a certain point (i.e. ignore anything beyond that point).
+ * Search for the last exactly matching name in an attribute list
*/
-static char *reverse_strstr(const char *searched, const char *search_for,
- const char *searched_start)
+static int reverse_name_search(const char *searched, const char *search_for,
+ const char **result)
{
- char *result = NULL;
+ int result_size = 0;
+ const char *cur_searched = searched;
+
+ if (result)
+ *result = NULL;
if (*search_for == '\0')
return (char *)searched;
for (;;) {
- char *match = strstr(searched, search_for);
-
- /*
-* Stop looking if no new match is found or looking past the
-* searched_start pointer
-*/
- if (match == NULL || (searched_start != NULL
- match + strlen(search_for) searched_start))
+ const char *match = strstr(cur_searched, search_for);
+ const char *prevch;
+ const char *nextch;
+
+ /* Stop looking if no new match is found */
+ if (match == NULL)
break;
- result = match;
- searched = match + 1;
+ prevch = match - 1;
+ nextch = match + strlen(search_for);
+
+ /* Skip spaces */
+ while (*prevch == ' ')
+ prevch--;
+ while (*nextch == ' ')
+ nextch++;
+
+ /* Start looking past the current match so last is found */
+ cur_searched = match + 1;
+
+ /* Check for an exact match */
+ if (match != searched
+ *prevch != ENV_ATTR_LIST_DELIM)
+ continue;
+ if (*nextch != ENV_ATTR_SEP
+ *nextch != ENV_ATTR_LIST_DELIM
+ *nextch != '\0')
+ continue;
+
+ *result = match;
+ result_size = strlen(search_for);
}
- return result;
+ return result_size;
}
/*
@@ -145,6 +167,7 @@ static char *reverse_strstr(const char *searched, const
char *search_for,
int env_attr_lookup(const char *attr_list, const char *name, char
*attributes)
{
const char *entry = NULL;
+ int entry_len;
if (!attributes)
/* bad parameter */
@@ -153,32 +176,12 @@ int env_attr_lookup(const char *attr_list, const char
*name, char *attributes)
/* list not found */
return -EINVAL;
- entry = reverse_strstr(attr_list, name, NULL);
- while (entry != NULL) {
- const char *prevch = entry - 1;
- const char *nextch = entry + strlen(name);
-
- /* Skip spaces */
- while (*prevch == ' ')
- prevch--;
- while (*nextch == ' ')
- nextch++;
-
- /* check for an exact match */
- if ((entry == attr_list ||
-*prevch == ENV_ATTR_LIST_DELIM)
- (*nextch == ENV_ATTR_SEP ||
-*nextch == ENV_ATTR_LIST_DELIM ||
-*nextch == '\0'))
- break;
-
- entry = reverse_strstr(attr_list, name, entry);
- }
+ entry_len = reverse_name_search(attr_list, name, entry);
if (entry != NULL) {
int len;
/* skip the name */
- entry += strlen(name);
+ entry += entry_len;
/* skip spaces */
while (*entry == ' ')
entry++;
--
1.7.11.5
Regards,
Simon
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Re: [U-Boot] [PATCH] Add bootscript support to esbc_validate.
On 03/10/2015 01:38 AM, Gaurav Rana wrote: 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ setenv bs_hdraddr 0xe8e0; \ esbc_validate $bs_hdraddr;\ source $img_addr; \ esbc_halt; #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Gaurav Rana gaurav.r...@freescale.com --- Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2][v2] pci/layerscape: remove unnecessary pcie_layerscape.h
On 03/11/2015 07:58 PM, Minghuan Lian wrote: The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian minghuan.l...@freescale.com --- change log: v1-v2: remove unnecessary pcie_layerscape.h Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: am437x: mux: Update mux names
On Thu, Apr 02, 2015 at 10:57:07AM +0200, Bryan De Faria wrote: Correct and complete the mux names following AM437x Technical Reference Manual. Signed-off-by: Bryan De Faria bdefaria-...@adeneo-embedded.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] m68k: add architecture-specific u-boot.lds
On Sun, Mar 29, 2015 at 10:54:16PM +0200, ang...@sysam.it wrote: Add architecture-specific u-boot.lds and remove all board-specific u-boot.lds. All the .text customization that was board-specific have been moved inside the related include/configs, inside a LDS_BOARD_TEXT define. Signed-off-by: Angelo Dureghello ang...@sysam.it Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers/net/e1000.c: Cleanup whitespace
On 03/19/2015 10:16 AM, Joe Hershberger wrote: On Thu, Mar 19, 2015 at 11:43 AM, York Sun york...@freescale.com mailto:york...@freescale.com wrote: From: Minghuan Lian minghuan.l...@freescale.com mailto:minghuan.l...@freescale.com The patch removes unnecessary whitespace to fix checkpatch's warning: unnecessary whitespace before a quoted newline Signed-off-by: Minghuan Lian minghuan.l...@freescale.com mailto:minghuan.l...@freescale.com CC: Joe Hershberger joe.hershber...@ni.com mailto:joe.hershber...@ni.com Acked-by: Joe Hershberger joe.hershber...@ni.com mailto:joe.hershber...@ni.com Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ls102xa: ddr4: Use LPUART as console output to verify DCU driver
On 03/09/2015 02:23 AM, Alison Wang wrote: On QDS board with DDR4 DIMM, LPUART is used as console output to verify DCU driver. This patch adds ls1021aqds_ddr4_nor_lpuart_defconfig for this support. Signed-off-by: Alison Wang alison.w...@freescale.com --- Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4, 3/3] fastboot: ARM: OMAP5: Enable reboot-bootloader
On Fri, Mar 27, 2015 at 11:06:57PM +0530, Dileep Katta wrote: Implemented fb_set_reboot_flag() for OMAP5 to set an environment variable 'dofastboot' when reboot-bootloader called. This environment variable will be checked in boot command and fastboot will be called if the variable is set. If the bootcmd env variable of OMAP5 common is overwritten with board-specific command, then these changes will not apply. This was originally intended for DRA7 platform, but now applies to all OMAP5. Ref: http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=19da2e436e9806259cf1f4988b9e046ab256bf2c Signed-off-by: Angela Stegmaier angelaba...@ti.com Signed-off-by: Dileep Katta dileep.ka...@linaro.org Reviewed-by: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post-relocation
Shaohui, Thanks for confirmation. Please reply with your Test-by or Acked-by signature. The signature will be capture when the patch is applied. York On 04/23/2015 08:01 PM, Xie Shaohui-B21989 wrote: Tested on T4240QDS_NAND and T4240QDS_SDCARD, the hang issue fixed. Thanks! Best Regards, Shaohui Xie -Original Message- From: Wood Scott-B07421 Sent: Friday, April 24, 2015 9:02 AM To: u-boot@lists.denx.de; Sun York-R58495 Cc: Wood Scott-B07421; Alexander Graf; Xie Shaohui-B21989 Subject: [PATCH] powerpc/mpc85xx: Use GOT when loading IVORs post- relocation Commit 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors) simplified IVOR initialization a bit too much, failing to use the post- relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post- relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb952bb (powerpc/mpc85xx: Don't relocate exception vectors) Signed-off-by: Scott Wood scottw...@freescale.com Cc: Alexander Graf ag...@suse.de Cc: Shaohui Xie shaohui@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S | 35 -- - 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 28f04ee..e61d8e0 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1664,41 +1664,46 @@ clear_bss: */ .globl trap_init trap_init: +mflrr11 +bl _GLOBAL_OFFSET_TABLE_-4 +mflrr12 + /* Update IVORs as per relocation */ mtspr IVPR,r3 -li r4,CriticalInput@l +lwz r4,CriticalInput@got(r12) mtspr IVOR0,r4/* 0: Critical input */ -li r4,MachineCheck@l +lwz r4,MachineCheck@got(r12) mtspr IVOR1,r4/* 1: Machine check */ -li r4,DataStorage@l +lwz r4,DataStorage@got(r12) mtspr IVOR2,r4/* 2: Data storage */ -li r4,InstStorage@l +lwz r4,InstStorage@got(r12) mtspr IVOR3,r4/* 3: Instruction storage */ -li r4,ExtInterrupt@l +lwz r4,ExtInterrupt@got(r12) mtspr IVOR4,r4/* 4: External interrupt */ -li r4,Alignment@l +lwz r4,Alignment@got(r12) mtspr IVOR5,r4/* 5: Alignment */ -li r4,ProgramCheck@l +lwz r4,ProgramCheck@got(r12) mtspr IVOR6,r4/* 6: Program check */ -li r4,FPUnavailable@l +lwz r4,FPUnavailable@got(r12) mtspr IVOR7,r4/* 7: floating point unavailable */ -li r4,SystemCall@l +lwz r4,SystemCall@got(r12) mtspr IVOR8,r4/* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ -li r4,Decrementer@l +lwz r4,Decrementer@got(r12) mtspr IVOR10,r4 /* 10: Decrementer */ -li r4,IntervalTimer@l +lwz r4,IntervalTimer@got(r12) mtspr IVOR11,r4 /* 11: Interval timer */ -li r4,WatchdogTimer@l +lwz r4,WatchdogTimer@got(r12) mtspr IVOR12,r4 /* 12: Watchdog timer */ -li r4,DataTLBError@l +lwz r4,DataTLBError@got(r12) mtspr IVOR13,r4 /* 13: Data TLB error */ -li r4,InstructionTLBError@l +lwz r4,InstructionTLBError@got(r12) mtspr IVOR14,r4 /* 14: Instruction TLB error */ -li r4,DebugBreakpoint@l +lwz r4,DebugBreakpoint@got(r12) mtspr IVOR15,r4 /* 15: Debug */ +mtlrr11 blr .globl unlock_ram_in_cache -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] QE/DeepSleep: add QE deepsleep support for arm
On 04/07/2015 12:09 AM, Zhao Qiang wrote: Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang b45...@freescale.com --- Applied to fsl-qoriq master, awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] pci: Option rom class is a 24-bit number
We should pass a u32 class number to pci_rom_probe() instead of a u16.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/pci/pci_rom.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 48c0a77..49c118d 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -67,6 +67,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
struct pci_rom_data *rom_data;
u16 vendor, device;
u16 rom_vendor, rom_device;
+ u32 rom_class;
u32 vendev;
u32 mapped_vendev;
u32 rom_address;
@@ -125,13 +126,13 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
/* Continue anyway */
}
- debug(PCI ROM image, Class Code %04x%02x, Code Type %02x\n,
- rom_data-class_hi, rom_data-class_lo, rom_data-type);
+ rom_class = (le16_to_cpu(rom_data-class_hi) 8) | rom_data-class_lo;
+ debug(PCI ROM image, Class Code %06x, Code Type %02x\n,
+ rom_class, rom_data-type);
- if (class != ((rom_data-class_hi 8) | rom_data-class_lo)) {
- debug(Class Code mismatch ROM %08x, dev %08x\n,
- (rom_data-class_hi 8) | rom_data-class_lo,
- class);
+ if (class != rom_class) {
+ debug(Class Code mismatch ROM %06x, dev %06x\n,
+ rom_class, class);
}
*hdrp = rom_header;
@@ -232,17 +233,18 @@ int pci_run_vga_bios(pci_dev_t dev, int
(*int15_handler)(void), int exec_method)
{
struct pci_rom_header *rom, *ram;
int vesa_mode = -1;
- uint16_t class;
+ uint class;
bool emulate;
int ret;
/* Only execute VGA ROMs */
- pci_read_config_word(dev, PCI_CLASS_DEVICE, class);
- if ((class ^ PCI_CLASS_DISPLAY_VGA) 0xff00) {
+ pci_read_config_dword(dev, PCI_REVISION_ID, class);
+ if (((class 16) ^ PCI_CLASS_DISPLAY_VGA) 0xff00) {
debug(%s: Class %#x, should be %#x\n, __func__, class,
PCI_CLASS_DISPLAY_VGA);
return -ENODEV;
}
+ class = 8;
if (!should_load_oprom(dev))
return -ENXIO;
--
1.8.2.1
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[U-Boot] [PATCH 2/3] pci: Remove parameter 'class' of pci_rom_load()
pci_rom_load() does not use its parameter 'class', so remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/pci/pci_rom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 49c118d..37450c8 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -139,7 +139,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
return 0;
}
-int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
+int pci_rom_load(struct pci_rom_header *rom_header,
struct pci_rom_header **ram_headerp)
{
struct pci_rom_data *rom_data;
@@ -253,7 +253,7 @@ int pci_run_vga_bios(pci_dev_t dev, int
(*int15_handler)(void), int exec_method)
if (ret)
return ret;
- ret = pci_rom_load(class, rom, ram);
+ ret = pci_rom_load(rom, ram);
if (ret)
return ret;
--
1.8.2.1
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Re: [U-Boot] rtc: Set valid date after reset
On Fri, Apr 10, 2015 at 01:11:54AM +0200, Marek Vasut wrote: Some RTC chips tend to set garbage date after reset. This patch sets the date to 2000-01-01 00:00 immediatelly after the RTC chip reset is issued using the date reset command. Signed-off-by: Marek Vasut ma...@denx.de Cc: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 21/21] sunxi: emac: Remove non device-model code
All sunxi boards now use the device-model, so remove the non device-model
code.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 12 ---
drivers/net/sunxi_emac.c | 69
include/netdev.h | 1 -
3 files changed, 82 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index cde13ef..f0d87a8 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -12,10 +12,6 @@
#include common.h
#include i2c.h
-#ifndef CONFIG_DM_ETH
-#include netdev.h
-#endif
-#include miiphy.h
#include serial.h
#ifdef CONFIG_SPL_BUILD
#include spl.h
@@ -226,14 +222,6 @@ int cpu_eth_init(bd_t *bis)
mdelay(200);
#endif
-#if defined CONFIG_SUNXI_EMAC !defined CONFIG_DM_ETH
- rc = sunxi_emac_initialize(bis);
- if (rc 0) {
- printf(sunxi: failed to initialize emac\n);
- return rc;
- }
-#endif
-
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);
if (rc 0) {
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index a9efe11..5d4faf4 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -513,74 +513,6 @@ static void sunxi_emac_board_setup(struct emac_eth_dev
*priv)
clrsetbits_le32(regs-mac_mcfg, 0xf 2, 0xd 2);
}
-#ifndef CONFIG_DM_ETH
-static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bis)
-{
- return _sunxi_emac_eth_init(dev-priv, dev-enetaddr);
-}
-
-static void sunxi_emac_eth_halt(struct eth_device *dev)
-{
- /* Nothing to do here */
-}
-
-static int sunxi_emac_eth_recv(struct eth_device *dev)
-{
- int rx_len;
-
- rx_len = _sunxi_emac_eth_recv(dev-priv, net_rx_packets[0]);
- if (rx_len = 0)
- return 0;
-
- /* Pass to upper layer */
- net_process_received_packet(net_rx_packets[0], rx_len);
-
- return rx_len;
-}
-
-static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int
length)
-{
- return _sunxi_emac_eth_send(dev-priv, packet, length);
-}
-
-int sunxi_emac_initialize(void)
-{
- struct emac_regs *regs =
- (struct emac_regs *)SUNXI_EMAC_BASE;
- struct eth_device *dev;
- struct emac_eth_dev *priv;
-
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(struct emac_eth_dev));
-
- priv-regs = regs;
- dev-iobase = (int)regs;
- dev-priv = priv;
- dev-init = sunxi_emac_eth_init;
- dev-halt = sunxi_emac_eth_halt;
- dev-send = sunxi_emac_eth_send;
- dev-recv = sunxi_emac_eth_recv;
- strcpy(dev-name, emac);
-
- sunxi_emac_board_setup(priv);
-
- eth_register(dev);
-
- return sunxi_emac_init_phy(priv, dev);
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int sunxi_emac_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -653,4 +585,3 @@ U_BOOT_DRIVER(eth_sunxi_emac) = {
.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
-#endif
diff --git a/include/netdev.h b/include/netdev.h
index e6bdfdf..662d173 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -80,7 +80,6 @@ int sh_eth_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc9_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
-int sunxi_emac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
--
2.3.5
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Re: [U-Boot] [PATCH 11/21] sunxi: gpio: Add support for AXP gpios to the dm gpio code
Hi, On 24-04-15 15:48, Hans de Goede wrote: snip @@ -222,7 +266,7 @@ static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset, struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); u32 num = GPIO_NUM(offset); - clrsetbits_le32(plat-regs-dat, 1 num, value ? (1 num) : 0); +; clrsetbits_le32(plat-regs-dat, 1 num, value ? (1 num) : 0); return 0; } No idea how that got in there, dropped in my personal tree. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: omap3: Fix timeout handling
On 7 April 2015 at 05:55, Tom Rini tr...@konsulko.com wrote:
On Wed, Apr 01, 2015 at 04:21:50PM +0100, Andy Pont wrote:
Hi David,
snipped for brevity
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-
slave.cs].chstat));
return -1;
I have a couple of questions...
Firstly, when in SPL is there access to the get_timer() function?
We call timer_init() from board_init_r() in SPL, prior to diving down
into loading (or checking for Falcon vs Regular) so this is safe.
Secondly, when using Falcon mode to load Linux directly from SPI (Falcon
mode) then we want to maximise the throughput and save every CPU cycle we
possibly can. Adding yet another function call into the for loop and hence
calling it a couple of million times seems, on the face of it, like it is
going to slow things down.
I'd like to see measurements to prove me wrong but this both seems like
a bad idea (optimizing by being incorrect, this gives us a correct
timeout check like other drivers do) and really unlikely I would think
to be noticable. Since we'll be doing the same code-paths in both
regular and SPL, trying to time things (by loading a big file) would be
easy enough I think. Thanks!
Ping
thanks!
--
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[U-Boot] [PATCH v2 3/4] x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).
We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/Kconfig| 31
arch/x86/include/asm/pirq_routing.h | 139
arch/x86/lib/Makefile | 1 +
arch/x86/lib/pirq_routing.c | 129 +
4 files changed, 300 insertions(+)
create mode 100644 arch/x86/include/asm/pirq_routing.h
create mode 100644 arch/x86/lib/pirq_routing.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3f1401a..aaceaef 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -442,6 +442,37 @@ config TSC_FREQ_IN_MHZ
help
The running frequency in MHz of Time-Stamp Counter (TSC).
+menu System tables
+
+config GENERATE_PIRQ_TABLE
+ bool Generate a PIRQ table
+ default n
+ help
+ Generate a PIRQ routing table for this board. The PIRQ routing table
+ is generated by U-Boot in the system memory from 0xf to 0xf
+ at every 16-byte boundary with a PCI IRQ routing signature ($PIR).
+ It specifies the interrupt router information as well how all the PCI
+ devices' interrupt pins are wired to PIRQs.
+
+endmenu
+
+config MAX_PIRQ_LINKS
+ int
+ default 8
+ help
+ This variable specifies the number of PIRQ interrupt links which are
+ routable. On most older chipsets, this is 4, PIRQA through PIRQD.
+ Some newer chipsets offer more than four links, commonly up to PIRQH.
+
+config IRQ_SLOT_COUNT
+ int
+ default 128
+ help
+ U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
+ which in turns forms a table of exact 4KiB. The default value 128
+ should be enough for most boards. If this does not fit your board,
+ change it according to your needs.
+
source board/coreboot/coreboot/Kconfig
source board/google/chromebook_link/Kconfig
diff --git a/arch/x86/include/asm/pirq_routing.h
b/arch/x86/include/asm/pirq_routing.h
new file mode 100644
index 000..ddc08e1
--- /dev/null
+++ b/arch/x86/include/asm/pirq_routing.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2015, Bin Meng bmeng...@gmail.com
+ *
+ * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _PIRQ_ROUTING_H_
+#define _PIRQ_ROUTING_H_
+
+/*
+ * This is the maximum number on interrupt entries that a PCI device may have.
+ * This is NOT the number of slots or devices in the system
+ * This is NOT the number of entries in the PIRQ table
+ *
+ * This tells us that in the PIRQ table, we are going to have 4 link-bitmap
+ * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
+ *
+ * CAUTION: If you change this, PIRQ routing will not work correctly.
+ */
+#define MAX_INTX_ENTRIES 4
+
+#define PIRQ_SIGNATURE \
+ (('$' 0) + ('P' 8) + ('I' 16) + ('R' 24))
+#define PIRQ_VERSION 0x0100
+
+struct __packed irq_info {
+ u8 bus; /* Bus number */
+ u8 devfn; /* Device and function number */
+ struct __packed {
+ u8 link;/* IRQ line ID, 0=not routed */
+ u16 bitmap; /* Available IRQs */
+ } irq[MAX_INTX_ENTRIES];
+ u8 slot;/* Slot number, 0=onboard */
+ u8 rfu;
+};
+
+struct __packed irq_routing_table {
+ u32 signature; /* PIRQ_SIGNATURE */
+ u16 version;/* PIRQ_VERSION */
+ u16 size; /* Table size in bytes */
+ u8 rtr_bus; /* busno of the interrupt router */
+ u8 rtr_devfn; /* devfn of the interrupt router */
+ u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
+ u16 rtr_vendor; /* Vendor ID of the interrupt router */
+ u16 rtr_device; /* Device ID of the interrupt router */
+ u32 miniport_data;
+ u8 rfu[11];
+ u8 checksum;/* Modulo 256 checksum must give zero */
+ struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
+};
+
+/**
+ * get_irq_slot_count() - Get the number of entries in the irq_info table
+ *
+ * This calculates the number of entries for the irq_info table.
+ *
+ * @rt:pointer to the base address of the struct irq_info
+ * @return:number of entries
+ */
+static inline int get_irq_slot_count(struct irq_routing_table *rt)
+{
+ return (rt-size - 32) / sizeof(struct
[U-Boot] [PATCH 08/21] sunxi: gpio: Add compatible strings for all supported SoCs
We want to use device-model/fdt with other model SoCs too, so add
compatible strings for the other SoCs to the dm sunxi gpio code.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/gpio/sunxi_gpio.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 89209df..e6a90b9 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -322,7 +322,14 @@ static int gpio_sunxi_bind(struct udevice *parent)
}
static const struct udevice_id sunxi_gpio_ids[] = {
+ { .compatible = allwinner,sun4i-a10-pinctrl },
+ { .compatible = allwinner,sun5i-a10s-pinctrl },
+ { .compatible = allwinner,sun5i-a13-pinctrl },
+ { .compatible = allwinner,sun6i-a31-pinctrl },
+ { .compatible = allwinner,sun6i-a31s-pinctrl },
{ .compatible = allwinner,sun7i-a20-pinctrl },
+ { .compatible = allwinner,sun8i-a23-pinctrl },
+ { .compatible = allwinner,sun9i-a80-pinctrl },
{ }
};
--
2.3.5
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[U-Boot] [PATCH 03/21] sunxi: usbc: Fix vbus gpio handling to work with the device-model
The device-model gpio functions may return another value then -1 as error,
make the sunxi usbc properly handle this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/usbc.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 515549d..39452a7 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -17,6 +17,7 @@
#include asm/gpio.h
#include asm/io.h
#include common.h
+#include errno.h
#ifdef CONFIG_AXP152_POWER
#include axp152.h
#endif
@@ -90,7 +91,7 @@ static int get_vbus_gpio(int index)
case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
}
- return -1;
+ return -EINVAL;
}
static int get_vbus_detect_gpio(int index)
@@ -187,13 +188,13 @@ int sunxi_usbc_request_resources(int index)
int ret = 0;
sunxi_usbc-gpio_vbus = get_vbus_gpio(index);
- if (sunxi_usbc-gpio_vbus != -1) {
+ if (sunxi_usbc-gpio_vbus = 0) {
ret |= gpio_request(sunxi_usbc-gpio_vbus, usbc_vbus);
ret |= gpio_direction_output(sunxi_usbc-gpio_vbus, 0);
}
sunxi_usbc-gpio_vbus_det = get_vbus_detect_gpio(index);
- if (sunxi_usbc-gpio_vbus_det != -1) {
+ if (sunxi_usbc-gpio_vbus_det = 0) {
ret |= gpio_request(sunxi_usbc-gpio_vbus_det, usbc_vbus_det);
ret |= gpio_direction_input(sunxi_usbc-gpio_vbus_det);
}
@@ -206,10 +207,10 @@ int sunxi_usbc_free_resources(int index)
struct sunxi_usbc_hcd *sunxi_usbc = sunxi_usbc_hcd[index];
int ret = 0;
- if (sunxi_usbc-gpio_vbus != -1)
+ if (sunxi_usbc-gpio_vbus = 0)
ret |= gpio_free(sunxi_usbc-gpio_vbus);
- if (sunxi_usbc-gpio_vbus_det != -1)
+ if (sunxi_usbc-gpio_vbus_det = 0)
ret |= gpio_free(sunxi_usbc-gpio_vbus_det);
return ret;
@@ -263,7 +264,7 @@ void sunxi_usbc_vbus_enable(int index)
{
struct sunxi_usbc_hcd *sunxi_usbc = sunxi_usbc_hcd[index];
- if (sunxi_usbc-gpio_vbus != -1)
+ if (sunxi_usbc-gpio_vbus = 0)
gpio_set_value(sunxi_usbc-gpio_vbus, 1);
}
@@ -271,7 +272,7 @@ void sunxi_usbc_vbus_disable(int index)
{
struct sunxi_usbc_hcd *sunxi_usbc = sunxi_usbc_hcd[index];
- if (sunxi_usbc-gpio_vbus != -1)
+ if (sunxi_usbc-gpio_vbus = 0)
gpio_set_value(sunxi_usbc-gpio_vbus, 0);
}
@@ -280,9 +281,9 @@ int sunxi_usbc_vbus_detect(int index)
struct sunxi_usbc_hcd *sunxi_usbc = sunxi_usbc_hcd[index];
int err, retries = 3;
- if (sunxi_usbc-gpio_vbus_det == -1) {
+ if (sunxi_usbc-gpio_vbus_det 0) {
eprintf(Error: invalid vbus detection pin\n);
- return -1;
+ return sunxi_usbc-gpio_vbus_det;
}
err = gpio_get_value(sunxi_usbc-gpio_vbus_det);
--
2.3.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Correct a typo in the commit message
- Use a local variable in fill_irq_info()
- Print a debug message if creating pirq table fails
- Use a C structure for RCBA register access
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/irq.c | 242 +++
arch/x86/cpu/queensbay/tnc.c | 10 +-
arch/x86/include/asm/arch-queensbay/device.h | 94 +++
arch/x86/include/asm/arch-queensbay/irq.h| 55 ++
arch/x86/include/asm/arch-queensbay/tnc.h| 39 -
arch/x86/include/asm/u-boot-x86.h| 2 +
configs/crownbay_defconfig | 1 +
include/configs/crownbay.h | 1 +
9 files changed, 442 insertions(+), 4 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/irq.c
create mode 100644 arch/x86/include/asm/arch-queensbay/device.h
create mode 100644 arch/x86/include/asm/arch-queensbay/irq.h
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index d8761fd..4599a48 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,5 +5,5 @@
#
obj-y += fsp_configs.o
-obj-y += tnc.o topcliff.o
+obj-y += irq.o tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644
index 000..faf9515
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2015, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include malloc.h
+#include asm/io.h
+#include asm/pci.h
+#include asm/post.h
+#include asm/processor.h
+#include asm/pirq_routing.h
+#include asm/arch/device.h
+#include asm/arch/tnc.h
+#include asm/arch/irq.h
+
+static struct irq_routing_table *pirq_routing_table;
+
+bool pirq_check_irq_routed(int link, u8 irq)
+{
+ u8 pirq;
+
+ pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
+ pirq = 0xf;
+
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (pirq 3 || pirq == 8 || pirq == 13)
+ return false;
+
+ return pirq == irq ? true : false;
+}
+
+int pirq_translate_link(int link)
+{
+ return LINK_V2N(link);
+}
+
+void pirq_assign_irq(int link, u8 irq)
+{
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (irq 3 || irq == 8 || irq == 13)
+ return;
+
+ x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
+}
+
+static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
+u8 device, u8 func, u8 pin, u8 pirq)
+{
+ struct irq_info *slot = *slotp;
+
+ slot-bus = bus;
+ slot-devfn = (device 3) | func;
+ slot-irq[pin - 1].link = LINK_N2V(pirq);
+ slot-irq[pin - 1].bitmap = PIRQ_BITMAP;
+ (*entries)++;
+ (*slotp)++;
+}
+
+/* PCIe port downstream INTx swizzle */
+static inline u8 pin_swizzle(u8 pin, int port)
+{
+ return (pin + port) % 4;
+}
+
+__weak int board_fill_irq_info(struct irq_info *slot)
+{
+ return 0;
+}
+
+static int create_pirq_routing_table(void)
+{
+ struct irq_routing_table *rt;
+ struct irq_info *slot;
+ int irq_entries = 0;
+ pci_dev_t tcf_bdf;
+ u8 tcf_bus, bus;
+ int i;
+
+ rt = malloc(sizeof(struct irq_routing_table));
+ if (!rt)
+ return -ENOMEM;
+ memset((char *)rt, 0, sizeof(struct irq_routing_table));
+
+ /* Populate the PIRQ table fields */
+ rt-signature = PIRQ_SIGNATURE;
+ rt-version = PIRQ_VERSION;
+ rt-rtr_bus = 0;
+ rt-rtr_devfn = (TNC_LPC_DEV 3) | TNC_LPC_FUNC;
+ rt-rtr_vendor = PCI_VENDOR_ID_INTEL;
+ rt-rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
+
+ slot = rt-slots;
+
+ /*
+* Now fill in the irq_info entries in the PIRQ table
+*
+* We start from internal TunnelCreek PCI devices first, then
+* followed by all the 4 PCIe ports downstream devices, including
+* the Queensbay platform Topcliff chipset devices.
+*/
+ fill_irq_info(slot, irq_entries, 0, TNC_IGD_DEV,
+ TNC_IGD_FUNC, INTA, PIRQE);
+ fill_irq_info(slot, irq_entries, 0, TNC_SDVO_DEV,
+ TNC_SDVO_FUNC, INTA, PIRQF);
+ fill_irq_info(slot, irq_entries, 0, TNC_HDA_DEV,
+ TNC_HDA_FUNC, INTA, PIRQG);
+ fill_irq_info(slot, irq_entries, 0, TNC_PCIE0_DEV,
+ TNC_PCIE0_FUNC, INTA, PIRQE);
+ fill_irq_info(slot, irq_entries, 0, TNC_PCIE1_DEV,
+ TNC_PCIE1_FUNC, INTA, PIRQF);
+ fill_irq_info(slot, irq_entries, 0, TNC_PCIE2_DEV,
+ TNC_PCIE2_FUNC, INTA, PIRQG);
+ fill_irq_info(slot,
Re: [U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
Hi Simon,
On 04/23/2015 08:35 PM, Simon Glass wrote:
Hi,
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote:
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
Make sure you use tabs for indenting here.
You should create a binding file to describe your binding - in
doc/device-tree-bindings.
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
Comments on the above
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
Can you make the mask value an actual valid mask, like:
+#define IOPAD_PULL_ASSIGN_MASK (0x3 IOPAD_PULL_ASSIGN_SHIFT)
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
Can you reorder the functions to avoid the need for these forward
declarations? Also only one underscore prefix please.
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
Can the base come
Re: [U-Boot] [PATCH v5 2/3] mtd, nand: move common functions from cmd_nand.c to common place
Hello Scott, Am 23.04.2015 19:48, schrieb Scott Wood: On Thu, 2015-04-23 at 13:12 +0200, Heiko Schocher wrote: Hello Scott, Am 23.04.2015 08:55, schrieb Scott Wood: On Thu, 2015-04-23 at 07:57 +0200, Heiko Schocher wrote: Hello Scott, Am 23.04.2015 00:47, schrieb Scott Wood: On Mon, 2015-04-20 at 07:47 +0200, Heiko Schocher wrote: +int str2off(const char *p, loff_t *num); +int str2long(const char *p, ulong *num); These should be moved somewhere more generic, especially if they're no longer file-local. Hmm... the code is currently in drivers/mtd/mtd_uboot.c ... maybe we add a mtd_ prefix to them? I think these functions are mtd specific ... What is mtd-specific about them? Hmm... I thought: return *p != '\0' *endptr == '\0'; is more or less mtd specific ... but you are right, it is not really mtd specific ... so I move them to ./lib/vsprintf.c ... Ok? OK. Maybe change the return to bool while you're at it, to make it clear that it isn't return-zero-on-success. Hmm.. tried this, but I get: CC common/cmd_test.o In file included from /home/hs/abb/imx6/u-boot/include/common.h:760:0, from /home/hs/abb/imx6/u-boot/common/cmd_test.c:17: /home/hs/abb/imx6/u-boot/include/vsprintf.h:176:1: error: unknown type name 'bool' /home/hs/abb/imx6/u-boot/include/vsprintf.h:177:1: error: unknown type name 'bool' /home/hs/abb/imx6/u-boot/scripts/Makefile.build:276: recipe for target 'common/cmd_test.o' failed make[2]: *** [common/cmd_test.o] Error 1 /home/hs/abb/imx6/u-boot/Makefile:1156: recipe for target 'common' failed make[1]: *** [common] Error 2 reason is in common/cmd_test.c: /* * Define _STDBOOL_H here to avoid macro expansion of true and false. * If the future code requires macro true or false, remove this define * and undef true and false before U_BOOT_CMD. This define and comment * shall be removed if change to U_BOOT_CMD is made to take string * instead of stringifying it. */ #define _STDBOOL_H #include common.h Hmm... I tend to say, this is another patch changing the returntype from int to bool ... bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
On 04/23/2015 08:14 PM, Bin Meng wrote:
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
I guess the prefix 'ich6' is debatable.
I hesitated with 'x86' but I'm open to any suggestion.
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
return -ENODEV;
}
@@ -135,7 +146,138 @@ static int
Re: [U-Boot] [PATCH 01/21] sunxi: Do not build i2c support when we've no i2c controllers
Hi Hans, On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote: This fixes the following errors being printed during boot: Error, wrong i2c adapter 0 max 0 possible Error, wrong i2c adapter 0 max 0 possible Signed-off-by: Hans de Goede hdego...@redhat.com Where does the error come from? Reviewed-by: Simon Glass s...@chromium.org --- include/configs/sunxi-common.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 3e49aba..f97e626 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -261,14 +261,15 @@ #define CONFIG_SPL_I2C_SUPPORT #endif -#define CONFIG_SYS_I2C #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ defined CONFIG_I2C4_ENABLE +#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#endif #define CONFIG_SYS_I2C_SPEED 40 #define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_CMD_I2C +#endif #if defined CONFIG_VIDEO_LCD_PANEL_I2C !(defined CONFIG_SPL_BUILD) #define CONFIG_SYS_I2C_SOFT @@ -288,8 +289,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ #endif -#define CONFIG_CMD_I2C - /* PMU */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER #define CONFIG_SPL_POWER_SUPPORT -- 2.3.5 Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/21] sunxi: gpio: Change axp_gpio_foo prototype to match gpio uclass ops
Hi Hans,
On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote:
Change the axp_gpio_foo function prototypes to match the gpio uclass op
prototypes, so that they can be used directly when adding device-model
support for the axp gpios.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/gpio/sunxi_gpio.c | 8
drivers/power/axp209.c| 10 +-
drivers/power/axp221.c| 10 +-
include/axp209.h | 10 ++
include/axp221.h | 10 ++
5 files changed, 26 insertions(+), 22 deletions(-)
This AXP think should be a separate GPIO driver.
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 91af1a5..0774b70 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -81,7 +81,7 @@ int gpio_direction_input(unsigned gpio)
{
#ifdef AXP_GPIO
if (gpio = SUNXI_GPIO_AXP0_START)
- return axp_gpio_direction_input(gpio - SUNXI_GPIO_AXP0_START);
+ return axp_gpio_direction_input(NULL, gpio -
SUNXI_GPIO_AXP0_START);
#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
@@ -92,7 +92,7 @@ int gpio_direction_output(unsigned gpio, int value)
{
#ifdef AXP_GPIO
if (gpio = SUNXI_GPIO_AXP0_START)
- return axp_gpio_direction_output(gpio - SUNXI_GPIO_AXP0_START,
+ return axp_gpio_direction_output(NULL, gpio -
SUNXI_GPIO_AXP0_START,
value);
#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
@@ -104,7 +104,7 @@ int gpio_get_value(unsigned gpio)
{
#ifdef AXP_GPIO
if (gpio = SUNXI_GPIO_AXP0_START)
- return axp_gpio_get_value(gpio - SUNXI_GPIO_AXP0_START);
+ return axp_gpio_get_value(NULL, gpio - SUNXI_GPIO_AXP0_START);
#endif
return sunxi_gpio_input(gpio);
}
@@ -113,7 +113,7 @@ int gpio_set_value(unsigned gpio, int value)
{
#ifdef AXP_GPIO
if (gpio = SUNXI_GPIO_AXP0_START)
- return axp_gpio_set_value(gpio - SUNXI_GPIO_AXP0_START,
value);
+ return axp_gpio_set_value(NULL, gpio - SUNXI_GPIO_AXP0_START,
value);
#endif
return sunxi_gpio_output(gpio, value);
}
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
index 1d7be49..98c214f 100644
--- a/drivers/power/axp209.c
+++ b/drivers/power/axp209.c
@@ -167,7 +167,7 @@ static u8 axp209_get_gpio_ctrl_reg(unsigned int pin)
return 0;
}
-int axp_gpio_direction_input(unsigned int pin)
+int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
{
if (pin == SUNXI_GPIO_AXP0_VBUS_DETECT)
return 0;
@@ -179,7 +179,7 @@ int axp_gpio_direction_input(unsigned int pin)
return axp209_write(reg, val);
}
-int axp_gpio_direction_output(unsigned int pin, unsigned int val)
+int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int val)
{
u8 reg = axp209_get_gpio_ctrl_reg(pin);
@@ -194,7 +194,7 @@ int axp_gpio_direction_output(unsigned int pin, unsigned
int val)
return axp209_write(reg, val);
}
-int axp_gpio_get_value(unsigned int pin)
+int axp_gpio_get_value(struct udevice *dev, unsigned pin)
{
u8 val, mask;
int rc;
@@ -215,7 +215,7 @@ int axp_gpio_get_value(unsigned int pin)
return (val mask) ? 1 : 0;
}
-int axp_gpio_set_value(unsigned int pin, unsigned int val)
+int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
{
- return axp_gpio_direction_output(pin, val);
+ return axp_gpio_direction_output(dev, pin, val);
}
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index dc3a7f1..4970ab4 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -386,7 +386,7 @@ int axp221_get_sid(unsigned int *sid)
return 0;
}
-int axp_gpio_direction_input(unsigned int pin)
+int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
{
switch (pin) {
case SUNXI_GPIO_AXP0_VBUS_DETECT:
@@ -396,7 +396,7 @@ int axp_gpio_direction_input(unsigned int pin)
}
}
-int axp_gpio_direction_output(unsigned int pin, unsigned int val)
+int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int val)
{
int ret;
@@ -407,13 +407,13 @@ int axp_gpio_direction_output(unsigned int pin,
unsigned int val)
if (ret)
return ret;
- return axp_gpio_set_value(pin, val);
+ return axp_gpio_set_value(dev, pin, val);
default:
return -EINVAL;
}
}
-int axp_gpio_get_value(unsigned int pin)
+int axp_gpio_get_value(struct udevice *dev, unsigned pin)
{
int ret;
u8 val;
@@ -430,7 +430,7 @@ int axp_gpio_get_value(unsigned int pin)
}
}
-int axp_gpio_set_value(unsigned int pin, unsigned int val)
+int axp_gpio_set_value(struct udevice *dev,
Re: [U-Boot] [PATCH 11/21] sunxi: gpio: Add support for AXP gpios to the dm gpio code
Hi Hans,
On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote:
This really should be part of the axp pmic driver, but that is not converted
yet to device-model, and the upstream kernel does not support axp gpios
yet so there is no devicetree binding for them yet.
So for now bolt on the axp gpio support to the SoC's own gpio support like
we've been doing for the non dm case. This allows boards using axp gpios
to be converted to dm.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++--
drivers/gpio/sunxi_gpio.c | 64
+-
2 files changed, 60 insertions(+), 10 deletions(-)
This doesn't seem like a good idea. The device tree binding is just an
I2C one isn't it? Is the real problem that you are trying to convert
to driver model without converting to device tree? For I2C at least,
that is not supported.
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index c9bfb4c..cbb3328 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -204,8 +204,10 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_VBUS_DETECT8
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE9
+#define SUNXI_GPIO_AXP0_PREFIX AXP0-
+#define SUNXI_GPIO_AXP0_VBUS_DETECT4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32
val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 0774b70..38d72b7 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -126,7 +126,7 @@ int sunxi_name_to_gpio(const char *name)
char *eptr;
#ifdef AXP_GPIO
- if (strncasecmp(name, AXP0-, 5) == 0) {
+ if (strncasecmp(name, SUNXI_GPIO_AXP0_PREFIX, 5) == 0) {
name += 5;
if (strcmp(name, VBUS-DETECT) == 0)
return SUNXI_GPIO_AXP0_START +
@@ -172,12 +172,56 @@ int sunxi_name_to_gpio_bank(const char *name)
}
#ifdef CONFIG_DM_GPIO
+
+#ifdef AXP_GPIO
+/* FIXME this should be part of the axp drivers */
+static const struct dm_gpio_ops gpio_axp_ops = {
+ .direction_input= axp_gpio_direction_input,
+ .direction_output = axp_gpio_direction_output,
+ .get_value = axp_gpio_get_value,
+ .set_value = axp_gpio_set_value,
+};
+
+static int gpio_axp_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ /* Tell the uclass how many GPIOs we have */
+ uc_priv-bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
+ uc_priv-gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
+
+ return 0;
+}
+
+struct driver gpio_axp_driver = {
+ .name = gpio_axp,
+ .id = UCLASS_GPIO,
+ .ops= gpio_axp_ops,
+ .probe = gpio_axp_probe,
+};
+#endif
+
/* TODO(s...@chromium.org): Remove this function and use device tree */
int sunxi_name_to_gpio(const char *name)
{
unsigned int gpio;
int ret;
-
+#ifdef AXP_GPIO
+ char lookup[8];
+
+ if (strncasecmp(name, SUNXI_GPIO_AXP0_PREFIX, 5) == 0) {
+ int len = strlen(SUNXI_GPIO_AXP0_PREFIX);
+ if (strcmp(name + len, VBUS-DETECT) == 0) {
+ sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX %d,
+ SUNXI_GPIO_AXP0_VBUS_DETECT);
+ name = lookup;
+ } else if (strcmp(name + len, VBUS-ENABLE) == 0) {
+ sprintf(lookup, AXP0-%d\n,
+ SUNXI_GPIO_AXP0_VBUS_ENABLE);
+ name = lookup;
+ }
+ }
+#endif
ret = gpio_lookup_name(name, NULL, NULL, gpio);
return ret ? ret : gpio;
@@ -222,7 +266,7 @@ static int sunxi_gpio_set_value(struct udevice *dev,
unsigned offset,
struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
u32 num = GPIO_NUM(offset);
- clrsetbits_le32(plat-regs-dat, 1 num, value ? (1 num) : 0);
+; clrsetbits_le32(plat-regs-dat, 1 num, value ? (1 num) : 0);
return 0;
}
@@ -289,21 +333,19 @@ static int gpio_sunxi_probe(struct udevice *dev)
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
- struct sunxi_gpio_platdata *plat = parent-platdata;
+ struct sunxi_gpio_platdata *plat;
struct sunxi_gpio_reg *ctlr;
+ struct udevice *dev;
int bank;
int ret;
/* If this is a child device, there is nothing to do here */
- if (plat)
+ if (parent-platdata)
return 0;
ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd-fdt_blob,
Re: [U-Boot] [PATCH 15/21] sunxi: emac: Add device model support
Hi Hans,
On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote:
Modify the sunxi-emac eth driver to support device model.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 4 +-
drivers/net/sunxi_emac.c | 81
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
index 7e9cf11..cde13ef 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -12,7 +12,9 @@
#include common.h
#include i2c.h
+#ifndef CONFIG_DM_ETH
#include netdev.h
+#endif
#include miiphy.h
#include serial.h
#ifdef CONFIG_SPL_BUILD
@@ -224,7 +226,7 @@ int cpu_eth_init(bd_t *bis)
mdelay(200);
#endif
-#ifdef CONFIG_SUNXI_EMAC
+#if defined CONFIG_SUNXI_EMAC !defined CONFIG_DM_ETH
rc = sunxi_emac_initialize(bis);
if (rc 0) {
printf(sunxi: failed to initialize emac\n);
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 038f474..a9efe11 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -7,6 +7,7 @@
*/
#include common.h
+#include dm.h
#include linux/err.h
#include malloc.h
#include miiphy.h
@@ -160,6 +161,9 @@ struct emac_eth_dev {
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
+#ifdef CONFIG_DM_ETH
+ uchar rx_buf[DMA_CPU_TRRESHOLD];
THRESHOLD
Also does this need to be DMA-aligned? - e.g. DM_FLAG_ALLOC_PRIV_DMA
+#endif
};
struct emac_rxhdr {
@@ -509,6 +513,7 @@ static void sunxi_emac_board_setup(struct emac_eth_dev
*priv)
clrsetbits_le32(regs-mac_mcfg, 0xf 2, 0xd 2);
}
+#ifndef CONFIG_DM_ETH
static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bis)
{
return _sunxi_emac_eth_init(dev-priv, dev-enetaddr);
@@ -573,3 +578,79 @@ int sunxi_emac_initialize(void)
return sunxi_emac_init_phy(priv, dev);
}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int sunxi_emac_eth_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return _sunxi_emac_eth_init(dev-priv, pdata-enetaddr);
+}
+
+static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+
+ return _sunxi_emac_eth_send(priv, packet, length);
+}
+
+static int sunxi_emac_eth_recv(struct udevice *dev, uchar **packetp)
+{
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+ int rx_len;
+
+ rx_len = _sunxi_emac_eth_recv(priv, priv-rx_buf);
+ *packetp = priv-rx_buf;
+
+ return rx_len;
+}
+
+static void sunxi_emac_eth_stop(struct udevice *dev)
+{
+ /* Nothing to do here */
+}
+
+static int sunxi_emac_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+
+ priv-regs = (struct emac_regs *)pdata-iobase;
+ sunxi_emac_board_setup(priv);
+
+ return sunxi_emac_init_phy(priv, dev);
+}
+
+static const struct eth_ops sunxi_emac_eth_ops = {
+ .start = sunxi_emac_eth_start,
+ .send = sunxi_emac_eth_send,
+ .recv = sunxi_emac_eth_recv,
+ .stop = sunxi_emac_eth_stop,
+};
+
+static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ pdata-iobase = dev_get_addr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id sunxi_emac_eth_ids[] = {
+ { .compatible = allwinner,sun4i-a10-emac },
+ { }
+};
+
+U_BOOT_DRIVER(eth_sunxi_emac) = {
+ .name = eth_sunxi_emac,
+ .id = UCLASS_ETH,
+ .of_match = sunxi_emac_eth_ids,
+ .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
+ .probe = sunxi_emac_eth_probe,
+ .ops= sunxi_emac_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
--
2.3.5
Regards,
Simon
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Re: [U-Boot] [PATCH 08/21] sunxi: gpio: Add compatible strings for all supported SoCs
On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote:
We want to use device-model/fdt with other model SoCs too, so add
compatible strings for the other SoCs to the dm sunxi gpio code.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/gpio/sunxi_gpio.c | 7 +++
1 file changed, 7 insertions(+)
Reviewed-by: Simon Glass s...@chromium.org
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 89209df..e6a90b9 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -322,7 +322,14 @@ static int gpio_sunxi_bind(struct udevice *parent)
}
static const struct udevice_id sunxi_gpio_ids[] = {
+ { .compatible = allwinner,sun4i-a10-pinctrl },
+ { .compatible = allwinner,sun5i-a10s-pinctrl },
+ { .compatible = allwinner,sun5i-a13-pinctrl },
+ { .compatible = allwinner,sun6i-a31-pinctrl },
+ { .compatible = allwinner,sun6i-a31s-pinctrl },
{ .compatible = allwinner,sun7i-a20-pinctrl },
+ { .compatible = allwinner,sun8i-a23-pinctrl },
+ { .compatible = allwinner,sun9i-a80-pinctrl },
{ }
};
--
2.3.5
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Re: [U-Boot] [PATCH 20/21] sunxi: Move all boards to the device-model
On 24 April 2015 at 07:48, Hans de Goede hdego...@redhat.com wrote: Now that we've everything prepared for it remove the DM settings from the defconfig(s) and simply always set them for sunxi, so that all sunxi boards will allways use dm now. Signed-off-by: Hans de Goede hdego...@redhat.com --- arch/arm/Kconfig | 5 + board/sunxi/Kconfig| 12 configs/A20-OLinuXino-Lime2_defconfig | 2 -- configs/A20-OLinuXino-Lime_defconfig | 2 -- configs/A20-OLinuXino_MICRO_defconfig | 2 -- configs/Bananapi_defconfig | 2 -- configs/Bananapro_defconfig| 2 -- configs/CSQ_CS908_defconfig| 2 -- configs/Colombus_defconfig | 2 -- configs/Cubieboard2_defconfig | 2 -- configs/Cubietruck_defconfig | 2 -- configs/Hummingbird_A31_defconfig | 2 -- configs/Linksprite_pcDuino3_Nano_defconfig | 2 -- configs/Linksprite_pcDuino3_defconfig | 9 - configs/Mele_I7_defconfig | 2 -- configs/Mele_M3_defconfig | 2 -- configs/Mele_M5_defconfig | 2 -- configs/Mele_M9_defconfig | 2 -- configs/Orangepi_defconfig | 2 -- configs/Orangepi_mini_defconfig| 2 -- configs/UTOO_P66_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 2 -- configs/i12-tvbox_defconfig| 2 -- configs/mixtile_loftq_defconfig| 2 -- include/configs/sunxi-common.h | 2 +- 25 files changed, 19 insertions(+), 50 deletions(-) Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
