On Sun, 7 Jun 2015 08:48:31 -0600
Simon Glass s...@chromium.org wrote:
On 25 May 2015 at 08:50, Lukasz Majewski l.majew...@samsung.com
wrote:
Hi Paul,
Since we're now using a dynamic controller index for fastboot too,
usb_gadget_handle_interrupts should be using it instead of 0
On Sunday, June 07, 2015 at 08:58:04 AM, Nikhil Badola wrote:
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect
This text doesn't really make much sense, but the fix is reasonable.
I'll pick it, thanks!
Signed-off-by: Nikhil Badola
On Friday, May 29, 2015 at 11:17:14 AM, Ramneek Mehresh wrote:
A lot of dwc3 code has been duplicated in various xhci
drivers. Hence, to minimize this duplication, a new
dwc3 file is written that provides common APIs for
all other drivers.
First four patches introduce dwc3 file, and
On Saturday, June 06, 2015 at 10:21:22 AM, Hans de Goede wrote:
When CONFIG_DM_USB=y the various usb functions are available regardless of
any controller drivers being enabled, so always the usb function prototypes
when CONFIG_DM_USB=y.
This fixes compile warnings due to missing prototypes
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/baytrail/Makefile | 1 -
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci-uclass.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-uclass.c
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass s...@chromium.org
---
doc/README.x86 | 17 +
1 file changed, 17 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86
index c19f4a0..596b73c
Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like Address Hole seen by USB_OTG at address 57fff584,
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel,
Hello,
On 5 June 2015 at 13:52, Roy Spliet r.spl...@ultimaker.com wrote:
Based on the default layout of the android image used at least on Olimex Lime
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
include/configs/sunxi-common.h | 9 +
1 file changed, 9 insertions(+)
diff
Hi,
On Sun, Jun 07, 2015 at 04:59:30PM +0200, Hans de Goede wrote:
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Looks like we sent the same patch to the mailing list today :)
Hi Hector,
On Thu, Jun 4, 2015 at 8:23 AM, Palacios, Hector
hector.palac...@digi.com wrote:
Hello,
I can see the command 'mmc erase blk# cnt' fails with a DAT0 timeout on iMX6
boards when run over the eMMC.
= mmc dev 2
= mmc erase 4000 1000
MMC erase: dev # 2, block # 16384, count 4096
On Sun, 2015-06-07 at 16:59 +0200, Hans de Goede wrote:
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/board.c | 1 +
1 file
Ethernet device initialization fails with the following message:
Net: PH: dir_output: error: gpio PH23 not reserved
Phy 1 not found
PHY reset timed out
eth0: ethernet@01c5
Tested on Banana Pi board.
Signed-off-by: Maxin B. John maxin.j...@enea.com
---
arch/arm/cpu/armv7/sunxi/board.c | 1
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/minnowmax.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 547765d..d4d28a7
The status register is a single byte, so use byte access when writing to it,
to avoid updating the control register also.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/spi/ich.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/spi/ich.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_sf.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci-uclass.c
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci_x86.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Ethernet device initialization fails with the following message:
Net: PH: dir_output: error: gpio PH23 not reserved
Phy 1 not found
PHY reset timed out
eth0: ethernet@01c5
Tested on Banana Pi board.
Signed-off-by: Maxin B. John maxin.j...@enea.com
---
arch/arm/cpu/armv7/sunxi/board.c | 1
Hi Paul,
On Sun, Jun 07, 2015 at 03:12:41PM +0200, Paul Kocialkowski wrote:
Hi,
Ethernet device initialization fails with the following message:
Net: PH: dir_output: error: gpio PH23 not reserved
Phy 1 not found
PHY reset timed out
eth0: ethernet@01c5
Tested on Banana Pi
Hi,
Ethernet device initialization fails with the following message:
Net: PH: dir_output: error: gpio PH23 not reserved
Phy 1 not found
PHY reset timed out
eth0: ethernet@01c5
Tested on Banana Pi board.
Signed-off-by: Maxin B. John maxin.j...@enea.com
---
When running MAKEALL on omap3 boards, I noticed that the tricorder board
is not building, with error:
arm-linux-gnueabihf-ld.bfd: u-boot-spl section `.rodata' will not fit in
region `.sram'
arm-linux-gnueabihf-ld.bfd: region `.sram' overflowed by 1568 bytes
I quickly checked CONFIG_SPL_MAX_SIZE,
On 6 June 2015 at 21:33, Bin Meng bmeng...@gmail.com wrote:
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP
On 7 June 2015 at 08:06, Simon Glass s...@chromium.org wrote:
On 6 June 2015 at 21:33, Bin Meng bmeng...@gmail.com wrote:
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit
On 27 April 2015 at 09:54, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 09:34, Tom Rini tr...@konsulko.com wrote:
On i.MX platforms the SPL binary is called SPL so make sure we keep
that.
Cc: Simon Glass s...@chromium.org
Signed-off-by: Tom Rini tr...@konsulko.com
---
On 25 May 2015 at 08:50, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Paul,
Since we're now using a dynamic controller index for fastboot too,
usb_gadget_handle_interrupts should be using it instead of 0 (despite
the fact that it's currently not being used at all in the musb-new
On 6 June 2015 at 21:33, Bin Meng bmeng...@gmail.com wrote:
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Andrew Bradford
On 6 June 2015 at 21:33, Bin Meng bmeng...@gmail.com wrote:
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci-uclass.c | 3 ++-
1 file changed, 2
The SPI flash starts off protected on baytrail. The code which is supposed to
fix this is broken. This series fixes that, enables the SPI environment and
adds documentation.
Also when driver model is enabled for PCI some bugs appear. This series fixes
those and enables driver model for PCI on
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
The SPI flash starts off protected on baytrail. The code which is supposed to
fix this is broken. This series fixes that, enables the SPI environment and
adds documentation.
Also when driver model is enabled for
On Friday 05 June 2015 06:20 PM, Tom Rini wrote:
On Fri, Jun 05, 2015 at 03:19:21PM +0530, Lokesh Vutla wrote:
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
The status register is a single byte, so use byte access when writing to it,
to avoid updating the control register also.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/spi/ich.c | 2 +-
1 file
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/spi/ich.c | 4 ++--
1 file
Hi Tom,
On 5 June 2015 at 16:27, Tom Warren twar...@nvidia.com wrote:
Simon,
Applied to u-boot-tegra/master, then I rebased against u-boot/master and
uploaded it back to denx.de/u-boot-tegra/master. ./MAKEALL -s tegra works
OK. I didn't test on any real HW - my nyan-big system is offline
Hi Andre,
On 5 June 2015 at 18:14, Andre Przywara o...@andrep.de wrote:
On Fri, 5 Jun 2015 08:12:25 -0600
Simon Glass s...@chromium.org wrote:
Hi Simon,
thanks for taking a look.
On 4 June 2015 at 17:58, Andre Przywara o...@andrep.de wrote:
From: Rob Herring r...@kernel.org
Hi Bin,
On 5 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Jun 6, 2015 at 12:13 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 June 2015 at 06:09, Bin Meng bmeng...@gmail.com wrote:
New microcode for BayTrail-I D0 stepping.
Signed-off-by: Bin Meng
Hi Bin,
On 5 June 2015 at 19:30, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Jun 6, 2015 at 12:17 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 June 2015 at 20:03, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Jun 5, 2015 at 2:31 AM, Simon Glass s...@chromium.org
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_sf.c | 8 ++--
1 file changed, 6 insertions(+), 2
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/spi/ich.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ich.c
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Friday, June 05, 2015 7:38 PM
To: Badola Nikhil-B46172
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH] drivers:usb:fsl: Return if
USB_MAX_CONTROLLER_COUNT is incorrect
On Friday, June 05, 2015 at 06:19:16 AM, Badola
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2
- Added space between tags in Subject
- Replaced return value from -1 to -EINVAL
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/minnowmax.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
Hi, Marek
On 6/5/2015 9:18 PM, Marek Vasut wrote:
On Friday, June 05, 2015 at 09:47:30 AM, Josh Wu wrote:
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass s...@chromium.org
---
doc/README.x86 | 17 +
1 file changed, 17
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass s...@chromium.org
---
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Signed-off-by: Simon Glass
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