Hi,
On 06/16/2015 04:45 AM, Simon Glass wrote:
Hi Michal,
On 15 June 2015 at 03:24, Michal Simek michal.si...@xilinx.com wrote:
On 06/15/2015 11:03 AM, Masahiro Yamada wrote:
Hi Michal,
2015-06-15 17:53 GMT+09:00 Michal Simek mon...@monstr.eu:
On 06/10/2015 12:20 PM, Siva Durga Prasad
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an
Hi Heiko,
I noticed a little discrepancy concerning delay for DDR3. During
last rebase to v2015.04 I observed that delay needs to be
increased to boot successfully. Somehow some timing behavior
changed since v2014.04.
I set it to udelay(2000) and it works fine again. Please
update your patch.
On 06/16/2015 01:28 PM, Jagan Teki wrote:
Hi Michal,
On 10 May 2015 at 20:45, Jagan Teki jt...@openedev.com wrote:
This patch enables spi1 for zynq zc770_xm010 board dts.
Signed-off-by: Jagan Teki jt...@openedev.com
Acked-by: Simon Glass s...@chromium.org
Cc: Michal Simek
-Original Message-
From: Guillaume GARDET [mailto:guillaume.gar...@free.fr]
Sent: Tuesday, June 16, 2015 5:49 PM
To: u-boot@lists.denx.de
Cc: Guillaume GARDET; Liu Hui-R64343; Stefano Babic
Subject: [U-Boot] [PATCH] mx53loco: Use generic 'load' command instead of
'fatload'
This
updates for the siemens am335x based boards:
- draco: add delay for DDR3 configuration
- change MTD partition layout and add a possibility
to redefine MTD layout in board header.
- move ubi support to common header file
- draco: improve dtb naming
- draco: set CONFIG_SYS_CBSIZE to 1024
- add
Tested on Pandaboard (rev. A3) and Beagleboard xM (rev. B).
Compilation tested on TI armv7 boards and OMAP boards from other vendors.
Signed-off-by: Guillaume GARDET guillaume.gar...@free.fr
Cc: Tom Rini tr...@konsulko.com
---
include/configs/ti_armv7_common.h | 5 +
1 file changed, 5
Signed-off-by: Guillaume GARDET guillaume.gar...@free.fr
Cc: Tom Rini tr...@konsulko.com
---
include/configs/ti_omap4_common.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/ti_omap4_common.h
b/include/configs/ti_omap4_common.h
index 1c93aab..b0f199e 100644
---
First patch enables EXT support in SPL for all boards including
'ti_armv7_common.h' file, mostly TI armv7 boards and some OMAP boards from
other vendors.
To reduce size of MLO/SPL, in order to fit in SRAM (especially on OMAP3
boards), thumb build is used to build MLO/SPL.
Second patch remove
Hello Samuel,
Am 16.06.2015 um 14:08 schrieb Egli, Samuel:
Hi Heiko,
I noticed a little discrepancy concerning delay for DDR3. During
last rebase to v2015.04 I observed that delay needs to be
increased to boot successfully. Somehow some timing behavior
changed since v2014.04.
I set it to
add cpsw ethernet boot mode support to download spl and
u-boot.img via tftp protocol. Also adding a seperate config
for ethernet boot mode as the default build falcon mode and
environment on MMC is defined for ethernet boot mode
environment should be set to nowhere.
Signed-off-by: Mugunthan V N
From: Tom Rini tr...@konsulko.com
With 1.2 silicon this is now the documented starting usable point for
downloading images to (and corrects a problem with peripheral booting
with prior silicon). Prior silicon is OK using this address as well.
Signed-off-by: Tom Rini tr...@konsulko.com
This patch set adds support for usb host boot and
ethernet boot support
Changes from initial version:
* Used standard defines like CONFIG_SPL_USB_HOST_SUPPORT instead
of introducing new defines as commented by Tom Rini.
Mugunthan V N (2):
am43xx_evm: add usb host boot support
am43xx_evm:
While booting via usb host mode, ROM uses DMA to copy MLO over USB so
ARM internal RAM cannot be used. Adding USB host boot support by
introducing new config target which sets SPL_TEXT_BASE to OCMC ram.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
BeagleBoard-X15 uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
board/ti/beagle_x15/board.c | 23 +++
include/configs/beagle_x15.h | 2 ++
2 files changed, 25
On Tue, Jun 16, 2015 at 08:36:05PM +0530, Lokesh Vutla wrote:
BeagleBoard-X15 uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
signature.asc
On Tue, Jun 16, 2015 at 08:23:39PM +0530, Mugunthan V N wrote:
add cpsw ethernet boot mode support to download spl and
u-boot.img via tftp protocol. Also adding a seperate config
for ethernet boot mode as the default build falcon mode and
environment on MMC is defined for ethernet boot mode
On Tue, Jun 16, 2015 at 08:29:01AM -0500, Nishanth Menon wrote:
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF
On Tue, Jun 16, 2015 at 01:14:09AM +0200, Marek Vasut wrote:
The following changes since commit 5bcec545a6ca977ad74ee9fe0f2b335d348b5000:
image-fit: Fix compiler warning in fit_conf_print() (2015-06-06 09:30:20
-0400)
are available in the git repository at:
On Tue, Jun 16, 2015 at 08:23:38PM +0530, Mugunthan V N wrote:
While booting via usb host mode, ROM uses DMA to copy MLO over USB so
ARM internal RAM cannot be used. Adding USB host boot support by
introducing new config target which sets SPL_TEXT_BASE to OCMC ram.
Signed-off-by: Mugunthan
On Tue, Jun 16, 2015 at 03:00:09PM +0200, Guillaume GARDET wrote:
Tested on Pandaboard (rev. A3) and Beagleboard xM (rev. B).
Compilation tested on TI armv7 boards and OMAP boards from other vendors.
Signed-off-by: Guillaume GARDET guillaume.gar...@free.fr
Cc: Tom Rini tr...@konsulko.com
On Tue, Jun 16, 2015 at 03:00:10PM +0200, Guillaume GARDET wrote:
Signed-off-by: Guillaume GARDET guillaume.gar...@free.fr
Cc: Tom Rini tr...@konsulko.com
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
___
U-Boot mailing list
WHAT IS MINIMUM BATCH SIZE USING COMPULAB 48 COATING PAN WITH BD OF TABLETS IS
0.69
Gandha Naringrekar
Sr. Manager, RD
Aurobindo Pharma USA
6 Wheeling Road
Dayton, NJ 08810
Phone: 732-230-8229
Cell :732-310-5515
gnaringre...@aurobindousa.commailto:gnaringre...@aurobindousa.com
Hi,
On 13 June 2015 at 04:43, Andre Przywara o...@andrep.de wrote:
Avoid clearing the reg property in the memory DT node if no memory
banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
This allows boards to let U-Boot skip the DT memory tinkering in case
other firmware has
Hi Peter,
On 15 June 2015 at 13:40, Peter Robinson pbrobin...@gmail.com wrote:
In our Fedora builds we get the below errors if we build the following using
a vanilla u-boot 2015.07rc2. I'm not sure if it's the best fix but it fixes
the build for rc2.
make HOSTCC=gcc $RPM_OPT_FLAGS
+Joe (Network maintainer)
Hi,
On 14 June 2015 at 08:08, Karsten Merker mer...@debian.org wrote:
Hello,
I am trying to build current u-boot master for the (sunxi-based)
MSI_Primo81 target with support for an ASIX AX88772B USB ethernet
adapter. Setting
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Tuesday, June 16, 2015 1:29 PM
To: Tom Warren; Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren
Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC code/include files
for T210
On 06/15/2015 04:18
Thanks Jagan.
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Tuesday, June 16, 2015 3:50 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; tr...@konsulko.com
Subject: Re: [U-Boot] [PATCH 0/3] stv0991: spi env configs related board
changes
As these were new
On 15-06-16 02:25 PM, Paul Kocialkowski wrote:
Le mardi 16 juin 2015 à 13:58 -0700, Steve Rae a écrit :
Hi Paul,
On 15-06-12 10:57 AM, Paul Kocialkowski wrote:
Each USB download function command calls board_usb_init before registering the
USB gadget and board_usb_cleanup after
Hi Bin,
On 15 June 2015 at 18:19, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jun 16, 2015 at 4:45 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 13 June 2015 at 04:11, Bin Meng bmeng...@gmail.com wrote:
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the
Hi Markus,
On 16 June 2015 at 01:08, Markus Niebel list-09_u-b...@tqsc.de wrote:
From: Markus Niebel markus.nie...@tq-group.com
gpio often are needed to detect revision and variants.
Therefore gpio should be available ASAP.
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
+Masahiro, who might have some clues
Hi Tom,
On 16 June 2015 at 14:04, Tom Rini tr...@konsulko.com wrote:
On Tue, Jun 16, 2015 at 12:24:01PM -0600, Simon Glass wrote:
Hi Peter,
On 15 June 2015 at 13:40, Peter Robinson pbrobin...@gmail.com wrote:
In our Fedora builds we get the below errors
Le mardi 16 juin 2015 à 14:36 -0700, Steve Rae a écrit :
On 15-06-16 02:25 PM, Paul Kocialkowski wrote:
Le mardi 16 juin 2015 à 13:58 -0700, Steve Rae a écrit :
Hi Paul,
On 15-06-12 10:57 AM, Paul Kocialkowski wrote:
Each USB download function command calls board_usb_init before
Hi Paul,
On 15-06-12 10:57 AM, Paul Kocialkowski wrote:
Each USB download function command calls board_usb_init before registering the
USB gadget and board_usb_cleanup after de-registering it. On devices currently
using fasboot, musb-new is usually initialized earlier, but some other boards
Le mardi 16 juin 2015 à 13:58 -0700, Steve Rae a écrit :
Hi Paul,
On 15-06-12 10:57 AM, Paul Kocialkowski wrote:
Each USB download function command calls board_usb_init before registering
the
USB gadget and board_usb_cleanup after de-registering it. On devices
currently
using
On 06/15/2015 04:18 PM, Tom Warren wrote:
Update WRT gpio.h and hardware.h, below.
Tom Warren wrote at Monday, June 15, 2015 1:05 PM:
Stephen Warren wrote at Monday, June 15, 2015 10:11 AM:
On 06/03/2015 02:35 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought
On 06/15/2015 02:04 PM, Tom Warren wrote:
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, June 15, 2015 10:11 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH 1/4] ARM: Tegra210: Add SoC
On Tue, Jun 16, 2015 at 12:24:01PM -0600, Simon Glass wrote:
Hi Peter,
On 15 June 2015 at 13:40, Peter Robinson pbrobin...@gmail.com wrote:
In our Fedora builds we get the below errors if we build the following using
a vanilla u-boot 2015.07rc2. I'm not sure if it's the best fix but it
There is no need to check for sram fill level. If sram is empty, cpu
will go in the wait state till the time data is available from flash.
Also Relying on SRAM fill level only for deciding when the data should be
fetched from the local SRAM is not most efficient approach, particulary
if we are
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
drivers/spi/cadence_qspi.c |1 +
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 8eeb423..794d51d 100644
---
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 403230a..e1e1315 100644
--- a/drivers/spi/cadence_qspi_apb.c
This patchset:
- removes sram polling while reading/writing from flash.
- fixes trigger base transfer start address register programming. This fix
superseeds the previous patch spi: cadence_qspi: Fix the indirect ahb trigger
address setting
- adds support to get fifo width from device tree
Vikas
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c |6 --
1 file changed, 4 insertions(+), 2
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the
address which should be put on AHB bus to handle indirect transfer
triggered before.
To handle indirect transfer we need to issue addresses
There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 59 ++--
1 file changed, 15
This patchset is an initial attempt to support ACPI Tables for qemu-x86 target.
Changes in v2:
Dynamic generation of AML code for DSDT table.
Reading PCI registers for FADT table.
Incorporated Simon's review comments.
Signed-off-by: Saket Sinha saket.sinh...@gmail.com
---
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
Ivybridge is not ready for U-Boot MP initialization yet.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3:
- New patch to remove SMP from CPU_SPECIFIC_OPTIONS for ivybridge
Changes in v2: None
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v4:
- Remove parameter 'count' from cpu_get_count()
Changes in v3:
- Drop patches already applied and rebase on u-boot-x86/master
- New
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
-
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Saksham Jain saks...@freescale.com
Signed-off-by: Ruchika Gupta
From: Markus Niebel markus.nie...@tq-group.com
gpio often are needed to detect revision and variants.
Therefore gpio should be available ASAP.
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
drivers/gpio/mxc_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Hello Jagan,
Am 16.06.2015 um 10:04 schrieb Jagan Teki:
Hi Heiko,
On 20 May 2015 at 12:16, Heiko Schocher h...@denx.de wrote:
Hello Jagan,
Am 19.05.2015 22:09, schrieb Jagan Teki:
Hi Heiko,
I have tested this sf-mtd stuff, please see below and enabled prints
in all the func calls.
Pls- resend this series by adding Data Flash driver to it.
On 18 May 2015 at 18:55, Haikun Wang haikun.w...@freescale.com wrote:
From: Haikun Wang haikun.w...@freescale.com
Enable Driver Model SPI for ls1021atwr board.
DSPI and QSPI only be enabled when boot from QSPI.
DSPI and QSPI are
These options were merged into mx6_common and were seemingly missed
in mx6cuboxi so drop the duplicates
Signed-off-by: Peter Robinson pbrobin...@gmail.com
---
include/configs/mx6cuboxi.h | 8
1 file changed, 8 deletions(-)
diff --git a/include/configs/mx6cuboxi.h
Just a couple of small cleanups to remove duplicate options that are
already defined in mx6_common.h
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
It's defind earlier in the file
Signed-off-by: Peter Robinson pbrobin...@gmail.com
---
include/configs/mx6_common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 50370e1..b37477a 100644
--- a/include/configs/mx6_common.h
+++
As these were new feature additions I will take these into spi-next.
On 16 June 2015 at 02:23, Vikas MANOCHA vikas.mano...@st.com wrote:
Hi Tom,
Can you please apply these patchset for stv0991.
Rgds,
Vikas
-Original Message-
From: Vikas MANOCHA
Sent: Monday, June 08, 2015 5:47
On 16 June 2015 at 02:24, Vikas MANOCHA vikas.mano...@st.com wrote:
Hi Tom,
Can you please apply the stv0991 patchset.
As these were new feature additions I will take these into spi-next.
-Original Message-
From: Vikas MANOCHA
Sent: Wednesday, May 27, 2015 6:43 PM
To:
On 14 June 2015 at 23:03, Chakra Divi cd...@openedev.com wrote:
This patch clears the errors found by running checkpatch.pl on file
drivers/spi/fsl_espi.c
Signed-off-by: Chakra Divi cd...@openedev.com
---
drivers/spi/fsl_espi.c | 14 --
1 file changed, 8 insertions(+), 6
Hi Heiko,
On 20 May 2015 at 12:16, Heiko Schocher h...@denx.de wrote:
Hello Jagan,
Am 19.05.2015 22:09, schrieb Jagan Teki:
Hi Heiko,
I have tested this sf-mtd stuff, please see below and enabled prints
in all the func calls.
Thanks for testing!
zynq-uboot mtdparts add nor0
Hi Heiko,
On 16 June 2015 at 14:13, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015 um 10:04 schrieb Jagan Teki:
Hi Heiko,
On 20 May 2015 at 12:16, Heiko Schocher h...@denx.de wrote:
Hello Jagan,
Am 19.05.2015 22:09, schrieb Jagan Teki:
Hi Heiko,
I have tested
Hello Jagan,
Am 16.06.2015 um 10:52 schrieb Jagan Teki:
Hi Heiko,
On 16 June 2015 at 14:13, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015 um 10:04 schrieb Jagan Teki:
Hi Heiko,
On 20 May 2015 at 12:16, Heiko Schocher h...@denx.de wrote:
Hello Jagan,
Am 19.05.2015
On 16 June 2015 at 14:48, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015 um 10:52 schrieb Jagan Teki:
Hi Heiko,
On 16 June 2015 at 14:13, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015 um 10:04 schrieb Jagan Teki:
Hi Heiko,
On 20 May 2015
2015-06-16 11:36 GMT+02:00 Jagan Teki jt...@openedev.com:
On 16 June 2015 at 14:48, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015 um 10:52 schrieb Jagan Teki:
Hi Heiko,
On 16 June 2015 at 14:13, Heiko Schocher denx h...@denx.de wrote:
Hello Jagan,
Am 16.06.2015
This patch uses generic 'load' command instead of 'fatload' for
'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board.
This allows to use EXT partition instead of FAT, while keeping FAT
compatibility.
Signed-off-by: Guillaume GARDET guillaume.gar...@free.fr
Cc: Jason Liu
Hi,
On 12-06-15 02:53, Tom Rini wrote:
We want to see if the requested start or total block count are
unaligned. We discard the whole numbers and only care about the
remainder. Update the code to use div_u64_rem here and add a comment.
Cc: Hans de Goede hdego...@redhat.com
Cc: Pantelis
On 2015-06-16 06:01, Stephen Warren wrote:
On 06/11/2015 12:35 PM, Jakub Kicinski wrote:
Hello!
I'm using latest git source of U-Boot on Raspberry Pi Compute Module
and performance of fatload is quite bad. Does anyone have any clue
about what can be wrong? Is it the lack of cache?
The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.
Cc: Minkyu Kang mk7.k...@samsung.com
Signed-off-by:
On Thursday 11 June 2015 12:26 AM, Tom Rini wrote:
On Wed, Jun 10, 2015 at 03:04:16PM +0530, Mugunthan V N wrote:
While booting via usb host mode, ROM uses DMA to copy MLO over USB so
ARM internal RAM cannot be used. Adding USB host boot support by
introducing new config target which sets
Hi Michal,
On 10 May 2015 at 20:45, Jagan Teki jt...@openedev.com wrote:
This patch enables spi1 for zynq zc770_xm010 board dts.
Signed-off-by: Jagan Teki jt...@openedev.com
Acked-by: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu
Hi Peng,
On 16/06/2015 03:48, Peng Fan wrote:
What about just using SPL mechanism instead?
Hi Fabio,
I agree that SPL can give many benifits, but we default not support it.
CHECK_BITS_SET/CLR is supported by i.MX6, but current no user use this
feature.
This patch is actually for i.MX7
75 matches
Mail list logo
