This patch rewrites MMU translation table entries to achieve:
a) Start with all table entries as "invalid".
b) Rewrite the table entries as "device-ngnrne" for cache-inhibit
access.
c) Rewrite the table entries as "normal" for cache-enabled access.
Signed-off-by: Alison Wang
Signed-off-by: York S
On 7/10/2015 6:06 AM, Simon Glass wrote:
> Hi,
>
> On 9 July 2015 at 05:58, Haikun Wang wrote:
>> Showing both:
>> Model: Freescale Layerscape 2085a QDS Board
>> Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
>
> This looks like duplication (at least the first part).
>
>
The patch will initialize PCIe controller on EP mode
1. Setup bar:
bar0 32bit 4K for specific configuration
bar1 32bit 8K for MSIX
bar2 64bit 4K for descriptor of memory
bar4 64bit 1M for DMA memory test
2. Setup iATU:
iATU inbound 0-3 to map bar transaction to memory address
star
PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.
Signed-off-by: Minghuan Lian
---
Change log:
v2-v1:
1. add a descriptor of pci_find_next_ext_capability
2. fix a typo
drivers/pci/pc
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.
With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 1
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.
Signed-off-by: Bin Meng
---
Changes in v2:
- Use enum for x86 exception numbers
arch/x86/cpu/interrupts
Hi Minkyu,
On 9 July 2015 at 19:43, Minkyu Kang wrote:
> Hi Simon,
>
> On 08/07/15 11:38, Simon Glass wrote:
>> Hi Minkyu,
>>
>> On 6 July 2015 at 19:36, Minkyu Kang wrote:
>>> Dear Simon,
>>>
>>> On 07/07/15 00:27, Simon Glass wrote:
Hi Minkyu, Przemyslaw,
On 5 July 2015 at 00:15
Hi Simon,
On 08/07/15 11:38, Simon Glass wrote:
> Hi Minkyu,
>
> On 6 July 2015 at 19:36, Minkyu Kang wrote:
>> Dear Simon,
>>
>> On 07/07/15 00:27, Simon Glass wrote:
>>> Hi Minkyu, Przemyslaw,
>>>
>>> On 5 July 2015 at 00:15, Heiko Schocher wrote:
Hello Simon,
Am 03.07.2015 um
Ping. Anyone review/apply this patch?
On Thu, Jun 25, 2015 at 10:32:26AM +0800, Peng Fan wrote:
>DCIMVAC is upgraded to DCCIMVAC for the individual processor
>(Cortex-A7) that the DCIMVAC is executed on.
>
>We should follow the linux dma follow. Before DMA read, first
>invalidate dcache then after
Hi Simon,
On Fri, Jul 10, 2015 at 6:00 AM, Simon Glass wrote:
> Hi Bin,
>
> On 7 July 2015 at 23:17, Bin Meng wrote:
>> Some exceptions cause an error code to be saved on the current stack
>> after the EIP value. We should extract CS/EIP/EFLAGS from different
>> position on the stack based on th
This is an initial attempt to support ACPI on minnowmax and qemu-x86 targets.
This is still a work in progress.
The Linux kernel boot logs on minnowmax can be found at
http://pastebin.com/Vdk8PqaV .
Saket Sinha (1):
x86: Initial ACPI support for minnowmax and qemu.
arch/x86/Kconfig
Signed-off-by: Saket Sinha
---
arch/x86/Kconfig | 7 +
arch/x86/cpu/qemu/Makefile | 3 +-
arch/x86/cpu/qemu/acpi.c | 176 +++
arch/x86/cpu/qemu/acpi/cpu-hotplug.asl | 78 +
arch/x86/cpu/qemu/acpi/dbug.asl
Hi,
On 9 July 2015 at 05:58, Haikun Wang wrote:
> Showing both:
> Model: Freescale Layerscape 2085a QDS Board
> Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
This looks like duplication (at least the first part).
Anyway I don't see any problem with this change.
Revie
Hi Bin,
On 7 July 2015 at 23:17, Bin Meng wrote:
> Some exceptions cause an error code to be saved on the current stack
> after the EIP value. We should extract CS/EIP/EFLAGS from different
> position on the stack based on the exception number.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu
On 7 July 2015 at 23:17, Bin Meng wrote:
> Instead of using switch..case for architecture defined exceptions,
> simply unify the handling by printing a message of exception name,
> followed by registers dump then halt the CPU.
>
> With this unification, it also fixes the wrong exception numbers
>
On 9 July 2015 at 14:21, Simon Glass wrote:
> On 9 July 2015 at 04:37, Bin Meng wrote:
>> Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
>> result so that the config option order matches Kconfig.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> configs/crownbay_defconfig | 8
From: Jiandong Zheng
Signed-off-by: Jiandong Zheng
Signed-off-by: Steve Rae
---
Changes in v3:
- use "SZ_1M"
- undefine the 8-bit phy interface
Changes in v2:
- rebased against u-boot-dfu
board/broadcom/bcm28155_ap/bcm28155_ap.c | 40
drivers/usb/gadget/Make
From: Jiandong Zheng
Add the required files for the Broadcom UDC OTG interface.
Signed-off-by: Jiandong Zheng
Signed-off-by: Steve Rae
---
Changes in v3:
- use static inline functions instead of macros
- update the delay (2ms) to match the kernel code
Changes in v2: None
arch/arm/include/a
Signed-off-by: Steve Rae
---
Changes in v3: None
Changes in v2: None
include/g_dnl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/g_dnl.h b/include/g_dnl.h
index 4eeb5e4..ba49f1f 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -34,6 +34,7 @@ struct g_dnl_bind_callback {
};
The OTG hardware is a DWC2 controller and this series uses the
existing gadget driver ("s3c_udc_otg.c").
Changes in v3:
- use static inline functions instead of macros
- update the delay (2ms) to match the kernel code
- use "SZ_1M"
- undefine the 8-bit phy interface
Changes in v2:
- rebased again
Hi Jagan,
On 9 July 2015 at 14:31, Jagan Teki wrote:
> On 2 July 2015 at 12:33, Jagan Teki wrote:
>> On 1 July 2015 at 02:38, Simon Glass wrote:
>>> Hi Tom,
>>>
>>> On 30 June 2015 at 14:31, Tom Rini wrote:
On Tue, Jun 30, 2015 at 01:10:45PM -0700, York Sun wrote:
>
>
> On 06/
Dear Jagan,
In message
you wrote:
>
> On that note, I have tried the same by loading u-boot on external-RAM with
> TEXT_BASE and it ran very feasibly. the design is like the SOC has ROM with
> first stage bootloader and second stage is u-boot and external-RAM got
> initialized
> in first stage b
Dear Albert,
In message <20150708084625.5a18e9a5@lilith> you wrote:
>
> > http://www.denx.de/wiki/view/DULG/CanUBootBeConfiguredSuchThatItCanBeStartedInRAM
>
> If I may, this FAQ is slightly outdated, in that chainloading U-Boot is
> not only possible but actually made possible by design, at lea
On Thu, 2015-07-09 at 09:47 +0200, Marcel Ziswiler wrote:
> Hi Scott
>
> On Wed, 2015-07-08 at 18:25 -0500, Scott Wood wrote:
> >
> > As per discussion on v1, this isn't enough to guarantee that the stop
> > address
> > will be aligned. There needs to be a wrapper around memalign() that
> > c
On 2 July 2015 at 12:33, Jagan Teki wrote:
> On 1 July 2015 at 02:38, Simon Glass wrote:
>> Hi Tom,
>>
>> On 30 June 2015 at 14:31, Tom Rini wrote:
>>> On Tue, Jun 30, 2015 at 01:10:45PM -0700, York Sun wrote:
On 06/30/2015 12:01 PM, Tom Rini wrote:
> On Tue, Jun 30, 2015 at
On 9 July 2015 at 04:37, Bin Meng wrote:
> Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
> result so that the config option order matches Kconfig.
>
> Signed-off-by: Bin Meng
> ---
>
> configs/crownbay_defconfig | 8
> configs/minnowmax_defconfig | 4 ++--
> 2
On 8 July 2015 at 12:16, Albert ARIBAUD wrote:
> Hello Wolfgang,
>
> On Wed, 08 Jul 2015 00:36:52 +0200, Wolfgang Denk wrote:
>> Dear Jagan,
>>
>> In message
>> you
>> wrote:
>> >
>> > I'm running u-boot from u-boot prompt, just like a standalone
>> > application with CONFIG_SYS_TEXT_BASE addr
Hi Andre,
On 7 July 2015 at 19:22, Andre Wolokita wrote:
> Hi Simon,
>
> Hopefully you're the right person to be contacting about this; if not, please
> point me in the right direction.
>
> We've recently had a contractor write a hash driver for our crypto
> accelerator, intended to accelerate
Hi Ulrich,
On 9 July 2015 at 07:16, Ulrich Prinz wrote:
> Am 08.07.2015 um 17:25 schrieb Simon Glass:
>>
>> +ML
>>
>> Hi Ulrich,
>>
>> On 7 July 2015 at 08:32, Ulrich Prinz wrote:
>>>
>>> Am 24.06.2015 um 01:28 schrieb Simon Glass:
>>
>>
>> Great, nice to hear from you! There's lots to do.
>>
>
Hi Baruch,
On 09/07/2015 17:19, Baruch Siach wrote:
> When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine
> generates is empty. This causes HAB to complain that the command is invalid.
>
> - HAB Event 1 -
> event data:
> 0xdb 0x00 0x0c 0x41 0x3
On 07/09/2015 09:02 AM, Stefan Agner wrote:
On 08.07.2015 22:57, Stephen Warren wrote:
On 07/07/2015 12:04 AM, Marcel Ziswiler wrote:
On 6 July 2015 18:38:21 CEST, Simon Glass wrote:
Out of interest, is this just a message for the user? Why is it useful?
Well, we or customers might do ot
On 08.07.2015 22:57, Stephen Warren wrote:
> On 07/07/2015 12:04 AM, Marcel Ziswiler wrote:
>>
>>
>> On 6 July 2015 18:38:21 CEST, Simon Glass wrote:
>>
>>> Out of interest, is this just a message for the user? Why is it useful?
>>
>> Well, we or customers might do other interesting things on ente
When dcd_len is 0 the Write Data command that the set_dcd_rst_v2() routine
generates is empty. This causes HAB to complain that the command is invalid.
- HAB Event 1 -
event data:
0xdb 0x00 0x0c 0x41 0x33 0x06 0xc0 0x00
0xcc 0x00 0x04 0x04
To fix this set t
Hi Albert,
On 9 July 2015 at 09:03, Albert ARIBAUD wrote:
> Hello Simon,
>
> On Thu, 9 Jul 2015 07:31:05 -0600, Simon Glass wrote:
>> Hi,
>>
>> On 8 July 2015 at 23:41, Albert ARIBAUD wrote:
>> > Hello Masahiro,
>> >
>> > On Thu, 9 Jul 2015 14:16:33 +0900, Masahiro Yamada
>> > wrote:
>> >> Hi
Hello Simon,
On Thu, 9 Jul 2015 07:31:05 -0600, Simon Glass wrote:
> Hi,
>
> On 8 July 2015 at 23:41, Albert ARIBAUD wrote:
> > Hello Masahiro,
> >
> > On Thu, 9 Jul 2015 14:16:33 +0900, Masahiro Yamada
> > wrote:
> >> Hi Simon,
> >>
> >> > 3. How do we handle things like gpio_exynos_bind() wh
Hi,
On 9 July 2015 at 00:37, wrote:
> From: Tang Yuantian
>
> When compling under 64bit platforms, there are lots of warnings,
> like:
>
> drivers/block/ahci.c:114:18: warning: cast to pointer from integer
> of different size [-Wint-to-pointer-cast]
> u8 *port_mmio = (u8 *)probe_ent->port[po
On 9 July 2015 at 07:11, Masahiro Yamada wrote:
> Currently, DM_FLAG_ACTIVATED is set twice; before calling
> uclass_pre_probe_device() and again before calling drv->probe().
>
> It looks like Simon's intention is the first one.
> The DM_FLAG_ACTIVATED was moved twice, by commit 02eeb1bbb174
> (dm
Hi,
On 8 July 2015 at 23:41, Albert ARIBAUD wrote:
> Hello Masahiro,
>
> On Thu, 9 Jul 2015 14:16:33 +0900, Masahiro Yamada
> wrote:
>> Hi Simon,
>>
>> > 3. How do we handle things like gpio_exynos_bind() which allocs some
>> > data and passes it to a device it creates, as platform data? At
>> >
On Wed, 2015-07-08 at 15:03 -0600, Stephen Warren wrote:
>
> Do either of patches 12 and 13 make sense for all Tegra boards?
In German we would call that a Gretchenfrage.
BTW: I just noticed that somehow on T20 one can not quite use 16K as on
the T30 (e.g. it fails with "EHCI timed out on TD - t
Currently, DM_FLAG_ACTIVATED is set twice; before calling
uclass_pre_probe_device() and again before calling drv->probe().
It looks like Simon's intention is the first one.
The DM_FLAG_ACTIVATED was moved twice, by commit 02eeb1bbb174
(dm: core: Mark device as active before calling its probe()
met
On Wed, 2015-07-08 at 14:57 -0600, Stephen Warren wrote:
> But that's not what this patch does; it simply prints a message. It
> doesn't seem terribly useful.
Agreed but I look at it more like a documented entry point.
In our downstream U-Boot we use it to stop autoboot to allow for manual
reco
In case of enable CONFIG_OF_CONTROL and has a "model" property in the root node,
the board special "checkboard" will not be called.
Usually we show some useful version information in the function.
This patch enable call "checkboard" in any case.
It is not conflicting with showing "model" at the sam
Baltos has USB0 connected to a USB hub and thus is host-only. USB1
is connected to microUSB connector and thus should use OTG mode.
Signed-off-by: Yegor Yefremov
---
include/configs/baltos.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/baltos.h b/includ
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.
Signed-off-by: Bin Meng
---
configs/crownbay_defconfig | 8
configs/minnowmax_defconfig | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
Le jeudi 09 juillet 2015 à 13:29 +0530, Lokesh Vutla a écrit :
> On Friday 03 July 2015 01:23 AM, Paul Kocialkowski wrote:
> > Le jeudi 02 juillet 2015 à 15:10 -0400, Tom Rini a écrit :
> >> On Thu, Jul 02, 2015 at 12:19:41AM +0200, Paul Kocialkowski wrote:
> >>> OMAP devices might boot from periph
On Friday 03 July 2015 01:23 AM, Paul Kocialkowski wrote:
> Le jeudi 02 juillet 2015 à 15:10 -0400, Tom Rini a écrit :
>> On Thu, Jul 02, 2015 at 12:19:41AM +0200, Paul Kocialkowski wrote:
>>> OMAP devices might boot from peripheral devices, such as UART or USB.
>>> When that happens, the U-Boot SP
Hi Scott
On Wed, 2015-07-08 at 18:25 -0500, Scott Wood wrote:
>
> As per discussion on v1, this isn't enough to guarantee that the stop address
> will be aligned. There needs to be a wrapper around memalign() that cache-
> aligns the size as well.
>
> -Scott
Sorry, that isn't quite clear to me
T124 requires some specific configuration (VPR setup) to be performed by
the bootloader before the GPU can be used. For this reason, the GPU node
in the device tree is disabled by default. This patch enables the node
if U-boot has performed VPR configuration.
Boards enabled by this patch are T124'
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().
Also move VPR configuration into t
Tegra124 requires the bootloader to perform VPR initialization, otherwise the
GPU cannot be used by the system. Since using the GPU without that
initialization results in a hang, the GPU DT node is left disabled, and it is
the task of the bootloader to enable it after ensuring it is safe to use the
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