From: Miao Yan yanmiaob...@gmail.com
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/qemu-x86_i440fx.dts | 7 +++
arch/x86/dts/qemu-x86_q35.dts| 7 +++
configs/qemu-x86_defconfig | 2 ++
Hi,
Le dimanche 26 juillet 2015 à 02:46 +0900, Masahiro Yamada a écrit :
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu. Use hierarchic menu for each category.
That looks like a valuable addition to
Hi,
On 27-07-15 14:31, Paul Kocialkowski wrote:
Hi,
Le mercredi 22 juillet 2015 à 11:31 +0200, Hans de Goede a écrit :
Hi,
On 22-07-15 10:45, Paul Kocialkowski wrote:
This makes sunxi boards use the USB_EHCI_HCD Kconfig option instead of defining
USB_EHCI as a config define. This allows for
2015-07-27 19:52 GMT+09:00 Marek Vasut ma...@denx.de:
On Monday, July 27, 2015 at 09:05:03 AM, Pavel Machek wrote:
On Mon 2015-07-27 10:33:51, Masahiro Yamada wrote:
Hi Pavel,
2015-07-27 3:38 GMT+09:00 Pavel Machek pa...@denx.de:
Hi!
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.
On Monday, July 27, 2015 at 09:05:03 AM, Pavel Machek wrote:
On Mon 2015-07-27 10:33:51, Masahiro Yamada wrote:
Hi Pavel,
2015-07-27 3:38 GMT+09:00 Pavel Machek pa...@denx.de:
Hi!
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and
Hi,
Le mercredi 22 juillet 2015 à 11:31 +0200, Hans de Goede a écrit :
Hi,
On 22-07-15 10:45, Paul Kocialkowski wrote:
This makes sunxi boards use the USB_EHCI_HCD Kconfig option instead of
defining
USB_EHCI as a config define. This allows for more flexibility in enabling
the
On 24 July 2015 at 10:33, Michal Suchanek hramr...@gmail.com wrote:
Hello,
it seems extlinux.conf is pushed as *the* u-boot configuration.
As in it is promoted by many people and its flexibility is praised.
It overrides boot script when both are present.
However,
1) it is not
On Thu, Jul 23, 2015 at 08:31:56PM +0900, Masahiro Yamada wrote:
The previous commit introduced a useful macro used in makefiles,
which references to different variables (CONFIG_ or CONFIG_SPL_
prefixed), in order to enable/disable features independently
for each of images.
Per-image
On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
Commit e02ee2548afe (kconfig: switch to single .config
configuration) made the configuration itself pretty simple,
instead, we lost the way to systematically enable/disable config
options for each image independently.
Our
On Sat, Jul 25, 2015 at 08:59:35PM +0800, Peng Fan wrote:
Discard the empty video_set_lut function from platform video
drivers.
This commit 69d275458893eaec35229b589092c2a6bde5440f introduces
a weak function video_set_lut, so we do not need an strong function
in platform drivers, which
On Sun, Jul 26, 2015 at 03:18:13PM +0200, Stefano Babic wrote:
mcx was not updated according to changes in
NAND driver.
Signed-off-by: Stefano Babic sba...@denx.de
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
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On Sun, Jul 26, 2015 at 03:18:15PM +0200, Stefano Babic wrote:
Signed-off-by: Stefano Babic sba...@denx.de
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
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On Mon, Jul 27, 2015 at 11:10:58AM +0200, yegorsli...@googlemail.com wrote:
From: Yegor Yefremov yegorsli...@googlemail.com
Enable DTS support (CONFIG_OF_LIBFDT) and select
CONFIG_FIT in defconfig.
Signed-off-by: Yegor Yefremov yegorsli...@googlemail.com
Reviewed-by: Tom Rini
2015-07-26 17:49 GMT+09:00 Marek Vasut ma...@denx.de:
On Sunday, July 26, 2015 at 10:26:45 AM, Masahiro Yamada wrote:
The board-specific linker script board/vpac270/u-boot-spl.lds
obstructs further cleanup. This board has not been converted to
Generic Board yet in spite of the long-term
On Sun, Jul 26, 2015 at 03:18:14PM +0200, Stefano Babic wrote:
Signed-off-by: Stefano Babic sba...@denx.de
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
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On Tue, Jul 28, 2015 at 12:19:07AM +0900, Masahiro Yamada wrote:
Tom,
2015-07-28 0:08 GMT+09:00 Tom Rini tr...@konsulko.com:
On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
Commit e02ee2548afe (kconfig: switch to single .config
configuration) made the configuration
Tom,
2015-07-28 0:08 GMT+09:00 Tom Rini tr...@konsulko.com:
On Thu, Jul 23, 2015 at 08:31:55PM +0900, Masahiro Yamada wrote:
Commit e02ee2548afe (kconfig: switch to single .config
configuration) made the configuration itself pretty simple,
instead, we lost the way to systematically
Hi Marek, other USB guys,
I noticed commit dc9cdf859e11de (usb: dwc3: Add DWC3 controller driver
support) was pulled into the mainline a few days ago.
Now we have two drivers with similar names.
- drivers/usb/dwc3/
- drivers/usb/host/xhci-dwc3.c
Are they the same hardware, or completely
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 27, 2015 10:53 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V3 3/6] ARM: Tegra210: Add SoC
On 07/24/2015 04:01 PM, Tom Warren wrote:
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
diff --git a/include/configs/venice2.h
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 27, 2015 10:55 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V3 4/6] ARM: Tegra210: Add support to
Thanks, Stephen!
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 27, 2015 11:01 AM
To: Tom Warren
Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren;
tomcwarren3...@gmail.com
Subject: Re: [U-Boot] [PATCH V3 0/6] Tegra210/P2571 initial
From: Thierry Reding tred...@nvidia.com
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Tom Warren
Hello Scott,
On 18.07.2015 03:07, Vladimir Zapolskiy wrote:
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings
Hi,
Le 24/07/2015 17:22, Ash Charles a écrit :
On Fri, Jul 24, 2015 at 7:04 AM, Tom Rini tr...@konsulko.com wrote:
Can you give us more details on the exact nature of the failure? Thanks!
Oh sorry--that wasn't clear! The boards appear to get stuck in SPL
before anything can be printed to the
Hi Andre,
On 27 July 2015 at 11:08, Andre Przywara andre.przyw...@arm.com wrote:
Hi Simon,
On 24/06/15 00:29, Simon Glass wrote:
diff --git a/doc/README.rockchip b/doc/README.rockchip
new file mode 100644
index 000..a34e198
--- /dev/null
+++ b/doc/README.rockchip
+
Hi Simon,
On 24/06/15 00:29, Simon Glass wrote:
diff --git a/doc/README.rockchip b/doc/README.rockchip
new file mode 100644
index 000..a34e198
--- /dev/null
+++ b/doc/README.rockchip
+
+Future work
+===
+
+Immediate priorities are:
+
+- MMC support (in U-Boot
Hi,
On 23 July 2015 at 10:51, Stephen Warren swar...@wwwdotorg.org wrote:
From: Thierry Reding tred...@nvidia.com
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Tom Warren twar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
Simon,
When Thierry first
On 07/27/2015 09:36 AM, York Sun wrote:
On 07/26/2015 03:20 AM, Stefano Babic wrote:
I apply it to u-boot-imx - merging into mainline, we will have more
chances to get it tested on PowerPc.
Applied to u-boot-imx, thanks !
Sorry I didn't see this thread until Stefano CC'ed me. I will
On 07/24/2015 04:00 PM, Tom Warren wrote:
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
diff --git a/arch/arm/dts/tegra210.dtsi
Le lundi 20 juillet 2015 à 17:13 +0200, Heiko Schocher a écrit :
Hello Paul,
Am 20.07.2015 um 15:30 schrieb Paul Kocialkowski:
I am just on the jump into my holidays, so I have not yet the time
to test it ... I want to try it for all builds with the scripts
I posted with my v2 ... but a
On Monday, July 27, 2015 at 05:37:52 PM, Masahiro Yamada wrote:
Hi Marek, other USB guys,
Hi!
I noticed commit dc9cdf859e11de (usb: dwc3: Add DWC3 controller driver
support) was pulled into the mainline a few days ago.
Now we have two drivers with similar names.
- drivers/usb/dwc3/
On 07/24/2015 04:00 PM, Tom Warren wrote:
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for
From: Sylvain Lemieux slemi...@tycoint.com
Add support to specify the Ethernet buffer base address;
if none are supply by the board, the default value is use (from existing code).
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
drivers/net/lpc32xx_eth.c | 8 +---
1 file changed, 5
On 07/24/2015 04:00 PM, Tom Warren wrote:
This patch series adds support for the Tegra210
SoC and the P2571 board. Most of the T210 info
is identical to T124 at this point, so I just
cloned Venice2/Jetson-TK1 board files and T124
header/SoC code. Pinmux is the major area of
difference at this
From: Thierry Reding tred...@nvidia.com
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection,
From: Thierry Reding tred...@nvidia.com
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Tom Warren twar...@nvidia.com
Signed-off-by: Stephen Warren
From: Sylvain Lemieux slemi...@tycoint.com
The HCLK is not constant and can take different value; use the api function to
get the value of the HCLK for the I2C clock high and low computation.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
drivers/i2c/lpc32xx_i2c.c | 2 +-
1 file
From: Sylvain Lemieux slemi...@tycoint.com
Add support for optional soft reset (i.e. RESOUT_N not asserted during reset).
To be compatible with the original U-Boot code, when the addr parameter is 0,
a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain
From: Sylvain Lemieux slemi...@tycoint.com
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to LPC32x0 User
manual Rev. 3 - 22 July 2011).
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +-
From: Sylvain Lemieux slemi...@tycoint.com
Fix a condition that generate watchdog timeout inside lpc32xx_i2c_write when
parameters alen = 0 and len = 0.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
drivers/i2c/lpc32xx_i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Sylvain Lemieux slemi...@tycoint.com
Fix a condition that generate watchdog timeout inside lpc32xx_i2c_read when
parameters alen != 0 and len = 0.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
drivers/i2c/lpc32xx_i2c.c | 10 +-
1 file changed, 5 insertions(+), 5
From: Sylvain Lemieux slemi...@tycoint.com
This series of patches bring miscellaneous enhancement
and update to the existing lpc32xx support in u-boot.
Refer to each individual patches for details on the specific change.
The patch adding the LPC32xx MAC and SMSC RMII phy support
should be
From: Sylvain Lemieux slemi...@tycoint.com
Add LPC32xx GPIO interface macro for pin mapping.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
---
arch/arm/include/asm/arch-lpc32xx/gpio_grp.h | 40
1 file changed, 40 insertions(+)
create mode 100644
On 05/17/2015 11:31 PM, Priyanka Jain wrote:
sw variable in checkboard function is storing vbank value
which can only take 4-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
On Tue, 2015-07-21 at 00:35 +0200, Marcel Ziswiler wrote:
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Integrate cache alignment bounce buffer to workaround issues as follows:
Loading file '/boot/zImage' to addr 0x0100 with size 4499152
(0x0044a6d0)...
ERROR:
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Max Krummenacher max.krummenac...@toradex.com
Enable CONFIG_IP_DEFRAG and set CONFIG_TFTP_BLOCKSIZE to 16384.
This increases the tftp download speed considerably.
While at it enable CONFIG_TFTP_TSIZE which limits the progress bar to
fifty
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Enable optional raw initrd support to allow boot using an initrd.
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
Doesn't
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Unfortunately currently both Apalis T30 as well as Colibri T30 crash
upon starting USB host support. This is due to the following patch not
having taken into account that our T30 device trees were
On 27/07/2015 20:15, York Sun wrote:
On 07/27/2015 09:36 AM, York Sun wrote:
On 07/26/2015 03:20 AM, Stefano Babic wrote:
I apply it to u-boot-imx - merging into mainline, we will have more
chances to get it tested on PowerPc.
Applied to u-boot-imx, thanks !
Sorry I didn't see this
On 07/15/2015 12:34 AM, shh@gmail.com wrote:
From: Shaohui Xie shaohui@freescale.com
T4160 and T4080 support same serdes options, which serdes 2 3 support 8
Lanes, same as T4240, but serdes 1 4 support only 4 Lanes, Lanes A, B,
C, D are not available, updated the serdes table
On Tue, 2015-07-21 at 00:35 +0200, Marcel Ziswiler wrote:
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command now required for proper ONFI detection.
This fix is inspired by Lucas Stach's Linux
On 07/20/2015 04:35 PM, Marcel Ziswiler wrote:
From: Marcel Ziswiler marcel.ziswi...@toradex.com
This patch set is an assortment of tegra fixes/enhancements distilled
straight from our downstream integration work.
Other than the comments I already made and other than the NAND read_byte
There's no reason why simple-bus driver can not be used in SPL,
in fact it is necessary to get SoCFPGA SPL probe the cadence
SPI driver. So drop the restriction.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
drivers/core/Makefile | 2 --
1 file changed, 2
Use the proper structure which describes these registers,
especially since this is already in place.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 20 +---
drivers/ddr/altera/sequencer.h | 4
2 files changed, 9 insertions(+), 15 deletions(-)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 126 -
1 file changed, 63 insertions(+), 63 deletions(-)
diff --git
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 52 +-
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git
Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 141 -
drivers/ddr/altera/sequencer.h | 53 ++--
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 46 ++
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git
Add build target for generating boot partition images recognised by
the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the
u-boot-spl-dtb.sfp at the beginning of boot partition. Those are
u-boot-spl-dtb.bin augmented by a header with which the BootROM can
work. The u-boot-dtb.img
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 90 +-
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git
This is kind of microseries-within-series indent cleanup.
Rework the code for the third loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not
This is kind of microseries-within-series indent cleanup.
Rework the code for the the middle-loop of the mega-loop
this time and deal with the group_failed variable. Instead
of checking if the group failed in the previous calibration
part, just jump to the end of the loop if calibration did
fail
Add kerneldoc and do a minor comment cleanup. No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index
This is kind of microseries-within-series indent cleanup.
Rework the code for the second loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not
Perform minor coding style cleanup of the mem_skip_calibrate() function,
clean up comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
Perform minor reordering of the function to make the code more
organised, no functional change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c
Clean up the debug output handling at the end of the function
and factor out common function call from the condition.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git
The read_group and write_group arguments are the same in all
cases when this function is invoked, just merge them into one
rw_group argument. Also, clean up the function argument data
types and constify them.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 35
Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 124 +
1 file changed, 63 insertions(+), 61 deletions(-)
Fix the return value of the function to match common convention
where 0 means success and negative means error. Fix the return
values in case of an error to use errno.h codes.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 11 +++
1 file changed, 7
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 40 +---
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6999504..f7e2e40 100644
---
Add kerneldoc, no functional change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index efcf283..b81fc8c 100644
---
The d variable is set to 0 in sdr_backup_phase() and is not used
at all in sdr_nonworking_phase(). Make it local and zap it respectively.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
Clean up data types and constify where applicable. No function change.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c
It is now clear that the max_working_cnt variable is totally unused.
Zap the variable and zap other variables which became unused due to
this change too.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 40 +---
1 file changed, 9
The work_bgn parameter of sdr_nonworking_phase() is unused, zap it.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index
Wrap dtaps_per_ptap into the sdr_working_phase() function to trim
down the number of params. It's a constant too.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
Fix the arguments passed to these functions. The grp argument
does not have to be passed via reference, it's never modified
within either of those functions, so make it into a value.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 40
Rename find_working_phase() to sdr_working_phase() for the
sake of consistency.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
Fix the arguments passed to these functions. The bit_chk is
overriden by rw_mgr_mem_calibrate_read_test_all_ranks() which
is invoked by all three sdr_*_phase() functions, so just make
this into local variable.
Signed-off-by: Marek Vasut ma...@denx.de
---
drivers/ddr/altera/sequencer.c | 21
Get rid of found_{begin,end} variables. Instead of breaking out
through all of the loops, just return when the begin/end of the
window is found and be done with it. Also clean up the trailing
conditional expression, which is now much easier.
Signed-off-by: Marek Vasut ma...@denx.de
---
Pull out the loop for eaching working/non-working DQS enable phase
into a separate function, as this is mostly common code between.
Clean up sdr_working_phase() and sdr_nonworking_phase() while switching
these two functions to the common sdr_find_phase().
Signed-off-by: Marek Vasut ma...@denx.de
Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pantelis Antoniou
Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Dinh Nguyen dingu...@opensource.altera.com
---
include/configs/socfpga_arria5.h | 2 +-
include/configs/socfpga_common.h | 6 ++
Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
drivers/gpio/Makefile | 1 +
drivers/gpio/dwapb_gpio.c | 167 ++
2 files
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@konsulko.com
---
From: Dinh Nguyen dingu...@opensource.altera.com
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Acked-by: Marek Vasut ma...@denx.de
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git
Get rid of this cryptic typedef and replace it with explicit struct cm_config.
Signed-off-by: Marek Vasut ma...@denx.de
---
arch/arm/mach-socfpga/clock_manager.c | 2 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 +++---
arch/arm/mach-socfpga/spl.c
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut ma...@denx.de
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 +
arch/arm/mach-socfpga/reset_manager.c | 13 +
2 files
Reset the GMAC ethernets based on the resets OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen
We do not need full MTD support in the SPL build, it only adds size
and is not usable in any way. Exclude it.
Signed-off-by: Marek Vasut ma...@denx.de
---
include/configs/socfpga_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for
The GMAC can now be probed from OF, so enable DM ethernet and remove the
old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Joe Hershberger joe.hershber...@ni.com
---
arch/arm/mach-socfpga/misc.c | 4
Write necessary magic value into the Warm Boot from ON-Chip RAM
group Enable register to enable Warm reset support. Instead of
doing this in the reset_cpu() function, we do it in arch early
init to avoid breaking old kernel code which expects this magic
value to be already written into this
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by: Marek Vasut ma...@denx.de
---
arch/arm/mach-socfpga/spl.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl.c
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