Enable SDMMC calibration to determine the best setting for
drvsel and smpsel. It will be triggered whenever there is
a change of card frequency and bus width. This is to ensure
reliable transmission between the controller and the card.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh
Remove hard-coded SDMMC timing parameter drvsel and smplsel.
This setting now will come from SDMMC calibration
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Stefan Roese s...@denx.de
Hi,
On 08/19/2015 08:54 PM, Marek Vasut wrote:
On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
This patch is to separate the base trigger from the read/write transfer
start addresses.
Base trigger register address (0x1c register) corresponds to the address
which should be
On Thu, Aug 20, 2015 at 10:20:55AM +0900, Masahiro Yamada wrote:
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Acked-by: Heiko Schocher h...@denx.de
Acked-by:
From: Thierry Reding tred...@nvidia.com
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the
From: Thierry Reding tred...@nvidia.com
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the
From: Thierry Reding tred...@nvidia.com
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the
From: Thierry Reding tred...@nvidia.com
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies.
From: Thierry Reding tred...@nvidia.com
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code
From: Thierry Reding tred...@nvidia.com
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/cpu/armv8/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Thierry Reding tred...@nvidia.com
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier marc.zyng...@arm.com
Suggested-by: Mark Rutland
From: Thierry Reding tred...@nvidia.com
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
From: Thierry Reding tred...@nvidia.com
Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Thierry Reding
On Thursday, August 20, 2015 at 08:58:23 AM, Chin Liang See wrote:
On Thu, 2015-08-20 at 07:27 +0200, ma...@denx.de wrote:
On Thursday, August 20, 2015 at 07:15:25 AM, Chin Liang See wrote:
Hi Marek,
Hi,
On Wed, 2015-08-19 at 03:22 -0500, Chin Liang See wrote:
Hi,
On
On Thu, 2015-08-20 at 07:27 +0200, ma...@denx.de wrote:
On Thursday, August 20, 2015 at 07:15:25 AM, Chin Liang See wrote:
Hi Marek,
Hi,
On Wed, 2015-08-19 at 03:22 -0500, Chin Liang See wrote:
Hi,
On Wed, 2015-08-19 at 09:37 +0200, ma...@denx.de wrote:
On Wednesday, August
Enable early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon
That MAX_I2C_RETRY define has been a copy/paste left over not actually
used anywhere in this file therefore get rid of it.
Signed-off-by: Marcel Ziswiler marcel.ziswi...@toradex.com
---
board/toradex/colibri_t20/colibri_t20.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Hi,
On 08/19/2015 03:45 PM, Maxime Ripard wrote:
On Sat, Aug 15, 2015 at 10:02:34PM +0200, Hans de Goede wrote:
CONFIG_SPL_NAND_SUPPORT gets used via IS_ENABLED so it must be defined
to 1, rather then just being defined.
While at remove 2 other unused NAND related defines from sunxi-common.h.
On Wed, Aug 19, 2015 at 11:41:09AM -0600, Stephen Warren wrote:
On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: Use named constants
Hi Bin, Simon,
On 18 August 2015 at 15:47, Stoppa, Igor igor.sto...@intel.com wrote:
Hi,
I have verified that I can reproduce a working build of U-Boot as
x86-64bit EFI payload for Qemu: I can boot it, interact with various
filesystems of both real and emulated disks, etc.
Now I would
From: Thierry Reding tred...@nvidia.com
GCC 5.1 starts warning for comparisons such as !a 0, assuming that the
negation was meant to apply to the whole expression rather than just the
left operand.
Indeed the comparison in the FIT loadable code is confusingly written,
though it does end up
Hi,
On 08/19/2015 03:48 PM, Maxime Ripard wrote:
On Sat, Aug 15, 2015 at 10:02:40PM +0200, Hans de Goede wrote:
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.
Without this the kernel
On 08/21/2015 06:06 AM, Marek Vasut wrote:
On Thursday, August 20, 2015 at 07:29:52 AM, Michal Simek wrote:
On 08/19/2015 10:47 PM, Marek Vasut wrote:
On Wednesday, August 19, 2015 at 10:29:18 PM, Marek Vasut wrote:
Repair the maintainer entries so they match the current state of code.
On Friday, August 21, 2015 at 01:38:05 AM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
When an EHCI device is registered in device mode, the HW isn't actually
initialized at all, and hence isn't left in a running state. Consequently,
when the device is deregistered,
On Friday, August 21, 2015 at 07:43:44 AM, Kishon Vijay Abraham I wrote:
Hi Marek,
On Friday 21 August 2015 11:03 AM, Marek Vasut wrote:
On Friday, August 21, 2015 at 07:32:04 AM, Kishon Vijay Abraham I wrote:
Commit 8bfc288c3955 (usb: gadget: ether: Perform board
initialization from
Hi Tom,
On Thursday 20 August 2015 11:26 PM, Tom Rini wrote:
On Wed, Aug 19, 2015 at 02:13:21PM +0530, Kishon Vijay Abraham I wrote:
Enabled configs for dwc3, dwc3-omap and PHY for dwc3 in
ti_omap5_common. Also enabled support for DFU.
Since ti_omap5_common is used by dra7 too, removed
Hi Bin ,
Please find my response inline -
On Tue, Aug 18, 2015 at 2:53 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:10 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 9:25 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue,
Hi,
On Fri, 2015-08-21 at 05:03 +0200, ma...@denx.de wrote:
On Friday, August 21, 2015 at 03:25:00 AM, Chin Liang See wrote:
On Fri, 2015-08-21 at 03:07 +0200, ma...@denx.de wrote:
On Friday, August 21, 2015 at 02:54:00 AM, Chin Liang See wrote:
Hi guys,
Hi,
Hi,
Any
On Thursday, August 20, 2015 at 07:29:52 AM, Michal Simek wrote:
On 08/19/2015 10:47 PM, Marek Vasut wrote:
On Wednesday, August 19, 2015 at 10:29:18 PM, Marek Vasut wrote:
Repair the maintainer entries so they match the current state of code.
Signed-off-by: Marek Vasut ma...@denx.de
Commit 8bfc288c3955 (usb: gadget: ether: Perform board
initialization from ethernet gadget driver) added board_usb_init
and board_usb_cleanup in ethernet gadget driver. But h2200 board
didn't have board_usb_init and board_usb_cleanup implementations.
This introduced the following build errors
On Friday, August 21, 2015 at 07:32:04 AM, Kishon Vijay Abraham I wrote:
Commit 8bfc288c3955 (usb: gadget: ether: Perform board
initialization from ethernet gadget driver) added board_usb_init
and board_usb_cleanup in ethernet gadget driver. But h2200 board
didn't have board_usb_init and
Make Generic Driver Options menu show on the top in the Kconfig.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 092bc02..b25c59c 100644
--- a/drivers/Kconfig
+++
On Friday 21 August 2015 11:15 AM, Marek Vasut wrote:
On Friday, August 21, 2015 at 07:43:44 AM, Kishon Vijay Abraham I wrote:
Hi Marek,
On Friday 21 August 2015 11:03 AM, Marek Vasut wrote:
On Friday, August 21, 2015 at 07:32:04 AM, Kishon Vijay Abraham I wrote:
Commit 8bfc288c3955 (usb:
Hi,
Can anyone tell me if there is any work going on for further ext4 support
in u-boot. In particular ext4load mmc and ls. This is notoriously slow for
a large number of files.
Cheers
Glen
___
U-Boot mailing list
U-Boot@lists.denx.de
On popular request this series integrates the display driver from T20
to work on T30 as well and enables it for our Apalis/Colibri T30
computer/system on modules. Enjoy.
Marcel Ziswiler (5):
arm: tegra20: video: rename display header ifdef gating
arm: tegra20: video: ifdef gate hard-coded
On 08/13/2015 09:46 AM, Michal Simek wrote:
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is tftpboot 8 uImage echo yes
and press CTRL+C. Then the second command is called which is incorrect.
On Wednesday, August 19, 2015 at 02:02:18 PM, Tom Rini wrote:
On Wed, Aug 19, 2015 at 06:39:29AM +0200, Marek Vasut wrote:
On Tuesday, August 18, 2015 at 07:53:23 PM, Tom Rini wrote:
On Wed, Aug 12, 2015 at 07:31:55AM +0900, Masahiro Yamada wrote:
We have flipped
Dell Customer Communication
PURPOSE:
This email is with respect to the fitupd command.
In looking at the source in the current u-boot tree, fitupd supports a NOR
flash only.
OUR GOAL:
We would like to expand fitupd to be able to flash a SPI NOR, and MMC block
devices.
This would require
2015-08-19 13:35 GMT+09:00 Simon Glass s...@chromium.org:
All boards should be converted to generic board by now. Change the rest
over. If this causes run-time breakages then we can remove those boards.
Signed-off-by: Simon Glass s...@chromium.org
With this, we will lose reason to drop old
As a preparatory step make sure the display driver is buildable for
Tegra30 as well by ifdef gating any hard-coded ugly Tegra20 pin muxing
stuff.
Signed-off-by: Marcel Ziswiler marcel.ziswi...@toradex.com
---
drivers/video/tegra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be
2015-08-19 20:19 GMT+02:00 Govindraj Raja govindraj.r...@imgtec.com:
From: Govindraj Raja govindraj.r...@imgtec.com
The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.
Third parameter is no more used in these api's
Refer to :
2015-08-19 20:19 GMT+02:00 Govindraj Raja govindraj.r...@imgtec.com:
From: Govindraj Raja govindraj.r...@imgtec.com
usb stack utilizes the clr/set_bits macros
also usb stack needs phy_to_bus/bus_to_phys functions.
Thus adding these macro and functions for mips platform.
This makes usb stack
Enable the display driver on Apalis T30. Unfortunately the PWM pin
muxing wasn't any good neither which made that display stay dark.
Signed-off-by: Marcel Ziswiler marcel.ziswi...@toradex.com
---
arch/arm/dts/tegra30-apalis.dts| 29 ++
On popular request enable the display driver on Colibri T30. A few
notes about some things encountered during porting: While analogue VGA
(e.g. via the on-carrier RAMDAC) worked just fine from the beginning
the EDT display flickered like crazy which turned out to be a pin
muxing issue.
As a preparatory step make sure the Tegra20 display header file is
properly ifdef gated with its name.
Signed-off-by: Marcel Ziswiler marcel.ziswi...@toradex.com
---
arch/arm/include/asm/arch-tegra20/display.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Hi guys,
Any comment or ack for this patch?
Thanks
Chin Liang
On Thu, 2015-08-20 at 02:18 -0500, Chin Liang See wrote:
Remove hard-coded SDMMC timing parameter drvsel and smplsel.
This setting now will come from SDMMC calibration
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh
On Friday, August 21, 2015 at 02:54:00 AM, Chin Liang See wrote:
Hi guys,
Hi,
Any comment or ack for this patch?
Please don't expect that the reviewers/maintainers have nothing else on
their plate but to review your patch. Besides, this change is really low
priority one, since thus far the
On 20 Aug 2015 21:58, Stephen Warren swar...@wwwdotorg.org wrote:
Is there any guarantee that the voltage levels are high enough for the
AVP to run correctly before the CORE rail is adjusted? It sounds to me
like a HW design issue; the SoC reset output should reset the PMIC too.
If by
On 20 Aug 2015 22:09, Stephen Warren swar...@wwwdotorg.org wrote:
Hopefully the process was to copy the Linux Tegra30 DT verbatim?
No, the T20 one is far from verbatim neither. So I just did the adjustments
analogous by comparing the T20 and T30 Linux DTs.
That's
far more likely to yield a
On 8/20/15 4:59 PM, Marek Vasut wrote:
On Thursday, August 20, 2015 at 11:55:02 PM, Dinh Nguyen wrote:
+CC: Simon Glass
Hi Dinh,
On Thu, Aug 20, 2015 at 12:32 AM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 20, 2015 at 07:28:02 AM, Chin Liang See wrote:
Hi,
On Wed,
On Fri, 2015-08-21 at 03:07 +0200, ma...@denx.de wrote:
On Friday, August 21, 2015 at 02:54:00 AM, Chin Liang See wrote:
Hi guys,
Hi,
Any comment or ack for this patch?
Please don't expect that the reviewers/maintainers have nothing else on
their plate but to review your patch.
On 20 Aug 2015 22:00, Stephen Warren swar...@wwwdotorg.org wrote:
Does the CORE rail get adjusted by DVFS? Hopefully if it does, it is
never set so low that AVP operation at reset is impossible...
Exactly.
+ udelay(1000);
all the delays in this patch seem very large. What drove the
On Friday, August 21, 2015 at 02:54:15 AM, Chin Liang See wrote:
Hi guys,
Any comment or ack for this patch?
Thanks
Please stop top-posting ;-)
This one is all right ; it's 1/2 which is the problem.
Best regards,
Marek Vasut
___
U-Boot mailing
On Friday, August 21, 2015 at 12:25:54 AM, vikas wrote:
Hi,
Hi,
On 08/20/2015 02:56 PM, Marek Vasut wrote:
On Thursday, August 20, 2015 at 06:48:36 PM, vikas wrote:
Hi,
On 08/19/2015 08:54 PM, Marek Vasut wrote:
On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
On 20 Aug 2015 22:01, Stephen Warren swar...@wwwdotorg.org wrote:
Rather than enable this with yet another CONFIG_ option, perhaps we can
put this code into a C file dedicated to the colibri_t20 board, and then
have the common code call it (and implement a weak function that does
nothing to
On Friday, August 21, 2015 at 03:25:00 AM, Chin Liang See wrote:
On Fri, 2015-08-21 at 03:07 +0200, ma...@denx.de wrote:
On Friday, August 21, 2015 at 02:54:00 AM, Chin Liang See wrote:
Hi guys,
Hi,
Hi,
Any comment or ack for this patch?
Please don't expect that the
On Wed, Aug 19, 2015 at 02:13:19PM +0530, Kishon Vijay Abraham I wrote:
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in beagle_x15 board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
On Wed, Aug 19, 2015 at 04:16:25PM +0530, Kishon Vijay Abraham I wrote:
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros rog...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Nishanth Menon n...@ti.com
On Wed, Aug 19, 2015 at 02:13:20PM +0530, Kishon Vijay Abraham I wrote:
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in omap5 board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by:
On Wed, Aug 19, 2015 at 02:13:21PM +0530, Kishon Vijay Abraham I wrote:
Enabled configs for dwc3, dwc3-omap and PHY for dwc3 in
ti_omap5_common. Also enabled support for DFU.
Since ti_omap5_common is used by dra7 too, removed these configs
from dra7xx_evm config file.
Signed-off-by:
Hi,
I've not done sunxi development for a while. So I need to ask you guys
about some details. I hope you don't mind. Please see questions below.
On 06.08.2015 09:55, Piotr Zierhoffer wrote:
I've merged patches 1 - 3 in my sunxi-wip branch,
and I'll include them in the next u-boot-sunxi
Add some comments in start.S for the fact that with FSP U-Boot
actually enters the code twice. Also change to use fsp_init()
and fsp_continue for accuracy.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/Kconfig | 2 +-
arch/x86/cpu/start.S | 6
It turns out that calling fsp_init_phase_pci() in arch_misc_init()
is subject to break pci device drivers as with driver model, when
the bus enumeration happens is not deterministic.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 8
Hi again,
On 20 August 2015 at 12:44, Stoppa, Igor igor.sto...@intel.com wrote:
It happens much earlier than I thought: I was expecting it would get
stuck during the handover from the stub to the real U-Boot, after the
jump_to_uboot call, instead it never reaches that point.
Now I am able to
Hi Hans,
On 20.08.2015 15:42, Hans de Goede wrote:
Okay, this driver SPL NAND is now integrated in mainline. Great.
But how about NAND support for the main U-Boot (load Linux from NAND
etc.)? It seems to be missing. Is somebody working on this?
Yes, see:
Hi,
On 08/20/2015 02:37 PM, Stefan Roese wrote:
Hi,
I've not done sunxi development for a while. So I need to ask you guys about
some details. I hope you don't mind. Please see questions below.
On 06.08.2015 09:55, Piotr Zierhoffer wrote:
I've merged patches 1 - 3 in my sunxi-wip branch,
Move x86_fsp_init() call after initf_malloc() so that we can fix up
the gd-malloc_limit later.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/board_f.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr.
Mask bus number before save it to pplat-devfn.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
drivers/pci/pci-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Add some
During pci_bind_bus_devices() before finding a proper driver to bind
the device, pci_bus_find_devfn() is called to find if this device
already exists. However since device is even not bound, this call
always returns -ENODEV. It is really unnecessary hence remove it.
Signed-off-by: Bin Meng
This is the 2nd attempt to support pci uart devices with driver model.
The v1 patch series is at [1].
Instead of creating a pci-specific device driver for ns16550 in v1, this
v2 patch supports binding pci devices using device tree.
As previously mentioned in the ML, we should call fsp_notify()
Document how pci devices are bound to device drivers.
Also mention its limitation in the pre-relocation phase.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
doc/driver-model/pci-info.txt | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic
devices except bridges won't be
When there is no valid compatible string in current list,
we should advance to next one in the compatible string list.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
lib/fdtdec.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/lib/fdtdec.c
Per Intel FSP specification, we should call FSP notify API to
inform FSP that PCI enumeration has been done so that FSP will
do any necessary initialization as required by the chipset's
BIOS Writer's Guide (BWG).
Unfortunately we have to put this call here as with driver model,
the enumeration is
With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enumeration
is not done yet. Actually we don't need to do this in that early phase,
hence we delay this call to arch_misc_init().
Signed-off-by: Bin Meng
The dm pci doc says it supports binding pci device which appears
in the device tree. However it is not true, at least on Intel
Crown Bay. Currently the crownbay.dts defines 4 pci uart devices
within the pci bus controller's node. pci_find_and_bind_driver()
only scans U_BOOT_PCI_DEVICE defined
Hi Bin,
Please find my response inline -
On Tue, Aug 18, 2015 at 12:36 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing
Hi Saket,
On Fri, Aug 21, 2015 at 12:24 PM, Saket Sinha saket.sinh...@gmail.com wrote:
Hi Bin,
Please find my response inline.
On Tue, Aug 18, 2015 at 12:36 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
This
On Friday, August 21, 2015 at 07:00:46 AM, Chin Liang See wrote:
Hi,
Hi,
Any comment or ack for this patch?
Please don't expect that the reviewers/maintainers have nothing else
on their plate but to review your patch. Besides, this change is
really low priority one, since
Hi Bin,
Please find my response inline -
On Tue, Aug 18, 2015 at 12:36 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
The DSDT table contains a bytecode that is executed by a driver in the
kernel.
Hi Saket,
On Fri, Aug 21, 2015 at 12:33 PM, Saket Sinha saket.sinh...@gmail.com wrote:
Hi Bin,
Please find my response inline -
On Tue, Aug 18, 2015 at 12:36 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
On Friday, August 21, 2015 at 07:25:57 AM, Michal Simek wrote:
On 08/21/2015 06:06 AM, Marek Vasut wrote:
On Thursday, August 20, 2015 at 07:29:52 AM, Michal Simek wrote:
On 08/19/2015 10:47 PM, Marek Vasut wrote:
On Wednesday, August 19, 2015 at 10:29:18 PM, Marek Vasut wrote:
Repair the
Right now PHYS_TO_BUS shows in the Kconfig main menu, move it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b25c59c..9d0df9b 100644
--- a/drivers/Kconfig
+++
Hi Marek,
On Friday 21 August 2015 11:03 AM, Marek Vasut wrote:
On Friday, August 21, 2015 at 07:32:04 AM, Kishon Vijay Abraham I wrote:
Commit 8bfc288c3955 (usb: gadget: ether: Perform board
initialization from ethernet gadget driver) added board_usb_init
and board_usb_cleanup in ethernet
Sort different types of drivers in alphabetical order.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/Kconfig | 50 ++
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9d0df9b..524d73e
Hello Nobuhiro-san,
Could you provide any response for this patchset.
TIA,
Vladimir
On 20.07.2015 20:48, Vladimir Barinov wrote:
This patch series adds the following:
1) sh-pfc: fix gpio input read
2) serial-sh: SCIFA interface for R-Car Gen2 SoCs
3) rmobile: add SCIFA port base offsets
4)
From: Govindraj Raja govindraj.r...@imgtec.com
usb stack utilizes the clr/set_bits macros
also usb stack needs phy_to_bus/bus_to_phys functions.
Thus adding these macro and functions for mips platform.
This makes usb stack usable with mips platform.
Signed-off-by: Govindraj Raja
On 08/20/2015 03:42 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Aside from the one comment I already made, the series,
Acked-by: Stephen Warren
On 08/20/2015 03:42 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down
On 08/20/2015 03:42 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating
On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at
On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Enable early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at
On 08/20/2015 05:29 AM, Marcel Ziswiler wrote:
As a preparatory step make sure the display driver is buildable for
Tegra30 as well by ifdef gating any hard-coded ugly Tegra20 pin muxing
stuff.
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
@@ -215,8 +215,10 @@ static int
Hello Albert,
Could you provide any response on this patch.
TIA,
Vladimir
On 20.03.2015 18:16, Vladimir Barinov wrote:
From: Valentine Barshak valentine.bars...@cogentembedded.com
This enables ARMv7 barrier operations support when
march=armv7-a is enabled.
Using CP15 barriers causes U-Boot
On 08/20/2015 10:04 AM, Hans de Goede wrote:
ubifs does not go though the generic block layer because mtd devices
are special, so the any filesystem option to sysboot does not work,
this adds support for a ubifs filesystem to the sysboot command which
makes it possible to boot from ubifs using
On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at
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