Re: [U-Boot] [PATCH 10/13] sunxi: Make the fastboot buffer larger

[Ian Campbell]

On Sun, 2015-09-06 at 13:22 +0200, Maxime Ripard wrote:
> On Fri, Sep 04, 2015 at 12:59:24PM -0400, Tom Rini wrote:
> > On Tue, Sep 01, 2015 at 09:57:16AM +0200, Maxime Ripard wrote:
> > 
> > [snip]
> > > Of course, this will all depend on the ratio between the empty space
> > > and the files themselves, and what files you actually have there, but
> > > while 32MB is definitely useless, 256MB is already a decent size.
> > 
> > So there's not any automatic chunking and writing of the image?  Maybe
> > I'm confusing this with DFU and/or my wishlist/imagination...
> 
> Apparently, Rob was saying there was some, but I'm not sure we support
> that yet, I'd need to look into it.

It seems this is pretty critical, given that storage (both capacity and
actual required space within the fs) are growing and 256MB is only barely
big enough for the 4GB image you have today (210MB after the various
compression strategies are applied).

Ian.
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Re: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel

[Jaehoon Chung]

Hi,

On 09/04/2015 07:41 PM, Pavel Machek wrote:
> Hi!
> 
>>> How is this SMPLSEL and DRVSEL implemented on Exynos ?
>
> Exynos is using CLKSEL register in dw-mmc controller.
> It's exynos specific register in dwmmc controller. It's also
> represented 45 degree increment. SELCK_DRV is bit[18:16] or more.
> SELCLK_SAMPLE is bit[2:0] or more. There are other bits relevant to
> tuning clock. '_more_' means that it can be changed bandwidth.
>
> Anyway, I think there is no right method about finding the best smplclk
> and drvsel. If this is generic method, i will pick this. But i don't
> think so, and there is no benefit for exynos.
>
> smplclk and drvsel value need to process the tuning sequence.
> There is no tuning case at bootloader, since it's not implemented about
> HS200 or upper mode.
>
> Clksel an drvsel value are passed by device tree.

 In that case, maybe SoCFPGA should also pick those values from DT ? It
 would keep the code simple and in case there is a problematic board, it
 could use u-boot application to perform the tuning.
>>>
>>> I prefer not to do that as it narrows the supported use case for the
>>> driver.
>>
>> How so? It keeps the driver code clean and this code you're adding seems
>> like a special-purpose stuff which needs to be done once for particular
>> board, no ?
> 
> Well... stuff that can be automatically detected is not supposed to be
> in the device tree.
> 
> clksel and drvsel can be calibrated, so I see some arguments why we
> should calibrate them, and not hardcode them in the device tree.

My opinions are 

1. This code is not generic dwmmc code. So i don't want to locate into dwmmc 
core.
If need to apply, i agree that it applies this in socfpga-dw_mmc.c.

2. In exynos, value of devcie-tree is the tested value.
After has tested with every values, it defined the best value into device-tree.
(Working fine with values.)
At every time, it doesn't need to detect the best value with same SoC.
(Especially, at bootloader)

3. In my experiment, there should be side-effect during finding best sample/drv 
value.

4. If HS200 or upper mode is supported at bootloader, it needs the tuning 
sequence.
Then it needs to find the best sampl/drv values. but it doesn't support HS200 
or other at bootloader.

5. Affect at booting time??


Best Regards,
Jaehoon Chung

>   Pavel
> 

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[U-Boot] [PATCH 2/2] igep00x0: Switch to use the generic distro configuration and environment.

[Enric Balletbo i Serra]

This patch changes a little bit the environment, current environment was broken
for a long time, and board don't as expected sometimes, on production systems
this is fixed adding boot script. I think it's time to change this to make a
system conformant environment and use generic distro configurations and
environment instead. We can use a boot script for the old way boot mode.

Signed-off-by: Enric Balletbo i Serra 
---
 board/isee/igep00x0/igep00x0.c   |  4 +-
 include/configs/omap3_igep00x0.h | 95 
 2 files changed, 30 insertions(+), 69 deletions(-)

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 693fce7..6eb191c 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -153,10 +153,10 @@ void set_fdt(void)
 {
switch (gd->bd->bi_arch_number) {
case MACH_TYPE_IGEP0020:
-   setenv("dtbfile", "omap3-igep0020.dtb");
+   setenv("fdtfile", "omap3-igep0020.dtb");
break;
case MACH_TYPE_IGEP0030:
-   setenv("dtbfile", "omap3-igep0030.dtb");
+   setenv("fdtfile", "omap3-igep0030.dtb");
break;
}
 }
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 04433ed..4409103 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -19,6 +19,8 @@
 #include 
 #include 
 
+#undef CONFIG_BOOTDELAY
+
 /*
  * Display CPU and Board information
  */
@@ -81,74 +83,33 @@
 
 /*#undef CONFIG_ENV_IS_NOWHERE*/
 
+#ifndef CONFIG_SPL_BUILD
+
+#include 
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+   "stdin=serial\0" \
+   "stdout=serial\0" \
+   "stderr=serial\0"
+
+#define MEM_LAYOUT_SETTINGS \
+   DEFAULT_LINUX_BOOT_ENV \
+   "scriptaddr=0x87E0\0" \
+   "pxefile_addr_r=0x87F0\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0)
+
+#include 
+
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
-   "usbtty=cdc_acm\0" \
-   "loadaddr=0x8200\0" \
-   "dtbaddr=0x8160\0" \
-   "bootdir=/boot\0" \
-   "bootfile=zImage\0" \
-   "usbtty=cdc_acm\0" \
-   "console=ttyO2,115200n8\0" \
-   "mpurate=auto\0" \
-   "vram=12M\0" \
-   "dvimode=1024x768MR-16@60\0" \
-   "defaultdisplay=dvi\0" \
-   "mmcdev=0\0" \
-   "mmcroot=/dev/mmcblk0p2 rw\0" \
-   "mmcrootfstype=ext4 rootwait\0" \
-   "nandroot=/dev/mtdblock4 rw\0" \
-   "nandrootfstype=jffs2\0" \
-   "mmcargs=setenv bootargs console=${console} " \
-   "mpurate=${mpurate} " \
-   "vram=${vram} " \
-   "omapfb.mode=dvi:${dvimode} " \
-   "omapfb.debug=y " \
-   "omapdss.def_disp=${defaultdisplay} " \
-   "root=${mmcroot} " \
-   "rootfstype=${mmcrootfstype}\0" \
-   "nandargs=setenv bootargs console=${console} " \
-   "mpurate=${mpurate} " \
-   "vram=${vram} " \
-   "omapfb.mode=dvi:${dvimode} " \
-   "omapfb.debug=y " \
-   "omapdss.def_disp=${defaultdisplay} " \
-   "root=${nandroot} " \
-   "rootfstype=${nandrootfstype}\0" \
-   "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-   "importbootenv=echo Importing environment from mmc ...; " \
-   "env import -t $loadaddr $filesize\0" \
-   "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
-   "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "bootz ${loadaddr}\0" \
-   "mmcbootfdt=echo Booting with DT from mmc ...; " \
-   "bootz ${loadaddr} - ${dtbaddr}\0" \
-   "nandboot=echo Booting from onenand ...; " \
-   "run nandargs; " \
-   "onenand read ${loadaddr} 28 40; " \
-   "bootz ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-   "mmc dev ${mmcdev}; if mmc rescan; then " \
-   "echo SD/MMC found on device ${mmcdev};" \
-   "if run loadbootenv; then " \
-   "run importbootenv;" \
-   "fi;" \
-   "if test -n $uenvcmd; then " \
-   "echo Running uenvcmd ...;" \
-   "run uenvcmd;" \
-   "fi;" \
-   "if run loadzimage; then " \
-   "if test -n $dtbfile; then " \
-   "if run loadfdt; then " \
-   "run mmcbootfdt;" \
-   "fi;" \
-   "fi;" \
-   "run mmcboot;" \
-   "fi;" \
-   "fi;" \
-   "run nandboot;" \
+   ENV_DEVICE_SETTINGS \
+   MEM_LAYOUT_SETTINGS \
+   BOOTENV
+
+#endif
 
 /*
  * FLASH and environment 

[U-Boot] [PATCH 1/2] igep00xx: MAINTAINERS: update eballetbo's email address.

[Enric Balletbo i Serra]

Signed-off-by: Enric Balletbo i Serra 
---
 board/isee/igep0033/MAINTAINERS | 2 +-
 board/isee/igep00x0/MAINTAINERS | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep0033/MAINTAINERS
index d162d77..bd8a1f2 100644
--- a/board/isee/igep0033/MAINTAINERS
+++ b/board/isee/igep0033/MAINTAINERS
@@ -1,5 +1,5 @@
 IGEP0033 BOARD
-M: Enric Balletbo i Serra 
+M: Enric Balletbo i Serra 
 S: Maintained
 F: board/isee/igep0033/
 F: include/configs/am335x_igep0033.h
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
index 3fc2c6c..d355c46 100644
--- a/board/isee/igep00x0/MAINTAINERS
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -1,5 +1,5 @@
 IGEP00X0 BOARD
-M: Enric Balletbo i Serra 
+M: Enric Balletbo i Serra 
 S: Maintained
 F: board/isee/igep00x0/
 F: include/configs/omap3_igep00x0.h
-- 
2.1.0

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Re: [U-Boot] [PATCH 1/2] mx6: remove SYS_SOC from board Kconfig

[Stefan Roese]

On 07.09.2015 08:59, Peng Fan wrote:

Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Heiko Schocher 
Cc: Christian Gmeiner 
Cc: Stefan Roese 
Cc: Troy Kisky 
Cc: Nikita Kiryanov 
Cc: "Eric Bénard" 
Cc: Fabio Estevam 
Cc: Tim Harvey 
Cc: Marek Vasut 
Cc: Markus Niebel 
Cc: Otavio Salvador 


For the board I maintain:

Acked-by: Stefan Roese 

Thanks,
Stefan

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Re: [U-Boot] [PATCH v4 1/2] usb: zynqmp: Add XHCI driver support

[Siva Durga Prasad Paladugu]

Hi Marek,

> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Saturday, September 05, 2015 6:46 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Siva Durga Prasad Paladugu
> Subject: Re: [PATCH v4 1/2] usb: zynqmp: Add XHCI driver support
> 
> On Friday, September 04, 2015 at 08:31:07 AM, Siva Durga Prasad Paladugu
> wrote:
> > Added USB XHCI driver support for zynqmp.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu 
> 
> Hi,
> 
> looks like in the meantime, some xhci implementations switches to OF (see
> for example xhci-exynos5.c), which I believe is also already used on Zynq.
> Maybe you should consider that as well, given that this patch is scheduled
> after 2015.10 release anyway.
This patch is for ZynqMP not for Zynq.
 ZynqMP, we haven't yet moved to OF.

Regards,
Siva

> 
> > +struct zynqmp_xhci {
> > +   struct xhci_hccr *hcd;
> > +   struct dwc3 *dwc3_reg;
> > +};
> > +
> > +static struct zynqmp_xhci zynqmp_xhci;
> >
> > +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST;
> > +
> > +__weak int __board_usb_init(int index, enum usb_init_type init)
> 
> Please, no functions starting with underscores.
> 
> > +{
> > +   return 0;
> 
> This function is not used, remove it?
> 
> > +}
> > +
> > +void usb_phy_reset(struct dwc3 *dwc3_reg) {
> > +   /* Assert USB3 PHY reset */
> > +   setbits_le32(_reg->g_usb3pipectl[0],
> > +DWC3_GUSB3PIPECTL_PHYSOFTRST);
> > +
> > +   /* Assert USB2 PHY reset */
> > +   setbits_le32(_reg->g_usb2phycfg,
> DWC3_GUSB2PHYCFG_PHYSOFTRST);
> > +
> > +   udelay(10);
> > +
> > +   /* Clear USB3 PHY reset */
> > +   clrbits_le32(_reg->g_usb3pipectl[0],
> > +DWC3_GUSB3PIPECTL_PHYSOFTRST);
> > +
> > +   /* Clear USB2 PHY reset */
> > +   clrbits_le32(_reg->g_usb2phycfg,
> DWC3_GUSB2PHYCFG_PHYSOFTRST);
> > +}
> [...]
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH 2/2] nios2: Split timer code into timer.c

[Thomas Chou]

Hi Marek,

On 09/04/2015 05:51 PM, Marek Vasut wrote

diff --git a/arch/nios2/cpu/timer.c b/arch/nios2/cpu/timer.c
new file mode 100644
index 000..006b19b
--- /dev/null
+++ b/arch/nios2/cpu/timer.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * (C) Copyright 2004, Psyent Corporation 
+ * Scott McNutt 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct nios_timer {
+   u32 status; /* Timer status reg */
+   u32 control;/* Timer control reg */
+   u32 periodl;/* Timeout period low */
+   u32 periodh;/* Timeout period high */
+   u32 snapl;  /* Snapshot low */
+   u32 snaph;  /* Snapshot high */
+};
+
+/* status register */
+#define NIOS_TIMER_TO  (1 << 0)  /* Timeout */
+#define NIOS_TIMER_RUN (1 << 1)  /* Timer running */
+
+/* control register */
+#define NIOS_TIMER_ITO (1 << 0)  /* Timeout int ena */
+#define NIOS_TIMER_CONT(1 << 1)  /* Continuous mode */
+#define NIOS_TIMER_START   (1 << 2)  /* Start timer */
+#define NIOS_TIMER_STOP(1 << 3)  /* Stop timer */
+
+#if defined(CONFIG_SYS_TIMER_BASE) && !defined(CONFIG_SYS_TIMER_IRQ)
+#error CONFIG_SYS_TIMER_IRQ not defined (see documentation)
+#endif


Since the timer interrupt is removed, there is no need to perform the check.

Best regards,
Thomas Chou
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[U-Boot] [PATCH v2 1/6] am335x_evm: prepare for eth driver model support

[Mugunthan V N]

Prepare board file so that ethernet registration are
commented for DM conversion

Signed-off-by: Mugunthan V N 
Reviewed-by: Tom Rini 
---
 board/ti/am335x/board.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 1dc2ed0..f0cb1e2 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,7 +38,10 @@ DECLARE_GLOBAL_DATA_PTR;
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN7
 
+#if defined(CONFIG_SPL_BUILD) || \
+   (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
 
 /*
  * Read header information from EEPROM into global structure.
@@ -513,6 +516,8 @@ int board_late_init(void)
 }
 #endif
 
+#ifndef CONFIG_DM_ETH
+
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
@@ -670,3 +675,5 @@ int board_eth_init(bd_t *bis)
return n;
 }
 #endif
+
+#endif /* CONFIG_DM_ETH */
-- 
2.6.0.rc0.24.gec371ff

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[U-Boot] [PATCH v2 0/6] device model bringup of cpsw on am335x bone black

[Mugunthan V N]

This patch seires enables cpsw to adopt driver model. This has
been tested on AM335x beagle bone black and GP EVM (logs [1]).
Also pushed a branch for testing [2]

This patch depends on [3] for getting cpsw address space from DT

[1]: http://pastebin.ubuntu.com/12305998/
[2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git 
cpsw-dt-conversion-v2
[3]: http://patchwork.ozlabs.org/patch/504918/

Changes from initial version:
* Dropped "drivers: of: add support for get device address based on index"
  and used http://patchwork.ozlabs.org/patch/504918/ as it fixes the same
* Added AM335x GP EVM also with the series.

Mugunthan V N (6):
  am335x_evm: prepare for eth driver model support
  am335x_evm: do not define usb ether gadget when Eth DM is defined
  drivers: net: cpsw: prepare driver for device model migration
  drivers: net: cpsw: convert driver to adopt device driver model
  defconfig: am335x: bbb: enable ethernet driver model
  defconfig: am335x: gp_evm: enable ethernet driver model

 board/ti/am335x/board.c  |   7 +
 configs/am335x_boneblack_vboot_defconfig |   1 +
 configs/am335x_gp_evm_defconfig  |   1 +
 drivers/net/cpsw.c   | 378 +++
 include/configs/am335x_evm.h |   3 +
 include/cpsw.h   |   2 +
 6 files changed, 347 insertions(+), 45 deletions(-)

-- 
2.6.0.rc0.24.gec371ff

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[U-Boot] [PATCH v2 2/6] am335x_evm: do not define usb ether gadget when Eth DM is defined

[Mugunthan V N]

Since usb ether gadget doesn't have support for driver model, so
not defining usb ether gadget when ethernet driver model is
defined.

Signed-off-by: Mugunthan V N 
Reviewed-by: Tom Rini 
---
 include/configs/am335x_evm.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e89c49e..56de3d4 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -315,9 +315,12 @@
 #endif
 
 #ifdef CONFIG_USB_MUSB_GADGET
+/* Removing USB gadget and can be enabled adter adding support usb DM */
+#ifndef CONFIG_DM_ETH
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_HOST_ADDR"de:ad:be:af:00:00"
+#endif /* CONFIG_DM_ETH */
 
 /* USB TI's IDs */
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
-- 
2.6.0.rc0.24.gec371ff

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[U-Boot] [PATCH v2 4/6] drivers: net: cpsw: convert driver to adopt device driver model

[Mugunthan V N]

adopt cpsw driver to device driver model

Signed-off-by: Mugunthan V N 
Reviewed-by: Simon Glass 
---
 drivers/net/cpsw.c | 245 -
 include/cpsw.h |   2 +
 2 files changed, 246 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index a114d4d..3dff9df 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -25,6 +25,9 @@
 #include 
 #include 
 #include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define BITMASK(bits)  (BIT(bits) - 1)
 #define PHY_REG_MASK   0x1f
@@ -37,6 +40,23 @@
 #define FULLDUPLEXEN   BIT(0)
 #define MIIEN  BIT(15)
 
+/* reg offset */
+#define CPSW_HOST_PORT_OFFSET  0x108
+#define CPSW_SLAVE0_OFFSET 0x208
+#define CPSW_SLAVE1_OFFSET 0x308
+#define CPSW_SLAVE_SIZE0x100
+#define CPSW_CPDMA_OFFSET  0x800
+#define CPSW_HW_STATS  0x900
+#define CPSW_STATERAM_OFFSET   0xa00
+#define CPSW_CPTS_OFFSET   0xc00
+#define CPSW_ALE_OFFSET0xd00
+#define CPSW_SLIVER0_OFFSET0xd80
+#define CPSW_SLIVER1_OFFSET0xdc0
+#define CPSW_BD_OFFSET 0x2000
+#define CPSW_MDIO_DIV  0xff
+
+#define AM335X_GMII_SEL_OFFSET 0x630
+
 /* DMA Registers */
 #define CPDMA_TXCONTROL0x004
 #define CPDMA_RXCONTROL0x014
@@ -218,7 +238,11 @@ struct cpdma_chan {
(priv)->data.slaves; slave++)
 
 struct cpsw_priv {
+#ifdef CONFIG_DM_ETH
+   struct udevice  *dev;
+#else
struct eth_device   *dev;
+#endif
struct cpsw_platform_data   data;
int host_port;
 
@@ -522,7 +546,7 @@ static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, 
int dev_addr,
return 0;
 }
 
-static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
+static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
 {
struct mii_dev *bus = mdio_alloc();
 
@@ -563,8 +587,15 @@ static inline void setbit_and_wait_for_clear32(void *addr)
 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
   struct cpsw_priv *priv)
 {
+#ifdef CONFIG_DM_ETH
+   struct eth_pdata *pdata = dev_get_platdata(priv->dev);
+
+   writel(mac_hi(pdata->enetaddr), >regs->sa_hi);
+   writel(mac_lo(pdata->enetaddr), >regs->sa_lo);
+#else
__raw_writel(mac_hi(priv->dev->enetaddr), >regs->sa_hi);
__raw_writel(mac_lo(priv->dev->enetaddr), >regs->sa_lo);
+#endif
 }
 
 static void cpsw_slave_update_link(struct cpsw_slave *slave,
@@ -973,6 +1004,7 @@ int _cpsw_register(struct cpsw_priv *priv)
return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 {
struct cpsw_priv*priv = dev->priv;
@@ -1049,3 +1081,214 @@ int cpsw_register(struct cpsw_platform_data *data)
 
return 1;
 }
+#else
+static int cpsw_eth_start(struct udevice *dev)
+{
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   return _cpsw_init(priv, pdata->enetaddr);
+}
+
+static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
+{
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   return _cpsw_send(priv, packet, length);
+}
+
+static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   return _cpsw_recv(priv, packetp);
+}
+
+static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
+  int length)
+{
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   return cpdma_submit(priv, >rx_chan, packet, PKTSIZE);
+}
+
+static void cpsw_eth_stop(struct udevice *dev)
+{
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   return _cpsw_halt(priv);
+}
+
+
+static int cpsw_eth_probe(struct udevice *dev)
+{
+   struct cpsw_priv *priv = dev_get_priv(dev);
+
+   priv->dev = dev;
+
+   return _cpsw_register(priv);
+}
+
+static const struct eth_ops cpsw_eth_ops = {
+   .start  = cpsw_eth_start,
+   .send   = cpsw_eth_send,
+   .recv   = cpsw_eth_recv,
+   .free_pkt   = cpsw_eth_free_pkt,
+   .stop   = cpsw_eth_stop,
+};
+
+static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
+{
+   struct eth_pdata *pdata = dev_get_platdata(dev);
+   struct cpsw_priv *priv = dev_get_priv(dev);
+   const char *phy_mode;
+   const void *fdt = gd->fdt_blob;
+   int node = dev->of_offset;
+   int subnode;
+   int slave_index = 0;
+   uint32_t mac_hi, mac_lo;
+   fdt32_t gmii = 0;
+   int active_slave;
+
+   pdata->iobase = dev_get_addr(dev);
+   priv->data.version = CPSW_CTRL_VERSION_2;
+   priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
+   priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
+   

[U-Boot] [PATCH v2 6/6] defconfig: am335x: gp_evm: enable ethernet driver model

[Mugunthan V N]

enable ethernet driver model for am335x gp evm as cpsw supports
driver model

Signed-off-by: Mugunthan V N 
---
 configs/am335x_gp_evm_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 62d3b6b..c87d7a9 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -12,3 +12,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_SPL_DISABLE_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
 CONFIG_RSA=y
+CONFIG_DM_ETH=y
-- 
2.6.0.rc0.24.gec371ff

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[U-Boot] [PATCH v2 5/6] defconfig: am335x: bbb: enable ethernet driver model

[Mugunthan V N]

enable ethernet driver model for am335x beagle bone black as cpsw
supports driver model

Signed-off-by: Mugunthan V N 
Reviewed-by: Tom Rini 
---
 configs/am335x_boneblack_vboot_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am335x_boneblack_vboot_defconfig 
b/configs/am335x_boneblack_vboot_defconfig
index b52ddfd..117a146 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -13,3 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
-- 
2.6.0.rc0.24.gec371ff

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Re: [U-Boot] [PATCH v2 0/8] nios2: add device tree control of U-Boot

[Ley Foon Tan]

On Sab, 2015-09-05 at 11:20 +0800, Thomas Chou wrote:
> Hi Marek,
> 
> On 09/04/2015 10:04 PM, Marek Vasut wrote:
> > I can start picking the NIOS2 stuff into U-Boot as well if you want.
> 
> That's great! You are very kind and responsive. Thanks a lot. You can 
> take over the custodianship of nios2 arch. Then I will be retired. :)
Added Altera socfpga U-boot owner in CC list. 
> 
> BTW, please also look over the earlier patches,
> 
> [PATCH] nios2: move command line configuration to Kconfig, Aug,28
> [PATCH] nios2: enable CONFIG_NET_RANDOM_ETHADDR, Aug,29
> And perhaps,
> [PATCH] mmc_spi: fix big-endian support error on be_to_cpu16, Aug,31
> 
> Cheers,
> Thomas Chou

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[U-Boot] [PATCH 0/2] igep00x0: standardize boot commmands

[Enric Balletbo i Serra]

Hi,

Please consider adding these two patches. I saw that I missed some emails
because my MAINTAINERS address was obsolete, so the first patch only updates
my email. The second one switches igep00x0 to use generic distro configuration
and environment instead of custom boot commands to be more generic.

Best regards,

Enric Balletbo i Serra (2):
  igep00xx: MAINTAINERS: update eballetbo's email address.
  igep00x0: Switch to use the generic distro configuration and
environment.

 board/isee/igep0033/MAINTAINERS  |  2 +-
 board/isee/igep00x0/MAINTAINERS  |  2 +-
 board/isee/igep00x0/igep00x0.c   |  4 +-
 include/configs/omap3_igep00x0.h | 95 
 4 files changed, 32 insertions(+), 71 deletions(-)

-- 
2.1.0

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[U-Boot] [PATCH 2/2] imx: mx6 discard 'select CPU_V7' for different targets

[Peng Fan]

Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/Kconfig | 24 
 1 file changed, 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index b3f7eaf..0b02e9e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,19 +35,15 @@ choice
 
 config TARGET_ARISTAINETOS
bool "aristainetos"
-   select CPU_V7
 
 config TARGET_ARISTAINETOS2
bool "aristainetos2"
-   select CPU_V7
 
 config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
-   select CPU_V7
 
 config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
-   select CPU_V7
 
 config TARGET_CM_FX6
bool "CM-FX6"
@@ -58,48 +54,39 @@ config TARGET_CM_FX6
 
 config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
-   select CPU_V7
 
 config TARGET_GW_VENTANA
bool "gw_ventana"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_MX6QARM2
bool "mx6qarm2"
-   select CPU_V7
 
 config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
-   select CPU_V7
select DM
select DM_THERMAL
 
 config TARGET_MX6SABRESD
bool "mx6sabresd"
-   select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
 
 config TARGET_MX6SLEVK
bool "mx6slevk"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
-   select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
@@ -107,7 +94,6 @@ config TARGET_MX6SXSABRESD
 config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select MX6UL
-   select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
@@ -115,28 +101,23 @@ config TARGET_MX6UL_9X9_EVK
 config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select MX6UL
-   select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
 
 config TARGET_NITROGEN6X
bool "nitrogen6x"
-   select CPU_V7
 
 config TARGET_OT1200
bool "Bachmann OT1200"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_PLATINUM_PICON
bool "platinum-picon"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_SECOMX6
@@ -144,28 +125,23 @@ config TARGET_SECOMX6
 
 config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
-   select CPU_V7
 
 config TARGET_TITANIUM
bool "titanium"
-   select CPU_V7
 
 config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
 
 config TARGET_UDOO
bool "udoo"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_WANDBOARD
bool "wandboard"
-   select CPU_V7
select SUPPORT_SPL
 
 config TARGET_WARP
bool "WaRP"
-   select CPU_V7
 
 endchoice
 
-- 
1.8.4


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[U-Boot] [PATCH 1/2] mx6: remove SYS_SOC from board Kconfig

[Peng Fan]

Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Heiko Schocher 
Cc: Christian Gmeiner 
Cc: Stefan Roese 
Cc: Troy Kisky 
Cc: Nikita Kiryanov 
Cc: "Eric Bénard" 
Cc: Fabio Estevam 
Cc: Tim Harvey 
Cc: Marek Vasut 
Cc: Markus Niebel 
Cc: Otavio Salvador 
---
 board/aristainetos/Kconfig  | 9 -
 board/bachmann/ot1200/Kconfig   | 3 ---
 board/barco/platinum/Kconfig| 6 --
 board/barco/titanium/Kconfig| 3 ---
 board/boundary/nitrogen6x/Kconfig   | 3 ---
 board/compulab/cm_fx6/Kconfig   | 3 ---
 board/congatec/cgtqmx6eval/Kconfig  | 3 ---
 board/embest/mx6boards/Kconfig  | 3 ---
 board/freescale/mx6qarm2/Kconfig| 3 ---
 board/freescale/mx6qsabreauto/Kconfig   | 3 ---
 board/freescale/mx6sabresd/Kconfig  | 3 ---
 board/freescale/mx6slevk/Kconfig| 3 ---
 board/freescale/mx6sxsabresd/Kconfig| 3 ---
 board/freescale/mx6ul_14x14_evk/Kconfig | 3 ---
 board/gateworks/gw_ventana/Kconfig  | 3 ---
 board/kosagi/novena/Kconfig | 3 ---
 board/solidrun/mx6cuboxi/Kconfig| 3 ---
 board/tqc/tqma6/Kconfig | 3 ---
 board/udoo/Kconfig  | 3 ---
 board/wandboard/Kconfig | 3 ---
 board/warp/Kconfig  | 3 ---
 21 files changed, 72 deletions(-)

diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index e987f38..e416c9a 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -3,9 +3,6 @@ if TARGET_ARISTAINETOS
 config SYS_BOARD
default "aristainetos"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "aristainetos"
 
@@ -16,9 +13,6 @@ if TARGET_ARISTAINETOS2
 config SYS_BOARD
default "aristainetos"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "aristainetos2"
 
@@ -29,9 +23,6 @@ if TARGET_ARISTAINETOS2B
 config SYS_BOARD
default "aristainetos"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "aristainetos2b"
 
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
index 7f8a6a1..4ccb60a 100644
--- a/board/bachmann/ot1200/Kconfig
+++ b/board/bachmann/ot1200/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
default "bachmann"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "ot1200"
 
diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig
index 8bbad24..cc0648c 100644
--- a/board/barco/platinum/Kconfig
+++ b/board/barco/platinum/Kconfig
@@ -6,9 +6,6 @@ config SYS_CPU
 config SYS_VENDOR
default "barco"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_BOARD
default "platinum"
 
@@ -25,9 +22,6 @@ config SYS_CPU
 config SYS_VENDOR
default "barco"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_BOARD
default "platinum"
 
diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig
index b6f7c85..21bc36e 100644
--- a/board/barco/titanium/Kconfig
+++ b/board/barco/titanium/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
default "barco"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "titanium"
 
diff --git a/board/boundary/nitrogen6x/Kconfig 
b/board/boundary/nitrogen6x/Kconfig
index 03b0f6f..f4db56d 100644
--- a/board/boundary/nitrogen6x/Kconfig
+++ b/board/boundary/nitrogen6x/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
default "boundary"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "nitrogen6x"
 
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
index 508c21f..59070c5 100644
--- a/board/compulab/cm_fx6/Kconfig
+++ b/board/compulab/cm_fx6/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
default "compulab"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "cm_fx6"
 
diff --git a/board/congatec/cgtqmx6eval/Kconfig 
b/board/congatec/cgtqmx6eval/Kconfig
index 0a837bd..773551b 100644
--- a/board/congatec/cgtqmx6eval/Kconfig
+++ b/board/congatec/cgtqmx6eval/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
default "congatec"
 
-config SYS_SOC
-   default "mx6"
-
 config SYS_CONFIG_NAME
default "cgtqmx6eval"
 
diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig
index 53a39d3..24d01f2 100644
--- a/board/embest/mx6boards/Kconfig
+++ b/board/embest/mx6boards/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config 

[U-Boot] [PATCH V3] mtd: nand: mxs check maximum ecc that platfrom supports

[Peng Fan]

Check maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.

Signed-off-by: Peng Fan 
Signed-off-by: Han Xu 
Tested-By: Tim Harvey 
Reviewed-by: Marek Vasut 
Acked-by: Scott Wood 
Cc: Stefano Babic 
---

Original V2 mail thread:
http://lists.denx.de/pipermail/u-boot/2015-August/225362.html

Because is_cpu_type was not merged to uboot upstream at that time,
this patch can not be compiled successfully. Since now is_cpu_type
is already in uboot upstream master branch, this patch can be applied
and built without failure.

Changes v3:
 Add Scott's Acked by
 Add Tim's Tested by

Changes v2:
 Add Marek's reviewed by.

 drivers/mtd/nand/mxs_nand.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 1d68901..f15cf36 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -149,6 +149,13 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t 
page_data_size,
uint32_t page_oob_size)
 {
int ecc_strength;
+   int max_ecc_strength_supported;
+
+   /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
+   if (is_cpu_type(MXC_CPU_MX6SX))
+   max_ecc_strength_supported = 62;
+   else
+   max_ecc_strength_supported = 40;
 
/*
 * Determine the ECC layout with the formula:
@@ -162,7 +169,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t 
page_data_size,
/ (galois_field *
   mxs_nand_ecc_chunk_cnt(page_data_size));
 
-   return round_down(ecc_strength, 2);
+   return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
 }
 
 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
-- 
1.8.4


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[U-Boot] [PATCH v2 3/6] drivers: net: cpsw: prepare driver for device model migration

[Mugunthan V N]

prepare driver for device model migration

Signed-off-by: Mugunthan V N 
Reviewed-by: Simon Glass 
---
 drivers/net/cpsw.c | 133 +++--
 1 file changed, 89 insertions(+), 44 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index fb4d621..a114d4d 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -745,9 +745,8 @@ static int cpdma_process(struct cpsw_priv *priv, struct 
cpdma_chan *chan,
return 0;
 }
 
-static int cpsw_init(struct eth_device *dev, bd_t *bis)
+static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 {
-   struct cpsw_priv*priv = dev->priv;
struct cpsw_slave   *slave;
int i, ret;
 
@@ -772,8 +771,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
 
cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 
-   cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
-  ALE_SECURE);
+   cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 
for_active_slave(slave, priv)
@@ -857,10 +855,8 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
return 0;
 }
 
-static void cpsw_halt(struct eth_device *dev)
+static void _cpsw_halt(struct cpsw_priv *priv)
 {
-   struct cpsw_priv*priv = dev->priv;
-
writel(0, priv->dma_regs + CPDMA_TXCONTROL);
writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 
@@ -870,12 +866,10 @@ static void cpsw_halt(struct eth_device *dev)
/* clear dma state */
setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 
-   priv->data.control(0);
 }
 
-static int cpsw_send(struct eth_device *dev, void *packet, int length)
+static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 {
-   struct cpsw_priv*priv = dev->priv;
void *buffer;
int len;
int timeout = CPDMA_TIMEOUT;
@@ -896,20 +890,21 @@ static int cpsw_send(struct eth_device *dev, void 
*packet, int length)
return cpdma_submit(priv, >tx_chan, packet, length);
 }
 
-static int cpsw_recv(struct eth_device *dev)
+static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 {
-   struct cpsw_priv*priv = dev->priv;
void *buffer;
int len;
+   int ret = -EAGAIN;
 
-   while (cpdma_process(priv, >rx_chan, , ) >= 0) {
-   invalidate_dcache_range((unsigned long)buffer,
-   (unsigned long)buffer + PKTSIZE_ALIGN);
-   net_process_received_packet(buffer, len);
-   cpdma_submit(priv, >rx_chan, buffer, PKTSIZE);
-   }
+   ret = cpdma_process(priv, >rx_chan, , );
+   if (ret < 0)
+   return ret;
 
-   return 0;
+   invalidate_dcache_range((unsigned long)buffer,
+   (unsigned long)buffer + PKTSIZE_ALIGN);
+   *pkt = buffer;
+
+   return len;
 }
 
 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
@@ -923,15 +918,14 @@ static void cpsw_slave_setup(struct cpsw_slave *slave, 
int slave_num,
slave->sliver   = regs + data->sliver_reg_ofs;
 }
 
-static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
+static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 {
-   struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
 
phydev = phy_connect(priv->bus,
slave->data->phy_addr,
-   dev,
+   priv->dev,
slave->data->phy_if);
 
if (!phydev)
@@ -946,30 +940,14 @@ static int cpsw_phy_init(struct eth_device *dev, struct 
cpsw_slave *slave)
return 1;
 }
 
-int cpsw_register(struct cpsw_platform_data *data)
+int _cpsw_register(struct cpsw_priv *priv)
 {
-   struct cpsw_priv*priv;
struct cpsw_slave   *slave;
+   struct cpsw_platform_data *data = >data;
void*regs = (void *)data->cpsw_base;
-   struct eth_device   *dev;
-
-   dev = calloc(sizeof(*dev), 1);
-   if (!dev)
-   return -ENOMEM;
-
-   priv = calloc(sizeof(*priv), 1);
-   if (!priv) {
-   free(dev);
-   return -ENOMEM;
-   }
-
-   priv->data = *data;
-   priv->dev = dev;
 
priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
if (!priv->slaves) {
-   free(dev);
-   free(priv);
return -ENOMEM;
}
 
@@ -987,6 +965,70 @@ int cpsw_register(struct cpsw_platform_data *data)
idx = idx + 1;
}
 
+   cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
+   priv->bus = miiphy_get_dev_by_name(priv->dev->name);
+  

Re: [U-Boot] [PATCH] fdt: add new fdt address parsing functions

[Mugunthan V N]

On Friday 07 August 2015 03:01 AM, Stephen Warren wrote:
> From: Stephen Warren 
> 
> fdtdec_get_addr_size() hard-codes the number of cells used to represent
> an address or size in DT. This is incorrect in many cases depending on
> the DT binding for a particular node or property (e.g. it is incorrect
> for the "reg" property). In most cases, DT parsing code must use the
> properties #address-cells and #size-cells to parse addres properties.
> 
> This change splits up the implementation of fdtdec_get_addr_size() so
> that the core logic can be used for both hard-coded and non-hard-coded
> cases. Various wrapper functions are implemented that support cases
> where hard-coded cell counts should or should not be used, and where
> the client does and doesn't know the parent node ID that contains the
> properties #address-cells and #size-cells.
> 
> dev_get_addr() is updated to use the new functions.
> 
> Core functionality in fdtdec_get_addr_size_fixed() is widely tested via
> fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and
> dev_get_addr() by manually modifying the Tegra I2C driver to invoke them.
> 
> Much of the core implementation of fdtdec_get_addr_size_fixed(),
> fdtdec_get_addr_size_auto_parent(), and
> fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's
> previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit".

Tested this patch for cpsw ethernet dt migration to getting cpsw address
space. Also dropped *#define DEBUG* in lib/fdtdev.c file.

Tested-by: Mugunthan V N 

Regards
Mugunthan V N
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Re: [U-Boot] [PATCH v4 1/4] bitops: introduce BIT() definition

[Andreas Bießmann]

On 08/21/2015 07:01 PM, Heiko Schocher wrote:
> introduce BIT() definition, used in at91_udc gadget
> driver.
> 
> Signed-off-by: Heiko Schocher 
> 

NAK, this one breaks a lot of boards which already defined BIT()

> ---
> 
> Changes in v4: None
> Changes in v3:
> - new in v3
> 
> Changes in v2: None
> 
>  include/linux/bitops.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/bitops.h b/include/linux/bitops.h
> index e724310..7d30ace 100644
> --- a/include/linux/bitops.h
> +++ b/include/linux/bitops.h
> @@ -3,6 +3,8 @@
>  
>  #include 
>  
> +#define BIT(nr)  (1UL << (nr))
> +
>  /*
>   * ffs: find first bit set. This is defined the same way as
>   * the libc and compiler builtin ffs routines, therefore
> 

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Re: [U-Boot] [PATCH v2 4/8] nios2: enlarge the code relocation range

[Marek Vasut]

On Monday, September 07, 2015 at 03:47:46 AM, Thomas Chou wrote:
> Hi Marek,

Hi!

> On 09/07/2015 08:53 AM, Marek Vasut wrote:
> > Where did that 64KB figure come from ? :O
> 
> This is estimated from 41KB of the SPL of socfpga. The code density of
> nios2 is worse than ARM.
> 
> > I assume the simple loader is just a copy loop, huh ? And you synthesise
> > a small RAM or ROM into the FPGA and point NIOS to boot from that, right?
> 
> Right. It is hidden from the user in qsys. You will need to dig into the
> code to find out. The EPCS boot copier is coded in nios2 ASM.

Oh, I see.

> > What about U-Boot TPL, can that cook the loader ? (yes, I'd like to be as
> > independent of the external code as possible).
> 
> I'd like to be independent of the external code, too. In the past, I
> have my own SPI core (now the oc_tiny_spi) to control EPCS, which is
> actually SPI flash, and my own boot copier with/out decompression.
> 
> It is possible to add an TPL support for nios2 EPCS. If someone want to
> work on it.. :)

I'll keep this in mind, thanks :)

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] mx6: remove SYS_SOC from board Kconfig

[Marek Vasut]

On Monday, September 07, 2015 at 11:20:03 AM, Stefan Roese wrote:
> On 07.09.2015 08:59, Peng Fan wrote:
> > Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
> > because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.
> > 
> > Signed-off-by: Peng Fan 
> > Cc: Stefano Babic 
> > Cc: Heiko Schocher 
> > Cc: Christian Gmeiner 
> > Cc: Stefan Roese 
> > Cc: Troy Kisky 
> > Cc: Nikita Kiryanov 
> > Cc: "Eric Bénard" 
> > Cc: Fabio Estevam 
> > Cc: Tim Harvey 
> > Cc: Marek Vasut 
> > Cc: Markus Niebel 
> > Cc: Otavio Salvador 
> 
> For the board I maintain:
> 
> Acked-by: Stefan Roese 

For Novena:

Acked-by: Marek Vasut 

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v4 0/7] nios2: add device tree control of U-Boot

[Marek Vasut]

On Monday, September 07, 2015 at 03:03:19 AM, Thomas Chou wrote:
> These patches add device tree control of U-Boot to nios2 boards.
> 
> v2
>   use SPDX license header.
>   use fdt relocation in board_init_f.
> v3
>   fix comment style.
> v4
>   drop fdt_blob print in board info, which needs more discussion.
> 
> Thomas Chou (7):
>   nios2: permit device tree control of U-Boot
>   nios2: move altera_pio_init to board_early_init_r
>   nios2: BSS should be cleared only after board_init_f
>   nios2: enlarge the code relocation range
>   nios2: remove gp assignments in link script
>   nios2: define _end in link script
>   nios2: enable device tree control of U-Boot

Hi,

Nice, I like seeing how NIOS2 getting back to shape. btw you could have
waited a few days before applying patches that were just posted.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] nios2: enable Driver Model

[Thomas Chou]

On 09/07/2015 10:49 AM, Thomas Chou wrote:

Enable the Driver Model config. The driver subsystems
are not enabled until we enable each of them.

Signed-off-by: Thomas Chou 
---
  configs/nios2-generic_defconfig | 2 ++
  1 file changed, 2 insertions(+)


Applied to u-boot-nios.
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Re: [U-Boot] [PATCH v4 1/4] bitops: introduce BIT() definition

[Heiko Schocher]

Hello Andreas,

Am 07.09.2015 um 13:20 schrieb Andreas Bießmann:

On 08/21/2015 07:01 PM, Heiko Schocher wrote:

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher 



NAK, this one breaks a lot of boards which already defined BIT()


Uhh... seems this BIT() macro is a big mess ...

Hmm Wolfgang Denk NACKed a similiar patch:
http://lists.denx.de/pipermail/u-boot/2014-February/173669.html

In drivers/usb/gadget/at91_udc.c BIT(x) is used only once...
So I fix it there and use (1 << x) there. Would be this OK?

bye,
Heiko



---

Changes in v4: None
Changes in v3:
- new in v3

Changes in v2: None

  include/linux/bitops.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index e724310..7d30ace 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -3,6 +3,8 @@

  #include 

+#define BIT(nr)(1UL << (nr))
+
  /*
   * ffs: find first bit set. This is defined the same way as
   * the libc and compiler builtin ffs routines, therefore





--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH v4 1/4] bitops: introduce BIT() definition

[Andreas Bießmann]

Hi Heiko,

On 2015-09-07 13:52, Heiko Schocher wrote:

Hello Andreas,

Am 07.09.2015 um 13:20 schrieb Andreas Bießmann:

On 08/21/2015 07:01 PM, Heiko Schocher wrote:

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher 



NAK, this one breaks a lot of boards which already defined BIT()


Uhh... seems this BIT() macro is a big mess ...

Hmm Wolfgang Denk NACKed a similiar patch:
http://lists.denx.de/pipermail/u-boot/2014-February/173669.html

In drivers/usb/gadget/at91_udc.c BIT(x) is used only once...
So I fix it there and use (1 << x) there. Would be this OK?


I'm fine with this solution.

Andreas



bye,
Heiko



---

Changes in v4: None
Changes in v3:
- new in v3

Changes in v2: None

  include/linux/bitops.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index e724310..7d30ace 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -3,6 +3,8 @@

  #include 

+#define BIT(nr)(1UL << (nr))
+
  /*
   * ffs: find first bit set. This is defined the same way as
   * the libc and compiler builtin ffs routines, therefore





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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:

  doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git 

for you to fetch changes up to a7ed0ac2620b00c6eb85227f3c66bc169ad11f44:

  net: altera_tse: Zap unused variable (2015-09-04 16:09:44 +0200)


Dinh Nguyen (1):
  arm: socfpga: Add support for the Terasic DE-0 Atlas board

Marek Vasut (8):
  mmc: dw_mmc: Probe the MMC from OF
  arm: socfpga: Assure ISWGRP 0 and 1 are inited
  arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROL
  arm: socfpga: Zap OF_CONTROL checks, it's always enabled
  arm: socfpga: Do not call board_init_r() from board_init_f()
  arm: socfpga: Add support for Terasic SoCkit board
  arm: socfpga: Add support for DENX MCV SoM and MCVEVK board
  net: altera_tse: Zap unused variable

 arch/arm/Kconfig   |   2 +
 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts |  61 +
 arch/arm/dts/socfpga_cyclone5_mcvevk.dts   |  53 
 arch/arm/dts/socfpga_cyclone5_sockit.dts   |  92 +
 arch/arm/mach-socfpga/Kconfig  |  21 +++
 arch/arm/mach-socfpga/include/mach/dwmmc.h |   2 +-
 arch/arm/mach-socfpga/misc.c   |   9 +-
 arch/arm/mach-socfpga/reset_manager.c  |   8 +-
  
 arch/arm/mach-socfpga/spl.c|   2 - 
  
 board/denx/mcvevk/MAINTAINERS  |   5 + 
  
 board/denx/mcvevk/Makefile |   9 ++
  
 board/denx/mcvevk/qts/iocsr_config.h   | 660 
+++
 
 board/denx/mcvevk/qts/pinmux_config.h  | 219 
++  

 board/denx/mcvevk/qts/pll_config.h |  85   
  
 board/denx/mcvevk/qts/sdram_config.h   | 341 
+++ 

 board/denx/mcvevk/socfpga.c|  45 +++
 board/terasic/de0-nano-soc/MAINTAINERS |   5 +
 board/terasic/de0-nano-soc/Makefile|   9 ++
 board/terasic/de0-nano-soc/qts/iocsr_config.h  | 658 
++
 board/terasic/de0-nano-soc/qts/pinmux_config.h | 220 
+++
 board/terasic/de0-nano-soc/qts/pll_config.h|  85 
 board/terasic/de0-nano-soc/qts/sdram_config.h  | 342 
+++
 board/terasic/de0-nano-soc/socfpga.c   |  72 ++
 board/terasic/sockit/MAINTAINERS   |   5 +
 board/terasic/sockit/Makefile  |   9 ++
 board/terasic/sockit/qts/iocsr_config.h| 660 
+++
 board/terasic/sockit/qts/pinmux_config.h   | 219 
++
 board/terasic/sockit/qts/pll_config.h  |  85 
 board/terasic/sockit/qts/sdram_config.h| 341 
+++
 board/terasic/sockit/socfpga.c |  85 
 configs/socfpga_de0_nano_soc_defconfig |  20 +++
 configs/socfpga_mcvevk_defconfig   |  21 +++
 configs/socfpga_sockit_defconfig   |  26 
 drivers/mmc/socfpga_dw_mmc.c   |  81 ++--
 drivers/net/altera_tse.c   |   2 -
 include/configs/socfpga_common.h   |   7 +-
 include/configs/socfpga_de0_nano_soc.h |  87 
 include/configs/socfpga_mcvevk.h   | 132 +++
 include/configs/socfpga_sockit.h   |  92 +
 include/fdtdec.h   |   1 +
 lib/fdtdec.c   |   1 +
 42 files changed, 4851 insertions(+), 31 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
 create mode 100644 arch/arm/dts/socfpga_cyclone5_mcvevk.dts
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit.dts
 create mode 100644 board/denx/mcvevk/MAINTAINERS
 create mode 100644 board/denx/mcvevk/Makefile
 create mode 100644 board/denx/mcvevk/qts/iocsr_config.h
 create mode 100644 

Re: [U-Boot] [PATCH v4 1/4] bitops: introduce BIT() definition

[Marek Vasut]

On Monday, September 07, 2015 at 02:01:11 PM, Andreas Bießmann wrote:
> Hi Heiko,
> 
> On 2015-09-07 13:52, Heiko Schocher wrote:
> > Hello Andreas,
> > 
> > Am 07.09.2015 um 13:20 schrieb Andreas Bießmann:
> >> On 08/21/2015 07:01 PM, Heiko Schocher wrote:
> >>> introduce BIT() definition, used in at91_udc gadget
> >>> driver.
> >>> 
> >>> Signed-off-by: Heiko Schocher 
> >> 
> >> NAK, this one breaks a lot of boards which already defined BIT()
> > 
> > Uhh... seems this BIT() macro is a big mess ...
> > 
> > Hmm Wolfgang Denk NACKed a similiar patch:
> > http://lists.denx.de/pipermail/u-boot/2014-February/173669.html
> > 
> > In drivers/usb/gadget/at91_udc.c BIT(x) is used only once...
> > So I fix it there and use (1 << x) there. Would be this OK?
> 
> I'm fine with this solution.

On the other hand, mainline Linux is moving towards GENMASK() and BIT(),
so we should probably go with that as well.

Best regards,
Marek Vasut
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[U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:

  doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git 

for you to fetch changes up to 49b4c5c700077e387fef61a7225f92d190ee0c45:

  usb: ehci: remember init mode (2015-09-07 13:41:05 +0200)


Jiandong Zheng (1):
  implement Fastboot via USB OTG on bcm28155_ap boards

Kishon Vijay Abraham I (1):
  h2200: Fix build error

Lukasz Majewski (11):
  dfu:tests: Modify dfu_gadget_test.sh to accept USB device vendor:product 
ID
  dfu: Delete superfluous initialization of the dfu_buf_size static variable
  doc: dfu: tftp: README entry for TFTP extension of DFU
  net: tftp: Move tftp.h file from ./net to ./include/net
  tftp: update: Allow some parts of the code to be reused when 
CONFIG_SYS_NO_FLASH is set
  dfu: tftp: update: Provide tftp support for the DFU subsystem
  dfu: tftp: update: Add dfu_write_from_mem_addr() function
  update: tftp: dfu: Extend update_tftp() function to support DFU
  dfu: command: Extend "dfu" command to handle receiving data via TFTP
  dfu: tftp: Kconfig: Add Kconfig entry for dfu tftp feature
  dfu: tftp: Kconfig: Enable DFU_TFTP support on the 
am335x_boneblack_defconfig

Siva Durga Prasad Paladugu (2):
  f_thor: Dont perform reset at the end of thor
  usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZE

Stephen Warren (1):
  usb: ehci: remember init mode

 board/h2200/h2200.c|  12 +++
 common/Makefile|   1 +
 common/cmd_dfu.c   |  20 ++
 common/cmd_fitupd.c|   2 +-
 common/main.c  |   2 +-
 common/update.c|  58 
+---
 configs/am335x_boneblack_defconfig |   1 +
 doc/README.dfutftp | 114 
+++
 doc/README.update  |   7 +++
 drivers/dfu/Kconfig|  10 +
 drivers/dfu/Makefile   |   1 +
 drivers/dfu/dfu.c  |  39 ++-
 drivers/dfu/dfu_tftp.c |  65 
+++
 drivers/usb/gadget/f_thor.c|   9 -
 drivers/usb/gadget/f_thor.h|   3 +++
 drivers/usb/host/ehci-hcd.c|   7 ++-
 drivers/usb/host/ehci.h|   1 +
 include/configs/bcm28155_ap.h  |  19 ++
 include/dfu.h  |  41 +
 include/net.h  |  14 +++--
 {net => include/net}/tftp.h|   0
 net/bootp.c|   2 +-
 net/net.c  |   2 +-
 net/rarp.c |   2 +-
 net/tftp.c |   2 +-
 test/dfu/README|   9 -
 test/dfu/dfu_gadget_test.sh|  18 ++---
 27 files changed, 426 insertions(+), 35 deletions(-)
 create mode 100644 doc/README.dfutftp
 create mode 100644 drivers/dfu/dfu_tftp.c
 rename {net => include/net}/tftp.h (100%)
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Re: [U-Boot] [PATCH 1/2] nios2: Switch to generic timer

[Marek Vasut]

On Saturday, September 05, 2015 at 02:10:37 AM, Thomas Chou wrote:
> Hi Marek,

Hi!

> On 09/04/2015 10:08 PM, Marek Vasut wrote:
> > I think I removed this led nonsense somewhere along the way indeed.
> > This is a timer code, not some LED blinking code afterall, so it
> > should not be poluted by such stuff.
> 
> I will look into this today. It was late last night.
> 
> > Where can I get this board btw? I've been using DE0-NANO for my NIOS
> > fiddling thus far.
> 
> There are LEDs on the DE0-nano. Did you try them?

Yes, but I didn't hook them up in this design experiment.

> The 3c120 dev board is a cycloneIII based dev board from Altera, which
> is used as the "golden hardware reference design" for nios2 linux
> development. It is a bit old though. Maybe you can ask one from Altera.
> 
> https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyc3.ht
> ml

Maybe, but it seems that NIOS is in good hands, so I might just be a casual
contributor here :)

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] nios2: Switch to generic timer

[Thomas Chou]

Hi Marek,

On 09/07/2015 05:32 PM, Marek Vasut wrote:

Could you please rebase and submit this series again?


Yes, that's my plan shortly. We're aiming for after 2015.10 release
with all these NIOS changes, so this is not urgent, right ?


Yes, they will be after 2015.10. No hurry. I just hope to set them down 
to u-boot-nios before I am distracted away. It will also help others to 
test more easily. :)


Best regards,
Thomas Chou
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[U-Boot] [PATCH V2 1/2] nios2: Switch to generic timer

[Marek Vasut]

Zap almost all of the ad-hoc timer code from interrupts.c and
use the code in lib/time.c instead.

Signed-off-by: Marek Vasut 
---
 arch/nios2/cpu/interrupts.c | 132 
 arch/nios2/lib/Makefile |   1 -
 arch/nios2/lib/time.c   |  22 ---
 common/board_f.c|   3 +-
 include/configs/nios2-generic.h |   9 +--
 5 files changed, 43 insertions(+), 124 deletions(-)
 delete mode 100644 arch/nios2/lib/time.c

V2: Rebase on top of u-boot/master

diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c
index 9d7e193..36d3ef7 100644
--- a/arch/nios2/cpu/interrupts.c
+++ b/arch/nios2/cpu/interrupts.c
@@ -8,7 +8,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-
 #include 
 #include 
 #include 
@@ -20,14 +19,14 @@
 #include 
 #endif
 
-typedef volatile struct {
-   unsignedstatus; /* Timer status reg */
-   unsignedcontrol;/* Timer control reg */
-   unsignedperiodl;/* Timeout period low */
-   unsignedperiodh;/* Timeout period high */
-   unsignedsnapl;  /* Snapshot low */
-   unsignedsnaph;  /* Snapshot high */
-} nios_timer_t;
+struct nios_timer {
+   u32 status; /* Timer status reg */
+   u32 control;/* Timer control reg */
+   u32 periodl;/* Timeout period low */
+   u32 periodh;/* Timeout period high */
+   u32 snapl;  /* Snapshot low */
+   u32 snaph;  /* Snapshot high */
+};
 
 /* status register */
 #define NIOS_TIMER_TO  (1 << 0)/* Timeout */
@@ -39,8 +38,8 @@ typedef volatile struct {
 #define NIOS_TIMER_START   (1 << 2)/* Start timer */
 #define NIOS_TIMER_STOP(1 << 3)/* Stop timer */
 
-#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
-#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
+#if defined(CONFIG_SYS_TIMER_BASE) && !defined(CONFIG_SYS_TIMER_IRQ)
+#error CONFIG_SYS_TIMER_IRQ not defined (see documentation)
 #endif
 
 //
@@ -54,80 +53,15 @@ struct  irq_action {
 static struct irq_action vecs[32];
 
 /*/
-volatile ulong timestamp = 0;
-
-void reset_timer (void)
-{
-   nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
-
-   /* From Embedded Peripherals Handbook:
-*
-* "When the hardware is configured with Writeable period
-* disabled, writing to one of the period_n registers causes
-* the counter to reset to the fixed Timeout Period specified
-* at system generation time."
-*
-* Here we force a reload to prevent early timeouts from
-* get_timer() when the interrupt period is greater than
-* than 1 msec.
-*
-* Simply write to periodl with its own value to force an
-* internal counter reload, THEN reset the timestamp.
-*/
-   writel (readl (>periodl), >periodl);
-   timestamp = 0;
-
-   /* From Embedded Peripherals Handbook:
-*
-* "Writing to one of the period_n registers stops the internal
-* counter, except when the hardware is configured with Start/Stop
-* control bits off. If Start/Stop control bits is off, writing
-* either register does not stop the counter."
-*
-* In order to accomodate either configuration, the control
-* register is re-written. If the counter is stopped, it will
-* be restarted. If it is running, the write is essentially
-* a nop.
-*/
-   writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
-   >control);
-
-}
-
-ulong get_timer (ulong base)
-{
-   WATCHDOG_RESET ();
-   return (timestamp - base);
-}
-
-/*
- * This function is derived from Blackfin code (read timebase as long long).
- * On Nios2 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-   return get_timer(0);
-}
+static volatile ulong timestamp;
 
 /*
- * This function is derived from Blackfin code.
- * On Nios2 it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-   ulong tbclk;
-
-   tbclk = CONFIG_SYS_HZ;
-   return tbclk;
-}
-
-/* The board must handle this interrupt if a timer is not
+ * The board must handle this interrupt if a timer is not
  * provided.
  */
-#if defined(CONFIG_SYS_NIOS_TMRBASE)
 void tmr_isr (void *arg)
 {
-   nios_timer_t *tmr = (nios_timer_t *)arg;
+   struct nios_timer *tmr = (struct nios_timer *)arg;
/* Interrupt is cleared by writing anything to the
 * status register.
 */
@@ -138,24 +72,38 @@ void tmr_isr (void *arg)
 #endif
 }
 

[U-Boot] [PATCH 2/2] nios2: Split timer code into timer.c

[Marek Vasut]

Move the timer code from interrupts.c into timer.c . Eliminate the
installation of timer interrupt handler, which is no longer used.

Signed-off-by: Marek Vasut 
---
 arch/nios2/cpu/Makefile |  2 +-
 arch/nios2/cpu/interrupts.c | 84 +
 arch/nios2/cpu/timer.c  | 65 +++
 include/configs/nios2-generic.h |  3 +-
 4 files changed, 68 insertions(+), 86 deletions(-)
 create mode 100644 arch/nios2/cpu/timer.c

V2: Rebase on top of u-boot/master
Zap the CONFIG_SYS_TIMER_IRQ check

diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile
index 3fe7847..c85e261 100644
--- a/arch/nios2/cpu/Makefile
+++ b/arch/nios2/cpu/Makefile
@@ -7,5 +7,5 @@
 
 extra-y= start.o
 obj-y  = exceptions.o
-obj-y  += cpu.o interrupts.o sysid.o traps.o
+obj-y  += cpu.o interrupts.o sysid.o timer.o traps.o
 obj-y  += fdt.o
diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c
index 36d3ef7..9d85eb0 100644
--- a/arch/nios2/cpu/interrupts.c
+++ b/arch/nios2/cpu/interrupts.c
@@ -14,36 +14,8 @@
 #include 
 #include 
 #include 
-#include 
-#ifdef CONFIG_STATUS_LED
-#include 
-#endif
-
-struct nios_timer {
-   u32 status; /* Timer status reg */
-   u32 control;/* Timer control reg */
-   u32 periodl;/* Timeout period low */
-   u32 periodh;/* Timeout period high */
-   u32 snapl;  /* Snapshot low */
-   u32 snaph;  /* Snapshot high */
-};
-
-/* status register */
-#define NIOS_TIMER_TO  (1 << 0)/* Timeout */
-#define NIOS_TIMER_RUN (1 << 1)/* Timer running */
-
-/* control register */
-#define NIOS_TIMER_ITO (1 << 0)/* Timeout int ena */
-#define NIOS_TIMER_CONT(1 << 1)/* Continuous mode */
-#define NIOS_TIMER_START   (1 << 2)/* Start timer */
-#define NIOS_TIMER_STOP(1 << 3)/* Stop timer */
-
-#if defined(CONFIG_SYS_TIMER_BASE) && !defined(CONFIG_SYS_TIMER_IRQ)
-#error CONFIG_SYS_TIMER_IRQ not defined (see documentation)
-#endif
-
-//
 
+/*/
 struct irq_action {
interrupt_handler_t *handler;
void *arg;
@@ -52,60 +24,6 @@ struct   irq_action {
 
 static struct irq_action vecs[32];
 
-/*/
-static volatile ulong timestamp;
-
-/*
- * The board must handle this interrupt if a timer is not
- * provided.
- */
-void tmr_isr (void *arg)
-{
-   struct nios_timer *tmr = (struct nios_timer *)arg;
-   /* Interrupt is cleared by writing anything to the
-* status register.
-*/
-   writel (0, >status);
-   timestamp += CONFIG_SYS_NIOS_TMRMS;
-#ifdef CONFIG_STATUS_LED
-   status_led_tick(timestamp);
-#endif
-}
-
-unsigned long notrace timer_read_counter(void)
-{
-   struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE;
-   u32 val;
-
-   /* Trigger update */
-   writel(0x0, >snapl);
-
-   /* Read timer value */
-   val = readl(>snapl) & 0x;
-   val |= (readl(>snaph) & 0x) << 16;
-
-   return ~val;
-}
-
-int timer_init(void)
-{
-   struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE;
-
-   writel (0, >status);
-   writel (0, >control);
-   writel (NIOS_TIMER_STOP, >control);
-
-   writel (0x, >periodl);
-   writel (0x, >periodh);
-
-   writel (NIOS_TIMER_CONT | NIOS_TIMER_START, >control);
-   /* FIXME */
-   irq_install_handler(CONFIG_SYS_TIMER_IRQ, tmr_isr, (void *)tmr);
-
-   return 0;
-}
-
-/*/
 int disable_interrupts (void)
 {
int val = rdctl (CTL_STATUS);
diff --git a/arch/nios2/cpu/timer.c b/arch/nios2/cpu/timer.c
new file mode 100644
index 000..b8aa9dd
--- /dev/null
+++ b/arch/nios2/cpu/timer.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * (C) Copyright 2004, Psyent Corporation 
+ * Scott McNutt 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct nios_timer {
+   u32 status; /* Timer status reg */
+   u32 control;/* Timer control reg */
+   u32 periodl;/* Timeout period low */
+   u32 periodh;/* Timeout period high */
+   u32 snapl;  /* Snapshot low */
+   u32 snaph;  /* Snapshot high */
+};
+
+/* status register */
+#define NIOS_TIMER_TO  (1 << 0)/* Timeout */
+#define NIOS_TIMER_RUN (1 << 1)/* Timer running */
+
+/* control register */
+#define NIOS_TIMER_ITO (1 << 0)

[U-Boot] [PATCH v5] bitops: introduce BIT() definition

[Andreas Bießmann]

From: Heiko Schocher 

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher 
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann 
---
Full buildman is running

Would be nice to get some Acked-by/Reviewed-by since this is a fixup of one
patch in a series that should go into 2015.10.

Andreas

Changes in v5:
 - remove other definitions of BIT()

Changes in v3:
 - new in this version

 arch/arm/include/asm/arch-am33xx/cpu.h   | 1 -
 arch/arm/include/asm/arch-hi6220/gpio.h  | 2 --
 arch/arm/include/asm/arch-omap5/cpu.h| 2 --
 arch/arm/include/asm/arch-tegra/dc.h | 2 --
 arch/arm/mach-davinci/cpu.c  | 2 --
 arch/arm/mach-keystone/include/mach/clock_defs.h | 2 --
 arch/arm/mach-keystone/include/mach/hardware.h   | 2 --
 arch/arm/mach-mvebu/include/mach/soc.h   | 2 --
 arch/arm/mach-zynq/include/mach/gpio.h   | 2 --
 drivers/ddr/marvell/a38x/ddr3_init.h | 2 --
 drivers/mtd/nand/jz4740_nand.c   | 1 -
 drivers/spi/davinci_spi.c| 2 --
 drivers/spi/ep93xx_spi.c | 2 --
 drivers/video/anx9804.c  | 2 --
 include/fsl-mc/fsl_mc.h  | 1 -
 include/linux/bitops.h   | 2 ++
 16 files changed, 2 insertions(+), 27 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h 
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 13a9cad..112ac5e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -17,7 +17,6 @@
 
 #include 
 
-#define BIT(x) (1 << x)
 #define CL_BIT(x)  (0 << x)
 
 /* Timer register bits */
diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h 
b/arch/arm/include/asm/arch-hi6220/gpio.h
index 98122a2..4fafaef 100644
--- a/arch/arm/include/asm/arch-hi6220/gpio.h
+++ b/arch/arm/include/asm/arch-hi6220/gpio.h
@@ -11,8 +11,6 @@
 #define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
0xf702 - 0x4000) + (0x1000 * bank))
 
-#define BIT(x) (1 << (x))
-
 #define HI6220_GPIO_PER_BANK   8
 #define HI6220_GPIO_DIR0x400
 
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h 
b/arch/arm/include/asm/arch-omap5/cpu.h
index 6109b92..b1513e9 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -56,8 +56,6 @@ struct watchdog {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
-#define BIT(x) (1 << (x))
-
 #define WD_UNLOCK1 0x
 #define WD_UNLOCK2 0x
 
diff --git a/arch/arm/include/asm/arch-tegra/dc.h 
b/arch/arm/include/asm/arch-tegra/dc.h
index 6ffb468..3a87f0b 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -364,8 +364,6 @@ struct dc_ctlr {
struct dc_winbuf_reg winbuf;/* WINBUF A/B/C 0x800 ~ 0x80d */
 };
 
-#define BIT(pos)   (1U << pos)
-
 /* DC_CMD_DISPLAY_COMMAND 0x032 */
 #define CTRL_MODE_SHIFT5
 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index ff61147..74c3d5d 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PLLC_PLLDIV8   0x170
 #define PLLC_PLLDIV9   0x174
 
-#define BIT(x) (1 << (x))
-
 /* SOC-specific pll info */
 #ifdef CONFIG_SOC_DM355
 #define ARM_PLLDIV PLLC_PLLDIV1
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h 
b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 8ad371f..f8d61d6 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -11,8 +11,6 @@
 
 #include 
 
-#define BIT(x) (1 << (x))
-
 /* PLL Control Registers */
 struct pllctl_regs {
u32 ctl;/* 00 */
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h 
b/arch/arm/mach-keystone/include/mach/hardware.h
index 53f28ec..f98a24e 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -24,8 +24,6 @@ typedef volatile unsigned int   *dv_reg_p;
 
 #endif
 
-#defineBIT(x)  (1 << (x))
-
 #define KS2_DDRPHY_PIR_OFFSET   0x04
 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index a8a6b27..02c21bc 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,8 +11,6 @@
 #ifndef _MVEBU_SOC_H
 #define _MVEBU_SOC_H
 
-#define BIT(x) (1 << (x))
-
 #define SOC_MV78460_ID 0x7846
 #define 

[U-Boot] [PATCH] fs: ext4: fix symlink read function

[Gary Bisson]

Since last API changes for files >2GB, the read of symlink is broken as
ext4fs_read_file now returns 0 instead of the length of the actual read.

Signed-off-by: Gary Bisson 
---
Hi all,

Switching from an old v2014.07 to v2015.07 we've noticed that we couldn't
read symlinks any more. This is due to the API changes made to
ext4fs_read_file (commit 9f12cd0).

This patch makes the read symlink check both for errors (status < 0) and
actual read length.

Regards,
Gary
---
 fs/ext4/ext4_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index cab5465..e2ab145 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2040,7 +2040,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node)
status = ext4fs_read_file(diro, 0,
   __le32_to_cpu(diro->inode.size),
   symlink, );
-   if (status == 0) {
+   if ((status < 0) || (actread == 0)) {
free(symlink);
return 0;
}
-- 
2.5.1

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[U-Boot] [PATCH v1 1/1] fix: possible overflow when copying the string

[Imran Zaman]

Bigger source buffer than dest buffer could
overflow when copying strings.
Source and destination buffer sizes are same now.

Signed-off-by: Imran Zaman 
---
 common/cli_simple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cli_simple.c b/common/cli_simple.c
index 00a8d2f..d8b40c9 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -258,7 +258,7 @@ int cli_simple_run_command(const char *cmd, int flag)
 
 void cli_simple_loop(void)
 {
-   static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
+   static char lastcommand[CONFIG_SYS_CBSIZE + 1] = { 0, };
 
int len;
int flag;
-- 
1.9.1

-
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Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
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[U-Boot] [PATCH v2] spi: tegra20: Add support for mode selection

[Mirza Krak]

From: Mirza Krak 

Respect the mode passed in claim_bus call.

Signed-off-by: Mirza Krak 
---

Changes in v2:
* Refactor clearing the CPOL and CPHA bits. Based on comments from Jagan Teki.

 drivers/spi/tegra20_slink.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index fbb665b86f3f..fa39dea2daf1 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_ENB  (1 << 31)
 #define SLINK_CMD_GO   (1 << 30)
 #define SLINK_CMD_M_S  (1 << 28)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW  (0 << 24)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24)
+#define SLINK_CMD_IDLE_SCLK_PULL_LOW   (2 << 24)
+#define SLINK_CMD_IDLE_SCLK_PULL_HIGH  (3 << 24)
+#define SLINK_CMD_IDLE_SCLK_MASK   (3 << 24)
 #define SLINK_CMD_CK_SDA   (1 << 21)
 #define SLINK_CMD_CS_POL   (1 << 13)
 #define SLINK_CMD_CS_VAL   (1 << 12)
@@ -146,6 +151,7 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
struct udevice *bus = dev->parent;
struct tegra30_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs = priv->regs;
+   unsigned int mode = priv->mode;
u32 reg;

/* Change SPI clock to correct frequency, PLLP_OUT0 source */
@@ -161,6 +167,17 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
/* Set master mode and sw controlled CS */
reg = readl(>command);
reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
+
+   /* Set CPOL and CPHA */
+   reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
+   if (mode & SPI_CPHA)
+   reg |= SLINK_CMD_CK_SDA;
+
+   if (mode & SPI_CPOL)
+   reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
+   else
+   reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
+
writel(reg, >command);
debug("%s: COMMAND = %08x\n", __func__, readl(>command));

--
2.1.0

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[U-Boot] [PATCH v1] fix: possible overflow when copying the string

[Imran Zaman]

Bigger source buffer than dest buffer could
overflow when copying strings.
Source and destination buffer sizes are same now.

Signed-off-by: Imran Zaman 
---
 common/cli_simple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cli_simple.c b/common/cli_simple.c
index 00a8d2f..d8b40c9 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -258,7 +258,7 @@ int cli_simple_run_command(const char *cmd, int flag)
 
 void cli_simple_loop(void)
 {
-   static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
+   static char lastcommand[CONFIG_SYS_CBSIZE + 1] = { 0, };
 
int len;
int flag;
-- 
1.9.1

-
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Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
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[U-Boot] u-boot hangs in spl fat load when Linux image size exceeds one cluster

[Lixun . Lin]

Hi there,

I am using u-boot 2015.04. I am trying to use spl mode to boot Linux 
without loading u-boot. I am working on the Zynq-7000 zc706 board.

I enabled the debug mode and here is the output:

U-Boot SPL 2015.04 (Sep 07 2015 - 08:22:08)
>>spl:board_init_r()
using memory 0x10c0-0x20c0 for malloc()
fpga_init
mmc boot
boot device - 1
mmc_init: 0, time 67
boot mode - FS

...(omitted, successfully initialize and load dts from SD card)

RootName: uimage, start: 0x90, size:  0x351478
Filesize: 3478648 bytes
64 bytes
gc - clustnum: 144, startsect: 17520
Size: 3478648, got: 64
spl: payload image: Linu load addr: 0x7fc0 size: 3478648
reading uImage
VFAT Support enabled
FAT32, fat_sect: 1304, fatlength: 7540
Rootdir begins at cluster: 2, sector: 16384, offset: 80
Data begins at: 16368
Sector size: 512, cluster size: 8
FAT read(sect=16384, cnt:8), clust_size=8, DIRENTSPERBLOCK=16
RootMismatch: |boot.bin||
RootMismatch: |system.dtb||
RootMismatch: |u-boot.img||
Rootvfatname: |uimage|
RootName: uimage, start: 0x90, size:  0x351478
Filesize: 3478648 bytes
3478648 bytes
FAT32: entry: 0x0090 = 144, offset: 0x0090 = 144
FAT32: ret: 0091, offset: 0090
FAT32: entry: 0x0091 = 145, offset: 0x0091 = 145
FAT32: ret: 0092, offset: 0091
FAT32: entry: 0x0092 = 146, offset: 0x0092 = 146
FAT32: ret: 0093, offset: 0092
FAT32: entry: 0x0093 = 147, offset: 0x0093 = 147
FAT32: ret: 0094, offset: 0093

...

FAT32: entry: 0x02fd = 765, offset: 0x02fd = 765
FAT32: ret: 02fe, offset: 02fd
FAT32: entry: 0x02fe = 766, offset: 0x02fe = 766
FAT32: ret: 02ff, offset: 02fe
FAT32: entry: 0x02ff = 767, offset: 0x02ff = 767
FAT32: ret: 0300, offset: 02ff
FAT32: entry: 0x0300 = 768, offset: 0x = 0 <== notice here
FAT32: ret: 0301, offset: 
FAT32: entry: 0x0301 = 769, offset: 0x0001 = 1
FAT32: ret: 0302, offset: 0001
FAT32: entry: 0x0302 = 770, offset: 0x0002 = 2
FAT32: ret: 0303, offset: 0002
FAT32: entry: 0x0303 = 771, offset: 0x0003 = 3
FAT32: ret: 0304, offset: 0003
FAT32: entry: 0x0304 = 772, offset: 0x0004 = 4
FAT32: ret: 0305, offset: 0004
...

FAT32: entry: 0x03da = 986, offset: 0x00da = 218
FAT32: ret: 03db, offset: 00da
FAT32: entry: 0x03db = 987, offset: 0x00db = 219
FAT32: ret: 03dc, offset: 00db
FAT32: entry: 0x03dc = 988, offset: 0x00dc = 220
FAT32: ret: 03dd, offset: 00dc
FAT32: entry: 0x03dd = 989, offset: 0x00dd = 221
FAT32: ret: 03de, offset: 00dd
FAT32: entry: 0x03de = 990, offset: 0x00de = 222
FAT32: ret: 03df, offset: 00de
FAT32: entry: 0x03df = 991, offset: 0x00df = 223
FAT32: ret: 03e0, offset: 00df
FAT32: entry: 0x03e0 = 992, offset: 0x00e0 = 224
FAT32: ret: 03e1, offset: 00e0
gc - clustnum: 144, startsect: 17520

After the last line, u-boot does not proceed any more. I have tried 
loading the u-boot.img, which is much smaller than the uImage and that is 
successful. Could this a problem with fat load in the spl mode? In 
fs/fat/fat.c get_contents() function, it seems it only read at data from 
at most cluster.

I am sorry if I missed something. I am new to u-boot. Thank you very much 
in advance.

Best Regards,
Lixun
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Re: [U-Boot] [PATCH] arc: make AXS101 default platform

[Alexey Brodkin]

On Mon, 2015-08-24 at 19:00 +0300, Alexey Brodkin wrote:
> This fixes building in automated flow that doesn't use defconfigs.
> 
> See discussion on that topic here:
>  http://patchwork.ozlabs.org/patch/502558/
> 
> See similar patches for other architectures/platforms  here:
>  [1] 
> http://git.denx.de/?p=u-boot.git;a=commit;h=ff560a13056a565a4e9ce1761bd04276a3cace88
>  [2] 
> http://git.denx.de/?p=u-boot.git;a=commit;h=589907e2c187ec69b351c38ccda36730d25ab5d6
> 
> And while at it add missing shell prompt to axs103.
> 
> Cc: Tom Rini 
> Cc: Joe Hershberger 
> Cc: Masahiro Yamada 
> Signed-off-by: Alexey Brodkin 
> ---

Applied, thanks.

-Alexey
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Re: [U-Boot] [PATCH v5] bitops: introduce BIT() definition

[Stefan Roese]

On 07.09.2015 13:43, Andreas Bießmann wrote:

From: Heiko Schocher 

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher 
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann 
---
Full buildman is running

Would be nice to get some Acked-by/Reviewed-by since this is a fixup of one
patch in a series that should go into 2015.10.


Thanks Andreas for cleaning this up. I didn't compile test this yet, but 
for the mvebu related stuff:


Acked-by: Stefan Roese 

Thanks,
Stefan

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[U-Boot] please pull u-boot-arc master

[Alexey Brodkin]

Hi Tom,

The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:

  doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-arc.git 

for you to fetch changes up to a883f83e6d62fef1830b1634ccb72535c43696f7:

  arc: make AXS101 default platform (2015-09-07 13:38:24 +0300)


Alexey Brodkin (1):
  arc: make AXS101 default platform

 arch/arc/Kconfig | 2 +-
 configs/axs101_defconfig | 3 +--
 configs/axs103_defconfig | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

Regards,
Alexey
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Re: [U-Boot] [PATCH 1/2] nios2: Switch to generic timer

[Marek Vasut]

On Monday, September 07, 2015 at 03:10:18 AM, Thomas Chou wrote:
> Hi Marek,

Hi!

> On 09/04/2015 10:08 PM, Marek Vasut wrote:
> >> The patch cannot apply to board_f.c due to conflict in
> >> 
> >> commit 2e88bb28d8061286d2f1cabcac224df15b941b82
> >> NDS32: Generic Board Support and Unsupport
> > 
> > Aw, right, looks trivial. Thanks :)
> 
> Could you please rebase and submit this series again?

Yes, that's my plan shortly. We're aiming for after 2015.10 release
with all these NIOS changes, so this is not urgent, right ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] nios2: enable Driver Model

[Marek Vasut]

On Monday, September 07, 2015 at 04:49:20 AM, Thomas Chou wrote:
> Enable the Driver Model config. The driver subsystems
> are not enabled until we enable each of them.
> 
> Signed-off-by: Thomas Chou 

Cool, let's do this :)

Acked-by: Marek Vasut 

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] mx6: remove SYS_SOC from board Kconfig

[Markus Niebel]

Hello,

Am 07.09.2015 um 08:59 schrieb Peng Fan:
> Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
> because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Heiko Schocher 
> Cc: Christian Gmeiner 
> Cc: Stefan Roese 
> Cc: Troy Kisky 
> Cc: Nikita Kiryanov 
> Cc: "Eric Bénard" 
> Cc: Fabio Estevam 
> Cc: Tim Harvey 
> Cc: Marek Vasut 
> Cc: Markus Niebel 
> Cc: Otavio Salvador 
> ---
>  board/aristainetos/Kconfig  | 9 -
>  board/bachmann/ot1200/Kconfig   | 3 ---
>  board/barco/platinum/Kconfig| 6 --
>  board/barco/titanium/Kconfig| 3 ---
>  board/boundary/nitrogen6x/Kconfig   | 3 ---
>  board/compulab/cm_fx6/Kconfig   | 3 ---
>  board/congatec/cgtqmx6eval/Kconfig  | 3 ---
>  board/embest/mx6boards/Kconfig  | 3 ---
>  board/freescale/mx6qarm2/Kconfig| 3 ---
>  board/freescale/mx6qsabreauto/Kconfig   | 3 ---
>  board/freescale/mx6sabresd/Kconfig  | 3 ---
>  board/freescale/mx6slevk/Kconfig| 3 ---
>  board/freescale/mx6sxsabresd/Kconfig| 3 ---
>  board/freescale/mx6ul_14x14_evk/Kconfig | 3 ---
>  board/gateworks/gw_ventana/Kconfig  | 3 ---
>  board/kosagi/novena/Kconfig | 3 ---
>  board/solidrun/mx6cuboxi/Kconfig| 3 ---
>  board/tqc/tqma6/Kconfig | 3 ---
>  board/udoo/Kconfig  | 3 ---
>  board/wandboard/Kconfig | 3 ---
>  board/warp/Kconfig  | 3 ---
>  21 files changed, 72 deletions(-)
> 
> diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
> index e987f38..e416c9a 100644
> --- a/board/aristainetos/Kconfig
> +++ b/board/aristainetos/Kconfig
> @@ -3,9 +3,6 @@ if TARGET_ARISTAINETOS
>  config SYS_BOARD
>   default "aristainetos"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "aristainetos"
>  
> @@ -16,9 +13,6 @@ if TARGET_ARISTAINETOS2
>  config SYS_BOARD
>   default "aristainetos"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "aristainetos2"
>  
> @@ -29,9 +23,6 @@ if TARGET_ARISTAINETOS2B
>  config SYS_BOARD
>   default "aristainetos"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "aristainetos2b"
>  
> diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
> index 7f8a6a1..4ccb60a 100644
> --- a/board/bachmann/ot1200/Kconfig
> +++ b/board/bachmann/ot1200/Kconfig
> @@ -6,9 +6,6 @@ config SYS_BOARD
>  config SYS_VENDOR
>   default "bachmann"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "ot1200"
>  
> diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig
> index 8bbad24..cc0648c 100644
> --- a/board/barco/platinum/Kconfig
> +++ b/board/barco/platinum/Kconfig
> @@ -6,9 +6,6 @@ config SYS_CPU
>  config SYS_VENDOR
>   default "barco"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_BOARD
>   default "platinum"
>  
> @@ -25,9 +22,6 @@ config SYS_CPU
>  config SYS_VENDOR
>   default "barco"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_BOARD
>   default "platinum"
>  
> diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig
> index b6f7c85..21bc36e 100644
> --- a/board/barco/titanium/Kconfig
> +++ b/board/barco/titanium/Kconfig
> @@ -6,9 +6,6 @@ config SYS_BOARD
>  config SYS_VENDOR
>   default "barco"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "titanium"
>  
> diff --git a/board/boundary/nitrogen6x/Kconfig 
> b/board/boundary/nitrogen6x/Kconfig
> index 03b0f6f..f4db56d 100644
> --- a/board/boundary/nitrogen6x/Kconfig
> +++ b/board/boundary/nitrogen6x/Kconfig
> @@ -6,9 +6,6 @@ config SYS_BOARD
>  config SYS_VENDOR
>   default "boundary"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "nitrogen6x"
>  
> diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
> index 508c21f..59070c5 100644
> --- a/board/compulab/cm_fx6/Kconfig
> +++ b/board/compulab/cm_fx6/Kconfig
> @@ -6,9 +6,6 @@ config SYS_BOARD
>  config SYS_VENDOR
>   default "compulab"
>  
> -config SYS_SOC
> - default "mx6"
> -
>  config SYS_CONFIG_NAME
>   default "cm_fx6"
>  
> diff --git a/board/congatec/cgtqmx6eval/Kconfig 
> b/board/congatec/cgtqmx6eval/Kconfig
> index 0a837bd..773551b 100644
> --- a/board/congatec/cgtqmx6eval/Kconfig
> +++ b/board/congatec/cgtqmx6eval/Kconfig
> @@ -6,9 +6,6 @@ config SYS_BOARD
>  config SYS_VENDOR
>   default "congatec"
>  
> 

[U-Boot] [PATCH v5 7/9] armv8: cavium: Add ThunderX 88xx board definition

[Sergey Temerkhanov]

This commit adds basic Cavium ThunderX 88xx board definitions and support.

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 

---

Changes in v5:
- Added CONFIG_OF_CONTROL support
- Changed memory attributes

Changes in v4:
- Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig
- Added proper DM_SERIAL definitions

Changes in v3:
- Fixed formatting
- Added MAINTAINERS
- Moved command definitions to defconfig

Changes in v2: None

 arch/arm/Kconfig  |   5 ++
 board/cavium/thunderx/Kconfig |  19 +
 board/cavium/thunderx/MAINTAINERS |   6 ++
 board/cavium/thunderx/Makefile|   8 +++
 board/cavium/thunderx/thunderx.c  |  75 
 configs/thunderx_88xx_defconfig   |  29 
 include/configs/thunderx_88xx.h   | 146 ++
 7 files changed, 288 insertions(+)
 create mode 100644 board/cavium/thunderx/Kconfig
 create mode 100644 board/cavium/thunderx/MAINTAINERS
 create mode 100644 board/cavium/thunderx/Makefile
 create mode 100644 board/cavium/thunderx/thunderx.c
 create mode 100644 configs/thunderx_88xx_defconfig
 create mode 100644 include/configs/thunderx_88xx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c598f5e..26f328f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -741,6 +741,10 @@ config ARCH_ROCKCHIP
select CPU_V7
select DM
 
+config TARGET_THUNDERX_88XX
+   bool "Support ThunderX 88xx"
+   select OF_CONTROL
+
 endchoice
 
 source "arch/arm/mach-at91/Kconfig"
@@ -894,6 +898,7 @@ source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
 source "board/xaeniax/Kconfig"
 source "board/zipitz2/Kconfig"
+source "board/cavium/thunderx/Kconfig"
 
 source "arch/arm/Kconfig.debug"
 
diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig
new file mode 100644
index 000..3e62abf
--- /dev/null
+++ b/board/cavium/thunderx/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_THUNDERX_88XX
+
+config SYS_CPU
+   string
+   default "armv8"
+
+config SYS_BOARD
+   string
+   default "thunderx"
+
+config SYS_VENDOR
+   string
+   default "cavium"
+
+config SYS_CONFIG_NAME
+   string
+   default "thunderx_88xx"
+
+endif
diff --git a/board/cavium/thunderx/MAINTAINERS 
b/board/cavium/thunderx/MAINTAINERS
new file mode 100644
index 000..c84d3b5
--- /dev/null
+++ b/board/cavium/thunderx/MAINTAINERS
@@ -0,0 +1,6 @@
+THUNDERX BOARD
+M: Sergey Temerkhanov 
+S: Maintained
+F: board/cavium/thunderx/
+F: include/configs/thunderx_88xx.h
+F: configs/thunderx_88xx_defconfig
diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile
new file mode 100644
index 000..306044a
--- /dev/null
+++ b/board/cavium/thunderx/Makefile
@@ -0,0 +1,8 @@
+#
+#
+# (C) Copyright 2014, Cavium Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := thunderx.o
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
new file mode 100644
index 000..ea6ae80
--- /dev/null
+++ b/board/cavium/thunderx/thunderx.c
@@ -0,0 +1,75 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include 
+#include 
+
+static const struct pl01x_serial_platdata serial0 = {
+   .base = CONFIG_SYS_SERIAL0,
+   .type = TYPE_PL011,
+   .clock = 0,
+   .flags = PL0X_PREINITIALIZED,
+};
+
+U_BOOT_DEVICE(thunderx_serial0) = {
+   .name = "serial_pl01x",
+   .platdata = ,
+};
+
+static const struct pl01x_serial_platdata serial1 = {
+   .base = CONFIG_SYS_SERIAL1,
+   .type = TYPE_PL011,
+   .clock = 0,
+   .flags = PL0x_PREINITIALIZED,
+};
+
+U_BOOT_DEVICE(thunderx_serial1) = {
+   .name = "serial_pl01x",
+   .platdata = ,
+};
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+   return 0;
+}
+
+int timer_init(void)
+{
+   return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+   int rc = 0;
+
+   return rc;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+   printf("DEBUG: PCI Init TODO *\n");
+}
+#endif
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
new file mode 100644
index 000..554686f
--- /dev/null
+++ b/configs/thunderx_88xx_defconfig
@@ -0,0 +1,29 @@
+CONFIG_SYS_EXTRA_OPTIONS="ARM64"
+CONFIG_ARM=y
+CONFIG_TARGET_THUNDERX_88XX=y
+CONFIG_SYS_PROMPT="ThunderX_88XX> "
+
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_STDIO=y
+CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
+
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_DIAG=y
+CONFIG_CMD_ENV=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_BOOTD=y

[U-Boot] [PATCH v5 8/9] armv8: cavium: Add an implementation of ATF calling functions

[Sergey Temerkhanov]

This commit adds functions issuing calls to the product-specific ATF
services

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/cavium/thunderx/Makefile  |   2 +-
 board/cavium/thunderx/atf.c | 312 
 include/cavium/atf.h|  22 +++
 include/cavium/atf_part.h   |  26 
 include/cavium/thunderx_svc.h   |  67 +
 include/configs/thunderx_88xx.h |   2 +
 6 files changed, 430 insertions(+), 1 deletion(-)
 create mode 100644 board/cavium/thunderx/atf.c
 create mode 100644 include/cavium/atf.h
 create mode 100644 include/cavium/atf_part.h
 create mode 100644 include/cavium/thunderx_svc.h

diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile
index 306044a..c78c414 100644
--- a/board/cavium/thunderx/Makefile
+++ b/board/cavium/thunderx/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := thunderx.o
+obj-y  := thunderx.o atf.o
diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c
new file mode 100644
index 000..6ab9de9
--- /dev/null
+++ b/board/cavium/thunderx/atf.c
@@ -0,0 +1,312 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_MMC_READ;
+   regs.regs[1] = offset;
+   regs.regs[2] = size;
+   regs.regs[3] = (uintptr_t)buffer;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_NOR_READ;
+   regs.regs[1] = offset;
+   regs.regs[2] = size;
+   regs.regs[3] = (uintptr_t)buffer;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_get_pcount(void)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_PART_COUNT;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_GET_PART;
+   regs.regs[1] = (uintptr_t)part;
+   regs.regs[2] = index;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_erase_nor(uintptr_t offset, size_t size)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = THUNDERX_NOR_ERASE;
+   regs.regs[1] = offset;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = THUNDERX_NOR_WRITE;
+   regs.regs[1] = offset;
+   regs.regs[2] = size;
+   regs.regs[3] = (uintptr_t)buffer;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = THUNDERX_MMC_WRITE;
+   regs.regs[1] = offset;
+   regs.regs[2] = size;
+   regs.regs[3] = (uintptr_t)buffer;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_dram_size(unsigned int node)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_DRAM_SIZE;
+   regs.regs[1] = node;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_node_count(void)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_NODE_COUNT;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_env_count(void)
+{
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_ENV_COUNT;
+
+   smc_call();
+
+   return regs.regs[0];
+}
+
+ssize_t atf_env_string(size_t index, char *str)
+{
+   uint64_t *buf = (void *)str;
+   struct pt_regs regs;
+   regs.regs[0] = THUNDERX_ENV_STRING;
+   regs.regs[1] = index;
+
+   smc_call();
+
+   if (regs.regs > 0) {
+   buf[0] = regs.regs[0];
+   buf[1] = regs.regs[1];
+   buf[2] = regs.regs[2];
+   buf[3] = regs.regs[3];
+
+   return 1;
+   } else {
+   return regs.regs[0];
+   }
+}
+
+#ifdef CONFIG_CMD_ATF
+
+static void atf_print_ver(void)
+{
+   struct pt_regs regs;
+   regs.regs[0] = ARM_STD_SVC_VERSION;
+
+   smc_call();
+
+   printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+
+   regs.regs[0] = THUNDERX_SVC_VERSION;
+
+   smc_call();
+
+   printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+}
+
+static void atf_print_uid(void)
+{
+}
+
+static void atf_print_part_table(void)
+{
+   size_t pcount;
+   unsigned long i;
+   int ret;
+   char *ptype;
+
+   

Re: [U-Boot] [PATCH v4 0/7] nios2: add device tree control of U-Boot

[Thomas Chou]

Hi Marek,

On 09/07/2015 05:29 PM, Marek Vasut wrote:

Nice, I like seeing how NIOS2 getting back to shape. btw you could have
waited a few days before applying patches that were just posted.


Thanks for reminding. I used to wait a week. But I hate too many things 
floating around, that would prevent me to focus. Something we might have 
enough discussion or too trivial..


Thank you again. And please continue your great work.

Cheers,
Thomas Chou
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Re: [U-Boot] [PATCH V2 1/2] nios2: Switch to generic timer

[Thomas Chou]

Hi Marek,

On 09/07/2015 08:31 PM, Marek Vasut wrote:

Zap almost all of the ad-hoc timer code from interrupts.c and
use the code in lib/time.c instead.

Signed-off-by: Marek Vasut 
---
  arch/nios2/cpu/interrupts.c | 132 
  arch/nios2/lib/Makefile |   1 -
  arch/nios2/lib/time.c   |  22 ---
  common/board_f.c|   3 +-
  include/configs/nios2-generic.h |   9 +--
  5 files changed, 43 insertions(+), 124 deletions(-)
  delete mode 100644 arch/nios2/lib/time.c

V2: Rebase on top of u-boot/master


Applied to u-boot-nios.
Thanks.

Best regards,
Thomas Chou



diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c
index 9d7e193..36d3ef7 100644
--- a/arch/nios2/cpu/interrupts.c
+++ b/arch/nios2/cpu/interrupts.c
@@ -8,7 +8,6 @@
   * SPDX-License-Identifier:   GPL-2.0+
   */

-
  #include 
  #include 
  #include 
@@ -20,14 +19,14 @@
  #include 
  #endif

-typedef volatile struct {
-   unsignedstatus; /* Timer status reg */
-   unsignedcontrol;/* Timer control reg */
-   unsignedperiodl;/* Timeout period low */
-   unsignedperiodh;/* Timeout period high */
-   unsignedsnapl;  /* Snapshot low */
-   unsignedsnaph;  /* Snapshot high */
-} nios_timer_t;
+struct nios_timer {
+   u32 status; /* Timer status reg */
+   u32 control;/* Timer control reg */
+   u32 periodl;/* Timeout period low */
+   u32 periodh;/* Timeout period high */
+   u32 snapl;  /* Snapshot low */
+   u32 snaph;  /* Snapshot high */
+};

  /* status register */
  #define NIOS_TIMER_TO (1 << 0)  /* Timeout */
@@ -39,8 +38,8 @@ typedef volatile struct {
  #define NIOS_TIMER_START  (1 << 2)  /* Start timer */
  #define NIOS_TIMER_STOP   (1 << 3)  /* Stop timer */

-#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
-#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
+#if defined(CONFIG_SYS_TIMER_BASE) && !defined(CONFIG_SYS_TIMER_IRQ)
+#error CONFIG_SYS_TIMER_IRQ not defined (see documentation)
  #endif

  //
@@ -54,80 +53,15 @@ struct  irq_action {
  static struct irq_action vecs[32];

  /*/
-volatile ulong timestamp = 0;
-
-void reset_timer (void)
-{
-   nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
-
-   /* From Embedded Peripherals Handbook:
-*
-* "When the hardware is configured with Writeable period
-* disabled, writing to one of the period_n registers causes
-* the counter to reset to the fixed Timeout Period specified
-* at system generation time."
-*
-* Here we force a reload to prevent early timeouts from
-* get_timer() when the interrupt period is greater than
-* than 1 msec.
-*
-* Simply write to periodl with its own value to force an
-* internal counter reload, THEN reset the timestamp.
-*/
-   writel (readl (>periodl), >periodl);
-   timestamp = 0;
-
-   /* From Embedded Peripherals Handbook:
-*
-* "Writing to one of the period_n registers stops the internal
-* counter, except when the hardware is configured with Start/Stop
-* control bits off. If Start/Stop control bits is off, writing
-* either register does not stop the counter."
-*
-* In order to accomodate either configuration, the control
-* register is re-written. If the counter is stopped, it will
-* be restarted. If it is running, the write is essentially
-* a nop.
-*/
-   writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
-   >control);
-
-}
-
-ulong get_timer (ulong base)
-{
-   WATCHDOG_RESET ();
-   return (timestamp - base);
-}
-
-/*
- * This function is derived from Blackfin code (read timebase as long long).
- * On Nios2 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-   return get_timer(0);
-}
+static volatile ulong timestamp;

  /*
- * This function is derived from Blackfin code.
- * On Nios2 it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-   ulong tbclk;
-
-   tbclk = CONFIG_SYS_HZ;
-   return tbclk;
-}
-
-/* The board must handle this interrupt if a timer is not
+ * The board must handle this interrupt if a timer is not
   * provided.
   */
-#if defined(CONFIG_SYS_NIOS_TMRBASE)
  void tmr_isr (void *arg)
  {
-   nios_timer_t *tmr = (nios_timer_t *)arg;
+   struct nios_timer *tmr = (struct nios_timer *)arg;
/* Interrupt is cleared by 

Re: [U-Boot] [PATCH 2/2] nios2: Split timer code into timer.c

[Thomas Chou]

Hi Marek,

On 09/07/2015 08:31 PM, Marek Vasut wrote:

Move the timer code from interrupts.c into timer.c . Eliminate the
installation of timer interrupt handler, which is no longer used.

Signed-off-by: Marek Vasut 
---
  arch/nios2/cpu/Makefile |  2 +-
  arch/nios2/cpu/interrupts.c | 84 +
  arch/nios2/cpu/timer.c  | 65 +++
  include/configs/nios2-generic.h |  3 +-
  4 files changed, 68 insertions(+), 86 deletions(-)
  create mode 100644 arch/nios2/cpu/timer.c

V2: Rebase on top of u-boot/master
 Zap the CONFIG_SYS_TIMER_IRQ check



Applied to u-boot-nios.
Thanks.

Best regards,
Thomas Chou
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[U-Boot] [PATCH v5 3/9] armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure

[Sergey Temerkhanov]

This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)

The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Corey Minyard 
Signed-off-by: Radha Mohan Chintakuntla 
Reviewed-by: Simon Glass 

---

Changes in v5: None
Changes in v4:
- Document FW calls

Changes in v3:
- Fixed clobber lists (thanks to Corey)

Changes in v2: None

 arch/arm/cpu/armv8/Makefile   |  1 +
 arch/arm/cpu/armv8/fwcall.c   | 75 +++
 arch/arm/include/asm/system.h | 21 
 3 files changed, 97 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fwcall.c

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..7579ea7 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -14,6 +14,7 @@ obj-y += exceptions.o
 obj-y  += cache.o
 obj-y  += tlb.o
 obj-y  += transition.o
+obj-y  += fwcall.o
 
 obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
new file mode 100644
index 000..9efcc5a
--- /dev/null
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -0,0 +1,75 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Issue the hypervisor call
+ *
+ * x0~x7: input arguments
+ * x0~x3: output arguments
+ */
+void hvc_call(struct pt_regs *args)
+{
+   asm volatile(
+   "ldr x0, %0\n"
+   "ldr x1, %1\n"
+   "ldr x2, %2\n"
+   "ldr x3, %3\n"
+   "ldr x4, %4\n"
+   "ldr x5, %5\n"
+   "ldr x6, %6\n"
+   "ldr x7, %7\n"
+   "hvc#0\n"
+   "str x0, %0\n"
+   "str x1, %1\n"
+   "str x2, %2\n"
+   "str x3, %3\n"
+   : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+   : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6]), "m" (args->regs[7])
+   : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
+
+/*
+ * void smc_call(arg0, arg1...arg7)
+ *
+ * issue the secure monitor call
+ *
+ * x0~x7: input arguments
+ * x0~x3: output arguments
+ */
+
+void smc_call(struct pt_regs *args)
+{
+   asm volatile(
+   "ldr x0, %0\n"
+   "ldr x1, %1\n"
+   "ldr x2, %2\n"
+   "ldr x3, %3\n"
+   "ldr x4, %4\n"
+   "ldr x5, %5\n"
+   "ldr x6, %6\n"
+   "smc#0\n"
+   "str x0, %0\n"
+   "str x1, %1\n"
+   "str x2, %2\n"
+   "str x3, %3\n"
+   : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+   : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6])
+   : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9288541..f3e2d1b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,9 @@
 #ifndef __ASM_ARM_SYSTEM_H
 #define __ASM_ARM_SYSTEM_H
 
+#include 
+#include 
+
 #ifdef CONFIG_ARM64
 
 /*
@@ -104,6 +107,24 @@ void smp_kick_all_cpus(void);
 
 void flush_l3_cache(void);
 
+/*
+ *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void hvc_call(struct pt_regs *args);
+
+/*
+ *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void smc_call(struct pt_regs *args);
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
-- 
2.2.0

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[U-Boot] [PATCH v5 6/9] armv8: cavium: Add the device tree for ThunderX

[Sergey Temerkhanov]

This commit adds the FDT for the ThunderX family of SoCs

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 

---

Changes in v5:
- Added FDT for ThunderX 88xx series

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/thunderx-88xx.dts  |  27 +++
 arch/arm/dts/thunderx-88xx.dtsi | 363 
 3 files changed, 391 insertions(+)
 create mode 100644 arch/arm/dts/thunderx-88xx.dts
 create mode 100644 arch/arm/dts/thunderx-88xx.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3babe65..3dd7b54 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
+dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
socfpga_arria5_socdk.dtb\
diff --git a/arch/arm/dts/thunderx-88xx.dts b/arch/arm/dts/thunderx-88xx.dts
new file mode 100644
index 000..7910305
--- /dev/null
+++ b/arch/arm/dts/thunderx-88xx.dts
@@ -0,0 +1,27 @@
+/*
+ * Cavium Thunder DTS file - Thunder board description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+ or X11
+ *
+ */
+
+/dts-v1/;
+
+/include/ "thunderx-88xx.dtsi"
+
+/ {
+   model = "Cavium ThunderX CN88XX board";
+   compatible = "cavium,thunder-88xx";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   memory@ {
+   device_type = "memory";
+   reg = <0x0 0x 0x0 0x8000>;
+   };
+};
diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi
new file mode 100644
index 000..086652f
--- /dev/null
+++ b/arch/arm/dts/thunderx-88xx.dtsi
@@ -0,0 +1,363 @@
+/*
+ * Cavium Thunder DTS file - Thunder SoC description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+ or X11
+ *
+ */
+
+/ {
+   compatible = "cavium,thunder-88xx";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu@000 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x000>;
+   enable-method = "psci";
+   };
+   cpu@001 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x001>;
+   enable-method = "psci";
+   };
+   cpu@002 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x002>;
+   enable-method = "psci";
+   };
+   cpu@003 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x003>;
+   enable-method = "psci";
+   };
+   cpu@004 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x004>;
+   enable-method = "psci";
+   };
+   cpu@005 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x005>;
+   enable-method = "psci";
+   };
+   cpu@006 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x006>;
+   enable-method = "psci";
+   };
+   cpu@007 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x007>;
+   enable-method = "psci";
+   };
+   cpu@008 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x008>;
+   enable-method = "psci";
+   };
+   cpu@009 {
+   device_type = "cpu";
+   compatible = "cavium,thunder", "arm,armv8";
+   reg = <0x0 0x009>;
+   enable-method = "psci";
+   };
+ 

[U-Boot] [PATCH v5 5/9] arm: serial: Add ability to use pre-initialized UARTs

[Sergey Temerkhanov]

On some systems, UART initialization is performed before running U-Boot.
This commit allows to skip UART re-initializaion on those systems

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 

---

Changes in v5:
- Added OF control support

Changes in v4:
- Fixed build warnings
- Moved to DM_SERIAL

Changes in v3:
- Added __used keyword

Changes in v2: None

 drivers/serial/serial_pl01x.c   | 13 +++--
 include/dm/platform_data/serial_pl01x.h |  6 ++
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index ecf3bc0..83151e0 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -125,7 +125,7 @@ static int pl011_set_line_control(struct pl01x_regs *regs)
 }
 
 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
-   int clock, int baudrate)
+  int clock, int baudrate)
 {
switch (type) {
case TYPE_PL010: {
@@ -295,7 +295,6 @@ __weak struct serial_device *default_serial_console(void)
 #endif /* nCONFIG_DM_SERIAL */
 
 #ifdef CONFIG_DM_SERIAL
-
 struct pl01x_priv {
struct pl01x_regs *regs;
enum pl01x_type type;
@@ -306,9 +305,9 @@ static int pl01x_serial_setbrg(struct udevice *dev, int 
baudrate)
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
 
-   pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
-
-   return 0;
+   return (plat->flags & PL0X_PREINITIALIZED) ? 0 :
+   pl01x_generic_setbrg(priv->regs, priv->type,
+plat->clock, baudrate);
 }
 
 static int pl01x_serial_probe(struct udevice *dev)
@@ -318,7 +317,8 @@ static int pl01x_serial_probe(struct udevice *dev)
 
priv->regs = (struct pl01x_regs *)plat->base;
priv->type = plat->type;
-   return pl01x_generic_serial_init(priv->regs, priv->type);
+   return (plat->flags & PL0X_PREINITIALIZED) ? 0 :
+   pl01x_generic_serial_init(priv->regs, priv->type);
 }
 
 static int pl01x_serial_getc(struct udevice *dev)
@@ -372,6 +372,7 @@ static int pl01x_serial_ofdata_to_platdata(struct udevice 
*dev)
plat->base = addr;
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
plat->type = dev_get_driver_data(dev);
+   plat->flags = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "flags", 0);
return 0;
 }
 #endif
diff --git a/include/dm/platform_data/serial_pl01x.h 
b/include/dm/platform_data/serial_pl01x.h
index 5e068f3..73e1be0 100644
--- a/include/dm/platform_data/serial_pl01x.h
+++ b/include/dm/platform_data/serial_pl01x.h
@@ -11,17 +11,23 @@ enum pl01x_type {
TYPE_PL011,
 };
 
+enum pl01x_flags {
+   PL0X_PREINITIALIZED = 1 << 0, /* Skip port initialization */
+};
+
 /*
  *Information about a serial port
  *
  * @base: Register base address
  * @type: Port type
  * @clock: Input clock rate, used for calculating the baud rate divisor
+ * @flags: Port flags
  */
 struct pl01x_serial_platdata {
unsigned long base;
enum pl01x_type type;
unsigned int clock;
+   unsigned long flags;
 };
 
 #endif
-- 
2.2.0

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[U-Boot] [PATCH v5 4/9] armv8: Add psci.h from the Linux kernel

[Sergey Temerkhanov]

This commit adds the psci.h header file from Linux kernel
which contains definitions related to the PSCI interface provided
by firmware

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/linux/psci.h | 90 
 1 file changed, 90 insertions(+)
 create mode 100644 include/linux/psci.h

diff --git a/include/linux/psci.h b/include/linux/psci.h
new file mode 100644
index 000..310d83e
--- /dev/null
+++ b/include/linux/psci.h
@@ -0,0 +1,90 @@
+/*
+ * ARM Power State and Coordination Interface (PSCI) header
+ *
+ * This header holds common PSCI defines and macros shared
+ * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
+ *
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Anup Patel 
+ */
+
+#ifndef _UAPI_LINUX_PSCI_H
+#define _UAPI_LINUX_PSCI_H
+
+/*
+ * PSCI v0.1 interface
+ *
+ * The PSCI v0.1 function numbers are implementation defined.
+ *
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE   0x8400
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x4000
+#define PSCI_0_2_FN64_BASE \
+   (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n)   (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION   PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPENDPSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFFPSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO  PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATEPSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE  PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPUPSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET   PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND  PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON   PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFOPSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE  PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU  PSCI_0_2_FN64(7)
+
+/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
+#define PSCI_0_2_POWER_STATE_ID_MASK   0x
+#define PSCI_0_2_POWER_STATE_ID_SHIFT  0
+#define PSCI_0_2_POWER_STATE_TYPE_SHIFT16
+#define PSCI_0_2_POWER_STATE_TYPE_MASK \
+   (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
+#define PSCI_0_2_POWER_STATE_AFFL_SHIFT24
+#define PSCI_0_2_POWER_STATE_AFFL_MASK \
+   (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
+
+/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
+#define PSCI_0_2_AFFINITY_LEVEL_ON 0
+#define PSCI_0_2_AFFINITY_LEVEL_OFF1
+#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2
+
+/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
+#define PSCI_0_2_TOS_UP_MIGRATE0
+#define PSCI_0_2_TOS_UP_NO_MIGRATE 1
+#define PSCI_0_2_TOS_MP2
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT   16
+#define PSCI_VERSION_MINOR_MASK\
+   ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK~PSCI_VERSION_MINOR_MASK
+#define PSCI_VERSION_MAJOR(ver)\
+   (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver)\
+   ((ver) & PSCI_VERSION_MINOR_MASK)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS   0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS-2
+#define PSCI_RET_DENIED-3
+#define PSCI_RET_ALREADY_ON-4
+#define PSCI_RET_ON_PENDING-5
+#define PSCI_RET_INTERNAL_FAILURE  -6
+#define PSCI_RET_NOT_PRESENT   -7
+#define PSCI_RET_DISABLED  -8
+
+#endif /* _UAPI_LINUX_PSCI_H */
-- 
2.2.0

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[U-Boot] [PATCH v5 9/9] armv8: cavium: Get DRAM size from ATF

[Sergey Temerkhanov]

Change the dram_init() function on ThunderX to query ATF services for
the real installed DRAM size

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 
DRAM fix

---

Changes in v5:
- Moved dram_init() from a separate file to thunderx.c

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/cavium/thunderx/thunderx.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index ea6ae80..89cf2c6 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -9,6 +9,8 @@
 #include 
 #include 
 
+#include 
+
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 #include 
 #include 
@@ -50,6 +52,31 @@ int timer_init(void)
return 0;
 }
 
+int dram_init(void)
+{
+   ssize_t node_count = atf_node_count();
+   ssize_t dram_size;
+   int node;
+
+   printf("Initializing\nNodes in system: %zd\n", node_count);
+
+   gd->ram_size = 0;
+
+   for (node = 0; node < node_count; node++) {
+   dram_size = atf_dram_size(node);
+   printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
+   gd->ram_size += dram_size;
+   }
+
+   gd->ram_size -= MEM_BASE;
+
+   *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+   puts("DRAM size:");
+
+   return 0;
+}
+
 /*
  * Board specific reset that is system reset.
  */
-- 
2.2.0

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[U-Boot] [PATCH v5 1/9] armv8: Add read_mpidr() function

[Sergey Temerkhanov]

This patch adds the read_mpidr() function which returns the
MPIDR_EL1 register value

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 

Reviewed-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/system.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 868ea54..323c43e 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -71,6 +71,17 @@ static inline void set_sctlr(unsigned int val)
asm volatile("isb");
 }
 
+static inline unsigned long read_mpidr(void)
+{
+   unsigned long val;
+
+   asm volatile("mrs %0, mpidr_el1" : "=r" (val));
+
+   return val;
+}
+
+#define BSP_COREID 0
+
 void __asm_flush_dcache_all(void);
 void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
-- 
2.2.0

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[U-Boot] Any more patches for x86?

[Simon Glass]

Hi Bin,

Do you have any other patches that you think should be applied for the
upcoming release? I'd like to get these in before sending out the last
big pull request.

Regards,
Simon
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Re: [U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change

[Chin Liang See]

Hi,

On Thu, 2015-09-03 at 16:17 +0200, ma...@denx.de wrote:
> On Thursday, September 03, 2015 at 03:41:59 PM, Chin Liang See wrote:
> > Ensuring spi_calibration is run when there is a change of sclk
> > frequency. This will ensure the qspi flash access works for high
> > sclk frequency
> > 
> > Signed-off-by: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> > Cc: Vikas Manocha 
> > Cc: Jagannadh Teki 
> > Cc: Pavel Machek 
> > ---
> >  drivers/spi/cadence_qspi.c |8 
> >  1 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > index 34a0f46..300934e 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -37,7 +37,7 @@ static int cadence_spi_write_speed(struct udevice *bus,
> > uint hz) }
> > 
> >  /* Calibration sequence to determine the read data capture delay register
> > */ -static int spi_calibration(struct udevice *bus)
> > +static int spi_calibration(struct udevice *bus, uint hz)
> >  {
> > struct cadence_spi_platdata *plat = bus->platdata;
> > struct cadence_spi_priv *priv = dev_get_priv(bus);
> > @@ -64,7 +64,7 @@ static int spi_calibration(struct udevice *bus)
> > }
> > 
> > /* use back the intended clock and find low range */
> > -   cadence_spi_write_speed(bus, plat->max_hz);
> > +   cadence_spi_write_speed(bus, hz);
> > for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
> > /* Disable QSPI */
> > cadence_qspi_apb_controller_disable(base);
> > @@ -111,7 +111,7 @@ static int spi_calibration(struct udevice *bus)
> >   (range_hi + range_lo) / 2, range_lo, range_hi);
> > 
> > /* just to ensure we do once only when speed or chip select change */
> > -   priv->qspi_calibrated_hz = plat->max_hz;
> > +   priv->qspi_calibrated_hz = hz;
> > priv->qspi_calibrated_cs = spi_chip_select(bus);
> > 
> > return 0;
> > @@ -131,7 +131,7 @@ static int cadence_spi_set_speed(struct udevice *bus,
> 
> Hi,
> 
> My impression is that the logic here should be like this:
> 
> if (hz > plat->max_hz) {
> printf("error, freq. too high");
> return -EINVAL;
> }
> if (priv->previous_hz != hz) /* Bus frequency changed, re-calibrate */
> spi_calibrate(bus, hz)
> cadence_spi_write_speed(bus, priv->qspi_calibrated_hz);
> priv->previous_hz = hz;
> 
> Note that you need a new private variable, previous_hz, to hold the previous
> value of "hz". This is needed since the calibrated frequency might not be
> equal to requested frequency.
> 

I know where you coming from. 
Yah, calibration can be skipped when requested frequency same as
previous or calibrated one.
Let me add that.

> > uint hz) /* Calibration required for different SCLK speed or chip select
> > */ if (priv->qspi_calibrated_hz != plat->max_hz ||
> > priv->qspi_calibrated_cs != spi_chip_select(bus)) {
> > -   err = spi_calibration(bus);
> > +   err = spi_calibration(bus, hz);
> 
> This is called after the frequency is configured in this function, this looks
> really backwards.

Yah, let me remove the old code.

Thanks
Chin Liang

> 
> > if (err)
> > return err;
> > }
> 
> Best regards,
> Marek Vasut


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Re: [U-Boot] [PATCH 2/4] spi: cadence_qspi: Fix fdt read of spi-max-frequency

[Chin Liang See]

Hi,

On Thu, 2015-09-03 at 16:19 +0200, ma...@denx.de wrote:
> On Thursday, September 03, 2015 at 03:42:00 PM, Chin Liang See wrote:
> > Fix the fdt read for spi-max-frequency as it's contained
> > in the child node. Current state of code is always
> > returning default value.
> > 
> > Signed-off-by: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> > Cc: Vikas Manocha 
> > Cc: Jagannadh Teki 
> > Cc: Pavel Machek 
> > ---
> >  drivers/spi/cadence_qspi.c |8 
> >  1 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > index 300934e..a00af87 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -291,10 +291,6 @@ static int cadence_spi_ofdata_to_platdata(struct
> > udevice *bus) plat->regbase = (void *)data[0];
> > plat->ahbbase = (void *)data[2];
> > 
> > -   /* Use 500KHz as a suitable default */
> > -   plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> > - 50);
> > -
> > /* All other paramters are embedded in the child node */
> > subnode = fdt_first_subnode(blob, node);
> > if (subnode < 0) {
> > @@ -302,6 +298,10 @@ static int cadence_spi_ofdata_to_platdata(struct
> > udevice *bus) return -ENODEV;
> > }
> > 
> > +   /* Use 500KHz as a suitable default */
> > +   plat->max_hz = fdtdec_get_int(blob, subnode, "spi-max-frequency",
> > + 50);
> 
> Use fdtdec_get_u32() or such, since the value is unsigned int (have you ever
> seen negative frequency ? ;-) ). Then check the fdtdec_get_u32() return value.
> 

I git grep and no unsigned version.
But I can add unsigned casting to avoid that.

Thanks
Chin Liang

> > /* Read other parameters from DT */
> > plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
> > plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
> 
> Best regards,
> Marek Vasut


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[U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change

[Chin Liang See]

Ensuring spi_calibration is run when there is a change of sclk
frequency. This will ensure the qspi flash access works for high
sclk frequency

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Marek Vasut 
Cc: Stefan Roese 
Cc: Vikas Manocha 
Cc: Jagannadh Teki 
Cc: Pavel Machek 
---
Changes for v2
- remove frequency set before calibration
- introducing previous_hz to store requested frequency
- prevent calibration run when request same frequency
---
 drivers/spi/cadence_qspi.c |   19 ---
 drivers/spi/cadence_qspi.h |1 +
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..23c88d5 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -37,7 +37,7 @@ static int cadence_spi_write_speed(struct udevice *bus, uint 
hz)
 }
 
 /* Calibration sequence to determine the read data capture delay register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
 {
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
@@ -46,6 +46,10 @@ static int spi_calibration(struct udevice *bus)
unsigned int idcode = 0, temp = 0;
int err = 0, i, range_lo = -1, range_hi = -1;
 
+   /* if calibrated frequency same as reqeusted, skip it */
+   if (priv->qspi_calibrated_hz == hz)
+   return 0;
+
/* start with slowest clock (1 MHz) */
cadence_spi_write_speed(bus, 100);
 
@@ -64,7 +68,7 @@ static int spi_calibration(struct udevice *bus)
}
 
/* use back the intended clock and find low range */
-   cadence_spi_write_speed(bus, plat->max_hz);
+   cadence_spi_write_speed(bus, hz);
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
@@ -111,7 +115,7 @@ static int spi_calibration(struct udevice *bus)
  (range_hi + range_lo) / 2, range_lo, range_hi);
 
/* just to ensure we do once only when speed or chip select change */
-   priv->qspi_calibrated_hz = plat->max_hz;
+   priv->qspi_calibrated_hz = hz;
priv->qspi_calibrated_cs = spi_chip_select(bus);
 
return 0;
@@ -126,14 +130,15 @@ static int cadence_spi_set_speed(struct udevice *bus, 
uint hz)
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
 
-   cadence_spi_write_speed(bus, hz);
-
/* Calibration required for different SCLK speed or chip select */
-   if (priv->qspi_calibrated_hz != plat->max_hz ||
+   if (priv->previous_hz != hz ||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
-   err = spi_calibration(bus);
+   err = spi_calibration(bus, hz);
if (err)
return err;
+
+   /* prevent calibration run when same as previous request */
+   priv->previous_hz = hz;
}
 
/* Enable QSPI */
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa..2912e36 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -38,6 +38,7 @@ struct cadence_spi_priv {
int qspi_is_init;
unsigned intqspi_calibrated_hz;
unsigned intqspi_calibrated_cs;
+   unsigned intprevious_hz;
 };
 
 /* Functions call declaration */
-- 
1.7.7.4

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[U-Boot] [PATCH 2/4] spi: cadence_qspi: Fix fdt read of spi-max-frequency

[Chin Liang See]

Fix the fdt read for spi-max-frequency as it's contained
in the child node. Current state of code is always
returning default value.

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Marek Vasut 
Cc: Stefan Roese 
Cc: Vikas Manocha 
Cc: Jagannadh Teki 
Cc: Pavel Machek 
---
Changes for v2
- Add unsigned casting for plat->max_hz
---
 drivers/spi/cadence_qspi.c |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 23c88d5..8c0f7dd 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -296,10 +296,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
 
-   /* Use 500KHz as a suitable default */
-   plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
- 50);
-
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
if (subnode < 0) {
@@ -307,6 +303,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
return -ENODEV;
}
 
+   /* Use 500KHz as a suitable default */
+   plat->max_hz = (unsigned int)fdtdec_get_int(blob, subnode,
+   "spi-max-frequency", 50);
+
/* Read other parameters from DT */
plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
-- 
1.7.7.4

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[U-Boot] [PATCH 4/4] arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash

[Chin Liang See]

With a working QSPI calibration, the SCLK can now run up to 100MHz

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Marek Vasut 
Cc: Stefan Roese 
Cc: Vikas Manocha 
Cc: Jagannadh Teki 
Cc: Pavel Machek 
Reviewed-by: Marek Vasut 
---
 arch/arm/dts/socfpga_cyclone5_socdk.dts |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts 
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9650eb0..04e5695 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -86,7 +86,7 @@
#size-cells = <1>;
compatible = "n25q00";
reg = <0>;  /* chip select */
-   spi-max-frequency = <5000>;
+   spi-max-frequency = <1>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
-- 
1.7.7.4

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[U-Boot] [PATCH 3/4] spi: cadence_qspi: Ensure check for max frequency in place

[Chin Liang See]

Ensure the intended SCLK frequency not exceeding the maximum
frequency. If that happen, SCLK will set to maximum frequency.

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Marek Vasut 
Cc: Stefan Roese 
Cc: Vikas Manocha 
Cc: Jagannadh Teki 
Cc: Pavel Machek 
---
 drivers/spi/cadence_qspi.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 8c0f7dd..f430b5d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -127,6 +127,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint 
hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
 
+   if (hz > plat->max_hz) {
+   hz = plat->max_hz;
+   puts("SF: Default to maximum supported SCLK frequency\n");
+   }
+
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
 
-- 
1.7.7.4

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[U-Boot] [PATCH] smsc95xx: Use zero length packets when RX fifo is empty

[Stefan Brüns]

Using NAKs on empty RX fifo for bulk in transfers is the right choice
for a interrupt driven model, but U-Boot uses polling and expects an
immediate answer if there is no incoming packet. Using ZLP Bulk In Response
(BIR) mode avoids unexpected timeouts in the host controller driver.

As ZLP mode is reset default, there is no need to set it.

Signed-off-by: Stefan Brüns 
---
The current setting results in timeouts in the dwc2 hc driver, if an expected
network response is lost. This is often hidden by incoming broadcast packets,
as these trigger the completion of the bulk in transfer as well.

 drivers/usb/eth/smsc95xx.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 6e80184..ae8bc18 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -531,22 +531,6 @@ static int smsc95xx_init_common(struct usb_device *udev, 
struct ueth_data *dev,
if (ret < 0)
return ret;
 
-   ret = smsc95xx_read_reg(udev, HW_CFG, _buf);
-   if (ret < 0)
-   return ret;
-   debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
-
-   read_buf |= HW_CFG_BIR_;
-   ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
-   if (ret < 0)
-   return ret;
-
-   ret = smsc95xx_read_reg(udev, HW_CFG, _buf);
-   if (ret < 0)
-   return ret;
-   debug("Read Value from HW_CFG after writing "
-   "HW_CFG_BIR_: 0x%08x\n", read_buf);
-
 #ifdef TURBO_MODE
if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
-- 
2.1.4

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Re: [U-Boot] [PATCH v5 5/9] arm: serial: Add ability to use pre-initialized UARTs

[Simon Glass]

Hi Sergey,

On 7 September 2015 at 09:18, Sergey Temerkhanov
 wrote:
> On some systems, UART initialization is performed before running U-Boot.
> This commit allows to skip UART re-initializaion on those systems
>
> Signed-off-by: Sergey Temerkhanov 
> Signed-off-by: Radha Mohan Chintakuntla 
>
> ---
>
> Changes in v5:
> - Added OF control support
>
> Changes in v4:
> - Fixed build warnings
> - Moved to DM_SERIAL
>
> Changes in v3:
> - Added __used keyword
>
> Changes in v2: None
>
>  drivers/serial/serial_pl01x.c   | 13 +++--
>  include/dm/platform_data/serial_pl01x.h |  6 ++
>  2 files changed, 13 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass 

But please see one issue below. Also you might consider implementing
the debug UART for this driver so you get early debugging,

>
> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
> index ecf3bc0..83151e0 100644
> --- a/drivers/serial/serial_pl01x.c
> +++ b/drivers/serial/serial_pl01x.c
> @@ -125,7 +125,7 @@ static int pl011_set_line_control(struct pl01x_regs *regs)
>  }
>
>  static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type 
> type,
> -   int clock, int baudrate)
> +  int clock, int baudrate)
>  {
> switch (type) {
> case TYPE_PL010: {
> @@ -295,7 +295,6 @@ __weak struct serial_device *default_serial_console(void)
>  #endif /* nCONFIG_DM_SERIAL */
>
>  #ifdef CONFIG_DM_SERIAL
> -
>  struct pl01x_priv {
> struct pl01x_regs *regs;
> enum pl01x_type type;
> @@ -306,9 +305,9 @@ static int pl01x_serial_setbrg(struct udevice *dev, int 
> baudrate)
> struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
> struct pl01x_priv *priv = dev_get_priv(dev);
>
> -   pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
> -
> -   return 0;
> +   return (plat->flags & PL0X_PREINITIALIZED) ? 0 :
> +   pl01x_generic_setbrg(priv->regs, priv->type,
> +plat->clock, baudrate);
>  }
>
>  static int pl01x_serial_probe(struct udevice *dev)
> @@ -318,7 +317,8 @@ static int pl01x_serial_probe(struct udevice *dev)
>
> priv->regs = (struct pl01x_regs *)plat->base;
> priv->type = plat->type;
> -   return pl01x_generic_serial_init(priv->regs, priv->type);
> +   return (plat->flags & PL0X_PREINITIALIZED) ? 0 :
> +   pl01x_generic_serial_init(priv->regs, priv->type);
>  }
>
>  static int pl01x_serial_getc(struct udevice *dev)
> @@ -372,6 +372,7 @@ static int pl01x_serial_ofdata_to_platdata(struct udevice 
> *dev)
> plat->base = addr;
> plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 
> 1);
> plat->type = dev_get_driver_data(dev);
> +   plat->flags = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "flags", 
> 0);

Can I suggest a boolean option here, like u-boot,skip-init? You can
use fdtdec_get_bool() to read it. Also please add it to
doc/device-tree-bindings/serial/pl01x.txt.

> return 0;
>  }
>  #endif
> diff --git a/include/dm/platform_data/serial_pl01x.h 
> b/include/dm/platform_data/serial_pl01x.h
> index 5e068f3..73e1be0 100644
> --- a/include/dm/platform_data/serial_pl01x.h
> +++ b/include/dm/platform_data/serial_pl01x.h
> @@ -11,17 +11,23 @@ enum pl01x_type {
> TYPE_PL011,
>  };
>
> +enum pl01x_flags {
> +   PL0X_PREINITIALIZED = 1 << 0, /* Skip port initialization */
> +};
> +
>  /*
>   *Information about a serial port
>   *
>   * @base: Register base address
>   * @type: Port type
>   * @clock: Input clock rate, used for calculating the baud rate divisor
> + * @flags: Port flags
>   */
>  struct pl01x_serial_platdata {
> unsigned long base;
> enum pl01x_type type;
> unsigned int clock;
> +   unsigned long flags;
>  };
>
>  #endif
> --
> 2.2.0
>

Regards,
Simon
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Re: [U-Boot] [PATCH v2 7/8] nios2: show fdt blob address in board info command

[Simon Glass]

Hi,

On 6 September 2015 at 08:27, Marek Vasut  wrote:
> On Sunday, September 06, 2015 at 03:20:21 PM, Thomas Chou wrote:
>> Hi Marek,
>>
>> >>> I think this will not work on 64bit machines.
>>
>> I tried 64bits with
>>
>>   print_lnum("fdt_blob", (u64)gd->fdt_blob);
>>
>> But got this warning,
>>
>>CC  common/cmd_bdinfo.o
>> common/cmd_bdinfo.c: In function 'do_bdinfo':
>> common/cmd_bdinfo.c:180:25: warning: cast from pointer to integer of
>> different size [-Wpointer-to-int-cast]
>>print_lnum("fdt_blob", (u64)gd->fdt_blob);
>>   ^
>> include/asm-generic/global_data.h
>>   const void *fdt_blob;   /* Our device tree, NULL if none */
>>
>> Actually, the print is guarded with CONFIG_NIOS2, so it is safe to use
>> 32bits.
>>
>> Or shall we invent a "print pointer address"?
>
> Simon, Tom, what's your take on this ?

>From what I can tell this code is not generic, and is built for NIOS
only. So IMO the patch is fine and we don't need to worry about
64-bit.

Regards,
Simon
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Re: [U-Boot] [PATCH] fs: ext4: fix symlink read function

[Simon Glass]

Hi Gary,

On 7 September 2015 at 03:20, Gary Bisson
 wrote:
> Since last API changes for files >2GB, the read of symlink is broken as
> ext4fs_read_file now returns 0 instead of the length of the actual read.
>
> Signed-off-by: Gary Bisson 
> ---
> Hi all,
>
> Switching from an old v2014.07 to v2015.07 we've noticed that we couldn't
> read symlinks any more. This is due to the API changes made to
> ext4fs_read_file (commit 9f12cd0).
>
> This patch makes the read symlink check both for errors (status < 0) and
> actual read length.
>
> Regards,
> Gary

Thanks for fixing this. Does the filesystem test (test/fs-test.sh)
show this error? How could we enhance the test to detect this?

> ---
>  fs/ext4/ext4_common.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
> index cab5465..e2ab145 100644
> --- a/fs/ext4/ext4_common.c
> +++ b/fs/ext4/ext4_common.c
> @@ -2040,7 +2040,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node 
> *node)
> status = ext4fs_read_file(diro, 0,
>__le32_to_cpu(diro->inode.size),
>symlink, );
> -   if (status == 0) {
> +   if ((status < 0) || (actread == 0)) {
> free(symlink);
> return 0;
> }
> --
> 2.5.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH v5 6/9] armv8: cavium: Add the device tree for ThunderX

[Simon Glass]

Hi Sergey,

On 7 September 2015 at 09:18, Sergey Temerkhanov
 wrote:
> This commit adds the FDT for the ThunderX family of SoCs
>
> Signed-off-by: Sergey Temerkhanov 
> Signed-off-by: Radha Mohan Chintakuntla 
>
> ---
>
> Changes in v5:
> - Added FDT for ThunderX 88xx series
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  arch/arm/dts/Makefile   |   1 +
>  arch/arm/dts/thunderx-88xx.dts  |  27 +++
>  arch/arm/dts/thunderx-88xx.dtsi | 363 
> 
>  3 files changed, 391 insertions(+)
>  create mode 100644 arch/arm/dts/thunderx-88xx.dts
>  create mode 100644 arch/arm/dts/thunderx-88xx.dtsi

Reviewed-by: Simon Glass 

You could add a chosen node with stdout-path for the UART.

Regards,
Simon
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Re: [U-Boot] please pull u-boot-arc master

[Tom Rini]

On Mon, Sep 07, 2015 at 10:46:26AM +, Alexey Brodkin wrote:

> Hi Tom,
> 
> The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:
> 
>   doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-arc.git 
> 
> for you to fetch changes up to a883f83e6d62fef1830b1634ccb72535c43696f7:
> 
>   arc: make AXS101 default platform (2015-09-07 13:38:24 +0300)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Mon, Sep 07, 2015 at 02:13:06PM +0200, Marek Vasut wrote:

> The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:
> 
>   doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git 
> 
> for you to fetch changes up to a7ed0ac2620b00c6eb85227f3c66bc169ad11f44:
> 
>   net: altera_tse: Zap unused variable (2015-09-04 16:09:44 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Mon, Sep 07, 2015 at 02:13:41PM +0200, Marek Vasut wrote:

> The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521:
> 
>   doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git 
> 
> for you to fetch changes up to 49b4c5c700077e387fef61a7225f92d190ee0c45:
> 
>   usb: ehci: remember init mode (2015-09-07 13:41:05 +0200)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [ANN] U-Boot v2015.10-rc3 released

[Tom Rini]

Hey all,

I've pushed v2015.10-rc3 out to the repository and tarballs should exist
soon.

I think this looks reasonable overall and we're on pace for release.
There's certainly a few fixes that need to come in but at least in the
case of the 64bit fdt nodes I want to be sure that we get a change in
that fixes everyone which I gather means a change in some boards dts
files too.  Thanks all!

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[U-Boot] [PATCH v3 2/2] arm: socfpga: config: Remove hard-coded drvsel and smpsel

[Chin Liang See]

Remove hard-coded SDMMC timing parameter drvsel and smplsel.
This setting now will come from SDMMC calibration

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 
---
 include/configs/socfpga_common.h |2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 38ae763..2a2fdc5 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -155,8 +155,6 @@
 #define CONFIG_DWMMC
 #define CONFIG_SOCFPGA_DWMMC
 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL0
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256 /* FIXME -- SPL only? */
-- 
1.7.7.4

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[U-Boot] [PATCH v3 1/2] mmc: socfpga_dw_mmc: Enable calibration for drvsel and smpsel

[Chin Liang See]

Enable SDMMC calibration to determine the best setting for
drvsel and smpsel. It will be triggered whenever there is
a change of card frequency and bus width. This is to ensure
reliable transmission between the controller and the card.

Signed-off-by: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Stefan Roese 
Cc: Pantelis Antoniou 
Cc: Simon Glass 
Cc: Jaehoon Chung 
---
Changes for v3
- Remove the && ok as its redundant
Changes for v2
- Using standard error return macro
- Split to small function to avoid deep identation
- Fix coding standard
---
 drivers/mmc/socfpga_dw_mmc.c |  198 --
 1 files changed, 191 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8076761..2161f694 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -13,25 +13,150 @@
 #include 
 #include 
 #include 
+#include "mmc_private.h"
 
 static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
 static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
 
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
+/*
+ * rows and columns of calibration rectange. The values are based on the value
+ * range of drvsel and smplsel register in system manager
+ */
+#define CAL_ROWS 7
+#define CAL_COLS 8
+
+int find_row_col_fit_rectangle(unsigned rect_width, unsigned rect_height,
+unsigned char cal_results[CAL_ROWS][CAL_COLS], unsigned int *cal_row,
+unsigned int *cal_col)
 {
-   unsigned int drvsel;
-   unsigned int smplsel;
+   unsigned char start_row, start_col;
+
+   /* Find the row and column where the candidate fits */
+   for (start_col = 0; start_col < (CAL_COLS - rect_width + 1);
+start_col++) {
+   for (start_row = 0; start_row < (CAL_ROWS - rect_height + 1);
+start_row++) {
+   unsigned ok = 1;
+   unsigned add_col, add_row;
+
+   /* Determine if the rectangle fits here */
+   for (add_col = 0; (add_col < rect_width); add_col++) {
+   for (add_row = 0; add_row < rect_height;
+add_row++) {
+   if (!cal_results[start_row + add_row]
+   [start_col + add_col]) {
+   ok = 0;
+   break;
+   }
+   }
+   }
+
+   /*
+* Return 'middle' of rectangle in case of
+* success
+*/
+   if (ok) {
+   if (rect_width > 1)
+   rect_width--;
+
+   if (rect_height > 1)
+   rect_height--;
 
+   *cal_row = start_row + (rect_height / 2);
+   *cal_col = start_col + (rect_width / 2);
+
+   return 0;
+   }
+   }
+   }
+   return -EINVAL;
+}
+
+/*
+ * This function determines the largest rectangle filled with 1's and returns
+ * the middle. This functon can be optimized, for example using the algorithm
+ * from http://www.drdobbs.com/database/the-maximal-rectangle-problem/184410529
+ * It currently takes less than 1ms, while creating the input data takes ~5ms
+ * so there is not a real need to optimize it.
+ */
+int find_calibration_point(unsigned char cal_results[CAL_ROWS][CAL_COLS],
+unsigned int sum, unsigned int *cal_row, unsigned int *cal_col)
+{
+   /* Structure containing a rectangle candidate */
+   struct rect_cand_t {
+   unsigned char height;
+   unsigned char width;
+   unsigned short area;
+   };
+
+   /* Array with the rectangle candidates */
+   struct rect_cand_t rect_cands[CAL_ROWS * CAL_COLS], tmp;
+   unsigned char cr_rect_cand = 0;
+   unsigned char height, width, k;
+
+   /* No solution if all combinations fail */
+   if (sum == 0)
+   return -EINVAL;
+
+   /* Simple solution if all combinations pass */
+   if (sum == (CAL_ROWS * CAL_COLS)) {
+   *cal_row = (CAL_ROWS - 1) / 2;
+   *cal_col = (CAL_COLS - 1) / 2;
+   return 0;
+   }
+
+   /*
+* Create list of all possible sub-rectangles, in descending area
+* order
+

Re: [U-Boot] Any more patches for x86?

[Bin Meng]

Hi Simon,

On Tue, Sep 8, 2015 at 11:50 AM, Simon Glass  wrote:
> Hi Bin,
>
> Do you have any other patches that you think should be applied for the
> upcoming release? I'd like to get these in before sending out the last
> big pull request.
>

I have one last Quark patch series I think it's good to get in the
upcoming release. The series enables booting Linux kernel on Quark.
Currently the Linux kernel boot just hangs on Galileo. I will be
sending the patch series today.

Regards,
Bin
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Re: [U-Boot] [PATCH] driver: misc: correct Kconfig entry

[Peng Fan]

Hi,

On Wed, Aug 26, 2015 at 06:19:38AM -0700, Simon Glass wrote:
>On 26 August 2015 at 00:41, Peng Fan  wrote:
>> Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry.
>>
>> Signed-off-by: Peng Fan 
>> Cc: Simon Glass 
>> Cc: Masahiro Yamada 
>> Cc: Fabio Estevam 
>> Cc: York Sun 
>> Cc: Stefan Roese 
>> Cc: Tom Rini 
>> ---
>>  drivers/misc/Kconfig | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
>Acked-by: Simon Glass 

Will this patch be applied? It's about two weeks since this patch sent out for 
review.

Thanks,
Peng.
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Re: [U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel

[Chin Liang See]

Hi,

On Mon, 2015-09-07 at 03:33 +, Jaehoon Chung wrote:
> Hi,
> 
> On 09/04/2015 07:41 PM, Pavel Machek wrote:
> > Hi!
> > 
> >>> How is this SMPLSEL and DRVSEL implemented on Exynos ?
> >
> > Exynos is using CLKSEL register in dw-mmc controller.
> > It's exynos specific register in dwmmc controller. It's also
> > represented 45 degree increment. SELCK_DRV is bit[18:16] or more.
> > SELCLK_SAMPLE is bit[2:0] or more. There are other bits relevant to
> > tuning clock. '_more_' means that it can be changed bandwidth.
> >
> > Anyway, I think there is no right method about finding the best smplclk
> > and drvsel. If this is generic method, i will pick this. But i don't
> > think so, and there is no benefit for exynos.
> >
> > smplclk and drvsel value need to process the tuning sequence.
> > There is no tuning case at bootloader, since it's not implemented about
> > HS200 or upper mode.
> >
> > Clksel an drvsel value are passed by device tree.
> 
>  In that case, maybe SoCFPGA should also pick those values from DT ? It
>  would keep the code simple and in case there is a problematic board, it
>  could use u-boot application to perform the tuning.
> >>>
> >>> I prefer not to do that as it narrows the supported use case for the
> >>> driver.
> >>
> >> How so? It keeps the driver code clean and this code you're adding seems
> >> like a special-purpose stuff which needs to be done once for particular
> >> board, no ?
> > 
> > Well... stuff that can be automatically detected is not supposed to be
> > in the device tree.
> > 
> > clksel and drvsel can be calibrated, so I see some arguments why we
> > should calibrate them, and not hardcode them in the device tree.
> 
> My opinions are 
> 
> 1. This code is not generic dwmmc code. So i don't want to locate into dwmmc 
> core.
> If need to apply, i agree that it applies this in socfpga-dw_mmc.c.
> 

Yup, let move that to socfpga-dw_mmc.c as majority believe that is
correct way to move forward. I shall send in v3 which integrate Pavel's
comment in v2

> 2. In exynos, value of devcie-tree is the tested value.
> After has tested with every values, it defined the best value into 
> device-tree.
> (Working fine with values.)
> At every time, it doesn't need to detect the best value with same SoC.
> (Especially, at bootloader)
> 
> 3. In my experiment, there should be side-effect during finding best 
> sample/drv value.
> 
> 4. If HS200 or upper mode is supported at bootloader, it needs the tuning 
> sequence.
> Then it needs to find the best sampl/drv values. but it doesn't support HS200 
> or other at bootloader.
> 

Yah, normally it will not need that.
As we are catering for various customer board design, this calibration
will help even they routed the SDMMC slot few inches away.

> 5. Affect at booting time??

We measured this before and it took around ~5.2ms for worst case.

Thanks
Chin Liang

> 
> 
> Best Regards,
> Jaehoon Chung
> 
> > Pavel
> > 
> 


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[U-Boot] [PATCH 1/3] spi: xilinx_spi: Fix to configure CPOL, CPHA mask

[Jagan Teki]

priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki 
---
 drivers/spi/xilinx_spi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 6c21acd..8ccc578 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -247,7 +247,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint 
speed)
 
priv->freq = speed;
 
-   debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs,
+   debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
  priv->freq);
 
return 0;
@@ -260,13 +260,13 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint 
mode)
uint32_t spicr;
 
spicr = readl(>spicr);
-   if (priv->mode & SPI_LSB_FIRST)
+   if (mode & SPI_LSB_FIRST)
spicr |= SPICR_LSB_FIRST;
-   if (priv->mode & SPI_CPHA)
+   if (mode & SPI_CPHA)
spicr |= SPICR_CPHA;
-   if (priv->mode & SPI_CPOL)
+   if (mode & SPI_CPOL)
spicr |= SPICR_CPOL;
-   if (priv->mode & SPI_LOOP)
+   if (mode & SPI_LOOP)
spicr |= SPICR_LOOP;
 
writel(spicr, >spicr);
-- 
1.9.1

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[U-Boot] [PATCH 2/3] spi: zynq_spi: Fix to configure CPOL, CPHA mask

[Jagan Teki]

priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki 
---
 drivers/spi/zynq_spi.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index d6057e6..65a9633 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -278,7 +278,8 @@ static int zynq_spi_set_speed(struct udevice *bus, uint 
speed)
writel(confr, >cr);
priv->freq = speed;
 
-   debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
+   debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
+ priv->regs, priv->freq);
 
return 0;
 }
@@ -293,9 +294,9 @@ static int zynq_spi_set_mode(struct udevice *bus, uint mode)
confr = readl(>cr);
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
 
-   if (priv->mode & SPI_CPHA)
+   if (mode & SPI_CPHA)
confr |= ZYNQ_SPI_CR_CPHA_MASK;
-   if (priv->mode & SPI_CPOL)
+   if (mode & SPI_CPOL)
confr |= ZYNQ_SPI_CR_CPOL_MASK;
 
writel(confr, >cr);
-- 
1.9.1

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[U-Boot] [PATCH 3/3] spi: zynq_qspi: Fix to configure CPOL, CPHA mask

[Jagan Teki]

priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki 
---
 drivers/spi/zynq_qspi.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 0ce6127..8aa61d7 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -569,7 +569,8 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint 
speed)
writel(confr, >cr);
priv->freq = speed;
 
-   debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
+   debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
+ priv->regs, priv->freq);
 
return 0;
 }
@@ -584,9 +585,9 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint 
mode)
confr = readl(>cr);
confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
 
-   if (priv->mode & SPI_CPHA)
+   if (mode & SPI_CPHA)
confr |= ZYNQ_QSPI_CR_CPHA_MASK;
-   if (priv->mode & SPI_CPOL)
+   if (mode & SPI_CPOL)
confr |= ZYNQ_QSPI_CR_CPOL_MASK;
 
writel(confr, >cr);
-- 
1.9.1

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Re: [U-Boot] [PATCH 1/2] mx6: remove SYS_SOC from board Kconfig

[Christian Gmeiner]

2015-09-07 8:59 GMT+02:00 Peng Fan :
> Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
> because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.
>
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Heiko Schocher 
> Cc: Christian Gmeiner 
> Cc: Stefan Roese 
> Cc: Troy Kisky 
> Cc: Nikita Kiryanov 
> Cc: "Eric Bénard" 
> Cc: Fabio Estevam 
> Cc: Tim Harvey 
> Cc: Marek Vasut 
> Cc: Markus Niebel 
> Cc: Otavio Salvador 

For ot1200:

Acked-by: Christian Gmeiner 

greets
--
Christian Gmeiner, MSc

https://soundcloud.com/christian-gmeiner
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Re: [U-Boot] [PATCH v4 5/8] arm: serial: Add ability to use pre-initialized UARTs

[Sergei Temerkhanov]

On Sat, Aug 22, 2015 at 3:36 AM, Simon Glass  wrote:
> Hi Serkey,
>
> On 18 August 2015 at 06:26, Sergey Temerkhanov  
> wrote:
>> On some systems, UART initialization is performed before running U-Boot.
>> This commit allows to skip UART re-initializaion on those systems
>>
>> Signed-off-by: Sergey Temerkhanov 
>> Signed-off-by: Radha Mohan Chintakuntla 
>>
>> ---
>>
>> Changes in v4:
>> - Fixed build warnings
>> - Moved to DM_SERIAL
>>
>> Changes in v3:
>> - Added __used keyword
>>
>> Changes in v2: None
>>
>>  drivers/serial/serial_pl01x.c   | 12 ++--
>>  include/dm/platform_data/serial_pl01x.h |  6 ++
>>  2 files changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
>> index ad503af..037fd23 100644
>> --- a/drivers/serial/serial_pl01x.c
>> +++ b/drivers/serial/serial_pl01x.c
>> @@ -125,7 +125,7 @@ static int pl011_set_line_control(struct pl01x_regs 
>> *regs)
>>  }
>>
>>  static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type 
>> type,
>> -   int clock, int baudrate)
>> +  int clock, int baudrate)
>>  {
>> switch (type) {
>> case TYPE_PL010: {
>> @@ -295,7 +295,6 @@ __weak struct serial_device *default_serial_console(void)
>>  #endif /* nCONFIG_DM_SERIAL */
>>
>>  #ifdef CONFIG_DM_SERIAL
>> -
>>  struct pl01x_priv {
>> struct pl01x_regs *regs;
>> enum pl01x_type type;
>> @@ -306,9 +305,9 @@ static int pl01x_serial_setbrg(struct udevice *dev, int 
>> baudrate)
>> struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
>> struct pl01x_priv *priv = dev_get_priv(dev);
>>
>> -   pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
>> -
>> -   return 0;
>> +   return (plat->flags & PL0x_PREINITIALIZED) ? 0 :
>> +   pl01x_generic_setbrg(priv->regs, priv->type,
>> +plat->clock, baudrate);
>>  }
>>
>>  static int pl01x_serial_probe(struct udevice *dev)
>> @@ -318,7 +317,8 @@ static int pl01x_serial_probe(struct udevice *dev)
>>
>> priv->regs = (struct pl01x_regs *)plat->base;
>> priv->type = plat->type;
>> -   return pl01x_generic_serial_init(priv->regs, priv->type);
>> +   return (plat->flags & PL0x_PREINITIALIZED) ? 0 :
>> +   pl01x_generic_serial_init(priv->regs, priv->type);
>>  }
>>
>>  static int pl01x_serial_getc(struct udevice *dev)
>> diff --git a/include/dm/platform_data/serial_pl01x.h 
>> b/include/dm/platform_data/serial_pl01x.h
>> index 5e068f3..455121b 100644
>> --- a/include/dm/platform_data/serial_pl01x.h
>> +++ b/include/dm/platform_data/serial_pl01x.h
>> @@ -11,17 +11,23 @@ enum pl01x_type {
>> TYPE_PL011,
>>  };
>>
>> +enum pl01x_flags {
>> +   PL0x_PREINITIALIZED = 1 << 0, /* Skip port initialization */
>> +};
>> +
>>  /*
>>   *Information about a serial port
>>   *
>>   * @base: Register base address
>>   * @type: Port type
>>   * @clock: Input clock rate, used for calculating the baud rate divisor
>> + * @flags: Port flags
>>   */
>>  struct pl01x_serial_platdata {
>> unsigned long base;
>> enum pl01x_type type;
>> unsigned int clock;
>> +   unsigned long flags;
>>  };
>>
>>  #endif
>
> This patch is fine as far as it goes (although the x in
> PL0x_PREINITIALIZED should be capitalised to match style I think).

Agreed

>
> But why doesn't this board use device tree (CONFIG_OF_CONTROL)? Do you
> have a device tree file for it?

OK, I'll import one from the Linux kernel.

>
> Regards,
> Simon

Regards,
Sergey
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Re: [U-Boot] [PATCH v4 1/4] bitops: introduce BIT() definition

[Jagan Teki]

On 7 September 2015 at 17:45, Marek Vasut  wrote:
> On Monday, September 07, 2015 at 02:01:11 PM, Andreas Bießmann wrote:
>> Hi Heiko,
>>
>> On 2015-09-07 13:52, Heiko Schocher wrote:
>> > Hello Andreas,
>> >
>> > Am 07.09.2015 um 13:20 schrieb Andreas Bießmann:
>> >> On 08/21/2015 07:01 PM, Heiko Schocher wrote:
>> >>> introduce BIT() definition, used in at91_udc gadget
>> >>> driver.
>> >>>
>> >>> Signed-off-by: Heiko Schocher 
>> >>
>> >> NAK, this one breaks a lot of boards which already defined BIT()
>> >
>> > Uhh... seems this BIT() macro is a big mess ...
>> >
>> > Hmm Wolfgang Denk NACKed a similiar patch:
>> > http://lists.denx.de/pipermail/u-boot/2014-February/173669.html
>> >
>> > In drivers/usb/gadget/at91_udc.c BIT(x) is used only once...
>> > So I fix it there and use (1 << x) there. Would be this OK?
>>
>> I'm fine with this solution.
>
> On the other hand, mainline Linux is moving towards GENMASK() and BIT(),
> so we should probably go with that as well.

Sent some couple of patches to use these macros, but Wolfgang Denk is
not quite OK, with this move.

https://patchwork.ozlabs.org/patch/470475/
https://patchwork.ozlabs.org/patch/470476/
https://patchwork.ozlabs.org/patch/470477/
https://patchwork.ozlabs.org/patch/470478/
https://patchwork.ozlabs.org/patch/470479/

thanks!
-- 
Jagan | openedev.
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Re: [U-Boot] [PATCH v2] spi: tegra20: Add support for mode selection

[Jagan Teki]

On 7 September 2015 at 12:09, Mirza Krak  wrote:
> From: Mirza Krak 
>
> Respect the mode passed in claim_bus call.
>
> Signed-off-by: Mirza Krak 
> ---
>
> Changes in v2:
> * Refactor clearing the CPOL and CPHA bits. Based on comments from Jagan Teki.
>
>  drivers/spi/tegra20_slink.c | 17 +
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
> index fbb665b86f3f..fa39dea2daf1 100644
> --- a/drivers/spi/tegra20_slink.c
> +++ b/drivers/spi/tegra20_slink.c
> @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define SLINK_CMD_ENB  (1 << 31)
>  #define SLINK_CMD_GO   (1 << 30)
>  #define SLINK_CMD_M_S  (1 << 28)
> +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW  (0 << 24)
> +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24)
> +#define SLINK_CMD_IDLE_SCLK_PULL_LOW   (2 << 24)
> +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH  (3 << 24)
> +#define SLINK_CMD_IDLE_SCLK_MASK   (3 << 24)
>  #define SLINK_CMD_CK_SDA   (1 << 21)
>  #define SLINK_CMD_CS_POL   (1 << 13)
>  #define SLINK_CMD_CS_VAL   (1 << 12)
> @@ -146,6 +151,7 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
> struct udevice *bus = dev->parent;
> struct tegra30_spi_priv *priv = dev_get_priv(bus);
> struct spi_regs *regs = priv->regs;
> +   unsigned int mode = priv->mode;
> u32 reg;
>
> /* Change SPI clock to correct frequency, PLLP_OUT0 source */
> @@ -161,6 +167,17 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
> /* Set master mode and sw controlled CS */
> reg = readl(>command);
> reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
> +
> +   /* Set CPOL and CPHA */
> +   reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
> +   if (mode & SPI_CPHA)
> +   reg |= SLINK_CMD_CK_SDA;
> +
> +   if (mode & SPI_CPOL)
> +   reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
> +   else
> +   reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
> +

And also this mode should be part of .set_mode ops like speed we have
one more ops to configure mode (clock phase and polarities)

> writel(reg, >command);
> debug("%s: COMMAND = %08x\n", __func__, readl(>command));
>
> --
> 2.1.0
>

thanks!
-- 
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[U-Boot] [PATCH v5 2/9] armv8: New MMU setup code allowing to use 48+ bits PA/VA

[Sergey Temerkhanov]

This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov 
Signed-off-by: Radha Mohan Chintakuntla 

---

Changes in v5:
- Allow setting of different memory attributes in the memory
  map

Changes in v4:
- Use ALIGN macro for address alignment

Changes in v3:
- Reduced code duplication
- Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
- Moved 'reset_sctrl' call to the 'reset' label
- Rebased to the actual upstream tree
- Documented newly added config options

Changes in v2:
- Changed code licensing
- Completed the patchset

 arch/arm/cpu/armv8/cache_v8.c  | 79 
 arch/arm/cpu/armv8/start.S | 36 +
 arch/arm/include/asm/armv8/mmu.h   | 82 +++---
 arch/arm/include/asm/global_data.h |  1 +
 arch/arm/include/asm/system.h  |  7 
 arch/arm/lib/board.c   |  6 ++-
 doc/README.arm64   | 35 +---
 7 files changed, 232 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6bde1cf..989b17e 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,6 +12,69 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_SYS_FULL_VA
+static void set_ptl1_entry(u64 index, u64 ptl2_entry)
+{
+   u64 *pgd = (u64 *)gd->arch.tlb_addr;
+   u64 value;
+
+   value = ptl2_entry | PTL1_TYPE_TABLE;
+   pgd[index] = value;
+}
+
+static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs)
+{
+   u64 *pmd = (u64 *)ptl1;
+   u64 value;
+
+   value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
+   value |= memory_attrs;
+   pmd[bfn] = value;
+}
+
+static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+
+#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
+#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+
+static void setup_pgtables(void)
+{
+   int l1_e, l2_e;
+   unsigned long pmd = 0;
+   unsigned long address;
+
+   /* Setup the PMD pointers */
+   for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
+   gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +
+   PTL1_ENTRIES * sizeof(u64);
+   gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
+   gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e],
+   0x1UL);
+   }
+
+   /* Setup the page tables */
+   for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
+   if (mem_map[pmd].base ==
+   (uintptr_t)l1_e << PTL2_BITS) {
+   set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);
+
+   for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {
+   address = mem_map[pmd].base
+   + (uintptr_t)l2_e * BLOCK_SIZE;
+   set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,
+  address, mem_map[pmd].attrs);
+   }
+
+   pmd++;
+   } else {
+   set_ptl1_entry(l1_e, 0);
+   }
+   }
+}
+
+#else
+
 inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
 u64 memory_type, u64 share)
 {
@@ -31,13 +94,25 @@ inline void set_pgtable_table(u64 *page_table, u64 index, 
u64 *table_addr)
page_table[index] = value;
 }
 
+#endif
+
+
 /* to activate the MMU we need to set up virtual memory */
 static void mmu_setup(void)
 {
+#ifndef CONFIG_SYS_FULL_VA
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
+#endif
int el;
 
+#ifdef CONFIG_SYS_FULL_VA
+   unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK;
+
+   /* Set up page tables only on BSP */
+   if (coreid == BSP_COREID)
+   setup_pgtables();
+#else
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
set_pgtable_section(page_table, i, i << SECTION_SHIFT,
@@ -55,6 +130,7 @@ static void mmu_setup(void)
}
}
 
+#endif
/* load TTBR0 */
el = current_el();
if (el == 1) {
@@ -154,6 +230,7 @@ u64 *__weak arch_get_page_table(void) {
return NULL;
 }
 
+#ifndef CONFIG_SYS_FULL_VA
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 enum dcache_option option)
 {
@@ 

[U-Boot] [PATCH v5 0/9] Add support for ThunderX 88xx SoC family

[Sergey Temerkhanov]

This patch series adds support for Cavium ThunderX 88xx SoC family
(http://cavium.com/ThunderX_ARM_Processors.html)

This is the version 5 of the series I posted at
http://lists.denx.de/pipermail/u-boot/2015-August/224324.html
http://lists.denx.de/pipermail/u-boot/2015-August/223618.html


Changes in v5:
- Allow setting of different memory attributes in the memory
  map
- Added OF control support
- Added FDT for ThunderX 88xx series
- Added CONFIG_OF_CONTROL support
- Changed memory attributes
- Moved dram_init() from a separate file to thunderx.c

Changes in v4:
- Use ALIGN macro for address alignment
- Document FW calls
- Fixed build warnings
- Moved to DM_SERIAL
- Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig
- Added proper DM_SERIAL definitions

Changes in v3:
- Reduced code duplication
- Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
- Moved 'reset_sctrl' call to the 'reset' label
- Rebased to the actual upstream tree
- Documented newly added config options
- Fixed clobber lists (thanks to Corey)
- Added __used keyword
- Fixed formatting
- Added MAINTAINERS
- Moved command definitions to defconfig

Changes in v2:
- Changed code licensing
- Completed the patchset

Sergey Temerkhanov (9):
  armv8: Add read_mpidr() function
  armv8: New MMU setup code allowing to use 48+ bits PA/VA
  armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
  armv8: Add psci.h from the Linux kernel
  arm: serial: Add ability to use pre-initialized UARTs
  armv8: cavium: Add the device tree for ThunderX
  armv8: cavium: Add ThunderX 88xx board definition
  armv8: cavium: Add an implementation of ATF calling functions
  armv8: cavium: Get DRAM size from ATF

 arch/arm/Kconfig|   5 +
 arch/arm/cpu/armv8/Makefile |   1 +
 arch/arm/cpu/armv8/cache_v8.c   |  79 +++
 arch/arm/cpu/armv8/fwcall.c |  75 +++
 arch/arm/cpu/armv8/start.S  |  36 
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/thunderx-88xx.dts  |  27 +++
 arch/arm/dts/thunderx-88xx.dtsi | 363 
 arch/arm/include/asm/armv8/mmu.h|  82 +++-
 arch/arm/include/asm/global_data.h  |   1 +
 arch/arm/include/asm/system.h   |  39 
 arch/arm/lib/board.c|   6 +-
 board/cavium/thunderx/Kconfig   |  19 ++
 board/cavium/thunderx/MAINTAINERS   |   6 +
 board/cavium/thunderx/Makefile  |   8 +
 board/cavium/thunderx/atf.c | 312 +++
 board/cavium/thunderx/thunderx.c| 102 +
 configs/thunderx_88xx_defconfig |  29 +++
 doc/README.arm64|  35 ++-
 drivers/serial/serial_pl01x.c   |  13 +-
 include/cavium/atf.h|  22 ++
 include/cavium/atf_part.h   |  26 +++
 include/cavium/thunderx_svc.h   |  67 ++
 include/configs/thunderx_88xx.h | 148 +
 include/dm/platform_data/serial_pl01x.h |   6 +
 include/linux/psci.h|  90 
 26 files changed, 1578 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fwcall.c
 create mode 100644 arch/arm/dts/thunderx-88xx.dts
 create mode 100644 arch/arm/dts/thunderx-88xx.dtsi
 create mode 100644 board/cavium/thunderx/Kconfig
 create mode 100644 board/cavium/thunderx/MAINTAINERS
 create mode 100644 board/cavium/thunderx/Makefile
 create mode 100644 board/cavium/thunderx/atf.c
 create mode 100644 board/cavium/thunderx/thunderx.c
 create mode 100644 configs/thunderx_88xx_defconfig
 create mode 100644 include/cavium/atf.h
 create mode 100644 include/cavium/atf_part.h
 create mode 100644 include/cavium/thunderx_svc.h
 create mode 100644 include/configs/thunderx_88xx.h
 create mode 100644 include/linux/psci.h

-- 
2.2.0

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