Re: [U-Boot] [PATCH v1 01/12] rockchip: define SUPPORT_SPL and SPL config in RK3288 config

[Eddie Cai]

Hi Simon

2015-10-22 22:07 GMT+08:00 Simon Glass :

> Hi Lin,
>
> On 20 October 2015 at 20:37, Lin Huang  wrote:
> > it may not use SPL in other rockchip SOC, so move SUPPORT_SPL and
> > SPL config to rk3288 configuration.
> >
> > Signed-off-by: Lin Huang 
> > ---
> > Changes in v1: None
> >
> >  arch/arm/Kconfig   | 2 --
> >  arch/arm/mach-rockchip/Kconfig | 2 ++
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 194fb7b..40fa741 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -831,8 +831,6 @@ config TARGET_STM32F429_DISCOVERY
> >
> >  config ARCH_ROCKCHIP
> > bool "Support Rockchip SoCs"
> > -   select SUPPORT_SPL
> > -   select SPL
> > select OF_CONTROL
> > select CPU_V7
> > select DM
> > diff --git a/arch/arm/mach-rockchip/Kconfig
> b/arch/arm/mach-rockchip/Kconfig
> > index ab50f4e..15cd380 100644
> > --- a/arch/arm/mach-rockchip/Kconfig
> > +++ b/arch/arm/mach-rockchip/Kconfig
> > @@ -2,6 +2,8 @@ if ARCH_ROCKCHIP
> >
> >  config ROCKCHIP_RK3288
> > bool "Support Rockchip RK3288"
> > +   select SUPPORT_SPL
> > +   select SPL
> > help
> >   The Rockchip RK3288 is a ARM-based SoC with a quad-core
> Cortex-A17
> >   including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
> > --
> > 1.9.1
> >
>
> We should avoid little binary blobs for booting the chip. I think we
> can live with this as a stepping stone to having a proper SPL, but
> what is the plan for a proper SPL in U-Boot?
>
RK3036 have only 8k sram. 4k used by boot rom. The ddr initialize code is
almost 4k. So i don't think we can do SPL.

>
> Regards,
> Simon
>
>
>


-- 
Eddie
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[U-Boot] [PATCH v3 1/4] spi: zynq_[q]spi: Use BIT macro

[Jagan Teki]

BIT macro used on zynq_spi.c and zynq_qspi.c

Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
Changes for v3, v2:
- none

 drivers/spi/zynq_qspi.c | 20 ++--
 drivers/spi/zynq_spi.c  | 16 
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 8aa61d7..dd530a1 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -16,20 +16,20 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq qspi register bit masks ZYNQ_QSPI___MASK */
-#define ZYNQ_QSPI_CR_IFMODE_MASK   (1 << 31)   /* Flash intrface mode*/
-#define ZYNQ_QSPI_CR_MSA_MASK  (1 << 15)   /* Manual start enb */
-#define ZYNQ_QSPI_CR_MCS_MASK  (1 << 14)   /* Manual chip select */
-#define ZYNQ_QSPI_CR_PCS_MASK  (1 << 10)   /* Peri chip select */
+#define ZYNQ_QSPI_CR_IFMODE_MASK   BIT(31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK  BIT(15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK  BIT(14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK  BIT(10) /* Peri chip select */
 #define ZYNQ_QSPI_CR_FW_MASK   (0x3 << 6)  /* FIFO width */
 #define ZYNQ_QSPI_CR_SS_MASK   (0xF << 10) /* Slave Select */
 #define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3)  /* Baud rate div */
-#define ZYNQ_QSPI_CR_CPHA_MASK (1 << 2)/* Clock phase */
-#define ZYNQ_QSPI_CR_CPOL_MASK (1 << 1)/* Clock polarity */
-#define ZYNQ_QSPI_CR_MSTREN_MASK   (1 << 0)/* Mode select */
-#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK(1 << 4)/* RX_FIFO_not_empty */
-#define ZYNQ_QSPI_IXR_TXOW_MASK(1 << 2)/* 
TX_FIFO_not_full */
+#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2)  /* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1)  /* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK   BIT(0)  /* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASKBIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASKBIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK 0x7F/* All IXR bits */
-#define ZYNQ_QSPI_ENR_SPI_EN_MASK  (1 << 0)/* SPI Enable */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK  BIT(0)  /* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C/* Transmit 4-byte inst */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 65a9633..92e5712 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -20,17 +20,17 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI___MASK */
-#define ZYNQ_SPI_CR_MSA_MASK   (1 << 15)   /* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK   (1 << 14)   /* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK   BIT(15) /* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK   BIT(14) /* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK(0xF << 10) /* Chip select */
 #define ZYNQ_SPI_CR_BAUD_MASK  (0x7 << 3)  /* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK  (1 << 2)/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK  (1 << 1)/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK(1 << 0)/* Mode select 
*/
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4)/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2)/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK  BIT(2)  /* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK  BIT(1)  /* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASKBIT(0)  /* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK  0x7F/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK   (1 << 0)/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK   BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX   8   /* Baud rate divisor max val */
 #define ZYNQ_SPI_CR_BAUD_SHIFT 3   /* Baud rate divisor shift */
-- 
1.9.1

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[U-Boot] [PATCH v3 4/4] spi: Use GENMASK instead of numeric hexcodes

[Jagan Teki]

Updated numeric hexcodes with GENMASK macro in spi drivers.

Cc: Tom Rini 
Cc: Simon Glass 
Cc: Masahiro Yamada 
Cc: Peng Fan 
Cc: Stefan Roese 
Cc: Marek Vasut 
Cc: Stephen Warren 
Cc: Tom Warren 
Signed-off-by: Jagan Teki 
---
Changes for v3, v2:
- none

 drivers/spi/atmel_spi.h|  2 +-
 drivers/spi/cadence_qspi_apb.c | 48 +-
 drivers/spi/designware_spi.c   |  2 +-
 drivers/spi/fsl_qspi.c |  2 +-
 drivers/spi/mxs_spi.c  |  2 +-
 drivers/spi/omap3_spi.h| 10 -
 drivers/spi/tegra114_spi.c | 12 +--
 drivers/spi/tegra20_sflash.c   |  2 +-
 drivers/spi/tegra20_slink.c|  4 ++--
 drivers/spi/xilinx_spi.c   | 14 ++--
 10 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 5b892d2..76b8556 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT   BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX0xff
+#define ATMEL_SPI_CSRx_SCBR_MAXGENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)   ((x) << 24)
 
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7786dd6..31e14ee 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -44,7 +44,7 @@
 #define CQSPI_INST_TYPE_QUAD   (2)
 
 #define CQSPI_STIG_DATA_LEN_MAX(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK(0xF)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASKGENMASK(19, 0)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
 #define CQSPI_DUMMY_BYTES_MAX  (4)
@@ -65,8 +65,8 @@
 #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10
 #defineCQSPI_REG_CONFIG_BAUD_LSB   19
 #defineCQSPI_REG_CONFIG_IDLE_LSB   31
-#defineCQSPI_REG_CONFIG_CHIPSELECT_MASK0xF
-#defineCQSPI_REG_CONFIG_BAUD_MASK  0xF
+#defineCQSPI_REG_CONFIG_CHIPSELECT_MASKGENMASK(3, 0)
+#defineCQSPI_REG_CONFIG_BAUD_MASK  GENMASK(3, 0)
 
 #defineCQSPI_REG_RD_INSTR  0x04
 #defineCQSPI_REG_RD_INSTR_OPCODE_LSB   0
@@ -75,10 +75,10 @@
 #defineCQSPI_REG_RD_INSTR_TYPE_DATA_LSB16
 #defineCQSPI_REG_RD_INSTR_MODE_EN_LSB  20
 #defineCQSPI_REG_RD_INSTR_DUMMY_LSB24
-#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   0x1F
+#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   GENMASK(4, 0)
 
 #defineCQSPI_REG_WR_INSTR  0x08
 #defineCQSPI_REG_WR_INSTR_OPCODE_LSB   0
@@ -88,23 +88,23 @@
 #defineCQSPI_REG_DELAY_TCHSH_LSB   8
 #defineCQSPI_REG_DELAY_TSD2D_LSB   16
 #defineCQSPI_REG_DELAY_TSHSL_LSB   24
-#defineCQSPI_REG_DELAY_TSLCH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TCHSH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSD2D_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSHSL_MASK  0xFF
+#defineCQSPI_REG_DELAY_TSLCH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TCHSH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSD2D_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSHSL_MASK  GENMASK(7, 0)
 
 #defineCQSPI_READLCAPTURE  0x10
 #defineCQSPI_READLCAPTURE_BYPASS_LSB   0
 #defineCQSPI_READLCAPTURE_DELAY_LSB1
-#defineCQSPI_READLCAPTURE_DELAY_MASK   0xF
+#defineCQSPI_READLCAPTURE_DELAY_MASK   GENMASK(3, 0)
 
 #defineCQSPI_REG_SIZE  0x14
 #defineCQSPI_REG_SIZE_ADDRESS_LSB  0
 #defineCQSPI_REG_SIZE_PAGE_LSB 4
 #defineCQSPI_REG_SIZE_BLOCK_LSB16
-#defineCQSPI_REG_SIZE_ADDRESS_MASK 0xF
-#defineCQSPI_REG_SIZE_PAGE_MASK0xFFF
-#defineCQSPI_REG_SIZE_BLOCK_MASK   0x3F
+#defineCQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0)

Re: [U-Boot] [PATCH v3 3/4] spi: Use BIT macro in spi/drivers/*

[Marek Vasut]

On Thursday, October 22, 2015 at 08:21:29 PM, Jagan Teki wrote:
> On 22 October 2015 at 23:45, Marek Vasut  wrote:
> > On Thursday, October 22, 2015 at 07:45:49 PM, Jagan Teki wrote:
> >> BIT macro used on drivers/spi/*
> >> 
> >> Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31
> >> 
> >> Cc: Tom Rini 
> >> Cc: Simon Glass 
> >> Cc: Masahiro Yamada 
> >> Cc: Peng Fan 
> >> Cc: Stefan Roese 
> >> Cc: Marek Vasut 
> >> Cc: Stephen Warren 
> >> Cc: Tom Warren 
> >> Signed-off-by: Jagan Teki 
> > 
> > So, you're sending this horrid blob of changes instead of splitting them
> > into more managable parts, sigh. Moreover, I have a feeling this is a
> > change for the sake of changing something, not great. Also, you did not
> > describe how you performed this change -- was it done using some sort of
> > sed script or by hand ?
> 
> Yes this is performed using sed

The script you used should be explained somewhere.

> and as this a common change I have
> combined all spi drivers as I belongs to - did you see any wrong on
> this?

It's hard to review such a big blob, furthermore if you need to adjust some
driver, you'd have to repost this whole thing instead of a single patch.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 01/12] spl: nand: remove code duplication

[Scott Wood]

On Thu, 2015-10-22 at 15:01 +0300, Nikita Kiryanov wrote:
> Remove code duplication in spl_nand_load_image().
> 
> No functional changes.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Scott Wood 
> Cc: Igor Grinberg 
> ---
>  common/spl/spl_nand.c | 31 ---
>  1 file changed, 16 insertions(+), 15 deletions(-)

Acked-by: Scott Wood 

-Scott

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[U-Boot] [PATCH v3] net: convert altera_tse to driver model and phylib

[Thomas Chou]

Convert altera_tse to driver model and phylib.

Signed-off-by: Thomas Chou 
Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
---
v2
  remove volatile and use I/O accessors as suggested by Marek.
  use virt_to_phys() to get dma address.
  add free_pkt() ops.
  add timeout to loop.
  allocate cache aligned rx buffer.
  refactor sgdma calls.
v3
  move the code into net ops for those with a single caller.

 configs/nios2-generic_defconfig |2 +
 doc/device-tree-bindings/net/altera_tse.txt |  112 +++
 drivers/net/Kconfig |9 +
 drivers/net/altera_tse.c| 1143 +--
 drivers/net/altera_tse.h|  277 +--
 include/configs/nios2-generic.h |8 +
 6 files changed, 504 insertions(+), 1047 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/altera_tse.txt

diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig
index ea07b56..fbc27ea 100644
--- a/configs/nios2-generic_defconfig
+++ b/configs/nios2-generic_defconfig
@@ -18,6 +18,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ALTERA_PIO=y
 CONFIG_MISC=y
 CONFIG_ALTERA_SYSID=y
+CONFIG_DM_ETH=y
+CONFIG_ALTERA_TSE=y
 CONFIG_ALTERA_JTAG_UART=y
 CONFIG_ALTERA_JTAG_UART_BYPASS=y
 CONFIG_TIMER=y
diff --git a/doc/device-tree-bindings/net/altera_tse.txt 
b/doc/device-tree-bindings/net/altera_tse.txt
new file mode 100644
index 000..cb190df
--- /dev/null
+++ b/doc/device-tree-bindings/net/altera_tse.txt
@@ -0,0 +1,112 @@
+* Altera Triple-Speed Ethernet MAC driver (TSE)
+
+Required properties:
+- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
+   be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  "control_port": MAC configuration space region
+  "tx_csr":   xDMA Tx dispatcher control and status space region
+  "tx_desc":  MSGDMA Tx dispatcher descriptor space region
+  "rx_csr" :  xDMA Rx dispatcher control and status space region
+  "rx_desc":  MSGDMA Rx dispatcher descriptor space region
+  "rx_resp":  MSGDMA Rx dispatcher response space region
+  "s1":  SGDMA descriptor memory
+- interrupts: Should contain the TSE interrupts and it's mode.
+- interrupt-names: Should contain the interrupt names
+  "rx_irq":   xDMA Rx dispatcher interrupt
+  "tx_irq":   xDMA Tx dispatcher interrupt
+- rx-fifo-depth: MAC receive FIFO buffer depth in bytes
+- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
+- phy-mode: See ethernet.txt in the same directory.
+- phy-handle: See ethernet.txt in the same directory.
+- phy-addr: See ethernet.txt in the same directory. A configuration should
+   include phy-handle or phy-addr.
+- altr,has-supplementary-unicast:
+   If present, TSE supports additional unicast addresses.
+   Otherwise additional unicast addresses are not supported.
+- altr,has-hash-multicast-filter:
+   If present, TSE supports a hash based multicast filter.
+   Otherwise, hash-based multicast filtering is not supported.
+
+- mdio device tree subnode: When the TSE has a phy connected to its local
+   mdio, there must be device tree subnode with the following
+   required properties:
+
+   - compatible: Must be "altr,tse-mdio".
+   - #address-cells: Must be <1>.
+   - #size-cells: Must be <0>.
+
+   For each phy on the mdio bus, there must be a node with the following
+   fields:
+
+   - reg: phy id used to communicate to phy.
+   - device_type: Must be "ethernet-phy".
+
+Optional properties:
+- local-mac-address: See ethernet.txt in the same directory.
+- max-frame-size: See ethernet.txt in the same directory.
+
+Example:
+
+   tse_sub_0_eth_tse_0: ethernet@0x1, {
+   compatible = "altr,tse-msgdma-1.0";
+   reg =   <0x0001 0x 0x0400>,
+   <0x0001 0x0460 0x0020>,
+   <0x0001 0x0480 0x0020>,
+   <0x0001 0x04A0 0x0008>,
+   <0x0001 0x0400 0x0020>,
+   <0x0001 0x0420 0x0020>;
+   reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", 
"tx_csr", "tx_desc";
+   interrupt-parent = <_0_arm_gic_0>;
+   interrupts = <0 41 4>, <0 40 4>;
+   interrupt-names = "rx_irq", "tx_irq";
+   rx-fifo-depth = <2048>;
+   tx-fifo-depth = <2048>;
+   address-bits = <48>;
+   max-frame-size = <1500>;
+   local-mac-address = [ 00 00 00 00 00 00 ];
+   phy-mode = "gmii";
+  

[U-Boot] [PATCH v2] am43xx_evm: Add DFU support for qspi flash

[Vignesh R]

This adds support to update firmware on qspi flash present on
am437x-sk-evm and am43xx-epos-evm via DFU.

On device:
=> setenv dfu_alt_info ${dfu_alt_info_qspi}
=> dfu 0 sf 0:0

On host:
$ sudo dfu-util -l
$ sudo dfu-util -D u-boot.bin -a u-boot.bin

Signed-off-by: Vignesh R 
---

v2:
 * change u-boot.img to u-boot.bin.

Tested on am437x-sk-evm by flashing u-boot.bin and zImage and verified
by reading back u-boot.bin and zImage in kernel.
QSPI XIP boot itself is broken on u-boot mainline (even w/o this patch),
hence cannot verify XIP boot using DFU.

 include/configs/am43xx_evm.h | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 67d5c48ddeb6..e3b7817cc3d9 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -165,11 +165,22 @@
"fdt ram 0x80f8 0x8;" \
"ramdisk ram 0x8100 0x400\0"
 
+#define CONFIG_DFU_SF
+#define DFU_ALT_INFO_QSPI \
+   "dfu_alt_info_qspi=" \
+   "u-boot.bin raw 0x0 0x08;" \
+   "u-boot.backup raw 0x08 0x08;" \
+   "u-boot-spl-os raw 0x10 0x01;" \
+   "u-boot-env raw 0x11 0x01;" \
+   "u-boot-env.backup raw 0x12 0x01;" \
+   "kernel raw 0x13 0x80\0"
+
 #define DFUARGS \
"dfu_bufsiz=0x1\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
-   DFU_ALT_INFO_RAM
+   DFU_ALT_INFO_RAM \
+   DFU_ALT_INFO_QSPI
 #else
 #define DFUARGS
 #endif
-- 
2.6.2

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Re: [U-Boot] [PATCH 1/2] arm: stm32f4: fix a bug when only first sector gets erased

[Albert ARIBAUD]

Hello Vadzim,

On Tue, 20 Oct 2015 02:41:44 +0300, Vadzim Dambrouski
 wrote:
> flash_lock call is inside a for cycle, so after the first iteration flash
> is locked and no more sectors can be erased.

Nitpick: the commit summary explains the problem well, but not the
(admittedly) trivial solution; just add it:

flash_lock call is inside a for cycle, so after the first
iteration flash is locked and no more sectors can be erased.
Move flash_lock out of the loop.

> Signed-off-by: Vadzim Dambrouski 

Amicalement,
-- 
Albert.
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[U-Boot] [PATCH v2] nios2: fix virt_to_phys for nios2 with MMU

[Thomas Chou]

As the virtual address and physical address mapping of nios2 with
MMU are different. Add a check of MMU, and fix the mapping.

Signed-off-by: Thomas Chou 
Acked-by: Marek Vasut 
Reviewed-by: Ley Foon Tan 
---
v2
  remove the parenthesis around vaddr as suggested by Marek.

 arch/nios2/include/asm/io.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index d0adf08..e7da35b 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -39,7 +39,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long 
flags)
 
 static inline phys_addr_t virt_to_phys(void * vaddr)
 {
-   return (phys_addr_t)(vaddr);
+   DECLARE_GLOBAL_DATA_PTR;
+   if (gd->arch.has_mmu)
+   return (phys_addr_t)vaddr & 0x1fff;
+   else
+   return (phys_addr_t)vaddr & 0x7fff;
 }
 
 static inline void *ioremap(unsigned long physaddr, unsigned long size)
-- 
2.1.4

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Re: [U-Boot] Fastboot behaviour with sparse images

[Maxime Ripard]

Hi Tom,

On Wed, Oct 21, 2015 at 10:09:28AM -0400, Tom Rini wrote:
> On Mon, Oct 12, 2015 at 03:43:01PM +0200, Maxime Ripard wrote:
> > Hi,
> > 
> > I'm currently writing the support in U-Boot for NAND-backed devices
> > using fastboot [1], and that work derived a bit to supporting the
> > sparse images.
> > 
> > For "regular" images that are being stored, we expect a pair of
> > download and flash commands. Simple.
> > 
> > Things start to get a bit more complex with sparse images that have
> > been split because of a max-download-size lower than the actual image
> > size.
> > 
> > Here, from what I could gather from various random blog posts, the
> > fastboot client implementation and dumping a few USB sessions, the
> > client simply creates several download / flash pairs, always on the
> > same partition, without any way to distinct that from several
> > subsequent writes issued by the user.
> > 
> > So, I'm guessing that the expectation is that the bootloader
> > implementation should store the last offset it wrote to, and simple
> > resume from there if the partition names in the flash commands are the
> > same, which would prevent two subsequent write on the same partition
> > by any client. Am I right?
> > 
> > A related question is when should we erase the NAND partition? Only
> > when doing fastboot erase, or also when doing fastboot write (which,
> > combined with the issue raised above, would also mean that we don't
> > want to do an erase on the whole partition everytime there's a flash
> > command on it).
> 
> I think for this last question, some experimentation with the existing
> tools might be required.  As there's no required explicit erase for MMC,
> I think it might make sense to say you erase nand up front and then
> write as anything else starts getting really tricky and we're just
> second-guessing the user.

Actually, the only FS the fastboot tool seems to be doing it for the
moment are ext4 and F2FS. It can probably be extended to UBI and raw
partitions, but that won't fix the tools that are bundled by the
distros at the moment.

So I guess we can always erase it now using the session counter: if we
are writing the first chunk, erase the whole partition, if we're not,
then simply flash it at the previous offset.

How does it sound?
Maxime

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Embedded Linux, Kernel and Android engineering
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Re: [U-Boot] [PATCH 1/4] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY

[Albert ARIBAUD]

Hello Stephen,

On Wed, 21 Oct 2015 10:35:59 -0600, Stephen Warren
 wrote:
> On 10/05/2015 12:08 PM, Stephen Warren wrote:
> > From: Stephen Warren 
> >
> > The implementation of noncached_init() uses define MMU_SECTION_SIZE.
> > Define this on ARM64.
> >
> > Move the prototype of noncached_{init,alloc}() to a location that
> > doesn't depend on !defined(CONFIG_ARM64).
> >
> > Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
> > relies on something having set up translation tables with 2MB block size.
> > The core ARMv8 MMU setup code does not do this by default, but currently
> > relies on SoC specific MMU setup code. Be aware of this before enabling
> > this feature on your platform!
> 
> Albert, it looks like I forgot to add you to the CC on this email. 
> Sorry! Could you please take a look at this series and tell me what you 
> think? If you need a resend just let me know.
> 
> Also note that this series is a dependency for PCIe support on 64-bit 
> Tegra systems; I guess either Tom Warren would be looking for an ack so 
> he can apply the series to the Tegra tree, or perhaps if you just apply 
> the whole series, he can base his branch on the branch where you apply this.

I'll have a look at it in the coming days.

Amicalement,
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Re: [U-Boot] [PATCH] arm: sunxi: Add icnova-a20-swac defconfig and dts file

[Maxime Ripard]

On Wed, Oct 21, 2015 at 04:44:00PM +0200, Stefan Roese wrote:
> >>What is the preferred method to support SoM's
> >>with multiple baseboards? Something like:
> >>
> >>sun7i-a20-icnova.dtsi
> >>sun7i-a20-icnova-adb4006.dts
> >>sun7i-a20-icnova-swac.dts
> >>
> >>?
> >
> >Yep, that would make much more sense. I have an ADB4006 here, so I can
> >do that one if you want, but we should totally split the common part
> >in a DTSI.
> 
> Okay. I'll try to find some time tomorrow to split this and send
> you a first version for Linux this time. Since I don't have the
> ADB4006 baseboard it would be great if you could step in here.

That can come as a second step, but yep, let's do it this way.

Thanks!
Maxime

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Re: [U-Boot] Reading data from SPI flash before relocation - what is the best way to do this?

[Wolfgang Denk]

Dear Marcin,

In message  
you wrote:
> 
> I want to chose the best aproach to achive something like this:
> There is a u-boot without SPL and it is copied by bootrom to SDRAM.

OK, the question why you don't use SPL has already been asked.

> In first phase (while running  *_f functions) I need to read some 
> configuration data from SPI NOR, and it must be done before DDR config.

Why do you need to read it separately?  Can you not "attach" it to the
U-Boot image, so the boot ROM will read that combined image (U-Boot
plus your config data) ?


Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH v3 3/4] spi: Use BIT macro in spi/drivers/*

[Jagan Teki]

On 22 October 2015 at 23:45, Marek Vasut  wrote:
> On Thursday, October 22, 2015 at 07:45:49 PM, Jagan Teki wrote:
>> BIT macro used on drivers/spi/*
>>
>> Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31
>>
>> Cc: Tom Rini 
>> Cc: Simon Glass 
>> Cc: Masahiro Yamada 
>> Cc: Peng Fan 
>> Cc: Stefan Roese 
>> Cc: Marek Vasut 
>> Cc: Stephen Warren 
>> Cc: Tom Warren 
>> Signed-off-by: Jagan Teki 
>
> So, you're sending this horrid blob of changes instead of splitting them
> into more managable parts, sigh. Moreover, I have a feeling this is a
> change for the sake of changing something, not great. Also, you did not
> describe how you performed this change -- was it done using some sort of
> sed script or by hand ?

Yes this is performed using sed and as this a common change I have
combined all spi drivers as I belongs to - did you see any wrong on
this?

-- 
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Re: [U-Boot] [PATCH v3 3/4] spi: Use BIT macro in spi/drivers/*

[Jagan Teki]

On 23 October 2015 at 00:35, Marek Vasut  wrote:
> On Thursday, October 22, 2015 at 08:21:29 PM, Jagan Teki wrote:
>> On 22 October 2015 at 23:45, Marek Vasut  wrote:
>> > On Thursday, October 22, 2015 at 07:45:49 PM, Jagan Teki wrote:
>> >> BIT macro used on drivers/spi/*
>> >>
>> >> Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31
>> >>
>> >> Cc: Tom Rini 
>> >> Cc: Simon Glass 
>> >> Cc: Masahiro Yamada 
>> >> Cc: Peng Fan 
>> >> Cc: Stefan Roese 
>> >> Cc: Marek Vasut 
>> >> Cc: Stephen Warren 
>> >> Cc: Tom Warren 
>> >> Signed-off-by: Jagan Teki 
>> >
>> > So, you're sending this horrid blob of changes instead of splitting them
>> > into more managable parts, sigh. Moreover, I have a feeling this is a
>> > change for the sake of changing something, not great. Also, you did not
>> > describe how you performed this change -- was it done using some sort of
>> > sed script or by hand ?
>>
>> Yes this is performed using sed
>
> The script you used should be explained somewhere.

OK, add in next version patches.

>
>> and as this a common change I have
>> combined all spi drivers as I belongs to - did you see any wrong on
>> this?
>
> It's hard to review such a big blob, furthermore if you need to adjust some
> driver, you'd have to repost this whole thing instead of a single patch.

OK, then I will resend it separate patches, for individual drivers.

-- 
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[U-Boot] [PATCH v3 3/4] spi: Use BIT macro in spi/drivers/*

[Jagan Teki]

BIT macro used on drivers/spi/*

Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31

Cc: Tom Rini 
Cc: Simon Glass 
Cc: Masahiro Yamada 
Cc: Peng Fan 
Cc: Stefan Roese 
Cc: Marek Vasut 
Cc: Stephen Warren 
Cc: Tom Warren 
Signed-off-by: Jagan Teki 
---
Changes for v3, v2:
- none

 drivers/spi/altera_spi.c   | 26 -
 drivers/spi/atmel_spi.h| 52 +-
 drivers/spi/bfin_spi6xx.c  |  8 +++---
 drivers/spi/cadence_qspi_apb.c | 28 +-
 drivers/spi/designware_spi.c   | 14 -
 drivers/spi/exynos_spi.c   |  4 +--
 drivers/spi/fsl_dspi.c |  2 +-
 drivers/spi/fsl_espi.c | 20 ++---
 drivers/spi/fsl_qspi.c |  4 +--
 drivers/spi/ich.c  |  4 +--
 drivers/spi/mpc8xxx_spi.c  |  2 +-
 drivers/spi/omap3_spi.h| 48 +++
 drivers/spi/sh_qspi.c  | 16 +--
 drivers/spi/tegra114_spi.c | 64 +-
 drivers/spi/tegra20_sflash.c   | 50 -
 drivers/spi/tegra20_slink.c| 58 +++---
 drivers/spi/ti_qspi.c  | 10 +++
 drivers/spi/xilinx_spi.c   | 32 ++---
 18 files changed, 221 insertions(+), 221 deletions(-)

diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index a4d03d9..2302117 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -29,19 +29,19 @@ struct altera_spi_regs {
u32 slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK  (1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK  (1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK  (1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK   (1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK   (1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK  (1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK  BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK  BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK  BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
+#define ALTERA_SPI_STATUS_E_MSKBIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSKBIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSKBIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK   BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK   BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK  BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
 
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 1538a23..5b892d2 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -15,19 +15,19 @@
 #define ATMEL_SPI_VERSION  0x00fc
 
 /* Bits in CR */
-#define ATMEL_SPI_CR_SPIEN (1 << 0)
-#define ATMEL_SPI_CR_SPIDIS(1 << 1)
-#define ATMEL_SPI_CR_SWRST (1 << 7)
-#define ATMEL_SPI_CR_LASTXFER  (1 << 24)
+#define ATMEL_SPI_CR_SPIEN BIT(0)
+#define ATMEL_SPI_CR_SPIDISBIT(1)
+#define ATMEL_SPI_CR_SWRST BIT(7)
+#define ATMEL_SPI_CR_LASTXFER  BIT(24)
 
 /* Bits in MR */
-#define ATMEL_SPI_MR_MSTR  (1 << 0)
-#define ATMEL_SPI_MR_PS(1 << 1)
-#define ATMEL_SPI_MR_PCSDEC(1 << 2)
-#define ATMEL_SPI_MR_FDIV  (1 << 3)
-#define ATMEL_SPI_MR_MODFDIS   (1 << 4)
-#define ATMEL_SPI_MR_WDRBT (1 << 5)
-#define ATMEL_SPI_MR_LLB   (1 << 7)
+#define ATMEL_SPI_MR_MSTR  BIT(0)
+#define ATMEL_SPI_MR_PSBIT(1)
+#define ATMEL_SPI_MR_PCSDECBIT(2)
+#define ATMEL_SPI_MR_FDIV  BIT(3)
+#define ATMEL_SPI_MR_MODFDIS   BIT(4)
+#define ATMEL_SPI_MR_WDRBT BIT(5)
+#define ATMEL_SPI_MR_LLB   BIT(7)
 #define ATMEL_SPI_MR_PCS(x)(((x) & 15) << 16)
 #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
 
@@ -38,25 +38,25 @@
 /* Bits in TDR */
 #define ATMEL_SPI_TDR_TD(x)(x)
 #define ATMEL_SPI_TDR_PCS(x)   ((x) << 16)
-#define ATMEL_SPI_TDR_LASTXFER (1 << 24)
+#define ATMEL_SPI_TDR_LASTXFER BIT(24)
 
 /* Bits in SR/IER/IDR/IMR */
-#define ATMEL_SPI_SR_RDRF  (1 << 0)
-#define ATMEL_SPI_SR_TDRE  (1 << 1)
-#define ATMEL_SPI_SR_MODF  (1 << 2)
-#define ATMEL_SPI_SR_OVRES (1 << 3)
-#define ATMEL_SPI_SR_ENDRX (1 << 4)
-#define ATMEL_SPI_SR_ENDTX (1 << 5)
-#define 

[U-Boot] [PATCH v3 2/4] spi: zynq_[q]spi: Use GENMASK macro

[Jagan Teki]

GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
Changes for v3, v2:
- none

 drivers/spi/zynq_qspi.c | 8 
 drivers/spi/zynq_spi.c  | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index dd530a1..64b4eea 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_MSA_MASK  BIT(15) /* Manual start enb */
 #define ZYNQ_QSPI_CR_MCS_MASK  BIT(14) /* Manual chip select */
 #define ZYNQ_QSPI_CR_PCS_MASK  BIT(10) /* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK   (0x3 << 6)  /* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK   (0xF << 10) /* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3)  /* Baud rate div */
+#define ZYNQ_QSPI_CR_FW_MASK   GENMASK(7, 6)   /* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK   GENMASK(13, 10) /* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2)  /* Clock phase */
 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1)  /* Clock polarity */
 #define ZYNQ_QSPI_CR_MSTREN_MASK   BIT(0)  /* Mode select */
 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASKBIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_QSPI_IXR_TXOW_MASKBIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F/* All IXR bits */
+#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK  BIT(0)  /* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 92e5712..9ede099 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI___MASK */
 #define ZYNQ_SPI_CR_MSA_MASK   BIT(15) /* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK   BIT(14) /* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK(0xF << 10) /* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK  (0x7 << 3)  /* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASKGENMASK(13, 10) /* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK  GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK  BIT(2)  /* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK  BIT(1)  /* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASKBIT(0)  /* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK  0x7F/* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK  GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK   BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX   8   /* Baud rate divisor max val */
-- 
1.9.1

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Re: [U-Boot] [PATCH v3 3/4] spi: Use BIT macro in spi/drivers/*

[Marek Vasut]

On Thursday, October 22, 2015 at 07:45:49 PM, Jagan Teki wrote:
> BIT macro used on drivers/spi/*
> 
> Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2  31
> 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Masahiro Yamada 
> Cc: Peng Fan 
> Cc: Stefan Roese 
> Cc: Marek Vasut 
> Cc: Stephen Warren 
> Cc: Tom Warren 
> Signed-off-by: Jagan Teki 

So, you're sending this horrid blob of changes instead of splitting them
into more managable parts, sigh. Moreover, I have a feeling this is a
change for the sake of changing something, not great. Also, you did not
describe how you performed this change -- was it done using some sort of
sed script or by hand ?

Best regards,
Marek Vasut
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Re: [U-Boot] Fastboot behaviour with sparse images

[Maxime Ripard]

On Thu, Oct 22, 2015 at 07:22:54AM -0400, Tom Rini wrote:
> On Thu, Oct 22, 2015 at 09:57:05AM +0200, Maxime Ripard wrote:
> > Hi Tom,
> > 
> > On Wed, Oct 21, 2015 at 10:09:28AM -0400, Tom Rini wrote:
> > > On Mon, Oct 12, 2015 at 03:43:01PM +0200, Maxime Ripard wrote:
> > > > Hi,
> > > > 
> > > > I'm currently writing the support in U-Boot for NAND-backed devices
> > > > using fastboot [1], and that work derived a bit to supporting the
> > > > sparse images.
> > > > 
> > > > For "regular" images that are being stored, we expect a pair of
> > > > download and flash commands. Simple.
> > > > 
> > > > Things start to get a bit more complex with sparse images that have
> > > > been split because of a max-download-size lower than the actual image
> > > > size.
> > > > 
> > > > Here, from what I could gather from various random blog posts, the
> > > > fastboot client implementation and dumping a few USB sessions, the
> > > > client simply creates several download / flash pairs, always on the
> > > > same partition, without any way to distinct that from several
> > > > subsequent writes issued by the user.
> > > > 
> > > > So, I'm guessing that the expectation is that the bootloader
> > > > implementation should store the last offset it wrote to, and simple
> > > > resume from there if the partition names in the flash commands are the
> > > > same, which would prevent two subsequent write on the same partition
> > > > by any client. Am I right?
> > > > 
> > > > A related question is when should we erase the NAND partition? Only
> > > > when doing fastboot erase, or also when doing fastboot write (which,
> > > > combined with the issue raised above, would also mean that we don't
> > > > want to do an erase on the whole partition everytime there's a flash
> > > > command on it).
> > > 
> > > I think for this last question, some experimentation with the existing
> > > tools might be required.  As there's no required explicit erase for MMC,
> > > I think it might make sense to say you erase nand up front and then
> > > write as anything else starts getting really tricky and we're just
> > > second-guessing the user.
> > 
> > Actually, the only FS the fastboot tool seems to be doing it for the
> > moment are ext4 and F2FS. It can probably be extended to UBI and raw
> > partitions, but that won't fix the tools that are bundled by the
> > distros at the moment.
> > 
> > So I guess we can always erase it now using the session counter: if we
> > are writing the first chunk, erase the whole partition, if we're not,
> > then simply flash it at the previous offset.
> > 
> > How does it sound?
> 
> Sounds workable but testing with the existing tools will be the key and
> the hard part here :(

Well, if we always erase when we write, the worst case scenario would
be one erase too many. It doesn't sound that bad, or hard.

Maxime

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Re: [U-Boot] u-boot device model SPI + SPI Flash

[Hoefle Marco]

> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Mittwoch, 21. Oktober 2015 18:45
> To: Hoefle Marco 
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
> 
> On 21 October 2015 at 22:10, Hoefle Marco 
> wrote:
> > Hello Jagan,
> > Thank you for your reply.
> > Please find my comments bellow. I missed to mention that I am using
> > mainline 2015.07
> >
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jt...@openedev.com]
> >> Sent: Mittwoch, 21. Oktober 2015 18:28
> >> To: Hoefle Marco 
> >> Cc: u-boot@lists.denx.de
> >> Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
> >>
> >> On 21 October 2015 at 16:25, Hoefle Marco
> >> 
> >> wrote:
> >> >
> >> >  Hello,
> >> > I saw that here is also a mailing list dedicated to device model
> >> > issues but it
> >> looks obsolete (last post February 2014) so I am using this forum.
> >>
> >> Please note its driver model - not a device model.
> > Ok
> >>
> >> >
> >> > I have a problem nearly identically to
> >> > http://lists.denx.de/pipermail/u-boot/2015-April/210754.html
> >> >
> >> >
> >> > The SPI initialization does not work:
> >> >
> >> > Invalid bus 0 (err=-19)
> >> > *** Warning - spi_flash_probe() failed, using default environment
> >>
> >> Which board it is? dts file name?
> > It is a custom dts file. It is for a Microblaze CPU in an Artix FPGA.
> > The dts reflects that one below
> >>
> >> >
> >> >
> >> > This is the device tree compiled into u-boot:
> >> >
> >> > U-Boot> fdt addr 0x8FEB8A7C
> >> > U-Boot> fdt print
> >> > / {
> >> > #address-cells = <0x0001>;
> >> > #size-cells = <0x0001>;
> >> > aliases {
> >> > serial0 = "serial@4060";
> >> > spi0 = "/axi_quad_spi@44a0";
> >> > };
> >> > memory {
> >> > device_type = "memory";
> >> > reg = <0x8000 0x1000>;
> >> > };
> >> > axi_quad_spi@44a0 {
> >> > compatible = "xlnx,xps-spi-2.00.a";
> >>
> >> Do you need zynq spi or qspi driver there is no compatible string
> >> with "xlnx,xps-spi-2.00.a" do know which source you're using?
> > This driver is used:
> > u-boot/drivers/spi/xilinx_spi.c
> 
> In that case, use the compatible in your dts as below
> 
> static const struct udevice_id xilinx_spi_ids[] = {
> { .compatible = "xlnx,xilinx-spi" },
> { }
> };
That was a copy paste failure, sorry for that. The reason was that in  the 
meanwhile I tried the original Xilinx driver from their github tree. They have 
the tag: compatible = "xlnx,xps-spi-2.00.a"

However, I changed back to have mainline code only an put a few printfs to it:
U-Boot 2015.07--33711bdd4a4dce942fb5ae85a68899a8357bdd94---dirty (Oct 22 2015 - 
07:57:35 +0200)

DRAM:  256 MiB
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1
   - not found
env_relocate: 267
spi_flash_probe: 410
busnum: 0, cs: 0, max_hz: 5000
spi_setup_slave: 336
spi_get_bus_and_cs: 248
uclass_find_device_by_seq: 0 0
   - -1 -1
   - not found
uclass_find_device_by_seq: 1 0
   - -1 -1
   - not found
Invalid bus 0 (err=-19)
*** Warning - spi_flash_probe() failed, using default environment


U-Boot> fdt addr 0x8FEB89FC
U-Boot> fdt print
/ {
#address-cells = <0x0001>;
#size-cells = <0x0001>;
aliases {
serial0 = "/serial@4060";
spi0 = "/axi_quad_spi@44a0";
};
memory {
device_type = "memory";
reg = <0x8000 0x1000>;
};
serial@4060 {
clock-frequency = <0x05f5e100>;
compatible = "xlnx,xps-uartlite-1.00.a";
current-speed = <0x0001c200>;
};
axi_quad_spi@44a0 {
compatible = "xlnx,xilinx-spi";
reg = <0x44a0 0x0001>;
spi-max-frequency = <0x423a35c7>;
#address-cells = <0x0001>;
#size-cells = <0x>;
status = "okay";
is-dual = <0x>;
num-cs = <0x0001>;
flash@0 {
compatible = "n25q128a11";
reg = <0x>;
spi-tx-bus-width = <0x0001>;
spi-rx-bus-width = <0x0004>;
spi-max-frequency = <0x0d3ed78e>;
#address-cells = <0x0001>;
#size-cells = <0x0001>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x 0x0010>;
};
partition@qspi-linux {

[U-Boot] [Patch V7 01/18] armv7/ls1021a: move ns_access to common file

[Gong Qianyu]

From: Mingkai Hu 

Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Gong Qianyu 
---
V7:
 - Fix the macro for ls1021atwr.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - No change.
V2:
 - Create include/fsl_csu.h instead of board/freescale/common/ns_access.h

 arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 --
 board/freescale/common/Makefile   |   2 +-
 board/freescale/common/ns_access.c|   8 +-
 board/freescale/ls1021aqds/ls1021aqds.c   | 101 ++---
 board/freescale/ls1021atwr/ls1021atwr.c   | 102 ++---
 include/configs/ls1021aqds.h  |   2 +-
 include/configs/ls1021atwr.h  |   2 +-
 include/fsl_csu.h |  34 +
 8 files changed, 141 insertions(+), 213 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h 
b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f699..a921fb6 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
 
-enum csu_cslx_access {
-   CSU_NS_SUP_R = 0x08,
-   CSU_NS_SUP_W = 0x80,
-   CSU_NS_SUP_RW = 0x88,
-   CSU_NS_USER_R = 0x04,
-   CSU_NS_USER_W = 0x40,
-   CSU_NS_USER_RW = 0x44,
-   CSU_S_SUP_R = 0x02,
-   CSU_S_SUP_W = 0x20,
-   CSU_S_SUP_RW = 0x22,
-   CSU_S_USER_R = 0x01,
-   CSU_S_USER_W = 0x10,
-   CSU_S_USER_RW = 0x11,
-   CSU_ALL_RW = 0xff,
-};
-
 enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
 };
 
-struct csu_ns_dev {
-   unsigned long ind;
-   uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+   { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+   { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+   { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+   { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+   { CSU_CSLX_OCRAM, CSU_ALL_RW },
+   { CSU_CSLX_GIC, CSU_ALL_RW },
+   { CSU_CSLX_PCIE1, CSU_ALL_RW },
+   { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+   { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+   { CSU_CSLX_PCIE2, CSU_ALL_RW },
+   { CSU_CSLX_SATA, CSU_ALL_RW },
+   { CSU_CSLX_USB3, CSU_ALL_RW },
+   { CSU_CSLX_SERDES, CSU_ALL_RW },
+   { CSU_CSLX_QDMA, CSU_ALL_RW },
+   { CSU_CSLX_LPUART2, CSU_ALL_RW },
+   { CSU_CSLX_LPUART1, CSU_ALL_RW },
+   { CSU_CSLX_LPUART4, CSU_ALL_RW },
+   { CSU_CSLX_LPUART3, CSU_ALL_RW },
+   { CSU_CSLX_LPUART6, CSU_ALL_RW },
+   { CSU_CSLX_LPUART5, CSU_ALL_RW },
+   { CSU_CSLX_DSPI2, CSU_ALL_RW },
+   { CSU_CSLX_DSPI1, CSU_ALL_RW },
+   { CSU_CSLX_QSPI, CSU_ALL_RW },
+   { CSU_CSLX_ESDHC, CSU_ALL_RW },
+   { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+   { CSU_CSLX_IFC, CSU_ALL_RW },
+   { CSU_CSLX_I2C1, CSU_ALL_RW },
+   { CSU_CSLX_USB2, CSU_ALL_RW },
+   { CSU_CSLX_I2C3, CSU_ALL_RW },
+   { CSU_CSLX_I2C2, CSU_ALL_RW },
+   { CSU_CSLX_DUART2, CSU_ALL_RW },
+   { CSU_CSLX_DUART1, CSU_ALL_RW },
+   { CSU_CSLX_WDT2, CSU_ALL_RW },
+   { CSU_CSLX_WDT1, CSU_ALL_RW },
+   { CSU_CSLX_EDMA, CSU_ALL_RW },
+   { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+   { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+   { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+   { CSU_CSLX_DDR, CSU_ALL_RW },
+   { CSU_CSLX_QUICC, CSU_ALL_RW },
+   { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+   { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+   { CSU_CSLX_SFP, CSU_ALL_RW },
+   { CSU_CSLX_TMU, CSU_ALL_RW },
+   { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+   { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+   { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+   { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+   { CSU_CSLX_GPIO2, CSU_ALL_RW },
+   { CSU_CSLX_GPIO1, CSU_ALL_RW },
+   { CSU_CSLX_GPIO4, CSU_ALL_RW },
+   { CSU_CSLX_GPIO3, CSU_ALL_RW },
+   { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+   { CSU_CSLX_CSU, CSU_ALL_RW },
+   { CSU_CSLX_ASRC, CSU_ALL_RW },
+   { CSU_CSLX_SPDIF, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+   { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+   { CSU_CSLX_SAI2, CSU_ALL_RW },
+   { CSU_CSLX_SAI1, CSU_ALL_RW },
+   { CSU_CSLX_SAI4, CSU_ALL_RW },
+   { CSU_CSLX_SAI3, CSU_ALL_RW },
+   { CSU_CSLX_FTM2, CSU_ALL_RW },
+   { CSU_CSLX_FTM1, CSU_ALL_RW },
+   { CSU_CSLX_FTM4, CSU_ALL_RW },
+   { CSU_CSLX_FTM3, CSU_ALL_RW },
+   { CSU_CSLX_FTM6, CSU_ALL_RW },

Re: [U-Boot] Bisected broken Ethernet support on ODROID-X (Exynos4412 board)

[Siarhei Siamashka]

On Wed, 21 Oct 2015 10:06:09 +0200
Lukasz Majewski  wrote:

> Hi Siarhei,
> 
> > On Tue, 20 Oct 2015 09:15:07 -0600
> > Simon Glass  wrote:
> > 
> > > Hi,
> > > 
> > > On 20 October 2015 at 08:13, Siarhei Siamashka
> > >  wrote:
> > > > Hello,
> > > >
> > > > Ethernet support does not work anymore when using the current
> > > > U-Boot (version v2014.10) on the ODROID-X board. Bisecting shows
> > > > that this happened starting from commit
> > > > 874dde80169e0a0c00020e2e0bbcd380c61097e3 ("dm: usb: exynos: Use
> > > > driver model for USB"):
> > > > http://git.denx.de/?p=u-boot.git;a=commitdiff;h=874dde80169e0a0c00020e2e0bbcd380c61097e3
> > > >
> > > > Below are the logs from the serial console.
> > > >
> > > > === works properly ==
> > > >
> > > > U-Boot 2015.04-00271-g52e6935-dirty (Oct 20 2015 - 16:38:09)
> > > >
> > > > CPU:Exynos4412@1000MHz
> > > > Model: Odroid based on Exynos4412
> > > > DRAM:  1 GiB
> > > > Board PMIC init
> > > > MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
> > > > Net:   No ethernet found.
> > > > Hit any key to stop autoboot:  0
> > > > reading boot.scr
> > > > 129 bytes read in 11 ms (10.7 KiB/s)
> > > > ## Executing script at 40408000
> > > > starting USB...
> > > > USB0:   USB EHCI 1.00
> > > > scanning bus 0 for devices... 4 USB Device(s) found
> > > >scanning usb for storage devices... 0 Storage Device(s)
> > > > found scanning usb for ethernet devices... 1 Ethernet Device(s)
> > > > found
> > > >
> > > > === fails ==
> > > >
> > > > U-Boot 2015.04-00273-g78ab40b-dirty (Oct 20 2015 - 16:41:11)
> > > >
> > > > CPU:Exynos4412@1000MHz
> > > > Model: Odroid based on Exynos4412
> > > > DRAM:  1 GiB
> > > > Board PMIC init
> > > > MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
> > > > Net:   No ethernet found.
> > > > Hit any key to stop autoboot:  0
> > > > reading boot.scr
> > > > 129 bytes read in 12 ms (9.8 KiB/s)
> > > > ## Executing script at 40408000
> > > > starting USB...
> > > > USB-1:   USB EHCI 1.00
> > > > scanning bus 0 for devices... 1 USB Device(s) found
> > > >scanning usb for ethernet devices... 0 Ethernet Device(s)
> > > > found
> > > >
> > > > ===
> > > >
> > > > As a test, reverting f56da290b8df14a058b43735494dbbb0f8521a89
> > > > ("Drop the code that doesn't use driver model for USB.") and
> > > > disabling CONFIG_DM_USB in odroid_defconfig makes it work again.
> > > 
> > > Does this problem happen on the XU3?
> > 
> 
> Yes, It does. 
> 
> I'm struggling to fix this issue for a few days now.
>
> What is interesting though, you can run ethernet by calling:
> "usb start" and afterwards "usb reset".

That's a very interesting observation indeed. 
 
> > I don't have XU3. My only board is ODROID-X (the same as ODROID-X2,
> > but with slower CPU clock speed and less RAM).
> > 
> > > Are you able to debug this?
> > 
> > I'm not sure if I can really spend much time on it. Debugging this
> > issue would require comparing the old exynos usb code and the new
> > dm code to see where exactly they differ. For example, the new
> > 'ehci_usb_probe()' function does not call 'board_usb_init()' while
> > the old 'ehci_hcd_init()' function did:
> > 
> > http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/usb/host/ehci-exynos.c;h=86cf6312febc30b7e142146c3b4763a6a871d5a6;hb=02e4d3fbc54b345883d9bead4f2a911d0f0f59b1#l329
> > And just calling 'board_usb_init()' on ODROID-X is still not enough
> 
> I will say even more - it seems like the issue is not related to any
> "basic" initialization (i.e. the lack of calling
> ehci_usb_probe|reset_usb_phy) called just before calling "usb start".
> 
> > to get this problem resolved for the CONFIG_DM_USB=y configuration,
> > so there must be something else.
> 
> +1
> 
> > 
> > I also don't quite like that the usb parts of the U-Boot dts files
> > for exynos differ from the Linux dts files.
> 
> This is a really good questions. We have discussed it recently on ELCE
> and there is no good solution for it.
> 
> We made a mistake to allow non Linux compliant bindings to slip into
> u-boot. Now we must cope with (or fix) this mess.

OK, I see. Thanks for explaining.

But if the kernel is considered to be the primary source of dts files,
then probably U-Boot needs to be eventually adjusted to match?

> > So far I'm satisfied that the old exynos usb code still works if
> > its removal is reverted.
> 
> As I've stated above - please try "usb start" and "usb reset"
> afterwards.

Thanks, doing "usb start" followed by "usb reset" makes the ethernet
work on ODROID-X with the CONFIG_DM_USB=y configuration if I also
add a missing call to the 'board_usb_init()' function. It does a bit
of necessary setup magic for odroid:

http://git.denx.de/?p=u-boot.git;a=blob;f=board/samsung/odroid/odroid.c;hb=v2015.10#l467

And if there is no call to 'board_usb_init()', then the ethernet
does not work on ODROID-X after "usb reset".

> > And debugging U-Boot was not my primary
> > 

Re: [U-Boot] TI8148 EVM

[Lad, Prabhakar]

Hi Tom,

Thanks for the quick reply.

On Thu, Oct 22, 2015 at 12:22 PM, Tom Rini  wrote:
> On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:
>
>> Copy the MLO and u-boot.bin to SD card boot partition which is
>> bootable, I see no prints coming from the 1st stage bootlaoder, cant
>> debug it as I don’t have access to JTAG.
>>
>> Any pointers is this code tested ?
>
> First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
> you have on the board?  We only have support for PG1.0 today and not
> PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.  The
> code should be easily ported from the old PSP tree to support PG2.0
> however.
>
I tried this on PG2.0, PG1.0 should also be handy.

Regarding u-boot.img, just copying this should work or also MLO needs
to be copied ?

Cheers,
--Prabhakar Lad
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Re: [U-Boot] TI8148 EVM

[Brian Hutchinson]

On Oct 22, 2015 7:21 AM, "Tom Rini"  wrote:
>
> On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:
>
> > Hi Tom,
> >
> > I was trying the latest master branch for ti8148 evm to boot from SD
> > card, following are the steps which I followed:
> >
> > 1:  make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean
distclean
> > 2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
ti814x_evm_config
> > 3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> >
> > Copy the MLO and u-boot.bin to SD card boot partition which is
> > bootable, I see no prints coming from the 1st stage bootlaoder, cant
> > debug it as I don’t have access to JTAG.
> >
> > Any pointers is this code tested ?
>
> First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
> you have on the board?  We only have support for PG1.0 today and not
> PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.  The
> code should be easily ported from the old PSP tree to support PG2.0
> however.
>
> --
> Tom
>
> ___
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> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

Tom,

What about DM816x support?  Mainline u-boot have anything for it?  We
finally have Linux 4.2.3 running on our board with .dts support.  Now I'm
starting the task of getting a mainline u-boot to work so we can get rid of
the legacy dtb being part of kernel.

Regards,

Brian
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Re: [U-Boot] TI8148 EVM

[Tom Rini]

On Thu, Oct 22, 2015 at 07:33:07AM -0400, Brian Hutchinson wrote:
> On Oct 22, 2015 7:21 AM, "Tom Rini"  wrote:
> >
> > On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:
> >
> > > Hi Tom,
> > >
> > > I was trying the latest master branch for ti8148 evm to boot from SD
> > > card, following are the steps which I followed:
> > >
> > > 1:  make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean
> distclean
> > > 2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> ti814x_evm_config
> > > 3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> > >
> > > Copy the MLO and u-boot.bin to SD card boot partition which is
> > > bootable, I see no prints coming from the 1st stage bootlaoder, cant
> > > debug it as I don’t have access to JTAG.
> > >
> > > Any pointers is this code tested ?
> >
> > First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
> > you have on the board?  We only have support for PG1.0 today and not
> > PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.  The
> > code should be easily ported from the old PSP tree to support PG2.0
> > however.
> 
> What about DM816x support?  Mainline u-boot have anything for it?  We
> finally have Linux 4.2.3 running on our board with .dts support.  Now I'm
> starting the task of getting a mainline u-boot to work so we can get rid of
> the legacy dtb being part of kernel.

Well, the ti816x support we have today should be a good starting point
at least for the "DM" variant of the chip.  I forget which one of the
boards I have technically but I _think_ the differences are high level
enough that for U-Boot it's OK.

-- 
Tom


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Re: [U-Boot] [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape

[Hou Zhiqiang]

> -Original Message-
> From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net]
> Sent: 2015年10月19日 19:59
> To: u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579;
> Wang Huan-B18965; Gong Qianyu-B52263
> Subject: [Patch V6 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape
> 
> From: Mingkai Hu 
> 
> There are two LS series processors are built on ARMv8 Layersacpe
> architecture currently, LS2085A and LS1043A. They are based on
> ARMv8 core although use different chassis, so create fsl-layerscape
> to refactor the common code for the LS series processors which also
> paves the way for adding LS1043A platform.
> 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 

Qianyu, you lost my Signed-off.

Thanks,
Zhqiang
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[U-Boot] Reading data from SPI flash before relocation - what is the best way to do this?

[Krzeminski, Marcin (Nokia - PL/Wroclaw)]

Hello,

I want to chose the best aproach to achive something like this:
There is a u-boot without SPL and it is copied by bootrom to SDRAM.
In first phase (while running  *_f functions) I need to read some configuration 
data from SPI NOR, and it must be done before DDR config.
I have SPI NOR  with enabled MTD support on SPI. Problem is that MTD uses bss 
wich is not avalaible yet.
My solutions:
*   Change linker script to divide bss and rel.dyn sections and clean bss 
by myself. Disadventage is that it will enlarge my binary, but it migh be 
acceptable.
*   Write code that do not use SPI/MTD frameworks to read configuration 
data (data will be on raw so MTD is not needed).
For sure - at least at the moment - I wan't to avoid using SPL and config 
compiled into binary.
Maybe there is another way that I can achive that?

Regards,
Marcin




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[U-Boot] [PATCH 10/12] spl: add support for alternative boot device

[Nikita Kiryanov]

Introduce spl_boot_list array, which defines a list of boot devices
that SPL will try before hanging. By default this list will consist
of only spl_boot_device(), but board_boot_order() can be overridden
by board code to populate the array with custom values.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl.c | 33 +
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 56fccca..7913c52 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -178,6 +178,23 @@ int spl_init(void)
return 0;
 }
 
+#ifndef BOOT_DEVICE_NONE
+#define BOOT_DEVICE_NONE 0xdeadbeef
+#endif
+
+static u32 spl_boot_list[] = {
+   BOOT_DEVICE_NONE,
+   BOOT_DEVICE_NONE,
+   BOOT_DEVICE_NONE,
+   BOOT_DEVICE_NONE,
+   BOOT_DEVICE_NONE,
+};
+
+__weak void board_boot_order(u32 *spl_boot_list)
+{
+   spl_boot_list[0] = spl_boot_device();
+}
+
 static int spl_load_image(u32 boot_device)
 {
switch (boot_device) {
@@ -247,7 +264,7 @@ static int spl_load_image(u32 boot_device)
 
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
-   u32 boot_device;
+   int i;
 
debug(">>spl:board_init_r()\n");
 
@@ -272,10 +289,18 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_board_init();
 #endif
 
-   boot_device = spl_boot_device();
-   debug("boot device - %d\n", boot_device);
-   if (spl_load_image(boot_device))
+   board_boot_order(spl_boot_list);
+   for (i = 0; i < ARRAY_SIZE(spl_boot_list) &&
+   spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
+   if (!spl_load_image(spl_boot_list[i]))
+   break;
+   }
+
+   if (i == ARRAY_SIZE(spl_boot_list) ||
+   spl_boot_list[i] == BOOT_DEVICE_NONE) {
+   puts("SPL: failed to boot from all boot devices\n");
hang();
+   }
 
switch (spl_image.os) {
case IH_OS_U_BOOT:
-- 
1.9.1

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[U-Boot] [PATCH 08/12] spl: change return values of spl_*_load_image()

[Nikita Kiryanov]

Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision whether to hang or not, thus preparing
it to support alternative boot devices.

Some boot devices (namely nand and spi) do not hang on error.
Instead, they return normally and SPL proceeds to boot the
contents of the load address. This is considered a bug and
is rectified by hanging on error for these devices as well.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Tom Rini 
Cc: Simon Glass 
Cc: Ian Campbell 
Cc: Hans De Goede 
Cc: Albert Aribaud 
Cc: Jagan Teki 
---
 arch/arm/cpu/armv7/sunxi/board.c |  4 +++-
 arch/arm/include/asm/spl.h   |  2 +-
 common/spl/spl.c | 43 +++-
 common/spl/spl_mmc.c | 27 ++---
 common/spl/spl_nand.c| 18 +++--
 common/spl/spl_net.c |  9 ++---
 common/spl/spl_nor.c |  6 --
 common/spl/spl_onenand.c |  4 +++-
 common/spl/spl_sata.c| 11 +++---
 common/spl/spl_usb.c | 17 ++--
 common/spl/spl_ymodem.c  |  5 +++--
 drivers/mtd/spi/spi_spl_load.c   | 17 +++-
 include/spl.h| 18 -
 13 files changed, 116 insertions(+), 65 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 4785ac6..9b5c46b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -95,10 +95,12 @@ static int gpio_init(void)
return 0;
 }
 
-void spl_board_load_image(void)
+int spl_board_load_image(void)
 {
debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
return_to_fel(fel_stash.sp, fel_stash.lr);
+
+   return 0;
 }
 
 void s_init(void)
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 6db405d..f8092c7 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -32,7 +32,7 @@ enum {
 #endif
 
 /* Board-specific load method */
-void spl_board_load_image(void);
+int spl_board_load_image(void);
 
 /* Linker symbols. */
 extern char __bss_start[], __bss_end[];
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4b319d6..ff1bad2 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -132,7 +132,7 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
 }
 
 #ifdef CONFIG_SPL_RAM_DEVICE
-static void spl_ram_load_image(void)
+static int spl_ram_load_image(void)
 {
const struct image_header *header;
 
@@ -145,6 +145,8 @@ static void spl_ram_load_image(void)
(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
 
spl_parse_image_header(header);
+
+   return 0;
 }
 #endif
 
@@ -208,68 +210,81 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
switch (boot_device) {
 #ifdef CONFIG_SPL_RAM_DEVICE
case BOOT_DEVICE_RAM:
-   spl_ram_load_image();
+   if (spl_ram_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
-   spl_mmc_load_image();
+   if (spl_mmc_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
-   spl_nand_load_image();
+   if (spl_nand_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
-   spl_onenand_load_image();
+   if (spl_onenand_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_NOR_SUPPORT
case BOOT_DEVICE_NOR:
-   spl_nor_load_image();
+   if (spl_nor_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_YMODEM_SUPPORT
case BOOT_DEVICE_UART:
-   spl_ymodem_load_image();
+   if (spl_ymodem_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_SPI_SUPPORT
case BOOT_DEVICE_SPI:
-   spl_spi_load_image();
+   if (spl_spi_load_image())
+   hang();
break;
 #endif
 #ifdef CONFIG_SPL_ETH_SUPPORT
case BOOT_DEVICE_CPGMAC:
 #ifdef CONFIG_SPL_ETH_DEVICE
-   spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
+   if (spl_net_load_image(CONFIG_SPL_ETH_DEVICE))
+   hang();
 #else
-   spl_net_load_image(NULL);
+   if (spl_net_load_image(NULL))
+   hang();
 

[U-Boot] [PATCH 12/12] arm: mx6: cm-fx6: define fallback boot devices for spl

[Nikita Kiryanov]

Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Stefano Babic 
Cc: Tom Rini 
---
 board/compulab/cm_fx6/spl.c | 19 ++-
 include/configs/cm_fx6.h|  1 -
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index d94ced9..d8328fd 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -337,16 +337,17 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
 }
 
-void spl_board_init(void)
+void board_boot_order(u32 *spl_boot_list)
 {
-   u32 boot_device = spl_boot_device();
-
-   if (boot_device == BOOT_DEVICE_SPI)
-   puts("Booting from SPI flash\n");
-   else if (boot_device == BOOT_DEVICE_MMC1)
-   puts("Booting from MMC\n");
-   else
-   puts("Unknown boot device\n");
+   spl_boot_list[0] = spl_boot_device();
+   switch (spl_boot_list[0]) {
+   case BOOT_DEVICE_SPI:
+   spl_boot_list[1] = BOOT_DEVICE_MMC1;
+   break;
+   case BOOT_DEVICE_MMC1:
+   spl_boot_list[1] = BOOT_DEVICE_SPI;
+   break;
+   }
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 0513204..180ea28 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -230,7 +230,6 @@
 
 /* SPL */
 #include "imx6_spl.h"
-#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x80 /* offset 64 kb */
 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
-- 
1.9.1

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[U-Boot] [PATCH 01/12] spl: nand: remove code duplication

[Nikita Kiryanov]

Remove code duplication in spl_nand_load_image().

No functional changes.

Signed-off-by: Nikita Kiryanov 
Cc: Scott Wood 
Cc: Igor Grinberg 
---
 common/spl/spl_nand.c | 31 ---
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index b8c369d..6e4e641 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -22,6 +22,19 @@ void spl_nand_load_image(void)
nand_deselect();
 }
 #else
+static int spl_nand_load_element(int offset, struct image_header *header)
+{
+   int err;
+
+   err = nand_spl_load_image(offset, sizeof(*header), (void *)header);
+   if (err)
+   return err;
+
+   spl_parse_image_header(header);
+   return nand_spl_load_image(offset, spl_image.size,
+  (void *)spl_image.load_addr);
+}
+
 void spl_nand_load_image(void)
 {
struct image_header *header;
@@ -73,25 +86,13 @@ void spl_nand_load_image(void)
}
 #endif
 #ifdef CONFIG_NAND_ENV_DST
-   nand_spl_load_image(CONFIG_ENV_OFFSET,
-   sizeof(*header), (void *)header);
-   spl_parse_image_header(header);
-   nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
-   (void *)spl_image.load_addr);
+   spl_nand_load_element(CONFIG_ENV_OFFSET, header);
 #ifdef CONFIG_ENV_OFFSET_REDUND
-   nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
-   sizeof(*header), (void *)header);
-   spl_parse_image_header(header);
-   nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
-   (void *)spl_image.load_addr);
+   spl_nand_load_element(CONFIG_ENV_OFFSET_REDUND, header);
 #endif
 #endif
/* Load u-boot */
-   nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-   sizeof(*header), (void *)header);
-   spl_parse_image_header(header);
-   nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-   spl_image.size, (void *)(unsigned long)spl_image.load_addr);
+   spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS, header);
nand_deselect();
 }
 #endif
-- 
1.9.1

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[U-Boot] [PATCH 05/12] spl: mmc: get rid of #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION check

[Nikita Kiryanov]

Implement defaults for the raw partition image loading so that the #ifdef
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION in spl_mmc_load_image() will no
longer be necessary.

This change makes it possible for mmc_load_image_raw_partition() and
mmc_load_image_raw_sector() to coexist.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index f0c4d56..fbdcf0d 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -133,6 +133,12 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, 
int partition)
return mmc_load_image_raw_sector(mmc, info.start);
 #endif
 }
+#else
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -1
+static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+{
+   return -ENOSYS;
+}
 #endif
 
 #ifdef CONFIG_SPL_OS_BOOT
@@ -193,12 +199,12 @@ void spl_mmc_load_image(void)
if (!err)
return;
}
-#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
+
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
if (!err)
return;
-#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
if (!err)
@@ -265,12 +271,11 @@ void spl_mmc_load_image(void)
if (!err)
return;
}
-#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
if (!err)
return;
-#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
err = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
if (!err)
-- 
1.9.1

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Re: [U-Boot] TI8148 EVM

[Brian Hutchinson]

On Oct 22, 2015 7:50 AM, "Tom Rini"  wrote:
>
> On Thu, Oct 22, 2015 at 07:33:07AM -0400, Brian Hutchinson wrote:
> > On Oct 22, 2015 7:21 AM, "Tom Rini"  wrote:
> > >
> > > On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > I was trying the latest master branch for ti8148 evm to boot from SD
> > > > card, following are the steps which I followed:
> > > >
> > > > 1:  make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean
> > distclean
> > > > 2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> > ti814x_evm_config
> > > > 3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> > > >
> > > > Copy the MLO and u-boot.bin to SD card boot partition which is
> > > > bootable, I see no prints coming from the 1st stage bootlaoder, cant
> > > > debug it as I don’t have access to JTAG.
> > > >
> > > > Any pointers is this code tested ?
> > >
> > > First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
> > > you have on the board?  We only have support for PG1.0 today and not
> > > PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.
The
> > > code should be easily ported from the old PSP tree to support PG2.0
> > > however.
> >
> > What about DM816x support?  Mainline u-boot have anything for it?  We
> > finally have Linux 4.2.3 running on our board with .dts support.  Now
I'm
> > starting the task of getting a mainline u-boot to work so we can get
rid of
> > the legacy dtb being part of kernel.
>
> Well, the ti816x support we have today should be a good starting point
> at least for the "DM" variant of the chip.  I forget which one of the
> boards I have technically but I _think_ the differences are high level
> enough that for U-Boot it's OK.
>
> --
> Tom

We are using PG2.1.  I "think" the only difference between 2.0 and 2.1 is
top end clock speed.

Regards,

Brian
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[U-Boot] [Patch V7 02/18] common/board_f.c: modify the macro to use get_clocks() more common

[Gong Qianyu]

get_clocks() should not be limited by ESDHC.

Signed-off-by: Gong Qianyu 
---
V7:
 - Change the name of the new macro and add readme file for it.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - Removed defines in PPC configs that have no need to use.
V2:
 - No change.

 common/board_f.c  | 2 +-
 doc/README.fsl-clk| 6 ++
 include/configs/colibri_vf.h  | 1 +
 include/configs/ls1021aqds.h  | 1 +
 include/configs/ls1021atwr.h  | 1 +
 include/configs/ls2085aqds.h  | 1 +
 include/configs/ls2085ardb.h  | 1 +
 include/configs/m53evk.h  | 1 +
 include/configs/mx25pdk.h | 1 +
 include/configs/mx35pdk.h | 1 +
 include/configs/mx51evk.h | 1 +
 include/configs/mx53ard.h | 1 +
 include/configs/mx53evk.h | 1 +
 include/configs/mx53loco.h| 1 +
 include/configs/mx53smd.h | 1 +
 include/configs/mx6_common.h  | 1 +
 include/configs/mx7_common.h  | 1 +
 include/configs/usbarmory.h   | 1 +
 include/configs/vf610twr.h| 1 +
 include/configs/woodburn_common.h | 1 +
 20 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 613332e..b3a6693 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
 #endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_SYS_FSL_CLK
get_clocks,
 #endif
 #ifdef CONFIG_M68K
diff --git a/doc/README.fsl-clk b/doc/README.fsl-clk
new file mode 100644
index 000..9e83c24
--- /dev/null
+++ b/doc/README.fsl-clk
@@ -0,0 +1,6 @@
+Freescale system clock options
+
+   - CONFIG_SYS_FSL_CLK
+   Enable to call get_clocks() in board_init_f() for
+   non-PPC platforms and PCC 8xx platforms such as
+   TQM866M and TQM885D.
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 2583155..92d1e88 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_USE_ARCH_MEMCPY
 #define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_ARCH_MISC_INIT
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 9b8b001..89243e8 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -12,6 +12,7 @@
 #define CONFIG_ARMV7_PSCI
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 676c096..d79a670 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,7 @@
 #define CONFIG_ARMV7_PSCI
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index f7f3870..406d0e6 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -16,6 +16,7 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index a190bc7..4395cff 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -18,6 +18,7 @@
 unsigned long get_board_sys_clk(void);
 #endif
 
+#define CONFIG_SYS_FSL_CLK
 #define CONFIG_SYS_CLK_FREQget_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ1
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 8853d8f..fe183e2 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -18,6 +18,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_REVISION_TAG
 #define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_FIT
 
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 0414086..c0a4528 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -15,6 +15,7 @@
 #define CONFIG_SYS_TEXT_BASE   0x8120
 #define CONFIG_MXC_GPIO
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_TIMER_RATE  32768
 #define CONFIG_SYS_TIMER_COUNTER   \
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 6bfdaa6..4ead6fb 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -20,6 +20,7 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_FSL_CLK
 
 /* Set TEXT at the beginning of the NOR flash 

Re: [U-Boot] TI8148 EVM

[Tom Rini]

On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:

> Hi Tom,
> 
> I was trying the latest master branch for ti8148 evm to boot from SD
> card, following are the steps which I followed:
> 
> 1:  make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean distclean
> 2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- ti814x_evm_config
> 3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-
> 
> Copy the MLO and u-boot.bin to SD card boot partition which is
> bootable, I see no prints coming from the 1st stage bootlaoder, cant
> debug it as I don’t have access to JTAG.
> 
> Any pointers is this code tested ?

First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
you have on the board?  We only have support for PG1.0 today and not
PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.  The
code should be easily ported from the old PSP tree to support PG2.0
however.

-- 
Tom


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[U-Boot] [PATCH 04/12] spl: mmc: remove #ifdef CONFIG_SPL_OS_BOOT check

[Nikita Kiryanov]

Implement default versions of falcon mode functions to make the
CONFIG_SPL_OS_BOOT check in spl_mmc_load_image() unnecessary, thus reducing
its #ifdef complexity.

No functional changes.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
Cc: Guillaume GARDET 
Cc: Suriyan Ramasami 
---
 common/spl/spl_ext.c |  6 ++
 common/spl/spl_fat.c |  6 ++
 common/spl/spl_mmc.c | 17 +
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 9d37fd3..a42fbd0 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #ifdef CONFIG_SPL_EXT_SUPPORT
@@ -135,5 +136,10 @@ defaults:
return spl_load_image_ext(block_dev, partition,
CONFIG_SPL_FS_LOAD_KERNEL_NAME);
 }
+#else
+int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
+{
+   return -ENOSYS;
+}
 #endif
 #endif
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 350f7d9..0daadbe 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 static int fat_registered;
@@ -119,5 +120,10 @@ defaults:
return spl_load_image_fat(block_dev, partition,
CONFIG_SPL_FS_LOAD_KERNEL_NAME);
 }
+#else
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
+{
+   return -ENOSYS;
+}
 #endif
 #endif
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index cfbda1a..f0c4d56 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -154,6 +154,15 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
return mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
 }
+#else
+int spl_start_uboot(void)
+{
+   return 1;
+}
+static int mmc_load_image_raw_os(struct mmc *mmc)
+{
+   return -ENOSYS;
+}
 #endif
 
 void spl_mmc_load_image(void)
@@ -179,13 +188,11 @@ void spl_mmc_load_image(void)
case MMCSD_MODE_RAW:
debug("spl: mmc boot mode: raw\n");
 
-#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
err = mmc_load_image_raw_os(mmc);
if (!err)
return;
}
-#endif
 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
@@ -203,14 +210,12 @@ void spl_mmc_load_image(void)
 
 #ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 #ifdef CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
err = spl_load_image_fat_os(>block_dev,
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
if (!err)
return;
}
-#endif
 #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_fat(>block_dev,
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
@@ -220,14 +225,12 @@ void spl_mmc_load_image(void)
 #endif
 #endif
 #ifdef CONFIG_SPL_EXT_SUPPORT
-#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
err = spl_load_image_ext_os(>block_dev,
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
if (!err)
return;
}
-#endif
 #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_ext(>block_dev,
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
@@ -257,13 +260,11 @@ void spl_mmc_load_image(void)
hang();
}
 
-#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
err = mmc_load_image_raw_os(mmc);
if (!err)
return;
}
-#endif
 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
err = mmc_load_image_raw_partition(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
-- 
1.9.1

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[U-Boot] [Patch V7 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape

[Gong Qianyu]

From: Mingkai Hu 

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Gong Qianyu 
---
V7:
 - Add Hou Zhiqiang Signed-off.
V6:
 - Remove GIC SMMU TZPC macros from ls2085a_common.h to config.h.
 - Modify fsl_lsch3_wake_secondary_cores() to 
fsl_layerscape_wake_seconday_cores()
 - Fix lsch3->layerscape changes for ls2085a emu and simu. 
V5:
 - Move LS2085A ddr macros out of soc #ifdef.
 - Move macros and structs from cpu.c to cpu.h.
 - Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
 - Modify fsl-layerscape/Makefile.
V4:
 - New patch.

 arch/arm/cpu/armv8/Makefile|   2 +-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |  21 ++
 .../README => fsl-layerscape/README.lsch3} |   2 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c  | 248 ++---
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h  |   2 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c  |  17 +-
 .../fsl_lsch3_serdes.c |   8 +-
 .../speed.c => fsl-layerscape/fsl_lsch3_speed.c}   |  12 +-
 .../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S |  14 +-
 .../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c |   3 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c   |  16 +-
 .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c  |  35 +--
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|  76 +++
 arch/arm/cpu/armv8/fsl-lsch3/Makefile  |  13 --
 arch/arm/cpu/armv8/fsl-lsch3/speed.h   |   7 -
 .../clock.h|   8 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  96 
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165 ++
 .../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h  |   4 +
 .../fsl_serdes.h   |  11 +-
 .../immap_lsch3.h  | 119 --
 .../arm/include/asm/arch-fsl-layerscape/imx-regs.h |  55 +
 .../ls2085a_stream_id.h|   0
 arch/arm/include/asm/arch-fsl-layerscape/mmu.h |  10 +
 .../asm/arch-fsl-layerscape}/mp.h  |  10 +-
 .../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h  |  21 +-
 arch/arm/include/asm/arch-fsl-layerscape/speed.h   |  10 +
 arch/arm/include/asm/arch-fsl-lsch3/config.h   | 185 ---
 arch/arm/include/asm/arch-fsl-lsch3/gpio.h |   9 -
 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h |  13 --
 arch/arm/include/asm/config.h  |   7 +-
 board/freescale/ls2085a/Kconfig|   4 +-
 board/freescale/ls2085a/ls2085a.c  |   2 +-
 board/freescale/ls2085aqds/Kconfig |   2 +-
 board/freescale/ls2085aqds/eth.c   |   1 -
 board/freescale/ls2085aqds/ls2085aqds.c|   2 +-
 board/freescale/ls2085ardb/Kconfig |   2 +-
 board/freescale/ls2085ardb/eth_ls2085rdb.c |   1 -
 board/freescale/ls2085ardb/ls2085ardb.c|   2 +-
 drivers/i2c/mxc_i2c.c  |   4 +-
 drivers/misc/fsl_debug_server.c|   1 -
 drivers/net/ldpaa_eth/ls2085a.c|   2 -
 drivers/pci/pcie_layerscape.c  |   4 +-
 include/common.h   |   3 +
 include/configs/ls2085a_common.h   |  10 +-
 45 files changed, 713 insertions(+), 526 deletions(-)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..48c041b 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y += cache.o
 obj-y  += tlb.o
 obj-y  += transition.o
 
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 000..ccb3aa5
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README 

[U-Boot] [Patch V7 12/18] armv8/fsl_lsch2: Add fsl_lsch2 SoC

[Gong Qianyu]

From: Mingkai Hu 

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - Remove GIC SMMU macros back to config.h.
V5:
 - Move LS1043A ddr macros out of soc #ifdef.
 - Move macros and structs from cpu.c to cpu.h.
 - Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
 - Modify fsl-layerscape/Makefile.
V4:
 - Add fsl_lsch2 to fsl-layerscape framework.
V3:
 - Update MMU table initialization to match the latest code.
 - Remove some dead code
 - Rename #include to #include
V2:
 - remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   5 +
 arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 |  10 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  13 +
 .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c| 117 +
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 137 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|  17 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  47 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  64 +++
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  91 
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 555 +
 .../include/asm/arch-fsl-layerscape/ns_access.h| 158 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   6 +
 arch/arm/include/asm/armv8/mmu.h   |   1 +
 include/common.h   |   3 +
 14 files changed, 1224 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index ccb3aa5..4754e59 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_SPL) += spl.o
 ifneq ($(CONFIG_FSL_LSCH3),)
 obj-y += fsl_lsch3_speed.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+else
+ifneq ($(CONFIG_FSL_LSCH2),)
+obj-y += fsl_lsch2_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
+endif
 endif
 
 ifneq ($(CONFIG_LS2085A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
new file mode 100644
index 000..a6ef830
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index be7442d..fe9d982 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -180,6 +180,8 @@ static inline void early_mmu_setup(void)
set_pgtable_table(level1_table0,
  CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
  level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+   set_pgtable_table(level1_table0, 1, level2_table1);
 #endif
/* Find the table and fill in the block entries */
for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
@@ -215,6 +217,9 @@ static inline void early_mmu_setup(void)
  *
  * For LSCH3:
  * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
  */
 static inline void final_mmu_setup(void)
 {
@@ -225,6 +230,9 @@ static inline void final_mmu_setup(void)
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
 #ifdef CONFIG_FSL_LSCH3
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
+   u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+   u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
 #endif
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
 
@@ -239,6 +247,11 @@ static inline void final_mmu_setup(void)
set_pgtable_table(level1_table0,
  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
  level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+   set_pgtable_table(level1_table0, 1, level2_table1);
+   set_pgtable_table(level1_table0,
+ CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+ level2_table2);
 #endif
 
/* Find the table and fill in the block entries */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
new file mode 100644
index 000..f7178d1
--- 

[U-Boot] [Patch V7 14/18] armv8/ls1043ardb: Add nand boot support

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - Add enable_layerscape_ns_access() in fsl-layerscape/spl.c
V3:
 - No change.
V2:
 - Removed unecessary NAND_PAGE_SIZE in ls1043a_common.h.
 - Fixed "select SUPPORT_SPL" in arch/arm/Kconfig.
 - Used CONFIG_FSL_IFC instead of SPL_NAND_SUPPORT for init_early_memctl_regs()
 - Replaced ns_access.h with fsl_csu.h

 arch/arm/Kconfig   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|  3 ++
 board/freescale/ls1043ardb/README  |  1 +
 board/freescale/ls1043ardb/cpld.c  | 19 +
 board/freescale/ls1043ardb/cpld.h  |  1 +
 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg  | 14 +++
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |  7 
 configs/ls1043ardb_nand_defconfig  |  4 ++
 include/configs/ls1043a_common.h   | 27 +
 include/configs/ls1043ardb.h   | 46 ++
 10 files changed, 123 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd99bfb..6584e85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -634,6 +634,7 @@ config TARGET_LS1021ATWR
 config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
+   select SUPPORT_SPL
help
  Support for Freescale LS1043ARDB platform.
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 2f30d4b..ba551aa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -71,6 +71,9 @@ void board_init_f(ulong dummy)
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
 
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+   enable_layerscape_ns_access();
+#endif
board_init_r(NULL, 0);
 }
 #endif
diff --git a/board/freescale/ls1043ardb/README 
b/board/freescale/ls1043ardb/README
index d5925a9..4f15557 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -83,3 +83,4 @@ Start Address End Address Description Size
 Booting Options
 ---
 a) NOR boot
+b) NAND boot
diff --git a/board/freescale/ls1043ardb/cpld.c 
b/board/freescale/ls1043ardb/cpld.c
index 3f1101e..f29383d 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -45,6 +45,22 @@ void cpld_set_defbank(void)
CPLD_WRITE(global_rst, 1);
 }
 
+void cpld_set_nand(void)
+{
+   u16 reg = CPLD_CFG_RCW_SRC_NAND;
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
+
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
+
+   CPLD_WRITE(system_rst, 1);
+}
+
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -91,6 +107,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
+   else if (strcmp(argv[2], "nand") == 0)
+   cpld_set_nand();
else
cpld_set_defbank();
 #ifdef DEBUG
@@ -109,6 +127,7 @@ U_BOOT_CMD(
"Reset the board or alternate bank",
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
+   "cpld reset nand: reset to boot from NAND flash\n"
 #ifdef DEBUG
"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h 
b/board/freescale/ls1043ardb/cpld.h
index ea4efd8..5f43a8a 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL   0x40
 #define CPLD_BANK_SEL_MASK 0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
+#define CPLD_CFG_RCW_SRC_NAND  0x106
 #endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 
b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 
+09570604 1000
+#Alt base register
+09570158 1000
+#Disable CCI barrier tranaction
+09570178 e010
+0918 0008
+#USB PHY frequency sel
+09570418 009e
+0957041c 009e
+09570420 009e
+#flush PBI data
+096100c0 000f
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 
b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 000..935ffc0
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble 

[U-Boot] [Patch V7 09/18] net/fm: Add QSGMII PCS init

[Gong Qianyu]

From: Shaohui Xie 

QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - Remove the "if(priv->phyaddr%4 != 0)" condition in qsgmii_loop.
V3:
 - No change.
V2:
 - No change.

 drivers/net/fm/eth.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index bf16101..1cb1f7a 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+   int i = 0;
 
+qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
 
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x14, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x4, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
/* Adjust link timer for SGMII  -
1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
+
+   if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+   i++;
+   goto qsgmii_loop;
+   }
 #else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,6 +98,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+   fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V7 05/18] net/fm: Add support for 64-bit platforms

[Gong Qianyu]

From: Hou Zhiqiang 

The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:

1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - New patch.

 drivers/net/fm/eth.c | 61 
 drivers/net/fm/fm.c  | 20 ++---
 drivers/net/fm/fm.h  | 12 +--
 3 files changed, 60 insertions(+), 33 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index ad02c66..6451dce 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -108,12 +108,12 @@ static int tgec_is_fibre(struct eth_device *dev)
 
 static u16 muram_readw(u16 *addr)
 {
-   u32 base = (u32)addr & ~0x3;
-   u32 val32 = in_be32((u32 *)base);
+   ulong base = (ulong)addr & ~0x3UL;
+   u32 val32 = in_be32((void *)base);
int byte_pos;
u16 ret;
 
-   byte_pos = (u32)addr & 0x3;
+   byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
ret = (u16)(val32 & 0x);
else
@@ -124,18 +124,18 @@ static u16 muram_readw(u16 *addr)
 
 static void muram_writew(u16 *addr, u16 val)
 {
-   u32 base = (u32)addr & ~0x3;
-   u32 org32 = in_be32((u32 *)base);
+   ulong base = (ulong)addr & ~0x3UL;
+   u32 org32 = in_be32((void *)base);
u32 val32;
int byte_pos;
 
-   byte_pos = (u32)addr & 0x3;
+   byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
val32 = (org32 & 0x) | val;
else
val32 = (org32 & 0x) | ((u32)val << 16);
 
-   out_be32((u32 *)base, val32);
+   out_be32((void *)base, val32);
 }
 
 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -199,6 +199,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
+   u32 bd_ring_base_lo, bd_ring_base_hi;
+   u32 buf_lo, buf_hi;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
@@ -207,10 +209,15 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+   if (!pram) {
+   printf("%s: No muram for Rx global parameter\n", __func__);
+   return 0;
+   }
+
fm_eth->rx_pram = pram;
 
/* parameter page offset to MURAM */
-   pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+   pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
out_be32(>mode, PRAM_MODE_GLOBAL);
@@ -234,6 +241,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
if (!rx_buf_pool)
return 0;
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
+   debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
 
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
@@ -245,17 +253,22 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
for (i = 0; i < RX_BD_RING_SIZE; i++) {
muram_writew(>status, RxBD_EMPTY);
muram_writew(>len, 0);
-   muram_writew(>buf_ptr_hi, 0);
-   out_be32(>buf_ptr_lo, (u32)rx_buf_pool +
-   i * MAX_RXBUF_LEN);
+   buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
+   i * MAX_RXBUF_LEN));
+   buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
+   i * MAX_RXBUF_LEN));
+   muram_writew(>buf_ptr_hi, (u16)buf_hi);
+   out_be32(>buf_ptr_lo, buf_lo);
rxbd++;
}
 
/* set the Rx queue descriptor */
rxqd = >rxqd;
muram_writew(>gen, 0);
-   muram_writew(>bd_ring_base_hi, 0);
-   out_be32(>bd_ring_base_lo, (u32)rx_bd_ring_base);
+   bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
+   bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
+   muram_writew(>bd_ring_base_hi, (u16)bd_ring_base_hi);
+   out_be32(>bd_ring_base_lo, bd_ring_base_lo);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -272,6 +285,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void 

[U-Boot] [Patch V7 08/18] net: Move some header files to include/

[Gong Qianyu]

From: Shaohui Xie 

The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - No change.
V2:
 - No change.

 arch/powerpc/include/asm/immap_85xx.h | 2 +-
 board/freescale/b4860qds/eth_b4860qds.c   | 2 +-
 board/freescale/corenet_ds/eth_hydra.c| 2 +-
 board/freescale/corenet_ds/eth_p4080.c| 2 +-
 board/freescale/corenet_ds/eth_superhydra.c   | 2 +-
 board/freescale/p1023rdb/p1023rdb.c   | 2 +-
 board/freescale/p2041rdb/eth.c| 2 +-
 board/freescale/t102xqds/eth_t102xqds.c   | 2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c   | 2 +-
 board/freescale/t1040qds/eth.c| 2 +-
 board/freescale/t104xrdb/eth.c| 2 +-
 board/freescale/t208xqds/eth_t208xqds.c   | 2 +-
 board/freescale/t208xrdb/eth_t208xrdb.c   | 2 +-
 board/freescale/t4qds/eth.c   | 2 +-
 board/freescale/t4rdb/eth.c   | 2 +-
 drivers/net/fm/dtsec.c| 2 +-
 drivers/net/fm/eth.c  | 4 ++--
 drivers/net/fm/fm.h   | 2 +-
 drivers/net/fm/tgec.c | 2 +-
 drivers/net/fm/tgec_phy.c | 2 +-
 {arch/powerpc/include/asm => include}/fsl_dtsec.h | 0
 {arch/powerpc/include/asm => include}/fsl_fman.h  | 0
 {arch/powerpc/include/asm => include}/fsl_tgec.h  | 0
 23 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85e..101b8db 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 typedef struct ccsr_local {
diff --git a/board/freescale/b4860qds/eth_b4860qds.c 
b/board/freescale/b4860qds/eth_b4860qds.c
index 501d4b3..df90476 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -26,7 +26,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_hydra.c 
b/board/freescale/corenet_ds/eth_hydra.c
index 396103f..172a55b 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -55,7 +55,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_p4080.c 
b/board/freescale/corenet_ds/eth_p4080.c
index 5cbec7f..c68dc2c 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -24,7 +24,7 @@
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
-#include 
+#include 
 
 #define EMI_NONE   0x
 #define EMI_MASK   0xf000
diff --git a/board/freescale/corenet_ds/eth_superhydra.c 
b/board/freescale/corenet_ds/eth_superhydra.c
index ad1bffd..62b1635 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -55,7 +55,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/p1023rdb/p1023rdb.c 
b/board/freescale/p1023rdb/p1023rdb.c
index 56f561a..074b713 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -26,7 +26,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 532eeac..95fe85b 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -19,7 +19,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "cpld.h"
 #include "../common/fman.h"
diff --git a/board/freescale/t102xqds/eth_t102xqds.c 
b/board/freescale/t102xqds/eth_t102xqds.c
index 441d6a3..99c23f7 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -21,7 +21,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include "../common/qixis.h"
 #include "../common/fman.h"
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c 
b/board/freescale/t102xrdb/eth_t102xrdb.c
index 856ec6e..02b283d 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,7 +21,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include "../common/fman.h"
 
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 8c82934..8bf34fa 

[U-Boot] [Patch V7 10/18] net/fm: fix MDIO controller base on FMAN2

[Gong Qianyu]

From: Shaohui Xie 

MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - No change.
V2:
 - No change.

 include/fm_eth.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/include/fm_eth.h b/include/fm_eth.h
index 3e1b9f4..d43f801 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -45,8 +45,10 @@ enum fm_eth_type {
 #ifdef CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
 #else
 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR + 
0xe1120)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
@@ -89,6 +91,7 @@ enum fm_eth_type {
 offsetof(struct ccsr_fman, memac[n-1]),\
 }
 #else
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {  \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@@ -101,6 +104,20 @@ enum fm_eth_type {
.compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{  \
+   FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+   .index  = idx,  \
+   .num= n - 1,\
+   .type   = FM_ETH_10G_E, \
+   .port   = FM##idx##_10GEC##n,   \
+   .rx_port_id = RX_PORT_10G_BASE + n - 1, \
+   .tx_port_id = TX_PORT_10G_BASE + n - 1, \
+   .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+   offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
 #endif
 
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
-- 
2.1.0.27.g96db324

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[U-Boot] TI8148 EVM

[Lad, Prabhakar]

Hi Tom,

I was trying the latest master branch for ti8148 evm to boot from SD
card, following are the steps which I followed:

1:  make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean distclean
2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- ti814x_evm_config
3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi-

Copy the MLO and u-boot.bin to SD card boot partition which is
bootable, I see no prints coming from the 1st stage bootlaoder, cant
debug it as I don’t have access to JTAG.

Any pointers is this code tested ?

Cheers,
--Prabhakar Lad
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Re: [U-Boot] [PATCH 0/8] ARM: keystone2: Enable OF_CONTROL and DM

[Tom Rini]

On Thu, Oct 22, 2015 at 03:07:55PM +0530, Lokesh Vutla wrote:
> Hi Tom,
> 
> On Saturday 19 September 2015 03:00 PM, Lokesh Vutla wrote:
> > This patch series enables OF_CONTROL and DM for all keystone platforms.
> > In order to add support for OF_CONTROL all the keystone2 specific DT
> > files are imported from Linux kernel. For now only DM_SERIAL is enabled
> > on all keystone2 platforms, moving forward all other drivers are
> > converted to DM and will be enabled in defconfig.
> > 
> > Build targets used:
> > UART boot: u-boot-dtb.bin
> > NAND boot: MLO
> > SPI boot: u-boot-spl.gph
> > 
> > Above three bootmodes are verified on the following platforms:
> > K2HK-evm, K2L-evm, K2E-evm.
> > 
> > This patch series is based on top of keystone serial driver posted 
> > previously:
> > https://www.mail-archive.com/u-boot%40lists.denx.de/msg186443.html
> 
> Gentle ping.

Thanks, I'm going to put together a PR of my own stuff today or
tomorrow.

-- 
Tom


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Re: [U-Boot] Fastboot behaviour with sparse images

[Tom Rini]

On Thu, Oct 22, 2015 at 09:57:05AM +0200, Maxime Ripard wrote:
> Hi Tom,
> 
> On Wed, Oct 21, 2015 at 10:09:28AM -0400, Tom Rini wrote:
> > On Mon, Oct 12, 2015 at 03:43:01PM +0200, Maxime Ripard wrote:
> > > Hi,
> > > 
> > > I'm currently writing the support in U-Boot for NAND-backed devices
> > > using fastboot [1], and that work derived a bit to supporting the
> > > sparse images.
> > > 
> > > For "regular" images that are being stored, we expect a pair of
> > > download and flash commands. Simple.
> > > 
> > > Things start to get a bit more complex with sparse images that have
> > > been split because of a max-download-size lower than the actual image
> > > size.
> > > 
> > > Here, from what I could gather from various random blog posts, the
> > > fastboot client implementation and dumping a few USB sessions, the
> > > client simply creates several download / flash pairs, always on the
> > > same partition, without any way to distinct that from several
> > > subsequent writes issued by the user.
> > > 
> > > So, I'm guessing that the expectation is that the bootloader
> > > implementation should store the last offset it wrote to, and simple
> > > resume from there if the partition names in the flash commands are the
> > > same, which would prevent two subsequent write on the same partition
> > > by any client. Am I right?
> > > 
> > > A related question is when should we erase the NAND partition? Only
> > > when doing fastboot erase, or also when doing fastboot write (which,
> > > combined with the issue raised above, would also mean that we don't
> > > want to do an erase on the whole partition everytime there's a flash
> > > command on it).
> > 
> > I think for this last question, some experimentation with the existing
> > tools might be required.  As there's no required explicit erase for MMC,
> > I think it might make sense to say you erase nand up front and then
> > write as anything else starts getting really tricky and we're just
> > second-guessing the user.
> 
> Actually, the only FS the fastboot tool seems to be doing it for the
> moment are ext4 and F2FS. It can probably be extended to UBI and raw
> partitions, but that won't fix the tools that are bundled by the
> distros at the moment.
> 
> So I guess we can always erase it now using the session counter: if we
> are writing the first chunk, erase the whole partition, if we're not,
> then simply flash it at the previous offset.
> 
> How does it sound?

Sounds workable but testing with the existing tools will be the key and
the hard part here :(

-- 
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Re: [U-Boot] [PATCH v3 2/2] linux/bitops.h: GENMASK copy from linux

[Tom Rini]

On Wed, Oct 21, 2015 at 04:46:51PM +0530, Jagan Teki wrote:

> GENMASK is used to create a contiguous bitmask([hi:lo]).
> 
> This patch is a copy from Linux, with below commit details
> "bitops: Fix shift overflow in GENMASK macros"
> (sha1: 00b4d9a14125f1e51874def2b9de6092e007412d)
> 
> Cc: Tom Rini 
> Cc: Masahiro Yamada 
> Signed-off-by: Jagan Teki 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-x86.git

[Tom Rini]

On Wed, Oct 21, 2015 at 05:15:17PM -0600, Simon Glass wrote:

> Hi Tom,
> 
> This includes support for booting VxWorks, the Advantech SOM-6896, MRC
> fixes (speeds up boot), expanded video support and some debug UART
> improvements.
> 
> 
> The following changes since commit 5ec0003b19cbdf06ccd6941237cbc0d1c3468e2d:
> 
>   Prepare v2015.10 (2015-10-19 19:59:38 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git
> 
> for you to fetch changes up to e0ae64880b61fdeaf261fddd747efa80fa53d386:
> 
>   x86: Add support for Advantech SOM-6896 (2015-10-21 16:29:27 -0600)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v3 1/2] linux/bitops: Move BIT definitions at top

[Tom Rini]

On Wed, Oct 21, 2015 at 05:30:34PM +0530, Jagan Teki wrote:

> Since it's a copy from Linux, this patch moved all
> BIT definitions to top so-that it looks same as Linux file.
> 
> Cc: Tom Rini 
> Cc: Albert ARIBAUD 
> Signed-off-by: Jagan Teki 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v9 1/4] include: Add log2 and generic bitops header files

[Fabio Estevam]

On Thu, Oct 22, 2015 at 8:25 AM, Jagan Teki  wrote:
> On 20 October 2015 at 18:33, Fabio Estevam  
> wrote:
>> Use the log2 and generic bitops header files directly from the kernel.
>
> Pls- add separate patches for log2 and biptops, do remember that use
> same Linux approach but don't add unneeded definitions now will add
> based on the need.

I cannot only add log2 definition without the bitops, as ilog2 needs them.

Also, I am not adding unneeded definitions. All the header files I
added are referenced.
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[U-Boot] [PATCH 09/12] common: spl: move image load to its own function

[Nikita Kiryanov]

Refactor spl image load code out of board_init_r and into its own
function. This is a preparation for supporting alternative boot
devices.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl.c | 117 ---
 1 file changed, 50 insertions(+), 67 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index ff1bad2..56fccca 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -178,122 +178,105 @@ int spl_init(void)
return 0;
 }
 
-void board_init_r(gd_t *dummy1, ulong dummy2)
+static int spl_load_image(u32 boot_device)
 {
-   u32 boot_device;
-
-   debug(">>spl:board_init_r()\n");
-
-#if defined(CONFIG_SYS_SPL_MALLOC_START)
-   mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
-   CONFIG_SYS_SPL_MALLOC_SIZE);
-   gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#endif
-   if (!(gd->flags & GD_FLG_SPL_INIT)) {
-   if (spl_init())
-   hang();
-   }
-#ifndef CONFIG_PPC
-   /*
-* timer_init() does not exist on PPC systems. The timer is initialized
-* and enabled (decrementer) in interrupt_init() here.
-*/
-   timer_init();
-#endif
-
-#ifdef CONFIG_SPL_BOARD_INIT
-   spl_board_init();
-#endif
-
-   boot_device = spl_boot_device();
-   debug("boot device - %d\n", boot_device);
switch (boot_device) {
 #ifdef CONFIG_SPL_RAM_DEVICE
case BOOT_DEVICE_RAM:
-   if (spl_ram_load_image())
-   hang();
-   break;
+   return spl_ram_load_image();
 #endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
-   if (spl_mmc_load_image())
-   hang();
-   break;
+   return spl_mmc_load_image();
 #endif
 #ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
-   if (spl_nand_load_image())
-   hang();
-   break;
+   return spl_nand_load_image();
 #endif
 #ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
-   if (spl_onenand_load_image())
-   hang();
-   break;
+   return spl_onenand_load_image();
 #endif
 #ifdef CONFIG_SPL_NOR_SUPPORT
case BOOT_DEVICE_NOR:
-   if (spl_nor_load_image())
-   hang();
-   break;
+   return spl_nor_load_image();
 #endif
 #ifdef CONFIG_SPL_YMODEM_SUPPORT
case BOOT_DEVICE_UART:
-   if (spl_ymodem_load_image())
-   hang();
-   break;
+   return spl_ymodem_load_image();
 #endif
 #ifdef CONFIG_SPL_SPI_SUPPORT
case BOOT_DEVICE_SPI:
-   if (spl_spi_load_image())
-   hang();
-   break;
+   return spl_spi_load_image();
 #endif
 #ifdef CONFIG_SPL_ETH_SUPPORT
case BOOT_DEVICE_CPGMAC:
 #ifdef CONFIG_SPL_ETH_DEVICE
-   if (spl_net_load_image(CONFIG_SPL_ETH_DEVICE))
-   hang();
+   return spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
 #else
-   if (spl_net_load_image(NULL))
-   hang();
+   return spl_net_load_image(NULL);
 #endif
-   break;
 #endif
 #ifdef CONFIG_SPL_USBETH_SUPPORT
case BOOT_DEVICE_USBETH:
-   if (spl_net_load_image("usb_ether"))
-   hang();
-   break;
+   return spl_net_load_image("usb_ether");
 #endif
 #ifdef CONFIG_SPL_USB_SUPPORT
case BOOT_DEVICE_USB:
-   if (spl_usb_load_image())
-   hang();
-   break;
+   return spl_usb_load_image();
 #endif
 #ifdef CONFIG_SPL_SATA_SUPPORT
case BOOT_DEVICE_SATA:
-   if (spl_sata_load_image())
-   hang();
-   break;
+   return spl_sata_load_image();
 #endif
 #ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
case BOOT_DEVICE_BOARD:
-   if (spl_board_load_image())
-   hang();
-   break;
+   return spl_board_load_image();
 #endif
default:
 #if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
puts("SPL: Unsupported Boot Device!\n");
 #endif
-   hang();
+   return -ENODEV;
}
 
+   return -EINVAL;
+}
+
+void board_init_r(gd_t *dummy1, ulong dummy2)
+{
+   u32 boot_device;
+
+   debug(">>spl:board_init_r()\n");
+
+#if defined(CONFIG_SYS_SPL_MALLOC_START)
+   mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+   CONFIG_SYS_SPL_MALLOC_SIZE);
+   gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+#endif
+  

[U-Boot] [PATCH 03/12] spl: mmc: refactor device location code to its own function

[Nikita Kiryanov]

Simplify spl_mmc_load_image() code by moving the part that finds the mmc device
into its own function spl_mmc_find_device(), available in two flavors: DM and
non-DM.

This refactor fixes a bug in which an error in the device location sequence
does not necessarily aborts the rest of the code. With this refactor, we fail
the moment there is an error.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c | 77 +---
 1 file changed, 55 insertions(+), 22 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index e831970..cfbda1a 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -59,6 +60,58 @@ end:
return 0;
 }
 
+#ifdef CONFIG_DM_MMC
+static int spl_mmc_find_device(struct mmc **mmc)
+{
+   struct udevice *dev;
+   int err;
+
+   err = mmc_initialize(NULL);
+   if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("spl: could not initialize mmc. error: %d\n", err);
+#endif
+   return err;
+   }
+
+   err = uclass_get_device(UCLASS_MMC, 0, );
+   if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   puts("spl: could not find mmc device. error: %d\n", err);
+#endif
+   return err;
+   }
+
+   *mmc = NULL;
+   *mmc = mmc_get_mmc_dev(dev);
+   return *mmc != NULL ? 0 : -ENODEV;
+}
+#else
+static int spl_mmc_find_device(struct mmc **mmc)
+{
+   int err;
+
+   err = mmc_initialize(gd->bd);
+   if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("spl: could not initialize mmc. error: %d\n", err);
+#endif
+   return err;
+   }
+
+   /* We register only one device. So, the dev id is always 0 */
+   *mmc = find_mmc_device(0);
+   if (!*mmc) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   puts("spl: mmc device not found\n");
+#endif
+   return -ENODEV;
+   }
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
 {
@@ -110,30 +163,10 @@ void spl_mmc_load_image(void)
int err = 0;
__maybe_unused int part;
 
-#ifdef CONFIG_DM_MMC
-   struct udevice *dev;
-
-   mmc_initialize(NULL);
-   err = uclass_get_device(UCLASS_MMC, 0, );
-   mmc = NULL;
-   if (!err)
-   mmc = mmc_get_mmc_dev(dev);
-#else
-   mmc_initialize(gd->bd);
-
-   /* We register only one device. So, the dev id is always 0 */
-   mmc = find_mmc_device(0);
-   if (!mmc) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   puts("spl: mmc device not found\n");
-#endif
+   if (spl_mmc_find_device())
hang();
-   }
-#endif
-
-   if (!err)
-   err = mmc_init(mmc);
 
+   err = mmc_init(mmc);
if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: mmc init failed with error: %d\n", err);
-- 
1.9.1

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[U-Boot] [PATCH 02/12] spl: mmc: add break statements in spl_mmc_load_image()

[Nikita Kiryanov]

The original intention of the mmc load_image() function was to try multiple
boot modes before failing. This is evident by the lack of break statements
in the switch, and the following line in the default case:
puts("spl: mmc: no boot mode left to try\n");

This implementation is problematic because:
- The availability of alternative boot modes is very arbitrary since it
depends on the specific order of the switch cases. If your boot mode happens to
be the first case, then you'll have a bunch of other boot modes as alternatives.
If it happens to be the last case, then you have none.
- Opting in/out is tied to config options, so the only way for you to prevent an
alternative boot mode from being attempted is to give up on the feature 
completely.
- This implementation makes the code more complicated and difficult to
understand.

Address these issues by inserting a break statements between the cases to make 
the
function try only one boot mode.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ce58c58..e831970 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -164,6 +164,7 @@ void spl_mmc_load_image(void)
if (!err)
return;
 #endif
+   break;
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
 
@@ -203,6 +204,7 @@ void spl_mmc_load_image(void)
 #endif
 #endif
 #endif
+   break;
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
case MMCSD_MODE_EMMCBOOT:
/*
@@ -240,15 +242,15 @@ void spl_mmc_load_image(void)
if (!err)
return;
 #endif
+   break;
 #endif
case MMCSD_MODE_UNDEFINED:
default:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   if (err)
-   puts("spl: mmc: no boot mode left to try\n");
-   else
-   puts("spl: mmc: wrong boot mode\n");
+   puts("spl: mmc: wrong boot mode\n");
 #endif
hang();
}
+
+   hang();
 }
-- 
1.9.1

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[U-Boot] [PATCH 00/12] SPL mmc refactor and alternate boot device feature

[Nikita Kiryanov]

This series has two parts: patches 1-7 perform refactors aimed at reducing the
ifdef complexity of SPL mmc code (and some nand as well). This refactor also
addresses a few design issues I noticed while working on the refactor.

The rest of the series introduces a new SPL feature that allows board code to
define a list of boot devices that SPL will try before failing (instead of the
only one device it attempts now). This feature is useful for implementing
fallbacks, as well as reacting to bootROM sequences. For example:

On CM-FX6, if boot from the alternate boot device (MMC) fails, the bootROM
proceeds to try boot from SPI flash. If the SPI flash boot is succesful, SPL
will still try to load U-Boot from MMC, instead of from the actual boot device
(SPI flash), and probably fail and hang. The alternate boot feature makes it
possible for SPL to follow the MMC boot attempt with boot from the SPI flash.
The CM-FX6 based miniature PC Utilite depends on this capability for its SPI
flash boot to work, since SPI flash boot is only attempted if MMC boot fails.

This series was tested on CM-FX6 and compile tested for arm and powerpc.

Cc: Igor Grinberg 
Cc: Tom Rini 
Cc: Pantelis Antoniou 

Nikita Kiryanov (12):
  spl: nand: remove code duplication
  spl: mmc: add break statements in spl_mmc_load_image()
  spl: mmc: refactor device location code to its own function
  spl: mmc: remove #ifdef CONFIG_SPL_OS_BOOT check
  spl: mmc: get rid of #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
check
  spl: mmc: move fs boot into its own function
  spl: mmc: get rid of emmc boot code duplication
  spl: change return values of spl_*_load_image()
  common: spl: move image load to its own function
  spl: add support for alternative boot device
  spl: announce boot devices
  arm: mx6: cm-fx6: define fallback boot devices for spl

 arch/arm/cpu/armv7/sunxi/board.c |   4 +-
 arch/arm/include/asm/spl.h   |   2 +-
 board/compulab/cm_fx6/spl.c  |  19 +--
 common/spl/spl.c | 191 ++--
 common/spl/spl_ext.c |   6 +
 common/spl/spl_fat.c |   6 +
 common/spl/spl_mmc.c | 263 +++
 common/spl/spl_nand.c|  47 ---
 common/spl/spl_net.c |   9 +-
 common/spl/spl_nor.c |   6 +-
 common/spl/spl_onenand.c |   4 +-
 common/spl/spl_sata.c|  11 +-
 common/spl/spl_usb.c |  17 ++-
 common/spl/spl_ymodem.c  |   5 +-
 drivers/mtd/spi/spi_spl_load.c   |  17 ++-
 include/configs/cm_fx6.h |   1 -
 include/spl.h|  18 +--
 17 files changed, 414 insertions(+), 212 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH 11/12] spl: announce boot devices

[Nikita Kiryanov]

Now that we support alternative boot devices, it can sometimes be
unclear which boot devices was actually used. Provide a function to
announce which boot devices are attempted during boot.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl.c | 86 
 1 file changed, 86 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7913c52..ee30290 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -178,6 +178,91 @@ int spl_init(void)
return 0;
 }
 
+#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
+__weak void spl_board_announce_boot_device(void) { }
+#endif
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+static void announce_boot_device(u32 boot_device)
+{
+   puts("Trying to boot from ");
+   switch (boot_device) {
+#ifdef CONFIG_SPL_RAM_DEVICE
+   case BOOT_DEVICE_RAM:
+   puts("RAM");
+   break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+   case BOOT_DEVICE_MMC1:
+   case BOOT_DEVICE_MMC2:
+   case BOOT_DEVICE_MMC2_2:
+   puts("MMC");
+   break;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+   case BOOT_DEVICE_NAND:
+   puts("NAND");
+   break;
+#endif
+#ifdef CONFIG_SPL_ONENAND_SUPPORT
+   case BOOT_DEVICE_ONENAND:
+   puts("OneNAND");
+   break;
+#endif
+#ifdef CONFIG_SPL_NOR_SUPPORT
+   case BOOT_DEVICE_NOR:
+   puts("NOR");
+   break;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+   case BOOT_DEVICE_UART:
+   puts("UART");
+   break;
+#endif
+#ifdef CONFIG_SPL_SPI_SUPPORT
+   case BOOT_DEVICE_SPI:
+   puts("SPI");
+   break;
+#endif
+#ifdef CONFIG_SPL_ETH_SUPPORT
+   case BOOT_DEVICE_CPGMAC:
+#ifdef CONFIG_SPL_ETH_DEVICE
+   puts("eth device");
+#else
+   puts("net");
+#endif
+   break;
+#endif
+#ifdef CONFIG_SPL_USBETH_SUPPORT
+   case BOOT_DEVICE_USBETH:
+   puts("USB eth");
+   break;
+#endif
+#ifdef CONFIG_SPL_USB_SUPPORT
+   case BOOT_DEVICE_USB:
+   puts("USB");
+   break;
+#endif
+#ifdef CONFIG_SPL_SATA_SUPPORT
+   case BOOT_DEVICE_SATA:
+   puts("SATA");
+   break;
+#endif
+#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
+   case BOOT_DEVICE_BOARD:
+   spl_board_announce_boot_device();
+   break;
+#endif
+   default:
+   printf("%d (unknown boot device)", boot_device);
+   }
+
+   puts("\n");
+}
+#else
+static inline void announce_boot_device(u32 boot_device) { }
+#endif
+
 #ifndef BOOT_DEVICE_NONE
 #define BOOT_DEVICE_NONE 0xdeadbeef
 #endif
@@ -292,6 +377,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
board_boot_order(spl_boot_list);
for (i = 0; i < ARRAY_SIZE(spl_boot_list) &&
spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
+   announce_boot_device(spl_boot_list[i]);
if (!spl_load_image(spl_boot_list[i]))
break;
}
-- 
1.9.1

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[U-Boot] [Patch V7 03/18] net/fm: Fix the endian issue to support both endianness platforms

[Gong Qianyu]

From: Hou Zhiqiang 

The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - Modify the subject to make the aim clear.
V2:
 - No change.

 drivers/net/fm/eth.c | 70 +++-
 drivers/net/fm/fm.c  | 11 +
 2 files changed, 43 insertions(+), 38 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6702f5a..368d554 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -109,7 +109,7 @@ static int tgec_is_fibre(struct eth_device *dev)
 static u16 muram_readw(u16 *addr)
 {
u32 base = (u32)addr & ~0x3;
-   u32 val32 = *(u32 *)base;
+   u32 val32 = in_be32((u32 *)base);
int byte_pos;
u16 ret;
 
@@ -125,7 +125,7 @@ static u16 muram_readw(u16 *addr)
 static void muram_writew(u16 *addr, u16 val)
 {
u32 base = (u32)addr & ~0x3;
-   u32 org32 = *(u32 *)base;
+   u32 org32 = in_be32((u32 *)base);
u32 val32;
int byte_pos;
 
@@ -135,7 +135,7 @@ static void muram_writew(u16 *addr, u16 val)
else
val32 = (org32 & 0x) | ((u32)val << 16);
 
-   *(u32 *)base = val32;
+   out_be32((u32 *)base, val32);
 }
 
 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -213,10 +213,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
-   pram->mode = PRAM_MODE_GLOBAL;
+   out_be32(>mode, PRAM_MODE_GLOBAL);
 
/* init the Rx queue descriptor pionter */
-   pram->rxqd_ptr = pram_page_offset + 0x20;
+   out_be32(>rxqd_ptr, pram_page_offset + 0x20);
 
/* set the max receive buffer length, power of 2 */
muram_writew(>mrblr, MAX_RXBUF_LOG2);
@@ -243,10 +243,11 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
-   rxbd->status = RxBD_EMPTY;
-   rxbd->len = 0;
-   rxbd->buf_ptr_hi = 0;
-   rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+   muram_writew(>status, RxBD_EMPTY);
+   muram_writew(>len, 0);
+   muram_writew(>buf_ptr_hi, 0);
+   out_be32(>buf_ptr_lo, (u32)rx_buf_pool +
+   i * MAX_RXBUF_LEN);
rxbd++;
}
 
@@ -254,7 +255,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
rxqd = >rxqd;
muram_writew(>gen, 0);
muram_writew(>bd_ring_base_hi, 0);
-   rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+   out_be32(>bd_ring_base_lo, (u32)rx_bd_ring_base);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -285,10 +286,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
-   pram->mode = PRAM_MODE_GLOBAL;
+   out_be32(>mode, PRAM_MODE_GLOBAL);
 
/* init the Tx queue descriptor pionter */
-   pram->txqd_ptr = pram_page_offset + 0x40;
+   out_be32(>txqd_ptr, pram_page_offset + 0x40);
 
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
@@ -304,16 +305,17 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
-   txbd->status = TxBD_LAST;
-   txbd->len = 0;
-   txbd->buf_ptr_hi = 0;
-   txbd->buf_ptr_lo = 0;
+   muram_writew(>status, TxBD_LAST);
+   muram_writew(>len, 0);
+   muram_writew(>buf_ptr_hi, 0);
+   out_be32(>buf_ptr_lo, 0);
+   txbd++;
}
 
/* set the Tx queue decriptor */
txqd = >txqd;
muram_writew(>bd_ring_base_hi, 0);
-   txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+   out_be32(>bd_ring_base_lo, (u32)tx_bd_ring_base);
muram_writew(>bd_ring_size, 

[U-Boot] [Patch V7 06/18] net/fm: Make the return value logic consistent with convention

[Gong Qianyu]

From: Hou Zhiqiang 

In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - New patch.

 drivers/net/fm/eth.c | 60 +++-
 1 file changed, 36 insertions(+), 24 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6451dce..d7d064b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -211,7 +211,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Rx global parameter\n", __func__);
-   return 0;
+   return -ENOMEM;
}
 
fm_eth->rx_pram = pram;
@@ -232,14 +232,16 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
-   return 0;
+   return -ENOMEM;
+
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
 
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
-   return 0;
+   return -ENOMEM;
+
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
 
@@ -277,7 +279,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(_rx_port->fmbm_rfqid, pram_page_offset);
 
-   return 1;
+   return 0;
 }
 
 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
@@ -296,7 +298,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Tx global parameter\n", __func__);
-   return 0;
+   return -ENOMEM;
}
fm_eth->tx_pram = pram;
 
@@ -313,7 +315,8 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
-   return 0;
+   return -ENOMEM;
+
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
@@ -344,29 +347,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(_tx_port->fmbm_tcfqid, pram_page_offset);
 
-   return 1;
+   return 0;
 }
 
 static int fm_eth_init(struct fm_eth *fm_eth)
 {
+   int ret;
 
-   if (!fm_eth_rx_port_parameter_init(fm_eth))
-   return 0;
+   ret = fm_eth_rx_port_parameter_init(fm_eth);
+   if (ret)
+   return ret;
 
-   if (!fm_eth_tx_port_parameter_init(fm_eth))
-   return 0;
+   ret = fm_eth_tx_port_parameter_init(fm_eth);
+   if (ret)
+   return ret;
 
-   return 1;
+   return 0;
 }
 
 static int fm_eth_startup(struct fm_eth *fm_eth)
 {
struct fsl_enet_mac *mac;
+   int ret;
+
mac = fm_eth->mac;
 
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
-   if (!fm_eth_init(fm_eth))
-   return 0;
+   ret = fm_eth_init(fm_eth);
+   if (ret)
+   return ret;
/* setup the MAC controller */
mac->init_mac(mac);
 
@@ -381,7 +390,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
 
-   return 1;
+   return 0;
 }
 
 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
@@ -628,7 +637,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct 
ccsr_fman *reg)
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
-   return 0;
+   return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
 
/* save the mac to fm_eth struct */
@@ -643,7 +652,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct 
ccsr_fman *reg)
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
 #endif
 
-   return 1;
+   return 0;
 }
 
 static int init_phy(struct eth_device *dev)
@@ -696,17 +705,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct 
fm_eth_info *info)
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
+   

[U-Boot] [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC

[Gong Qianyu]

From: Shaohui Xie 

Use mb() instead of sync() to be compatible for both ARM and PowerPC.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - New patch. Separated from patch 'net: Move some header files to include/'

 drivers/net/fm/eth.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 368d554..ad02c66 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -371,7 +371,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth 
*fm_eth)
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
setbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
-   sync();
+   mb();
 }
 
 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
@@ -381,7 +381,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth 
*fm_eth)
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
clrbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
-   sync();
+   mb();
 }
 
 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
@@ -483,9 +483,9 @@ static int fm_eth_send(struct eth_device *dev, void *buf, 
int len)
muram_writew(>buf_ptr_hi, 0);
out_be32(>buf_ptr_lo, (u32)buf);
muram_writew(>len, len);
-   sync();
+   mb();
muram_writew(>status, TxBD_READY | TxBD_LAST);
-   sync();
+   mb();
 
/* update TxQD, let RISC to send the packet */
offset_in = muram_readw(>txqd.offset_in);
@@ -493,7 +493,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf, 
int len)
if (offset_in >= muram_readw(>txqd.bd_ring_size))
offset_in = 0;
muram_writew(>txqd.offset_in, offset_in);
-   sync();
+   mb();
 
/* wait for buffer to be transmitted */
for (i = 0; muram_readw(>status) & TxBD_READY; i++) {
@@ -544,7 +544,7 @@ static int fm_eth_recv(struct eth_device *dev)
/* clear the RxBDs */
muram_writew(>status, RxBD_EMPTY);
muram_writew(>len, 0);
-   sync();
+   mb();
 
/* advance RxBD */
rxbd++;
@@ -560,7 +560,7 @@ static int fm_eth_recv(struct eth_device *dev)
if (offset_out >= muram_readw(>rxqd.bd_ring_size))
offset_out = 0;
muram_writew(>rxqd.offset_out, offset_out);
-   sync();
+   mb();
}
fm_eth->cur_rxbd = (void *)rxbd;
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V7 07/18] net: fm: bug fix when CONFIG_PHYLIB not defined

[Gong Qianyu]

From: Shaohui Xie 

codes related to phylib operations should be wrapped by CONFIG_PHYLIB.

Signed-off-by: Shaohui Xie 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - Fix all codes related to phylib to be wrapped by CONFIG_PHYLIB.
V5:
 - No change.
V4:
 - No change.
V3:
 - New patch.

 drivers/net/fm/eth.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index d7d064b..e262859 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -95,6 +95,7 @@ static void dtsec_init_phy(struct eth_device *dev)
dtsec_configure_serdes(fm_eth);
 }
 
+#ifdef CONFIG_PHYLIB
 static int tgec_is_fibre(struct eth_device *dev)
 {
struct fm_eth *fm = dev->priv;
@@ -105,6 +106,7 @@ static int tgec_is_fibre(struct eth_device *dev)
return hwconfig_arg_cmp(phyopt, "xfi");
 }
 #endif
+#endif
 
 static u16 muram_readw(u16 *addr)
 {
@@ -483,8 +485,10 @@ static void fm_eth_halt(struct eth_device *dev)
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
 
+#ifdef CONFIG_PHYLIB
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev);
+#endif
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
@@ -658,13 +662,15 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct 
ccsr_fman *reg)
 static int init_phy(struct eth_device *dev)
 {
struct fm_eth *fm_eth = dev->priv;
+#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
u32 supported;
+#endif
 
-#ifdef CONFIG_PHYLIB
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(dev);
 
+#ifdef CONFIG_PHYLIB
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V7 13/18] armv8/ls1043ardb: Add LS1043ARDB board support

[Gong Qianyu]

From: Mingkai Hu 

LS1043ARDB Specification:
-
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Li Yang 
Signed-off-by: Mingkai Hu 
Signed-off-by: York Sun 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - Move GIC SMMU macros out of ls1043a_common.h.
V5:
 - No change.
V4: 
 - Change arch to layerscape.
 - Add PCIe support.
 - Move SMMU_BASE, GICC_BASE, GICD_BASE to ls1043a_common.h.
V3:
 - Fix message typos.
 - Add ddr model number in comments.
 - Fix boot options in README.
 - Remove some dead code.
V2:
 - Replaced ns_access.h with fsl_csu.h.

 arch/arm/Kconfig   |   7 +
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c |  86 ++
 board/freescale/ls1043ardb/Kconfig |  16 ++
 board/freescale/ls1043ardb/MAINTAINERS |   7 +
 board/freescale/ls1043ardb/Makefile|   9 +
 board/freescale/ls1043ardb/README  |  85 +
 board/freescale/ls1043ardb/cpld.c  | 115 +
 board/freescale/ls1043ardb/cpld.h  |  43 +
 board/freescale/ls1043ardb/ddr.c   | 191 +
 board/freescale/ls1043ardb/ddr.h   |  45 +
 board/freescale/ls1043ardb/ls1043ardb.c| 131 ++
 configs/ls1043ardb_defconfig   |   4 +
 include/configs/ls1043a_common.h   | 174 +++
 include/configs/ls1043ardb.h   | 191 +
 15 files changed, 1108 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7981355..bd99bfb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -631,6 +631,12 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
 
+config TARGET_LS1043ARDB
+   bool "Support ls1043ardb"
+   select ARM64
+   help
+ Support for Freescale LS1043ARDB platform.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -745,6 +751,7 @@ source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 4754e59..6fa08c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -23,4 +23,8 @@ endif
 
 ifneq ($(CONFIG_LS2085A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+else
+ifneq ($(CONFIG_LS1043A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+endif
 endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
new file mode 100644
index 000..e54d389
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+struct serdes_config {
+   u32 protocol;
+   u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+   /* SerDes 1 */
+   {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+   {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+   {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+   {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+   {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+   {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+   {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ PCIE3} },
+   {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+   {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+   {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+   {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+   {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+   {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+   {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+   {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+   {0x2455, 

[U-Boot] [Patch V7 15/18] armv8/ls1043a: Add Fman support

[Gong Qianyu]

From: Shaohui Xie 

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - Change arch to layerscape.
V3:
 - No change.
V2:
 - No change.

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  12 +++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c|   6 ++
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  23 
 board/freescale/common/fman.c  |   6 +-
 board/freescale/ls1043ardb/Makefile|   1 +
 board/freescale/ls1043ardb/eth.c   |  77 +
 board/freescale/ls1043ardb/ls1043ardb.c|   4 +
 doc/README.fsl-dpaa|   4 +-
 drivers/net/fm/Makefile|   1 +
 drivers/net/fm/init.c  |  10 +-
 drivers/net/fm/ls1043.c| 119 +
 include/configs/ls1043a_common.h   |  12 +++
 include/configs/ls1043ardb.h   |  25 +
 13 files changed, 295 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index fe9d982..0cb0afa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -274,6 +274,9 @@ static inline void final_mmu_setup(void)
flush_dcache_range(gd->arch.tlb_addr,
   gd->arch.tlb_addr + gd->arch.tlb_size);
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+   flush_dcache_all();
+#endif
/* point TTBR to the new table */
el = current_el();
 
@@ -432,6 +435,9 @@ int print_cpuinfo(void)
printf("\n   Bus:  %-4s MHz  ",
   strmhz(buf, sysinfo.freq_systembus));
printf("DDR:  %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+   printf("  FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
 #ifdef CONFIG_FSL_LSCH3
printf(" DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
 #endif
@@ -468,6 +474,9 @@ int cpu_eth_init(bd_t *bis)
 #ifdef CONFIG_FSL_MC_ENET
error = fsl_mc_ldpaa_init(bis);
 #endif
+#ifdef CONFIG_FMAN_ENET
+   fm_standard_init(bis);
+#endif
return error;
 }
 
@@ -484,6 +493,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
 #endif
+#ifdef CONFIG_FMAN_ENET
+   fman_enet_init();
+#endif
return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index aa88d34..9c841c2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -18,6 +18,12 @@
 #include 
 #endif
 
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+   return fdt_setprop_string(blob, offset, "phy-connection-type",
+phy_string_for_interface(phyc));
+}
+
 #ifdef CONFIG_MP
 void ft_fixup_cpu(void *blob)
 {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index ea3723f..9d5bbe7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
 #endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+   u32 rcw_tmp;
+#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
@@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M1_CLK_SEL 0xe000
 #define HWA_CGA_M1_CLK_SHIFT   29
+#ifdef CONFIG_SYS_DPAA_FMAN
+   rcw_tmp = in_be32(>rcwsr[7]);
+   switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+   case 2:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+   break;
+   case 3:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+   break;
+   case 6:
+   sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+   break;
+   case 7:
+   sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+   break;
+   default:
+   printf("Error: Unknown FMan1 clock select!\n");
+   break;
+   }
+#endif
 
 #define HWA_CGA_M2_CLK_SEL 0x0007
 #define HWA_CGA_M2_CLK_SHIFT   0
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 9dc5402..26cf517 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
  *
 

[U-Boot] [Patch V7 17/18] armv8/ls1043ardb: Add sd boot support

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - No change.
V3:
 - Squash the add cpld command patch to it.
V2:
 - No change.

 board/freescale/ls1043ardb/README|  1 +
 board/freescale/ls1043ardb/cpld.c| 18 ++
 board/freescale/ls1043ardb/cpld.h|  1 +
 board/freescale/ls1043ardb/ls1043ardb.c  |  6 +
 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |  7 ++
 configs/ls1043ardb_sdcard_defconfig  |  4 
 include/configs/ls1043a_common.h | 30 
 include/configs/ls1043ardb.h | 11 -
 8 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/board/freescale/ls1043ardb/README 
b/board/freescale/ls1043ardb/README
index 4f15557..0556e73 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -84,3 +84,4 @@ Booting Options
 ---
 a) NOR boot
 b) NAND boot
+c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c 
b/board/freescale/ls1043ardb/cpld.c
index f29383d..78c2824 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -61,6 +61,21 @@ void cpld_set_nand(void)
CPLD_WRITE(system_rst, 1);
 }
 
+void cpld_set_sd(void)
+{
+   u16 reg = CPLD_CFG_RCW_SRC_SD;
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
+
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
+
+   CPLD_WRITE(system_rst, 1);
+}
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -109,6 +124,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
cpld_set_altbank();
else if (strcmp(argv[2], "nand") == 0)
cpld_set_nand();
+   else if (strcmp(argv[2], "sd") == 0)
+   cpld_set_sd();
else
cpld_set_defbank();
 #ifdef DEBUG
@@ -128,6 +145,7 @@ U_BOOT_CMD(
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
"cpld reset nand: reset to boot from NAND flash\n"
+   "cpld reset sd: reset to boot from SD card\n"
 #ifdef DEBUG
"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h 
b/board/freescale/ls1043ardb/cpld.h
index 5f43a8a..bd59c0e 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_BANK_SEL_MASK 0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
 #define CPLD_CFG_RCW_SRC_NAND  0x106
+#define CPLD_CFG_RCW_SRC_SD0x040
 #endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index 461a195..9032ed3 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -25,12 +25,17 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
u32 cfg_rcw_src;
+#endif
u32 sd1refclk_sel;
 
printf("Board: LS1043ARDB, boot from ");
 
+#ifdef CONFIG_SD_BOOT
+   puts("SD\n");
+#else
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(_rcw_src1);
@@ -43,6 +48,7 @@ int checkboard(void)
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
+#endif
 
printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
   CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 
b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 000..28cd958
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+081f 0c00  
+14550002 80004012 6004 61002000
+   00038800
+ 1100 0096 0001
diff --git a/configs/ls1043ardb_sdcard_defconfig 
b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644
index 000..5fe0470
--- /dev/null
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 490c39e..85d9426 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -62,6 +62,36 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define 

[U-Boot] [Patch V7 16/18] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb

[Gong Qianyu]

From: Yangbo Lu 

This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - No change.
V5:
 - No change.
V4:
 - Use CONFIG_FSL_ESDHC to enable get_sdhc_freq().
 - Merge lsch2 and lsch3 into layerscape.
V3:
 - No change.
V2:
 - No change.

 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 22 +-
 board/freescale/ls1043ardb/ls1043ardb.c|  1 +
 drivers/mmc/fsl_esdhc.c| 12 ++--
 include/configs/ls1043a_common.h   | 11 +++
 include/fsl_esdhc.h|  2 +-
 5 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 9d5bbe7..6f6a588 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
 #endif
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
u32 rcw_tmp;
 #endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M2_CLK_SEL 0x0007
 #define HWA_CGA_M2_CLK_SHIFT   0
+#ifdef CONFIG_FSL_ESDHC
+   rcw_tmp = in_be32(>rcwsr[15]);
+   rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+   sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
 
 #if defined(CONFIG_FSL_IFC)
ccr = ifc_in32(_regs.gregs->ifc_ccr);
@@ -123,6 +128,10 @@ int get_clocks(void)
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
 
+#ifdef CONFIG_FSL_ESDHC
+   gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
if (gd->cpu_clk != 0)
return 0;
else
@@ -139,6 +148,13 @@ ulong get_ddr_freq(ulong dummy)
return gd->mem_clk;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+   return gd->arch.sdhc_clk;
+}
+#endif
+
 int get_serial_clock(void)
 {
return gd->bus_clk;
@@ -149,6 +165,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+   case MXC_ESDHC_CLK:
+   return get_sdhc_freq(0);
+#endif
case MXC_DSPI_CLK:
return get_bus_freq(0);
case MXC_UART_CLK:
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index 6c0dd3f..461a195 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..471d6ee 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+   defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -184,7 +184,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
 #endif
uint wml_value;
@@ -197,7 +197,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
 
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -223,7 +223,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -277,7 +277,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
 static void check_and_invalidate_dcache_range
(struct mmc_cmd 

[U-Boot] [Patch V7 18/18] armv8/ls1043a: Enable secondary cores

[Gong Qianyu]

From: Hou Zhiqiang 

After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
V7:
 - No change.
V6:
 - New patch.

 arch/arm/Kconfig   |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/mp.c | 14 ++
 include/configs/ls1043a_common.h   |  3 +++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6584e85..6e30a5d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -634,6 +634,7 @@ config TARGET_LS1021ATWR
 config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
+   select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
  Support for Freescale LS1043ARDB platform.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c 
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 1b13d32..0d600db 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -25,7 +25,11 @@ phys_addr_t determine_mp_bootpg(void)
 int fsl_layerscape_wake_seconday_cores(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+   struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
@@ -48,13 +52,23 @@ int fsl_layerscape_wake_seconday_cores(void)
 
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
 
+#ifdef CONFIG_FSL_LSCH3
gur_out32(>bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(>bootlocptrl, (u32)gd->relocaddr);
gur_out32(>scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+   scfg_out32(>scratchrw[0], (u32)(gd->relocaddr >> 32));
+   scfg_out32(>scratchrw[1], (u32)gd->relocaddr);
+   asm volatile("dsb st" : : : "memory");
+   gur_out32(>brrl, cores);
+   asm volatile("dsb st" : : : "memory");
 
+   /* Bootup online cores */
+   scfg_out32(>corebcr, cores);
+#endif
/* This is needed as a precautionary measure.
 * If some code before this has accidentally  released the secondary
 * cores then the pre-bootloader code will trap them in a "wfe" unless
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 85d9426..53745aa 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH2
 #define CONFIG_LS1043A
+#define CONFIG_MP
 #define CONFIG_SYS_FSL_CLK
 #define CONFIG_GICV2
 
@@ -46,6 +47,8 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY  0
 #define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_SDRAM_BASE
 
+#define CPU_RELEASE_ADDR   secondary_boot_func
+
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY  2500/* 25MHz */
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V7 00/18] add LS1043A platform support

[Gong Qianyu]

Here are the changes for V7 patchset. Please help to review them.

 - Modified CONFIG_FSL_CLK to CONFIG_SYS_FSL_CLK and add a readme file
   for it.
 - Fixed the ns_access macros for ls1021atwr.

[Patch V7 01/18] armv7/ls1021a: move ns_access to common file
[Patch V7 02/18] common/board_f.c: modify the macro to use
[Patch V7 03/18] net/fm: Fix the endian issue to support both
[Patch V7 04/18] net/fm/eth: Use mb() to be compatible for both ARM
[Patch V7 05/18] net/fm: Add support for 64-bit platforms
[Patch V7 06/18] net/fm: Make the return value logic consistent with
[Patch V7 07/18] net: fm: bug fix when CONFIG_PHYLIB not defined
[Patch V7 08/18] net: Move some header files to include/
[Patch V7 09/18] net/fm: Add QSGMII PCS init
[Patch V7 10/18] net/fm: fix MDIO controller base on FMAN2
[Patch V7 11/18] armv8/fsl_lsch3: Change arch to fsl-layerscape
[Patch V7 12/18] armv8/fsl_lsch2: Add fsl_lsch2 SoC
[Patch V7 13/18] armv8/ls1043ardb: Add LS1043ARDB board support
[Patch V7 14/18] armv8/ls1043ardb: Add nand boot support
[Patch V7 15/18] armv8/ls1043a: Add Fman support
[Patch V7 16/18] armv8/ls1043ardb: esdhc: Add esdhc support for
[Patch V7 17/18] armv8/ls1043ardb: Add sd boot support
[Patch V7 18/18] armv8/ls1043a: Enable secondary cores
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Re: [U-Boot] Bisected broken Ethernet support on ODROID-X (Exynos4412 board)

[Lukasz Majewski]

Hi Siarhei,

> On Wed, 21 Oct 2015 10:06:09 +0200
> Lukasz Majewski  wrote:
> 
> > Hi Siarhei,
> > 
> > > On Tue, 20 Oct 2015 09:15:07 -0600
> > > Simon Glass  wrote:
> > > 
> > > > Hi,
> > > > 
> > > > On 20 October 2015 at 08:13, Siarhei Siamashka
> > > >  wrote:
> > > > > Hello,
> > > > >
> > > > > Ethernet support does not work anymore when using the current
> > > > > U-Boot (version v2014.10) on the ODROID-X board. Bisecting
> > > > > shows that this happened starting from commit
> > > > > 874dde80169e0a0c00020e2e0bbcd380c61097e3 ("dm: usb: exynos:
> > > > > Use driver model for USB"):
> > > > > http://git.denx.de/?p=u-boot.git;a=commitdiff;h=874dde80169e0a0c00020e2e0bbcd380c61097e3
> > > > >
> > > > > Below are the logs from the serial console.
> > > > >
> > > > > === works properly ==
> > > > >
> > > > > U-Boot 2015.04-00271-g52e6935-dirty (Oct 20 2015 - 16:38:09)
> > > > >
> > > > > CPU:Exynos4412@1000MHz
> > > > > Model: Odroid based on Exynos4412
> > > > > DRAM:  1 GiB
> > > > > Board PMIC init
> > > > > MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
> > > > > Net:   No ethernet found.
> > > > > Hit any key to stop autoboot:  0
> > > > > reading boot.scr
> > > > > 129 bytes read in 11 ms (10.7 KiB/s)
> > > > > ## Executing script at 40408000
> > > > > starting USB...
> > > > > USB0:   USB EHCI 1.00
> > > > > scanning bus 0 for devices... 4 USB Device(s) found
> > > > >scanning usb for storage devices... 0 Storage Device(s)
> > > > > found scanning usb for ethernet devices... 1 Ethernet
> > > > > Device(s) found
> > > > >
> > > > > === fails ==
> > > > >
> > > > > U-Boot 2015.04-00273-g78ab40b-dirty (Oct 20 2015 - 16:41:11)
> > > > >
> > > > > CPU:Exynos4412@1000MHz
> > > > > Model: Odroid based on Exynos4412
> > > > > DRAM:  1 GiB
> > > > > Board PMIC init
> > > > > MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
> > > > > Net:   No ethernet found.
> > > > > Hit any key to stop autoboot:  0
> > > > > reading boot.scr
> > > > > 129 bytes read in 12 ms (9.8 KiB/s)
> > > > > ## Executing script at 40408000
> > > > > starting USB...
> > > > > USB-1:   USB EHCI 1.00
> > > > > scanning bus 0 for devices... 1 USB Device(s) found
> > > > >scanning usb for ethernet devices... 0 Ethernet
> > > > > Device(s) found
> > > > >
> > > > > ===
> > > > >
> > > > > As a test, reverting f56da290b8df14a058b43735494dbbb0f8521a89
> > > > > ("Drop the code that doesn't use driver model for USB.") and
> > > > > disabling CONFIG_DM_USB in odroid_defconfig makes it work
> > > > > again.
> > > > 
> > > > Does this problem happen on the XU3?
> > > 
> > 
> > Yes, It does. 
> > 
> > I'm struggling to fix this issue for a few days now.
> >
> > What is interesting though, you can run ethernet by calling:
> > "usb start" and afterwards "usb reset".
> 
> That's a very interesting observation indeed. 
>  
> > > I don't have XU3. My only board is ODROID-X (the same as
> > > ODROID-X2, but with slower CPU clock speed and less RAM).
> > > 
> > > > Are you able to debug this?
> > > 
> > > I'm not sure if I can really spend much time on it. Debugging this
> > > issue would require comparing the old exynos usb code and the new
> > > dm code to see where exactly they differ. For example, the new
> > > 'ehci_usb_probe()' function does not call 'board_usb_init()' while
> > > the old 'ehci_hcd_init()' function did:
> > > 
> > > http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/usb/host/ehci-exynos.c;h=86cf6312febc30b7e142146c3b4763a6a871d5a6;hb=02e4d3fbc54b345883d9bead4f2a911d0f0f59b1#l329
> > > And just calling 'board_usb_init()' on ODROID-X is still not
> > > enough
> > 
> > I will say even more - it seems like the issue is not related to any
> > "basic" initialization (i.e. the lack of calling
> > ehci_usb_probe|reset_usb_phy) called just before calling "usb
> > start".
> > 
> > > to get this problem resolved for the CONFIG_DM_USB=y
> > > configuration, so there must be something else.
> > 
> > +1
> > 
> > > 
> > > I also don't quite like that the usb parts of the U-Boot dts files
> > > for exynos differ from the Linux dts files.
> > 
> > This is a really good questions. We have discussed it recently on
> > ELCE and there is no good solution for it.
> > 
> > We made a mistake to allow non Linux compliant bindings to slip into
> > u-boot. Now we must cope with (or fix) this mess.
> 
> OK, I see. Thanks for explaining.
> 
> But if the kernel is considered to be the primary source of dts files,
> then probably U-Boot needs to be eventually adjusted to match?

We will try to converge to linux kernel, however such process will take
some time, since it is almost impossible to change all bindings at once.

> 
> > > So far I'm satisfied that the old exynos usb code still works if
> > > its removal is reverted.
> > 
> > As I've stated above - please try "usb start" and "usb reset"
> > afterwards.
> 
> Thanks, doing "usb start" followed by "usb reset" makes the 

Re: [U-Boot] TI8148 EVM

[Tom Rini]

On Thu, Oct 22, 2015 at 12:27:54PM +0100, Lad, Prabhakar wrote:
> Hi Tom,
> 
> Thanks for the quick reply.
> 
> On Thu, Oct 22, 2015 at 12:22 PM, Tom Rini  wrote:
> > On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote:
> >
> >> Copy the MLO and u-boot.bin to SD card boot partition which is
> >> bootable, I see no prints coming from the 1st stage bootlaoder, cant
> >> debug it as I don’t have access to JTAG.
> >>
> >> Any pointers is this code tested ?
> >
> > First, you need to use u-boot.img not u-boot.bin.  Second, which PG do
> > you have on the board?  We only have support for PG1.0 today and not
> > PG2.0 as Matt did the initial bring-up and only has a PG1.0 board.  The
> > code should be easily ported from the old PSP tree to support PG2.0
> > however.
> >
> I tried this on PG2.0, PG1.0 should also be handy.

Yeah, PG2.0 doesn't work yet, that's what I have.

> Regarding u-boot.img, just copying this should work or also MLO needs
> to be copied ?

To be clear, MLO+u-boot.img not MLO+u-boot.bin

-- 
Tom


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Re: [U-Boot] [PATCH v9 1/4] include: Add log2 and generic bitops header files

[Fabio Estevam]

On Thu, Oct 22, 2015 at 9:28 AM, Fabio Estevam  wrote:
> On Thu, Oct 22, 2015 at 8:25 AM, Jagan Teki  wrote:
>> On 20 October 2015 at 18:33, Fabio Estevam  
>> wrote:
>>> Use the log2 and generic bitops header files directly from the kernel.
>>
>> Pls- add separate patches for log2 and biptops, do remember that use
>> same Linux approach but don't add unneeded definitions now will add
>> based on the need.
>
> I cannot only add log2 definition without the bitops, as ilog2 needs them.
>
> Also, I am not adding unneeded definitions. All the header files I
> added are referenced.

Or are you suggesting to do like this?

- Patch 1: only add log2 header from the kernel
- Patch 2: only add bitops headers from the kernel
- Patch 3: Add the users for log2 and bitops headers
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Re: [U-Boot] [Patch V6 01/18] armv7/ls1021a: move ns_access to common file

[Hou Zhiqiang]

> -Original Message-
> From: Gong Qianyu [mailto:b52...@rhuath.am.freescale.net]
> Sent: 2015年10月19日 19:59
> To: u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Kushwaha Prabhakar-B32579;
> Wang Huan-B18965; Gong Qianyu-B52263
> Subject: [Patch V6 01/18] armv7/ls1021a: move ns_access to common file
> 
> From: Mingkai Hu 
> 
> Config Security Level Register is different between different SoCs, so
> put the CSL register definition into the arch specific directory.
> 
> Signed-off-by: Mingkai Hu 
> Signed-off-by: Gong Qianyu 

Qianyu, you lost my Signed-off.

Thanks,
Zhqiang
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[U-Boot] [PATCH 06/12] spl: mmc: move fs boot into its own function

[Nikita Kiryanov]

Move the code that handles fs boot out of spl_mmc_load_image() and into its
own function to reduce the #ifdef complexit of spl_mmc_load_image().

No functional changes.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c | 81 +---
 1 file changed, 51 insertions(+), 30 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index fbdcf0d..959cdcc 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -171,6 +171,55 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
 }
 #endif
 
+#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+int spl_mmc_do_fs_boot(struct mmc *mmc)
+{
+   int err = -ENOSYS;
+
+#ifdef CONFIG_SPL_FAT_SUPPORT
+   if (!spl_start_uboot()) {
+   err = spl_load_image_fat_os(>block_dev,
+   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
+   if (!err)
+   return err;
+   }
+#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+   err = spl_load_image_fat(>block_dev,
+CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+   if (!err)
+   return err;
+#endif
+#endif
+#ifdef CONFIG_SPL_EXT_SUPPORT
+   if (!spl_start_uboot()) {
+   err = spl_load_image_ext_os(>block_dev,
+   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
+   if (!err)
+   return err;
+   }
+#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+   err = spl_load_image_ext(>block_dev,
+CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+   if (!err)
+   return err;
+#endif
+#endif
+
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   err = -ENOENT;
+#endif
+
+   return err;
+}
+#else
+int spl_mmc_do_fs_boot(struct mmc *mmc)
+{
+   return -ENOSYS;
+}
+#endif
+
 void spl_mmc_load_image(void)
 {
struct mmc *mmc;
@@ -214,38 +263,10 @@ void spl_mmc_load_image(void)
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
 
-#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
-#ifdef CONFIG_SPL_FAT_SUPPORT
-   if (!spl_start_uboot()) {
-   err = spl_load_image_fat_os(>block_dev,
-   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
-   if (!err)
-   return;
-   }
-#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
-   err = spl_load_image_fat(>block_dev,
-CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
-   if (!err)
-   return;
-#endif
-#endif
-#ifdef CONFIG_SPL_EXT_SUPPORT
-   if (!spl_start_uboot()) {
-   err = spl_load_image_ext_os(>block_dev,
-   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
-   if (!err)
-   return;
-   }
-#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
-   err = spl_load_image_ext(>block_dev,
-CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+   err = spl_mmc_do_fs_boot(mmc);
if (!err)
return;
-#endif
-#endif
-#endif
+
break;
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
case MMCSD_MODE_EMMCBOOT:
-- 
1.9.1

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[U-Boot] [PATCH 07/12] spl: mmc: get rid of emmc boot code duplication

[Nikita Kiryanov]

Get rid of emmc boot code duplication in spl_mmc_load_image() using a switch
case fallthrough into MMCSD_MODE_RAW. Since the #ifdef CONFIG_SUPPORT_EMMC_BOOT
check is not really necessary, remove it in the process.

No functional changes.

Signed-off-by: Nikita Kiryanov 
Cc: Igor Grinberg 
Cc: Paul Kocialkowski 
Cc: Pantelis Antoniou 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c | 54 ++--
 1 file changed, 18 insertions(+), 36 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 959cdcc..7bcdc89 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -240,6 +240,24 @@ void spl_mmc_load_image(void)
 
boot_mode = spl_boot_mode();
switch (boot_mode) {
+   case MMCSD_MODE_EMMCBOOT:
+   /*
+* We need to check what the partition is configured to.
+* 1 and 2 match up to boot0 / boot1 and 7 is user data
+* which is the first physical partition (0).
+*/
+   part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+   if (part == 7)
+   part = 0;
+
+   if (mmc_switch_part(0, part)) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   puts("spl: mmc partition switch failed\n");
+#endif
+   hang();
+   }
+   /* Fall through */
case MMCSD_MODE_RAW:
debug("spl: mmc boot mode: raw\n");
 
@@ -268,42 +286,6 @@ void spl_mmc_load_image(void)
return;
 
break;
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
-   case MMCSD_MODE_EMMCBOOT:
-   /*
-* We need to check what the partition is configured to.
-* 1 and 2 match up to boot0 / boot1 and 7 is user data
-* which is the first physical partition (0).
-*/
-   part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
-
-   if (part == 7)
-   part = 0;
-
-   if (mmc_switch_part(0, part)) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   puts("spl: mmc partition switch failed\n");
-#endif
-   hang();
-   }
-
-   if (!spl_start_uboot()) {
-   err = mmc_load_image_raw_os(mmc);
-   if (!err)
-   return;
-   }
-   err = mmc_load_image_raw_partition(mmc,
-   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
-   if (!err)
-   return;
-#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
-   err = mmc_load_image_raw_sector(mmc,
-   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
-   if (!err)
-   return;
-#endif
-   break;
-#endif
case MMCSD_MODE_UNDEFINED:
default:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-- 
1.9.1

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[U-Boot] [PATCH v4 19/24] spi: designware_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in designware_spi

Cc: Stefan Roese 
Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 drivers/spi/designware_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 7885e46..24a6e98 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CFS_OFFSET 12
 
 /* Bit fields in SR, 7 bits */
-#define SR_MASK0x7f/* cover 7 bits 
*/
+#define SR_MASKGENMASK(6, 0)   /* cover 7 bits 
*/
 #define SR_BUSYBIT(0)
 #define SR_TF_NOT_FULL BIT(1)
 #define SR_TF_EMPT BIT(2)
-- 
1.9.1

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[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb

Cc: Stefan Roese 
Cc: Vikas Manocha 
Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 drivers/spi/cadence_qspi_apb.c | 48 +-
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7786dd6..31e14ee 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -44,7 +44,7 @@
 #define CQSPI_INST_TYPE_QUAD   (2)
 
 #define CQSPI_STIG_DATA_LEN_MAX(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK(0xF)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASKGENMASK(19, 0)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
 #define CQSPI_DUMMY_BYTES_MAX  (4)
@@ -65,8 +65,8 @@
 #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10
 #defineCQSPI_REG_CONFIG_BAUD_LSB   19
 #defineCQSPI_REG_CONFIG_IDLE_LSB   31
-#defineCQSPI_REG_CONFIG_CHIPSELECT_MASK0xF
-#defineCQSPI_REG_CONFIG_BAUD_MASK  0xF
+#defineCQSPI_REG_CONFIG_CHIPSELECT_MASKGENMASK(3, 0)
+#defineCQSPI_REG_CONFIG_BAUD_MASK  GENMASK(3, 0)
 
 #defineCQSPI_REG_RD_INSTR  0x04
 #defineCQSPI_REG_RD_INSTR_OPCODE_LSB   0
@@ -75,10 +75,10 @@
 #defineCQSPI_REG_RD_INSTR_TYPE_DATA_LSB16
 #defineCQSPI_REG_RD_INSTR_MODE_EN_LSB  20
 #defineCQSPI_REG_RD_INSTR_DUMMY_LSB24
-#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   0x1F
+#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   GENMASK(4, 0)
 
 #defineCQSPI_REG_WR_INSTR  0x08
 #defineCQSPI_REG_WR_INSTR_OPCODE_LSB   0
@@ -88,23 +88,23 @@
 #defineCQSPI_REG_DELAY_TCHSH_LSB   8
 #defineCQSPI_REG_DELAY_TSD2D_LSB   16
 #defineCQSPI_REG_DELAY_TSHSL_LSB   24
-#defineCQSPI_REG_DELAY_TSLCH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TCHSH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSD2D_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSHSL_MASK  0xFF
+#defineCQSPI_REG_DELAY_TSLCH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TCHSH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSD2D_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSHSL_MASK  GENMASK(7, 0)
 
 #defineCQSPI_READLCAPTURE  0x10
 #defineCQSPI_READLCAPTURE_BYPASS_LSB   0
 #defineCQSPI_READLCAPTURE_DELAY_LSB1
-#defineCQSPI_READLCAPTURE_DELAY_MASK   0xF
+#defineCQSPI_READLCAPTURE_DELAY_MASK   GENMASK(3, 0)
 
 #defineCQSPI_REG_SIZE  0x14
 #defineCQSPI_REG_SIZE_ADDRESS_LSB  0
 #defineCQSPI_REG_SIZE_PAGE_LSB 4
 #defineCQSPI_REG_SIZE_BLOCK_LSB16
-#defineCQSPI_REG_SIZE_ADDRESS_MASK 0xF
-#defineCQSPI_REG_SIZE_PAGE_MASK0xFFF
-#defineCQSPI_REG_SIZE_BLOCK_MASK   0x3F
+#defineCQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0)
+#defineCQSPI_REG_SIZE_PAGE_MASKGENMASK(11, 0)
+#defineCQSPI_REG_SIZE_BLOCK_MASK   GENMASK(5, 0)
 
 #defineCQSPI_REG_SRAMPARTITION 0x18
 #defineCQSPI_REG_INDIRECTTRIGGER   0x1C
@@ -115,8 +115,8 @@
 #defineCQSPI_REG_SDRAMLEVEL0x2C
 #defineCQSPI_REG_SDRAMLEVEL_RD_LSB 0
 #defineCQSPI_REG_SDRAMLEVEL_WR_LSB 16
-#defineCQSPI_REG_SDRAMLEVEL_RD_MASK0x
-#defineCQSPI_REG_SDRAMLEVEL_WR_MASK0x
+#defineCQSPI_REG_SDRAMLEVEL_RD_MASKGENMASK(15, 0)
+#defineCQSPI_REG_SDRAMLEVEL_WR_MASKGENMASK(15, 0)
 
 #defineCQSPI_REG_IRQSTATUS 0x40
 #defineCQSPI_REG_IRQMASK   0x44
@@ -142,11 +142,11 @@
 #defineCQSPI_REG_CMDCTRL_RD_BYTES_LSB  20
 #defineCQSPI_REG_CMDCTRL_RD_EN_LSB 23
 #defineCQSPI_REG_CMDCTRL_OPCODE_LSB24
-#defineCQSPI_REG_CMDCTRL_DUMMY_MASK0x1F
-#define

[U-Boot] [PATCH v4 14/24] spi: tegra: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in tegra*.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Stephen Warren 
Cc: Tom Warren 
Signed-off-by: Jagan Teki 
---
 drivers/spi/tegra114_spi.c   | 64 ++--
 drivers/spi/tegra20_sflash.c | 50 +-
 drivers/spi/tegra20_slink.c  | 58 +++
 3 files changed, 86 insertions(+), 86 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index a965f80..d9edd11 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -33,54 +33,54 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND1 */
-#define SPI_CMD1_GO(1 << 31)
-#define SPI_CMD1_M_S   (1 << 30)
+#define SPI_CMD1_GOBIT(31)
+#define SPI_CMD1_M_S   BIT(30)
 #define SPI_CMD1_MODE_MASK 0x3
 #define SPI_CMD1_MODE_SHIFT28
 #define SPI_CMD1_CS_SEL_MASK   0x3
 #define SPI_CMD1_CS_SEL_SHIFT  26
-#define SPI_CMD1_CS_POL_INACTIVE3  (1 << 25)
-#define SPI_CMD1_CS_POL_INACTIVE2  (1 << 24)
-#define SPI_CMD1_CS_POL_INACTIVE1  (1 << 23)
-#define SPI_CMD1_CS_POL_INACTIVE0  (1 << 22)
-#define SPI_CMD1_CS_SW_HW  (1 << 21)
-#define SPI_CMD1_CS_SW_VAL (1 << 20)
+#define SPI_CMD1_CS_POL_INACTIVE3  BIT(25)
+#define SPI_CMD1_CS_POL_INACTIVE2  BIT(24)
+#define SPI_CMD1_CS_POL_INACTIVE1  BIT(23)
+#define SPI_CMD1_CS_POL_INACTIVE0  BIT(22)
+#define SPI_CMD1_CS_SW_HW  BIT(21)
+#define SPI_CMD1_CS_SW_VAL BIT(20)
 #define SPI_CMD1_IDLE_SDA_MASK 0x3
 #define SPI_CMD1_IDLE_SDA_SHIFT18
-#define SPI_CMD1_BIDIR (1 << 17)
-#define SPI_CMD1_LSBI_FE   (1 << 16)
-#define SPI_CMD1_LSBY_FE   (1 << 15)
-#define SPI_CMD1_BOTH_EN_BIT   (1 << 14)
-#define SPI_CMD1_BOTH_EN_BYTE  (1 << 13)
-#define SPI_CMD1_RX_EN (1 << 12)
-#define SPI_CMD1_TX_EN (1 << 11)
-#define SPI_CMD1_PACKED(1 << 5)
+#define SPI_CMD1_BIDIR BIT(17)
+#define SPI_CMD1_LSBI_FE   BIT(16)
+#define SPI_CMD1_LSBY_FE   BIT(15)
+#define SPI_CMD1_BOTH_EN_BIT   BIT(14)
+#define SPI_CMD1_BOTH_EN_BYTE  BIT(13)
+#define SPI_CMD1_RX_EN BIT(12)
+#define SPI_CMD1_TX_EN BIT(11)
+#define SPI_CMD1_PACKEDBIT(5)
 #define SPI_CMD1_BIT_LEN_MASK  0x1F
 #define SPI_CMD1_BIT_LEN_SHIFT 0
 
 /* COMMAND2 */
-#define SPI_CMD2_TX_CLK_TAP_DELAY  (1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY  BIT(6)
 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
-#define SPI_CMD2_RX_CLK_TAP_DELAY  (1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY  BIT(0)
 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
 
 /* TRANSFER STATUS */
-#define SPI_XFER_STS_RDY   (1 << 30)
+#define SPI_XFER_STS_RDY   BIT(30)
 
 /* FIFO STATUS */
-#define SPI_FIFO_STS_CS_INACTIVE   (1 << 31)
-#define SPI_FIFO_STS_FRAME_END (1 << 30)
-#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
-#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
-#define SPI_FIFO_STS_ERR   (1 << 8)
-#define SPI_FIFO_STS_TX_FIFO_OVF   (1 << 7)
-#define SPI_FIFO_STS_TX_FIFO_UNR   (1 << 6)
-#define SPI_FIFO_STS_RX_FIFO_OVF   (1 << 5)
-#define SPI_FIFO_STS_RX_FIFO_UNR   (1 << 4)
-#define SPI_FIFO_STS_TX_FIFO_FULL  (1 << 3)
-#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
-#define SPI_FIFO_STS_RX_FIFO_FULL  (1 << 1)
-#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
+#define SPI_FIFO_STS_CS_INACTIVE   BIT(31)
+#define SPI_FIFO_STS_FRAME_END BIT(30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
+#define SPI_FIFO_STS_ERR   BIT(8)
+#define SPI_FIFO_STS_TX_FIFO_OVF   BIT(7)
+#define SPI_FIFO_STS_TX_FIFO_UNR   BIT(6)
+#define SPI_FIFO_STS_RX_FIFO_OVF   BIT(5)
+#define SPI_FIFO_STS_RX_FIFO_UNR   BIT(4)
+#define SPI_FIFO_STS_TX_FIFO_FULL  BIT(3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
+#define SPI_FIFO_STS_RX_FIFO_FULL  BIT(1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
 
 #define SPI_TIMEOUT1000
 #define TEGRA_SPI_MAX_FREQ 5200
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index afa0848..5dc196b 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -20,37 +20,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define SPI_CMD_GO (1 << 30)
+#define SPI_CMD_GO BIT(30)
 #define SPI_CMD_ACTIVE_SCLK_SHIFT  26
 #define SPI_CMD_ACTIVE_SCLK_MASK   (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA (1 << 21)
+#define SPI_CMD_CK_SDA

[U-Boot] [PATCH v4 16/24] spi: xilinx_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in xilinx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Michal Simek 
Signed-off-by: Jagan Teki 
---
 drivers/spi/xilinx_spi.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8ccc578..7620163 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -32,24 +32,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST(1 << 9)
-#define SPICR_MASTER_INHIBIT   (1 << 8)
-#define SPICR_MANUAL_SS(1 << 7)
-#define SPICR_RXFIFO_RESEST(1 << 6)
-#define SPICR_TXFIFO_RESEST(1 << 5)
-#define SPICR_CPHA (1 << 4)
-#define SPICR_CPOL (1 << 3)
-#define SPICR_MASTER_MODE  (1 << 2)
-#define SPICR_SPE  (1 << 1)
-#define SPICR_LOOP (1 << 0)
+#define SPICR_LSB_FIRSTBIT(9)
+#define SPICR_MASTER_INHIBIT   BIT(8)
+#define SPICR_MANUAL_SSBIT(7)
+#define SPICR_RXFIFO_RESESTBIT(6)
+#define SPICR_TXFIFO_RESESTBIT(5)
+#define SPICR_CPHA BIT(4)
+#define SPICR_CPOL BIT(3)
+#define SPICR_MASTER_MODE  BIT(2)
+#define SPICR_SPE  BIT(1)
+#define SPICR_LOOP BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT(1 << 5)
-#define SPISR_MODF (1 << 4)
-#define SPISR_TX_FULL  (1 << 3)
-#define SPISR_TX_EMPTY (1 << 2)
-#define SPISR_RX_FULL  (1 << 1)
-#define SPISR_RX_EMPTY (1 << 0)
+#define SPISR_SLAVE_MODE_SELECTBIT(5)
+#define SPISR_MODF BIT(4)
+#define SPISR_TX_FULL  BIT(3)
+#define SPISR_TX_EMPTY BIT(2)
+#define SPISR_RX_FULL  BIT(1)
+#define SPISR_RX_EMPTY BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK   (0xff << 0)
-- 
1.9.1

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[U-Boot] [PATCH v4 17/24] spi: atmel_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in atmel_spi

Cc: Bo Shen 
Signed-off-by: Jagan Teki 
---
 drivers/spi/atmel_spi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 5b892d2..76b8556 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT   BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX0xff
+#define ATMEL_SPI_CSRx_SCBR_MAXGENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)   ((x) << 24)
 
-- 
1.9.1

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[U-Boot] [PATCH v4 20/24] spi: fsl_qspi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in fsl_qspi

Cc: York Sun 
Cc: Haikun Wang 
Signed-off-by: Jagan Teki 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e1a0ec9..10733df 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   0x00ff
+#define OFFSET_BITS_MASK   GENMASK(24, 0)
 
 #define FLASH_STATUS_WEL   0x02
 
-- 
1.9.1

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[U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro in mxs_spi

Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 drivers/spi/mxs_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 627644b..459c603 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -23,7 +23,7 @@
 
 #defineMXS_SPI_MAX_TIMEOUT 100
 #defineMXS_SPI_PORT_OFFSET 0x2000
-#define MXS_SSP_CHIPSELECT_MASK0x0030
+#define MXS_SSP_CHIPSELECT_MASKGENMASK(21, 20)
 #define MXS_SSP_CHIPSELECT_SHIFT   20
 
 #define MXSSSP_SMALL_TRANSFER  512
-- 
1.9.1

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[U-Boot] [PATCH v4 15/24] spi: ti_qspi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro in ti_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Tom Rini 
Cc: Vignesh R 
Signed-off-by: Jagan Teki 
---
 drivers/spi/ti_qspi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index bd63db8..ecd9d78 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -20,13 +20,13 @@
 #define QSPI_TIMEOUT200
 #define QSPI_FCLK   19200
 /* clock control */
-#define QSPI_CLK_EN (1 << 31)
+#define QSPI_CLK_EN BIT(31)
 #define QSPI_CLK_DIV_MAX0x
 /* command */
 #define QSPI_EN_CS(n)   (n << 28)
 #define QSPI_WLEN(n)((n-1) << 19)
-#define QSPI_3_PIN  (1 << 18)
-#define QSPI_RD_SNGL(1 << 16)
+#define QSPI_3_PIN  BIT(18)
+#define QSPI_RD_SNGLBIT(16)
 #define QSPI_WR_SNGL(2 << 16)
 #define QSPI_INVAL  (4 << 16)
 #define QSPI_RD_QUAD(7 << 16)
@@ -36,8 +36,8 @@
 #define QSPI_CSPOL(n)   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)   (1 << (n*8))
 /* status */
-#define QSPI_WC (1 << 1)
-#define QSPI_BUSY   (1 << 0)
+#define QSPI_WC BIT(1)
+#define QSPI_BUSY   BIT(0)
 #define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE  QSPI_WC
 #define MM_SWITCH   0x01
-- 
1.9.1

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Re: [U-Boot] [U-Boot,4/7] omap5: omap_die_id support

[Tom Rini]

On Thu, Aug 27, 2015 at 07:37:11PM +0200, Paul Kocialkowski wrote:

> This introduces omap5 support for omap_die_id, which matches the common
> omap_die_id definition. It replaces board-specific code to grab the die id 
> bits.
> 
> Signed-off-by: Paul Kocialkowski 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, U-BOOT] ARM Fix pandaboard es and a4 revision ID

[Tom Rini]

On Tue, Aug 25, 2015 at 08:55:30PM -0400, dbat...@dcbcyber.com wrote:

> board_name environment variable was not getting set correctly for Pandaboard 
> A4 and ES
> 
> Signed-off-by: David Batzle 
> CC: Albert Aribaud ; Tom Rini ; 
> Peter Robinson 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,2/7] omap3: omap_die_id support

[Tom Rini]

On Thu, Aug 27, 2015 at 07:37:09PM +0200, Paul Kocialkowski wrote:

> This replaces the previous get_dieid definition with omap_die_id, that matches
> the common omap_die_id definition.
> 
> Signed-off-by: Paul Kocialkowski 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 1/7] omap-common: Common omap_die_id definition

[Tom Rini]

On Thu, Aug 27, 2015 at 07:37:08PM +0200, Paul Kocialkowski wrote:

> This introduces a common definition for omap_die_id, that aims at providing a
> common interface for accessing omap platform's die id bits.
> 
> Signed-off-by: Paul Kocialkowski 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 4/6] drivers: net: cpsw: convert driver to adopt device driver model

[Tom Rini]

On Mon, Sep 07, 2015 at 02:22:21PM +0530, Mugunthan V N wrote:

> adopt cpsw driver to device driver model
> 
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 6/6] defconfig: am335x: gp_evm: enable ethernet driver model

[Tom Rini]

On Mon, Sep 07, 2015 at 02:22:23PM +0530, Mugunthan V N wrote:

> enable ethernet driver model for am335x gp evm as cpsw supports
> driver model
> 
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 5/6] defconfig: am335x: bbb: enable ethernet driver model

[Tom Rini]

On Mon, Sep 07, 2015 at 02:22:22PM +0530, Mugunthan V N wrote:

> enable ethernet driver model for am335x beagle bone black as cpsw
> supports driver model
> 
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, V3, 2/4] remoteproc: Introduce a sandbox dummy driver

[Tom Rini]

On Thu, Sep 17, 2015 at 03:42:40PM -0500, Nishanth Menon wrote:

> Introduce a dummy driver for sandbox that allows us to verify basic
> functionality. This is not meant to do anything functional - but is
> more or less meant as a framework plumbing debug helper.
> 
> The sandbox remoteproc driver maintains absolutey no states and is a
> simple driver which just is filled with empty hooks. Idea being to give
> an approximate idea to implement own remoteproc driver using this as a
> template.
> 
> Reviewed-by: Simon Glass 
> Signed-off-by: Nishanth Menon 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, V3, 1/4] drivers: Introduce a simplified remoteproc framework

[Tom Rini]

On Thu, Sep 17, 2015 at 03:42:39PM -0500, Nishanth Menon wrote:

> Many System on Chip(SoC) solutions are complex with multiple processors
> on the same die dedicated to either general purpose of specialized
> functions. Many examples do exist in today's SoCs from various vendors.
> Typical examples are micro controllers such as an ARM M3/M0 doing a
> offload of specific function such as event integration or power
> management or controlling camera etc.
> 
> Traditionally, the responsibility of loading up such a processor with a
> firmware and communication has been with a High Level Operating
> System(HLOS) such as Linux. However, there exists classes of products
> where Linux would need to expect services from such a processor or the
> delay of Linux and operating system being able to load up such a
> firmware is unacceptable.
> 
> To address these needs, we need some minimal capability to load such a
> system and ensure it is started prior to an Operating System(Linux or
> any other) is started up.
> 
> NOTE: This is NOT meant to be a solve-all solution, instead, it tries to
> address certain class of SoCs and products that need such a solution.
> 
> A very simple model is introduced here as part of the initial support
> that supports microcontrollers with internal memory (no MMU, no
> execution from external memory, or specific image format needs). This
> basic framework can then (hopefully) be extensible to other complex SoC
> processor support as need be.
> 
> Reviewed-by: Simon Glass 
> Signed-off-by: Nishanth Menon 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,V3,4/4] test: Add basic tests for remoteproc

[Tom Rini]

On Thu, Sep 17, 2015 at 03:42:42PM -0500, Nishanth Menon wrote:

> Use the sandbox environment for the basic tests.
> 
> Reviewed-by: Simon Glass 
> Tested-by: Simon Glass 
> Signed-off-by: Nishanth Menon 
> Acked-by: Simon Glass 

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Re: [U-Boot] [U-Boot, 10/19] ARM: k2g: update keystone nav rx queue numbers

[Tom Rini]

On Sat, Sep 19, 2015 at 04:26:47PM +0530, Lokesh Vutla wrote:

> From: Vitaly Andrianov 
> 
> update K2G nav rx queue number
> 
> Signed-off-by: Vitaly Andrianov 
> Signed-off-by: Mugunthan V N 
> Signed-off-by: Lokesh Vutla 

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Re: [U-Boot] [U-Boot, 11/19] driver: net: keystone_net: fix phy mode configuration

[Tom Rini]

On Sat, Sep 19, 2015 at 04:26:48PM +0530, Lokesh Vutla wrote:

> From: Mugunthan V N 
> 
> Phy mode is a board property and it can be different between
> multiple board and ports, so it should not be hardcoded in
> driver to one specific mode. So adding a field in eth_priv_t
> structure to pass phy mode to driver.
> 
> Signed-off-by: Mugunthan V N 
> Signed-off-by: Lokesh Vutla 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,09/19] ARM: k2g: Correct base addresses

[Tom Rini]

On Sat, Sep 19, 2015 at 04:26:46PM +0530, Lokesh Vutla wrote:

> From: Vitaly Andrianov 
> 
> Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
> and MSMC segments.
> 
> Signed-off-by: Vitaly Andrianov 
> Signed-off-by: Lokesh Vutla 

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Re: [U-Boot] [U-Boot,12/19] dma: keystone_nav: Fix linkram size

[Tom Rini]

On Sat, Sep 19, 2015 at 04:26:49PM +0530, Lokesh Vutla wrote:

> From: Vitaly Andrianov 
> 
> Fix Linkram size.
> 
> Signed-off-by: Vitaly Andrianov 
> Signed-off-by: Mugunthan V N 
> Signed-off-by: Lokesh Vutla 

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: AM335x: mux: change mmc0 cd pinmux from mmc0_sdcd to gpio

[Tom Rini]

On Tue, Oct 13, 2015 at 02:02:29PM +0530, Mugunthan V N wrote:

> Currently omap_hsmmc driver doesn't use sdcd pin to detect
> whether the card is present or not. Instead the same pin is used
> as GPIO to detect card presence. So change the pin mux mode from
> mmc0_sdcd to gpio0_6.
> 
> Signed-off-by: Mugunthan V N 
> Reviewed-by: Tom Rini 

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Re: [U-Boot] [RFC PATCH] ARM: Update phys_addr_t depending on CONFIG_PHYS_64BIT

[Tom Rini]

On Thu, Oct 22, 2015 at 07:59:37PM +0530, Lokesh Vutla wrote:

> Introduce CONFIG_PHYS_64BIT on ARM to deal with 32 bit ARM platforms
> with large physical addresses.
> This is inspired from commit e99ccb488181d0
> ("Introduce phys_size_t and move phys_addr_t into asm/types.h") done on
> powerpc.
> 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v4 01/24] spi: zynq_[q]spi: Use BIT macro

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:01AM +0530, Jagan Teki wrote:

> Used BIT macro on zynq_spi.c and zynq_qspi.c
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2  31
> 
> Cc: Siva Durga Prasad Paladugu 
> Cc: Michal Simek 
> Signed-off-by: Jagan Teki 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v4 19/24] spi: designware_spi: Use GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:19AM +0530, Jagan Teki wrote:

> Replace numeric mask hexcodes with GENMASK macro in designware_spi
> 
> Cc: Stefan Roese 
> Cc: Marek Vasut 
> Signed-off-by: Jagan Teki 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[Tom Rini]

On Fri, Oct 23, 2015 at 02:20:00AM +0530, Jagan Teki wrote:

> This series replaces numerical bit shitfts and mask values
> with BIT and GENMASK macro's
> 
> Changes for v4:
> - Patch split for individual drivers.
> Changes for v3, v2:
> - none

For the GENMASK changes, how did you do the conversion?  I only
reviewed-by the OMAP ones since I pulled out printf and manually
confirmed each change.

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Tom


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Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Tom Rini]

On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki  wrote:
> 
> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct 
> > cadence_spi_platdata *plat,
> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >  #else
> > -   writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> > +   writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
> 
> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> the register directly without any masking operation.

Indeed, with context on the #else side it looks like an old fashioned
"clear everything with magic value" which I suppose might technically be
the bitmask but it's not helping with clarity in this case.

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Tom


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Re: [U-Boot] [PATCH v4 21/24] spi: mxs_spi: Use GENMASK

[Tom Rini]

On Thu, Oct 22, 2015 at 07:08:32PM -0200, Fabio Estevam wrote:
> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki  wrote:
> > Replace numeric mask hexcodes with GENMASK macro in mxs_spi
> >
> > Cc: Marek Vasut 
> > Signed-off-by: Jagan Teki 
> > ---
> >  drivers/spi/mxs_spi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> > index 627644b..459c603 100644
> > --- a/drivers/spi/mxs_spi.c
> > +++ b/drivers/spi/mxs_spi.c
> > @@ -23,7 +23,7 @@
> >
> >  #defineMXS_SPI_MAX_TIMEOUT 100
> >  #defineMXS_SPI_PORT_OFFSET 0x2000
> > -#define MXS_SSP_CHIPSELECT_MASK0x0030
> > +#define MXS_SSP_CHIPSELECT_MASKGENMASK(21, 20)
> 
> Does this really improve the code?
> 
> Personally I prefer the original code as I don't need to go and look
> at the definition of the GENMASK() macro.

Fair point.  This is a kernel helper macro but it's "new" and still
gaining traction.  I personally do find GENMASK(hi, lo) and BIT(x) more
readable.  Others don't.  That's fine.  The question I have here is, who
is spending the most time in these drivers?

-- 
Tom


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