Re: [U-Boot] [PATCH] pci: fix address range check in __pci_hose_phys_to_bus()

[Ivan Mercier]

Well done Marcel!
I didn't have much more time to investigate on it.
OK with nvidia jetson TK1 with i210 AND RTL8169.


On 18/11/2015 15:19, Bin Meng wrote:

On Wed, Nov 18, 2015 at 10:05 PM, Marcel Ziswiler
 wrote:

The address range check may overflow if the memory region is located at
the top of the 32-bit address space. This can e.g. be seen on TK1 if
using the E1000 gigabit Ethernet driver where start and size are both
0x8000 leading to the following messages:

Apalis TK1 # tftpboot $loadaddr test_file
Using e1000#0 device
TFTP from server 192.168.10.1; our IP address is 192.168.10.2
Filename 'test_file'.
Load address: 0x80408000
Loading: pci_hose_phys_to_bus: invalid physical address

This patch fixes this by changing the order of the addition vs.
subtraction in the range check just like already done in
__pci_hose_bus_to_phys().

Reported-by: Ivan Mercier 
Signed-off-by: Marcel Ziswiler 
---

  drivers/pci/pci_common.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index a64792f..2a14902 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -268,7 +268,7 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
 bus_addr = phys_addr - res->phys_start + res->bus_start;

 if (bus_addr >= res->bus_start &&
-   bus_addr < res->bus_start + res->size) {
+   (bus_addr - res->bus_start) < res->size) {
 *ba = bus_addr;
 return 0;
 }
--

Reviewed-by: Bin Meng 



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Re: [U-Boot] [PATCH v1] armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

[York Sun]

On 11/16/2015 09:29 AM, York Sun wrote:
> 
> 
> On 11/16/2015 09:21 AM, Joakim Tjernlund wrote:
>> On Mon, 2015-11-16 at 09:03 -0800, York Sun wrote:
>>>
>>> On 11/12/2015 02:54 PM, Joakim Tjernlund wrote:
 On Thu, 2015-11-12 at 14:20 -0800, York Sun wrote:
> Introduce a new function to calculate reserved memory to replace macro
> CONFIG_SYS_MEM_TOP_HIDE for more flexibility. Legacy use of this macro is
> still supported. MC and debug server are not board-specific. Move the
> reservation function to SoC file. Reduce debug server memory by 2MB to
> make room for secure memory.

 I would make sure "pram" is first to reserve memory, is it?

>>>
>>> (previous reply wasn't caught by patchwork, adding more info)
>>>
>>> Yes, pram is used to reserve small memory from the top of u-boot memory, not
>>> necessarily the top of total memory. For example, a 32-bit u-boot with large
>>> memory. This patch deals with carving memory from the end of memory, which 
>>> could
>>> be far away from u-boot top. Even in system with small memory, it is still
>>> correct, because pram reserves memory from the _top_ of u-boot and this
>>> mechanism reserved memory is hidden from u-boot.
>>
>> And I realize I am mixing pram and CONFIG_SYS_MEM_TOP_HIDE. Your patch
>> reserves memory before CONFIG_SYS_MEM_TOP_HIDE which might be confusing
>> for some. Why do you need another( then CONFIG_SYS_MEM_TOP_HIDE) method to 
>> reserve memory?
>>
> 
> I am not going to discover the legacy reason to have CONFIG_SYS_MEM_TOP_HIDE.
> For my current use on ARMv8, we have management complex (aks MC) and debug
> server. They both require a big chunk of private memory (even after OS boots
> up). I am taking advantage of existing CONFIG_SYS_MEM_TOP_HIDE to reserve this
> memory without fragment memory and without the need to create reserved memory
> node in device tree.
> 
> With that in place, I think it makes sense to do the same way for reserving
> secure memory.
> 

Jocke,

Did I clear your questions? Let me know if you have further comments.

York



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Re: [U-Boot] [PATCH v7 15/23] rockchip: mmc: use non-removable property to distinguish emmc and sdcard register

[Simon Glass]

On 17 November 2015 at 18:37, Lin Huang  wrote:
> emmc and sdcard have different register address, use non-removeable property
> to distinguish them.
>
> Signed-off-by: Lin Huang 
> ---
> Changes in v1: None
> Changes in v2: None
> Changes in v3: None
> Changes in v4: None
> Changes in v5: None
> Changes in v6: None
> Changes in v7:
> - Adviced by Simon:
> - use fdtdec_get_bool() to get property
>
>  drivers/mmc/rockchip_dw_mmc.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index f11c8e0..dfe20f9 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -50,8 +50,9 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice 
> *dev)
> host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
> host->priv = dev;
>
> -   /* TODO(s...@chromium.org): Remove the need for this hack */
> -   host->dev_index = (ulong)host->ioaddr == 0xff0f ? 0 : 1;
> +   /* use non-removeable as sdcard and emmc as judgement */
> +   if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
> +   host->dev_index = 1;
>
> return 0;
>  }
> --
> 1.9.1
>

Acked-by: Simon Glass 
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[U-Boot] [PATCH v2] usb: add support for generic EHCI devices

[Alexey Brodkin]

This driver is meant to be used with any EHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.

Signed-off-by: Alexey Brodkin 
Reviewed-by: Simon Glass 
Reviewed-by: Marek Vasut 
Cc: Stephen Warren 
---

Changes compared to v1:
 * Updated commit message with removal of Synopsys board mention
 * Cleaned-up ehci_usb_remove()

 drivers/usb/host/Kconfig|  7 ++
 drivers/usb/host/Makefile   |  1 +
 drivers/usb/host/ehci-generic.c | 51 +
 3 files changed, 59 insertions(+)
 create mode 100644 drivers/usb/host/ehci-generic.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2a2bffe..a500578 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -73,4 +73,11 @@ config USB_EHCI_UNIPHIER
---help---
  Enables support for the on-chip EHCI controller on UniPhier SoCs.
 
+config USB_EHCI_GENERIC
+   bool "Support for generic EHCI USB controller"
+   depends on OF_CONTROL
+   default y
+   ---help---
+ Enables support for generic EHCI controller.
+
 endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index f70f38c..b9b4471 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -32,6 +32,7 @@ else
 obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
 obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
+obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
 obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
 obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
new file mode 100644
index 000..f0e2b85
--- /dev/null
+++ b/drivers/usb/host/ehci-generic.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2015 Alexey Brodkin 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include "ehci.h"
+
+/*
+ * Even though here we don't explicitly use "struct ehci_ctrl"
+ * ehci_register() expects it to be the first thing that resides in
+ * device's private data.
+ */
+struct generic_ehci {
+   struct ehci_ctrl ctrl;
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+   struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
+   struct ehci_hcor *hcor;
+
+   hcor = (struct ehci_hcor *)((uint32_t)hccr +
+   HC_LENGTH(ehci_readl(>cr_capbase)));
+
+   return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+   return ehci_deregister(dev);
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+   { .compatible = "generic-ehci" },
+   { }
+};
+
+U_BOOT_DRIVER(usb_ehci) = {
+   .name   = "ehci_generic",
+   .id = UCLASS_USB,
+   .of_match = ehci_usb_ids,
+   .probe = ehci_usb_probe,
+   .remove = ehci_usb_remove,
+   .ops= _usb_ops,
+   .priv_auto_alloc_size = sizeof(struct generic_ehci),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
-- 
2.5.0

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Re: [U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Mugunthan V N]

Jagan

On Tuesday 17 November 2015 11:51 AM, Jagan Teki wrote:
>> +   void *ctrl_mod_mmap;
> Looks like this patch manages to prepare for non-dm addition by using
> dm functions is it? and other than that some new things got added like
> RD_DUAL or ctrl_mod_mmap, please add them separately add do the dm
> conversion only on existing code.
> 

ctrl_mod_map is used in non DM mode as well. Earlier there was a define,
I changed it to a variable while preparing driver for DM conversion.

Regards
Mugunthan V N
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Re: [U-Boot] [PATCH v2 00/26] usb: Drop requirement for USB unbinding, add tests

[Simon Glass]

Hi,

On 9 November 2015 at 09:54, Simon Glass  wrote:
>
> Hi Hans,
>
> On 9 November 2015 at 00:14, Hans de Goede  wrote:
> > Hi Simon,
> >
> > On 09-11-15 07:47, Simon Glass wrote:
> >>
> >> There was quite a bit of discussion about the change that required the
> >> unbinding of USB devices for the subsystem to function correctly. E.g.
> >>
> >> https://patchwork.ozlabs.org/patch/485637/
> >>
> >> The key issue is the usb_get_dev_index() function which is not a good API
> >> for driver model. We can drop use of this function once everything is
> >> converted to driver model. Then I believe the problems raised by Hans go
> >> away. For now we can add a deprecation warning on the function.
> >>
> >> It is easy to convert USB keyboards to driver model. This series includes
> >> a patch for that.
> >>
> >> This series also includes reverts for the three commits which as discussed
> >> I would like to drop. U-Boot should be able to run normally and exit
> >> without
> >> unbinding anything.
> >>
> >> Also included are some tests for the 'usb tree' command. To make this
> >> work,
> >> console recording is implemented.
> >>
> >> Finally, a USB keyboard driver is provided for sandbox, so that this part
> >> of the stack can be tested automatically.
> >>
> >> Changes in v2:
> >> - Add various patches to support USB keyboards and additional tests
> >
> >
> > Do you have a git branch with this patch-set somewhere for me to test ?
>
> Yes I always upload branches before sending them. This one is
> u-boot-dm/usb-working. I should get better at including the branch
> name in the cover letter.
>
> I still need to write a test for having two device types which switch
> order. Now that I have a USB keyboard emulation I should be able to do
> that. I'll then see the impact on 'usb tree'. So you may want to
> review the test code only for now.
>
> Regards,
> Simon

Are there any more comments on this series please? I plan to bring it
in soon since we are already at RC1.

Regards,
Simon
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[U-Boot] [PATCH] fs: ext4: Prevent infinite loop in ext4fs_iterate_dir

[Thomas Fitzsimmons]

If the ext3 journal gets out of sync with what is written on disk, for
example because of an unexpected power cut, ext4fs_read_file can
return an all-zero directory entry.  In that case, ext4fs_iterate_dir
would infinite loop.

This patch detects when a directory entry's direntlen member is 0 and
returns a failure status, which breaks out of the infinite loop.  As a
result, U-Boot will not find files that may subsequently be recovered
when the journal is replayed.

This is better behaviour than hanging in an infinite loop, but as a
further improvement maybe U-Boot could interpret the ext3 journal and
actually find the unsynced entries.

Signed-off-by: Thomas Fitzsimmons 
---
 fs/ext4/ext4_common.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 727a2f7..e73223a 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -1920,6 +1920,11 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char 
*name,
if (status < 0)
return 0;
 
+   if (dirent.direntlen == 0) {
+   printf("Failed to iterate over directory %s\n", name);
+   return 0;
+   }
+
if (dirent.namelen != 0) {
char filename[dirent.namelen + 1];
struct ext2fs_node *fdiro;
-- 
1.8.3.1

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[U-Boot] [PATCH v6 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables

[York Sun]

DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun 

fixup
---

Changes in v6:
  Move cmd_bdinfo change to 1st patch in this set
  Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE

Changes in v5:
  Put ifdef where gd->secure_ram is used

Changes in v4:
  Drop RFC from patch prefix
  Drop excessive mmu table for secure ram for early MMU
  Update commit message accordingly
  Mark QBMan cacheable portal memory non-secure

Changes in v3:
  Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE
  Sanity check gd->secure_ram before using
  Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
  Include ls1043ardb
  Modified commit message.

Changes in v2:
  Move gd->arch.secure_ram to gd->secure_ram.
  Change the calculation of gd->secure_ram accordingly.
  Chnage commit message slightly accordingly.

Changes in v1: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  111 +++--
 arch/arm/include/asm/arch-fsl-layerscape/config.h |6 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h|   14 ++-
 board/freescale/ls1043ardb/ddr.c  |4 +
 board/freescale/ls2085a/ddr.c |   15 +++
 board/freescale/ls2085aqds/ddr.c  |   15 +++
 board/freescale/ls2085ardb/ddr.c  |   15 +++
 7 files changed, 165 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9d1c70f..501feb3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -206,11 +206,65 @@ static inline void early_mmu_setup(void)
set_sctlr(get_sctlr() | CR_M);
 }
 
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+/*
+ * Called from final mmu setup. The phys_addr is new, non-existing
+ * address. A new sub table is created @level2_table_secure to cover
+ * size of CONFIG_SYS_MEM_RESERVE_SECURE memory.
+ */
+static inline int final_secure_ddr(u64 *level0_table,
+  u64 *level2_table_secure,
+  phys_addr_t phys_addr)
+{
+   int ret = -EINVAL;
+   struct table_info table = {};
+   struct sys_mmu_table ddr_entry = {
+   0, 0, BLOCK_SIZE_L1, MT_NORMAL,
+   PMD_SECT_OUTER_SHARE | PMD_SECT_NS
+   };
+   u64 index;
+
+   /* Need to create a new table */
+   ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
+   ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
+   ret = find_table(_entry, , level0_table);
+   if (ret)
+   return ret;
+   index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1;
+   set_pgtable_table(table.ptr, index, level2_table_secure);
+   table.ptr = level2_table_secure;
+   table.table_base = ddr_entry.virt_addr;
+   table.entry_size = BLOCK_SIZE_L2;
+   ret = set_block_entry(_entry, );
+   if (ret) {
+   printf("MMU error: could not fill non-secure ddr block 
entries\n");
+   return ret;
+   }
+   ddr_entry.virt_addr = phys_addr;
+   ddr_entry.phys_addr = phys_addr;
+   ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
+   ddr_entry.attribute = PMD_SECT_OUTER_SHARE;
+   ret = find_table(_entry, , level0_table);
+   if (ret) {
+   printf("MMU error: could not find secure ddr table\n");
+   return ret;
+   }
+   ret = set_block_entry(_entry, );
+   if (ret)
+   printf("MMU error: could not set secure ddr block entry\n");
+
+   return ret;
+}
+#endif
+
 /*
  * The final tables look similar to early tables, but different in detail.
  * These tables are in DRAM. Sub tables are added to enable cache for
  * QBMan and OCRAM.
  *
+ * Put the MMU table in secure memory if gd->secure_ram is valid.
+ * OCRAM will be not used for this purpose so gd->secure_ram can't be 0.
+ *
  * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
  * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
  * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
@@ -224,17 +278,38 @@ static inline void early_mmu_setup(void)
 static inline void final_mmu_setup(void)
 {
unsigned int el, i;
-   u64 *level0_table = (u64 

[U-Boot] [PATCH v6 1/2] Reserve secure memory

[York Sun]

Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.

"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.

Signed-off-by: York Sun 

---

Changes in v6:
  Move cmd_bdinfo change into this patch
  Move flag macros and comments of secure_ram into this patch

Changes in v5: None
Changes in v4: None
Changes in v3:
  Put ifdef around secure_ram
  Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2

Changes in v2:
  Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism

Changes in v1:
  Initial patch.
  Depends on http://patchwork.ozlabs.org/patch/540248/

 README|8 
 common/board_f.c  |9 +
 common/cmd_bdinfo.c   |6 ++
 include/asm-generic/global_data.h |   14 ++
 4 files changed, 37 insertions(+)

diff --git a/README b/README
index ef8d437..61cbc82 100644
--- a/README
+++ b/README
@@ -3881,6 +3881,14 @@ Configuration Settings:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
 
+- CONFIG_SYS_MEM_RESERVE_SECURE
+   If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+   is substracted from total RAM and won't be reported to OS.
+   This memory can be used as secure memory. A variable
+   gd->secure_ram is used to track the location. In systems
+   the RAM base is not zero, or RAM is divided into banks,
+   this variable needs to be recalcuated to get the address.
+
 - CONFIG_SYS_MEM_TOP_HIDE (PPC only):
If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config 
header,
this specified memory area will get subtracted from the top
diff --git a/common/board_f.c b/common/board_f.c
index 725eb18..8061105 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -323,6 +323,15 @@ static int setup_dest_addr(void)
 * Ram is setup, size stored in gd !!
 */
debug("Ram size: %08lX\n", (ulong)gd->ram_size);
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   /* Reserve memory for secure MMU tables, and/or security monitor */
+   gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+   /*
+* Record secure memory location. Need recalcuate if memory splits
+* into banks, or the ram base is not zero.
+*/
+   gd->secure_ram = gd->ram_size;
+#endif
 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
/*
 * Subtract specified amount of memory to hide so that it won't
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index adda55a..deed6d8 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -382,6 +382,12 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
print_num("-> size",bd->bi_dram[i].size);
}
 
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+   if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) {
+   print_num("Secure ram",
+ gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
+   }
+#endif
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
print_eths();
 #endif
diff --git a/include/asm-generic/global_data.h 
b/include/asm-generic/global_data.h
index d0383f3..fc10528 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -58,6 +58,20 @@ typedef struct global_data {
 
unsigned long relocaddr;/* Start address of U-Boot in RAM */
phys_size_t ram_size;   /* RAM size */
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#define MEM_RESERVE_SECURE_SECURED 0x1
+#define MEM_RESERVE_SECURE_MAINTAINED  0x2
+#define MEM_RESERVE_SECURE_ADDR_MASK   (~0x3)
+   /*
+* Secure memory addr
+* This variable needs maintenance if the RAM base is not zero,
+* or if RAM splits into non-consecutive banks. It also has a
+* flag indicating the secure memory is marked as secure by MMU.
+* Flags used: 0x1 secured
+* 0x2 maintained
+*/
+   phys_addr_t secure_ram;
+#endif
unsigned long mon_len;  /* monitor len */
unsigned long irq_sp;   /* irq stack pointer */
unsigned long start_addr_sp;/* start_addr_stackpointer */
-- 
1.7.9.5

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[U-Boot] [PATCH v6 0/2] Make most DDR non-secure in MMU while keep a small block secure

[York Sun]

This set is to change MMU tables so DDR is in non-secure mode that
non-secure master such as SDHC DMA can access the data. To mix
secure and non-secure MMU entries, the MMU tables themselves have
to be in secure memory. A small portion memory is reserved at the
end of DDR (before debug server and MC) to host secure application
and the MMU tables.

This is different from existing armv7 secure_ram_addr() solution.
U-boot can run in the middle of memory if the memory is large.
Having security memory at the very end simplifies MMU setup.

Tested on LS2085AQDS with a known non-secure master test.


Changes in v6:
  Move flag macros and comments of secure_ram into 1st path in this set
  Move cmd_bdinfo change to 1st patch in this set
  Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE

Changes in v5:
  Put ifdef where gd->secure_ram is used

Changes in v4:
  Drop RFC from patch prefix
  Drop excessive mmu table for secure ram for early MMU
  Update commit message accordingly
  Mark QBMan cacheable portal memory non-secure

Changes in v3:
  Put ifdef around secure_ram
  Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2
  Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE
  Sanity check gd->secure_ram before using
  Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
  Include ls1043ardb
  Modified commit message.

Changes in v2:
  Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism
  Move gd->arch.secure_ram to gd->secure_ram.
  Change the calculation of gd->secure_ram accordingly.
  Chnage commit message slightly accordingly.

Changes in v1:
  Initial patch.
  Depends on http://patchwork.ozlabs.org/patch/540248/

York Sun (2):
  Reserve secure memory
  armv8: fsl-layerscape: Make DDR non secure in MMU tables

 README|8 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  111 +++--
 arch/arm/include/asm/arch-fsl-layerscape/config.h |6 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h|   14 ++-
 board/freescale/ls1043ardb/ddr.c  |4 +
 board/freescale/ls2085a/ddr.c |   15 +++
 board/freescale/ls2085aqds/ddr.c  |   15 +++
 board/freescale/ls2085ardb/ddr.c  |   15 +++
 common/board_f.c  |9 ++
 common/cmd_bdinfo.c   |6 ++
 include/asm-generic/global_data.h |   14 +++
 11 files changed, 202 insertions(+), 15 deletions(-)

-- 
1.7.9.5

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[U-Boot] [PATCH v2] armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server

[York Sun]

MC and debug server are not board-specific. Instead of reserving
memory in each board file, a weak function is introduced in board_f.c
to replace macro CONFIG_SYS_MEM_TOP_HIDE for more flexibility.
Legacy use of this macro is still supported. Move the reservation
calculation to SoC file. Reduce debug server memory by 2MB to
make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun 

---

Changes in v2:
  Revise commit message.

 README  |6 +++---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c |   18 ++
 board/freescale/ls2085a/ls2085a.c   |   17 -
 board/freescale/ls2085aqds/ls2085aqds.c |   17 -
 board/freescale/ls2085ardb/ls2085ardb.c |   17 -
 common/board_f.c|   14 +++---
 include/configs/ls2085a_common.h|5 ++---
 7 files changed, 34 insertions(+), 60 deletions(-)

diff --git a/README b/README
index 61cbc82..390ee10 100644
--- a/README
+++ b/README
@@ -3889,7 +3889,7 @@ Configuration Settings:
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
 
-- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
+- CONFIG_SYS_MEM_TOP_HIDE:
If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config 
header,
this specified memory area will get subtracted from the top
(end) of RAM and won't get "touched" at all by U-Boot. By
@@ -5068,8 +5068,8 @@ This firmware often needs to be loaded during U-Boot 
booting.
 - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
Define minimum DDR size required for debug server image
 
-- CONFIG_SYS_MEM_TOP_HIDE_MIN
-   Define minimum DDR size to be hided from top of the DDR memory
+- CONFIG_SYS_MC_RESERV_MEM_ALIGN
+   Define alignment of reserved memory MC requires
 
 Reproducible builds
 ---
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 501feb3..01e8f52 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -628,3 +628,21 @@ void reset_cpu(ulong addr)
val |= 0x02;
scfg_out32(rstcr, val);
 }
+
+unsigned long board_reserve_ram_top(unsigned long ram_size)
+{
+   unsigned long ram_top = ram_size;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+   ram_top -= debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+   ram_top -= mc_get_dram_block_size();
+   ram_top &= ~(CONFIG_SYS_MC_RESERV_MEM_ALIGN - 1);
+#endif
+
+   return ram_size - ram_top;
+}
diff --git a/board/freescale/ls2085a/ls2085a.c 
b/board/freescale/ls2085a/ls2085a.c
index 27481e2..6f4c3d4 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -66,23 +66,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-   unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-   dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-   dram_to_hide += mc_get_dram_block_size();
-#endif
-
-   return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
 int board_eth_init(bd_t *bis)
 {
int error = 0;
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c 
b/board/freescale/ls2085aqds/ls2085aqds.c
index b02d6e8..8898cc3 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -251,23 +251,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-   unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-   dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-   dram_to_hide += mc_get_dram_block_size();
-#endif
-
-   return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c 
b/board/freescale/ls2085ardb/ls2085ardb.c
index 18953b8..efddf74 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -217,23 +217,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-   unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef 

Re: [U-Boot] mxs: HAB experiments

[Marek Vasut]

On Wednesday, November 18, 2015 at 10:57:13 AM, Florian Achleitner wrote:
> Hi,
> 
> On Wednesday, November 18, 2015 09:55:12 AM Marek Vasut wrote:
> > On Tuesday, November 17, 2015 at 02:16:06 PM, Florian Achleitner wrote:
> > > Hi Marek,
> > 
> > Hi,
> > 
> > > thanks for you contributions to support mxs HAB v4 in u-boot. I'm
> > > currently
> > > experimenting with HAB on my imx28 board. I think I put everything
> > > together
> > > quite well.
> > > 
> > > 
> > > 
> > > But examining the HAB event log I see two successful authentications
> > > for the u-boot.bin and the IVT followed by a FAILURE with "unsupported
> > > command" in the "CSF Context".  It is the same for both the SPL and
> > > the main u-boot. Did you see something similar? It suggests a wrong
> > > command in the CSF file, but I think there is not a lot that can be
> > > wrong in the CSF input file for the cst tool. But probably the cst
> > > output is different between versions? I use version
> > > BLN_CST_MAIN_02.03.00.
> > > 
> > > 
> > > 
> > > I use u-boot's mkimage, which can generate a signed boot stream,
> > > together with your hand-crafted IVT generator in the Makefile.
> > 
> > Can you share your CSF files (make sure to blank out the private
> > material) ?
> 
> The CSF follows. It is the same for the spl and the main u-boot.
> 
> Anyways, I currently suspect the cst tool in its current version (2.3.1) to
> produce binaries that are incompatible with the mx28 HAB Rom. However, I
> couldn't find an older version of the cst yet, so I can't try it at the
> moment.
> 
> Thanks!
> Florian
> 
> [Header]
> Version = 4.0
> Hash Algorithm = sha256
> Engine Configuration = 0
> Certificate Format = X509
> Signature Format = CMS
> Engine = DCP

I use "Engine = ANY" here, not sure if it matters.

> 
> [Install SRK]
> File = "$SRK_1_2_table.bin"
> Source index = 0
> 
> [Install CSFK]
> File = "$CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
> 
> [Authenticate CSF]
> 
> [Install Key]
> Verification index = 0
> Target index = 2
> File = "$IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
> 
> [Authenticate Data]
> Verification index = 2

Here I use "Engine = DCP" (missing in your example)

I am using BLN_CST_MAIN_02.00.00 btw.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v0 1/5] pci: mvebu: Fix Armada 38x support

[Dirk Eibach]

Hi Anton,

2015-11-17 13:55 GMT+01:00 Anton Schubert :
> Hi Dirk,
>
> 2015-10-28 16:44 GMT+01:00 :
>>
>> From: Dirk Eibach 
>>
>> @@ -344,7 +345,6 @@ void pci_init_board(void)
>>
>> /* Don't read at all from pci registers if port power is
>> down */
>> if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0)
>> {
>> -   i += 3;
>> debug("%s: skipping port %d\n", __func__,
>> pcie->port);
>> continue;
>> }
>
>
> Is there a specific reason why you removed this line or was it just by
> mistake? Because I think doing so would break Armada XP in certain Serdes
> Configurations, as it doesn't like it's PCI registers being read if the port
> is off.

I assume the idea is to go to the next port if the current port is
disabled. But adding 3 to the index does not seem to be the right
thing to do, since Armada XP has ports with 4 lanes, but also with
ports with one lane.
I assume that iterating over all lanes would not be a problem, but by
mistake the pcie->lane == 0  was left in the condition. So this should
perform better:

/* Don't read at all from pci registers if port power is down */
if (SELECT(soc_ctrl, pcie->port) == 0) {
if (pcie->lane == 0)
debug("%s: skipping port %d\n", __func__, pcie->port);
continue;
}

What do you think?

Cheers
Dirk
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[U-Boot] [PATCH v2 1/4] vexpress64: compile Juno PCIe conditionally

[Ryan Harkin]

Only compile in PCIe support if the board really uses it. Provide
a __weak stub for the init function if e.g. FVP is being built.

Signed-off-by: Ryan Harkin 
Acked-by: Linus Walleij 
---
 board/armltd/vexpress64/Makefile | 3 ++-
 board/armltd/vexpress64/pcie.c   | 2 --
 board/armltd/vexpress64/vexpress64.c | 7 +++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
index a35db40..b4391a7 100644
--- a/board/armltd/vexpress64/Makefile
+++ b/board/armltd/vexpress64/Makefile
@@ -5,4 +5,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := vexpress64.o pcie.o
+obj-y  := vexpress64.o
+obj-$(CONFIG_TARGET_VEXPRESS64_JUNO)   += pcie.o
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index 7b999e8..311c450 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -191,7 +191,5 @@ void xr3pci_init(void)
 
 void vexpress64_pcie_init(void)
 {
-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
xr3pci_init();
-#endif
 }
diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index f4e8084..3add099 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -28,6 +28,13 @@ U_BOOT_DEVICE(vexpress_serials) = {
.platdata = _platdata,
 };
 
+/* This function gets replaced by platforms supporting PCIe.
+ * The replacement function, eg. on Juno, initialises the PCIe bus.
+ */
+__weak void vexpress64_pcie_init(void)
+{
+}
+
 int board_init(void)
 {
vexpress64_pcie_init();
-- 
2.1.4

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[U-Boot] [PATCH v2 4/4] vexpress64: store env in flash

[Ryan Harkin]

Add support for storing the environment in CFI NOR flash on Juno and FVP
models.

I also removed some config values that are not used by CFI flash parts.

Juno has 1 flash part with 259 sectors.  The first 255 sectors are
0x4 (256kb) and are followed by 4 sectors of 0x1 (64KB).

FVP models simulate a 64MB NOR flash part at base address 0x0FFC.
This part has 256 x 256kb sectors.  We use the last sector to store the
environment.

To save the NOR flash to a file, the following parameters should be
passed to the model:

-C bp.flashloader1.fname=${FILENAME}
-C bp.flashloader1.fnameWrite=${FILENAME}

Foundation models don't simulate the NOR flash, but having NOR support
in the u-boot binary does not harm:  attempting to write to the NOR will
fail gracefully.

Signed-off-by: Ryan Harkin 
Acked-by: Linus Walleij 
---
 configs/vexpress_aemv8a_dram_defconfig |  1 -
 configs/vexpress_aemv8a_semi_defconfig |  1 -
 include/configs/vexpress_aemv8a.h  | 37 ++
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/configs/vexpress_aemv8a_dram_defconfig 
b/configs/vexpress_aemv8a_dram_defconfig
index e9fc870..a8e4daa 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vexpress_aemv8a_semi_defconfig 
b/configs/vexpress_aemv8a_semi_defconfig
index a082d27..e899b90 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -10,7 +10,6 @@ CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 6734d7e..c767f90 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -276,10 +276,6 @@
 
 #endif
 
-/* Do not preserve environment */
-#define CONFIG_ENV_IS_NOWHERE  1
-#define CONFIG_ENV_SIZE0x1000
-
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE  512 /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
@@ -290,28 +286,35 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_MAXARGS 64  /* max command args */
 
-/* Flash memory is available on the Juno board only */
-#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_FLASH_BASE  0x0800
+/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT  259
+/* Store environment at top of flash in the same location as blank.img */
+/* in the Juno firmware. */
+#define CONFIG_ENV_ADDR0x0BFC
+#define CONFIG_ENV_SECT_SIZE   0x0001
 #else
+#define CONFIG_SYS_FLASH_BASE  0x0C00
+/* 256 x 256KiB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT  256
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR0x0FFC
+#define CONFIG_ENV_SECT_SIZE   0x0004
+#endif
+
 #define CONFIG_CMD_ARMFLASH
 #define CONFIG_SYS_FLASH_CFI   1
 #define CONFIG_FLASH_CFI_DRIVER1
 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CONFIG_SYS_FLASH_BASE  0x0800
-#define CONFIG_SYS_FLASH_SIZE  0x0400 /* 64 MiB */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
 
-/* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT(2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT(2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/* 255 0x4 sectors + first or last sector may have 4 erase regions = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT  259 /* Max sectors */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 #define CONFIG_SYS_FLASH_PROTECTION/* The devices have real protection */
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SIZE  0x0004
+#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_IN_FLASH 1
 
-#endif
 
 #endif /* __VEXPRESS_AEMV8A_H */
-- 
2.1.4

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[U-Boot] [PATCH v2 3/4] vexpress64: remove #error

[Ryan Harkin]

This patch allows vexpress64 targets to be compiled when
CONFIG_SYS_FLASH_CFI is enabled.

I considered using #warning instead of #error, but this just clutters up
the build output and hides real warnings.

Without this patch, you see errors during compilation like this:

include/configs/vexpress_aemv8a.h:42:2: error: #error "Unknown board
variant"
 #error "Unknown board variant"
include/configs/vexpress_aemv8a.h:115:2: error: #error "Unknown board
variant"
 #error "Unknown board variant"
include/configs/vexpress_aemv8a.h:280:2: error: #error "Unknown board
variant"
 #error "Unknown board variant"
make[1]: *** [tools/envcrc.o] Error 1
make: *** [tools] Error 2
In file included from include/config.h:5:0,
 from tools/envcrc.c:19:

Signed-off-by: Ryan Harkin 
Acked-by: Linus Walleij 
---
 include/configs/vexpress_aemv8a.h | 6 --
 1 file changed, 6 deletions(-)

diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 3c9faf4..6734d7e 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -35,8 +35,6 @@
 #elif CONFIG_TARGET_VEXPRESS64_JUNO
 #define CONFIG_SYS_TEXT_BASE   0xe000
 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#else
-#error "Unknown board variant"
 #endif
 
 #define CONFIG_SYS_BOOTM_LEN (64 << 20)  /* Increase max gunzip size */
@@ -108,8 +106,6 @@
 #elif CONFIG_TARGET_VEXPRESS64_JUNO
 #define GICD_BASE  (0x2C01)
 #define GICC_BASE  (0x2C02f000)
-#else
-#error "Unknown board variant"
 #endif
 #endif /* !CONFIG_GICV3 */
 
@@ -278,8 +274,6 @@
 
 #define CONFIG_BOOTDELAY   1
 
-#else
-#error "Unknown board variant"
 #endif
 
 /* Do not preserve environment */
-- 
2.1.4

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Re: [U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"

[Jörg Krause]

Hi Fabio,

On Di, 2015-11-17 at 14:25 -0200, Fabio Estevam wrote:
> This reverts commit 59370f3fcd135089c402c93720a87c688abe600c.
> 
> This commit breaks ethernet on at least mx6 Riotboard and
> mx6sxsabresd boards.
> 
> Reported-by: Catalin Crenguta 
> Signed-off-by: Fabio Estevam 
> ---
>  drivers/net/phy/phy.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index d7364ff..9e68f1d 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -771,13 +771,11 @@ struct phy_device *phy_find_by_mask(struct
> mii_dev *bus, unsigned phy_mask,
>   phy_interface_t interface)
>  {
>   /* Reset the bus */
> - if (bus->reset) {
> + if (bus->reset)
>   bus->reset(bus);
>  
> - /* Wait 15ms to make sure the PHY has come out of
> hard reset */
> - udelay(15000);
> - }
> -
> + /* Wait 15ms to make sure the PHY has come out of hard reset
> */
> + udelay(15000);
>   return get_phy_device_by_mask(bus, phy_mask, interface);
>  }
>  

I think this is not the right thing to do here. It is true that the
AR8035 ethernet chip of the RioTboard needs the clock to be stable for
at least 1ms before RESET can be deasserted. This why it fails, if
there is no MII reset function defined.

I think the right place to handle reset delays is the board_eth_init().
The value of 15ms currently used looks to me like an arbitrary value. I
am not sure where this value is comming from. Some chips need more,
some less time to delay after a reset.

This is snippet of how I do it for a custom i.MX28-EVK-based board:

int board_eth_init(bd_t *bis) {
  cpu_eth_init(bis);
  /* Power-on FEC */
  gpio_direction_output(MX28_PAD_LCD_D21__GPIO_1_21, 0);
  /* Reset FEC PHY */
  gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
  /* Deassert nRST after 25 ms from power-up on (= t_purstd) */
  udelay(25000);
  gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
  fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
}

Best regards
Jörg Krause
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Re: [U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"

[Fabio Estevam]

Hi Stefan,

On Wed, Nov 18, 2015 at 3:54 AM, Stefan Roese  wrote:

> I'm not sure if this revert is the right way to solve this problem.
> Please take a look at my answer a few weeks ago:
>
> https://www.mail-archive.com/u-boot@lists.denx.de/msg191206.html
>
> As mentioned in my mail above, the delay should be added after
> the deassertion of the PHY reset signal. And not here in
> phy_find_by_mask() for all boards.
>
> I just checked the code in mx6sxsabresd.c. Here also the delay is
> missing:
>
> /* Reset AR8031 PHY */
> gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
> udelay(500);
> gpio_set_value(IMX_GPIO_NR(2, 7), 1);
>
> Could you please test with this change:
>
> /* Reset AR8031 PHY */
> gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
> udelay(500);
> gpio_set_value(IMX_GPIO_NR(2, 7), 1);
> +   udelay(1500);
>
> Or even better, check how long the reset needs to be inactive
> before the PHY starts to work.

Sure, I have even tried:

--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -163,8 +163,9 @@ static int setup_fec(void)

/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-   udelay(500);
+   udelay(5);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+   udelay(5);

reg = readl(>pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;

and it does not work here:

U-Boot 2016.01-rc1-00022-gfe52456-dirty (Nov 18 2015 - 09:28:02 -0200)

CPU:   Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 44C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
PCI:   pcie phy link never came up
In:serial
Out:   serial
Err:   serial
Net:   Board Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
Booting from net ...
No ethernet found.
No ethernet found.
Bad Linux ARM zImage magic!

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"

[Fabio Estevam]

Hi Jörg,

On Wed, Nov 18, 2015 at 6:44 AM, Jörg Krause
 wrote:

> I think this is not the right thing to do here. It is true that the
> AR8035 ethernet chip of the RioTboard needs the clock to be stable for
> at least 1ms before RESET can be deasserted. This why it fails, if
> there is no MII reset function defined.

In my case I am testing on a mx6sxsabresd which has two AR8031 chips.

>
> I think the right place to handle reset delays is the board_eth_init().
> The value of 15ms currently used looks to me like an arbitrary value. I
> am not sure where this value is comming from. Some chips need more,
> some less time to delay after a reset.
>
> This is snippet of how I do it for a custom i.MX28-EVK-based board:
>
> int board_eth_init(bd_t *bis) {
>   cpu_eth_init(bis);
>   /* Power-on FEC */
>   gpio_direction_output(MX28_PAD_LCD_D21__GPIO_1_21, 0);
>   /* Reset FEC PHY */
>   gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
>   /* Deassert nRST after 25 ms from power-up on (= t_purstd) */
>   udelay(25000);
>   gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
>   fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
> }

We currently reset the Ethernet PHY inside setup_fec() inside board_eth_init().

Please check board/freescale/mx6sxsabresd/mx6sxsabresd.c.

I have also tried increasing the reset time and still do not have
Ethernel functional.

Regards,

Fabio Estevam
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[U-Boot] [PATCH v2 0/4] vexpress64 fixes and NOR support

[Ryan Harkin]

This series is a rework or repost of a few patches to fix vexpress64 FVP
support and to add NOR flash support to the boards that support it,
namely, Juno and the FVP AEMv8 models. The FVP Foundation model does not
simulate NOR flash, but will fail gracefully with this series.

The first patch was originally posted by Linus Walleij, but I took it
over with his permission when it needed reworking.

[PATCH v2 1/4] vexpress64: compile Juno PCIe conditionally
[PATCH v2 2/4] vexpress64: use 2nd DRAM bank only on juno
[PATCH v2 3/4] vexpress64: remove #error
[PATCH v2 4/4] vexpress64: store env in flash

 board/armltd/vexpress64/Makefile   |  3 ++-
 board/armltd/vexpress64/pcie.c |  2 --
 board/armltd/vexpress64/vexpress64.c   |  9 +
 configs/vexpress_aemv8a_dram_defconfig |  1 -
 configs/vexpress_aemv8a_semi_defconfig |  1 -
 include/configs/vexpress_aemv8a.h  | 54 
--

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[U-Boot] [PATCH v2 2/4] vexpress64: use 2nd DRAM bank only on juno

[Ryan Harkin]

This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.

The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:

commit 2d0cee1ca2b9d977fa3214896bb2e30cfec77059
Author: Liviu Dudau 
Date:   Mon Oct 19 11:08:31 2015 +0100

vexpress64: Juno: Declare all 8GB of RAM and make them visible to the 
kernel.

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau 
Reviewed-by: Linus Walleij 
Reviewed-by: Ryan Harkin 
Tested-by: Ryan Harkin 

Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model.  Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.

Signed-off-by: Ryan Harkin 
Acked-by: Liviu Dudau 
Reviewed-by: Linus Walleij 
---
 board/armltd/vexpress64/vexpress64.c |  2 ++
 include/configs/vexpress_aemv8a.h| 11 ---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index 3add099..6efc8c1 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -51,8 +51,10 @@ void dram_init_banksize(void)
 {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
 }
 
 /*
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index a99d712..3c9faf4 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -165,15 +165,20 @@
 #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x1000)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1   (V2M_BASE)  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2   (0x88000)
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE  0x0100
 #define PHYS_SDRAM_1_SIZE  0x8000 - DRAM_SEC_SIZE
-#define PHYS_SDRAM_2_SIZE  0x18000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_NR_DRAM_BANKS   2
+#define PHYS_SDRAM_2   (0x88000)
+#define PHYS_SDRAM_2_SIZE  0x18000
+#else
+#define CONFIG_NR_DRAM_BANKS   1
+#endif
+
 /* Enable memtest */
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
-- 
2.1.4

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[U-Boot] [PATCH 1/4] armv8: usec2ticks function defined

[Aneesh Bansal]

usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.

Signed-off-by: Aneesh Bansal 
---
 arch/arm/cpu/armv8/generic_timer.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/cpu/armv8/generic_timer.c 
b/arch/arm/cpu/armv8/generic_timer.c
index 8e60bae..8f47a82 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -40,3 +40,14 @@ unsigned long timer_read_counter(void)
 #endif
return cntpct;
 }
+
+unsigned long usec2ticks(unsigned long usec)
+{
+   ulong ticks;
+   if (usec < 1000)
+   ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+   else
+   ticks = ((usec / 10) * (get_tbclk() / 10));
+
+   return ticks;
+}
-- 
1.8.1.4

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[U-Boot] [PATCH 4/4] drivers/crypto/fsl: fix endianness issue in RNG

[Aneesh Bansal]

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal 
CC: Alex Porosanu 
---
 drivers/crypto/fsl/jr.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f63eacb..b553e3c 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -470,17 +470,13 @@ static void kick_trng(int ent_delay)
sec_out32(>rtfreqmin, ent_delay >> 2);
/* disable maximum frequency count */
sec_out32(>rtfreqmax, RTFRQMAX_DISABLE);
-   /* read the control register */
-   val = sec_in32(>rtmctl);
/*
 * select raw sampling in both entropy shifter
 * and statistical checker
 */
-   sec_setbits32(, RTMCTL_SAMP_MODE_RAW_ES_SC);
+   sec_setbits32(>rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
/* put RNG4 into run mode */
-   sec_clrbits32(, RTMCTL_PRGM);
-   /* write back the control register */
-   sec_out32(>rtmctl, val);
+   sec_clrbits32(>rtmctl, RTMCTL_PRGM);
 }
 
 static int rng_init(void)
-- 
1.8.1.4

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[U-Boot] [PATCH 3/4] armv8/ls1043ardb: SECURE BOOT target added for NOR

[Aneesh Bansal]

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal 
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 16 --
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  2 +-
 board/freescale/common/fsl_validate.c  | 35 +-
 board/freescale/ls1043ardb/MAINTAINERS |  5 
 board/freescale/ls1043ardb/ls1043ardb.c| 18 ++-
 common/cmd_blob.c  |  6 ++--
 configs/ls1043ardb_SECURE_BOOT_defconfig   |  4 +++
 include/configs/ls1043ardb.h   | 12 
 include/fsl_validate.h |  9 +-
 9 files changed, 85 insertions(+), 22 deletions(-)
 create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..d6729a0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -122,9 +122,21 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_FSL_SEC_MON
+#define CONFIG_SHA_PROG_HW_ACCEL
+#define CONFIG_DM
+#define CONFIG_RSA
+#define CONFIG_RSA_FREESCALE_EXP
+#ifndef CONFIG_FSL_CAAM
+#define CONFIG_FSL_CAAM
+#endif
+#endif
+
 #define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d941437..2a3a7da 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -38,7 +38,7 @@
 #define CONFIG_SYS_PCIE3_ADDR  (CONFIG_SYS_IMMR + 0x260)
 #define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 
0x70)
 #define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 
0x71)
-#define CONFIG_SYS_SNVS_ADDR   (CONFIG_SYS_IMMR + 0xe9)
+#define CONFIG_SYS_SEC_MON_ADDR(CONFIG_SYS_IMMR + 
0xe9)
 #define CONFIG_SYS_SFP_ADDR(CONFIG_SYS_IMMR + 0xe80200)
 
 #define CONFIG_SYS_FSL_TIMER_ADDR  0x02b0
diff --git a/board/freescale/common/fsl_validate.c 
b/board/freescale/common/fsl_validate.c
index 73b6718..1fb5eaa 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -15,9 +15,6 @@
 #include 
 #include 
 #include 
-#ifndef CONFIG_MPC85xx
-#include 
-#endif
 
 #define SHA256_BITS256
 #define SHA256_BYTES   (256/8)
@@ -99,7 +96,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(>scratchrw[0]);
 
-   if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+   if (memcmp((u8 *)(dma_addr_t)csf_hdr_addr,
+  barker_code, ESBC_BARKER_LEN))
return -1;
 
*csf_addr = csf_hdr_addr;
@@ -117,7 +115,7 @@ static int get_ie_info_addr(u32 *ie_addr)
if (get_csf_base_addr(_addr, _base_addr))
return -1;
 
-   hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+   hdr = (struct fsl_secboot_img_hdr *)(dma_addr_t)csf_addr;
 
/* For SoC's with Trust Architecture v1 with corenet bus
 * the sg table field in CSF header has absolute address
@@ -130,7 +128,7 @@ static int get_ie_info_addr(u32 *ie_addr)
 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
  flash_base_addr);
 #else
-   sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+   sg_tbl = (struct fsl_secboot_sg_table *)(dma_addr_t)(csf_addr +
 (u32)hdr->psgtable);
 #endif
 
@@ -379,8 +377,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv 
*img)
 #ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
-   (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
-   img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ (u8 *)(dma_addr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
srk = 1;
}
 #endif
@@ -438,8 +436,8 @@ static int calc_esbchdr_esbc_hash(struct 
fsl_secboot_img_priv *img)
 #ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {

[U-Boot] [PATCH 2/4] armv8: Make SEC read/write as Snoopable for LS1043

[Aneesh Bansal]

For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by: Aneesh Bansal 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 637853d..e7b188d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -81,11 +81,16 @@ void fsl_lsch3_early_init_f(void)
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_FSL_IFC
init_early_memctl_regs();   /* tighten IFC timing */
 #endif
 
+   /* Make SEC reads and writes snoopable */
+   setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP);
+
/*
 * Enable snoop requests and DVM message requests for
 * Slave insterface S4 (A53 core cluster)
-- 
1.8.1.4

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Re: [U-Boot] Cyclone 5 U-boot 2015.10

[Marek Vasut]

On Tuesday, November 17, 2015 at 04:20:16 PM, Simon Brown wrote:

Hi,

> I thought I checked out "v2015.10", rather than a rc.  I assumed that was
> the proper version.
> 
> The startup message says:
> U-Boot 2015.10-dirty (Nov 17 2015 - 14:31:48 +)

Try git describe HEAD ;-)

> I don't have USB either - only input means before ethernet is serial port.
> Not very clever, but at least we have ONE means of getting comms going.

What about ethernet ? Hell, you have an FPGA, you can route the eMMC pins on
some edge connector and plug that thing into a card reader :b

> Regards,
> Simon
> 
> On 17 November 2015 at 15:15, Marek Vasut  wrote:
> > On Tuesday, November 17, 2015 at 04:03:03 PM, Simon Brown wrote:
> > > Ok, that seems to have helped - I think one problem I had was using
> > > u-boot.img, not u-boot-dtb.img - what is the difference?
> > 
> > The later has the device tree attached to the end of the binary,
> > the former does not.
> > 
> > > It now prints the U-boot startup prompt, followed by some information
> > 
> > about
> > 
> > > setup, up to DRAM: 1 GiB
> > > then it says "Error binding driver 'gpio-dwapb'" three times, followed
> > > by
> > > 
> > > some other error messages:
> > > >Some drivers failed to bind
> > > >Error binding driver 'generic_simple_bus'
> > > >Some drivers failed to bind
> > > 
> > > finishing with "initcall sequence 3ffb1ce4 failed at call
> > > 010031bf(err=-1)".
> > 
> > Is this stock 2015.10 or u-boot/master ?
> > 
> > > As regards not configuring SD card until after we boot - we made the
> > > decision to use an EMMC chip rather than an SD card, but no means of
> > > programming it without Linux!
> > 
> > Oh, we do the same on MCVEVK. At one point, I just cooked stripped down
> > version of U-Boot with USB mass storage support and placed that into
> > RAM cells in the FPGA. Then I made the SoCFPGA boot from FPGA.
> > 
> > The MCVEVK behaves as a USB stick and the eMMC is the backing store.
> > 
> > > Anyway, will try and workout what the above errors signify.
> > > Kind regards,
> > > 
> > > Simon
> > > 
> > > On 17 November 2015 at 14:18, Marek Vasut  wrote:
> > > > On Tuesday, November 17, 2015 at 02:08:21 PM, Simon Brown wrote:
> > > > > Hi,
> > > > 
> > > > Hi,
> > > > 
> > > > > I've been in discussion with Marek on this issue, and he suggested
> > > > > I post to the u-boot mailing list.
> > > > > 
> > > > > I've git cloned uboot 2015.10 and checked it out in my own branch. 
> > > > > I wasn't about to submit anything back, but this way I hopefully
> > 
> > wouldn't
> > 
> > > > > break anything if I did!
> > > > > 
> > > > > I've created a new board, "Axim".  I've setup the DTS, Kconfig,
> > > > > defconfig files etc similar to the Atlas board addition, and things
> > > > > are compiling ok.  However, when I run U-boot it gets to a
> > > > > relatively early point and then says "### ERROR ### Please reset
> > > > > the board ###". I can't see it say this ,as it no longer talks to
> > > > > the UART, but I can see that it points to the memory address
> > > > > containing this string in
> > 
> > the
> > 
> > > > > debugger, so assume
> > > > 
> > > > that's
> > > > 
> > > > > what it prints out, before entering an endless loop.
> > > > > 
> > > > > My setup is slightly odd, in that I need to get U-boot running
> > 
> > before I
> > 
> > > > can
> > > > 
> > > > > configure an SD card.
> > > > 
> > > > Why ?
> > > > 
> > > > > This means I'm programming my FPGA via JTAG, then
> > > > > loading the preloader with the ARM DS-5 debugger via JTAG and
> > > > > running it.
> > > > 
> > > > OK, so what I suggest you do (to make things easy) is:
> > > > 
> > > > 1) edit arch/arm/mach-socfpga/spl.c
> > > > 2) locate board_init_f()
> > > > 3) Add the following code all the way to the end of board_init_f()
> > 
> > (which
> > 
> > > > is,
> > > > 
> > > >incidentally, at the end of the file):
> > > >asm volatile("x: b x");
> > > > 
> > > > This will make sure that the SPL starts spinning in an endless loop
> > > > at this point. Once you load this modified SPL with your debugger,
> > > > it will init the hardware, but it won't do anything funny anymore.
> > > > 
> > > > So once your hardware is running, load U-Boot (u-boot-dtb.bin) to
> > > > 0x0140
> > > > and execute it from that address. This should get you the prompt.
> > > > 
> > > > > I get output on the UART (via FPGA pins), to my PC, to suggest that
> > 
> > all
> > 
> > > > is
> > > > 
> > > > > running well.  I can then upload my u-boot.img file to the
> > > > > preloader
> > > > 
> > > > using
> > > > 
> > > > > Ymodem (preloader configured to accept this), and I can run U-boot.
> > > > > 
> > > > > Before I was using the preconfigured 2013.01.01 U-boot as provided
> > > > > on Rocketboards.org, but since we are using the KSZ9031 chip for
> > > > > our PHY
> > > > 
> > > > felt
> > > > 
> > > > > I needed a newer version to support this.  But 2013.01.01 runs ok,
> > 

Re: [U-Boot] MosChip

[Marek Vasut]

On Tuesday, November 17, 2015 at 01:16:15 PM, w...@denx.de wrote:

Hi,

[...]

> Hi Wolfgang Denk,
> 
> I have ARM9 processor board with uboot version u-boot-1.1.6. Now I want to
> change it to u-boot-2015.10. But the whole uboot structure got changed from
> version 1.1.6 to 2015.10.
> 
> Please guide me to do it.

Is this some new 6502 ? :-)

I think it's only make sense to start porting from scratch.

Best regards,
Marek Vasut
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Re: [U-Boot] mxs: HAB experiments

[Marek Vasut]

On Tuesday, November 17, 2015 at 02:16:06 PM, Florian Achleitner wrote:
> Hi Marek,

Hi,

> thanks for you contributions to support mxs HAB v4 in u-boot. I'm currently
> experimenting with HAB on my imx28 board. I think I put everything together
> quite well.
> 
> But examining the HAB event log I see two successful authentications for
> the u-boot.bin and the IVT followed by a FAILURE with "unsupported
> command" in the "CSF Context".  It is the same for both the SPL and the
> main u-boot. Did you see something similar? It suggests a wrong command in
> the CSF file, but I think there is not a lot that can be wrong in the CSF
> input file for the cst tool. But probably the cst output is different
> between versions? I use version BLN_CST_MAIN_02.03.00.
> 
> I use u-boot's mkimage, which can generate a signed boot stream, together
> with your hand-crafted IVT generator in the Makefile.

Can you share your CSF files (make sure to blank out the private material) ?

> I wonder if the image size field, which is appended to IVT is critical. In
> 9c2c8a3 you mention that the HAB Rom accepts a not exact size field value
> of your SPL image layout. So it seems to be not that critical.
> I found that my .sig file created by freescale's cst tool is 3372B, while
> yours seems to have been 3904B. Currently, I am experimenting with the
> image memory layout and the size field.
> 
> My CSF file is virtually identical to the example in the freescale's
> application notes, which uses sha256. I programmed the SRK fuses, but did
> not set any lock bits.
> HAB is in the open configuration. The SRK seems to be ok, otherwise there
> would be no SUCCESS events in the log.
> 
> Did HAB work without FAILURE events for you? Did anybody else on the list
> see something similar? Below, you can find the HAB event log.
> 
> Thanks!
> Florian
> 
> 
> 
> Status: Operation failed (0x33)
> Config: Non-secure IC (0xf0)
> State: No security state machine (0xf0)
>  HAB Event 0 
> event data:
>  db 00 10 40  f0 00 db 00
>  00 00 10 00  00 00 26 c0
>  status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT
> 
>  HAB Event 1 
> event data:
>  db 00 10 40  f0 00 db 00
>  00 00 80 00  00 00 00 40
>  status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT
> 
>  HAB Event 2 
> event data:
>  db 00 08 40  33 03 cf 00
>  status: HAB_STATUS_FAILURE reason: HAB_UNS_COMMAND context: HAB_CTX_CSF
> 
>  HAB Event 3 
> event data:
>  db 00 10 40  f0 00 db 00
>  40 00 20 00  00 06 ef 00
>  status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT
> 
>  HAB Event 4 
> event data:
>  db 00 10 40  f0 00 db 00
>  40 00 10 00  00 00 00 40
>  status: HAB_STATUS_SUCCESS reason: HAB_RSN_ANY context: HAB_CTX_AUT_DAT
> 
>  HAB Event 5 
> event data:
>  db 00 08 40  33 03 cf 00
>  status: HAB_STATUS_FAILURE reason: HAB_UNS_COMMAND context: HAB_CTX_CSF
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Re: [U-Boot] MosChip

[Marek Vasut]

On Wednesday, November 18, 2015 at 11:09:55 AM, Ravi Koganti wrote:
> Hi Marek Vasut

Hi,

> Can you give me any reference link to do it from scratch.

I don't think there's any reference document.

Look at other platforms, for example in arch/arm/mach-* (socfpga might be
a good pick). Then add the configuration into include/configs/board.h and
configs/board.h . The boards files go into board/

> Thanks,
> Ravi
> 
> On Wed, Nov 18, 2015 at 3:34 PM, Marek Vasut  wrote:
> > On Tuesday, November 17, 2015 at 01:16:15 PM, w...@denx.de wrote:
> > 
> > Hi,
> > 
> > [...]
> > 
> > > Hi Wolfgang Denk,
> > > 
> > > I have ARM9 processor board with uboot version u-boot-1.1.6. Now I want
> > 
> > to
> > 
> > > change it to u-boot-2015.10. But the whole uboot structure got changed
> > 
> > from
> > 
> > > version 1.1.6 to 2015.10.
> > > 
> > > Please guide me to do it.
> > 
> > Is this some new 6502 ? :-)
> > 
> > I think it's only make sense to start porting from scratch.
> > 
> > Best regards,
> > Marek Vasut

Best regards,
Marek Vasut
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[U-Boot] [PATCH v4] arm: socfpga: Add SoCFPGA SR1500 board

[Stefan Roese]

The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by: Stefan Roese 
Reviewed-by: Marek Vasut 
Cc: Pavel Machek 
Cc: Dinh Nguyen 
---
v4:
- Really remove board specific commands

v3:
- Removed README.socfpga changes
- Removed board specific commands
- Change CONFIG_LOADADDR to 0x0100 as suggested by Dinh

v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile|   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +
 arch/arm/mach-socfpga/Kconfig|   6 +
 board/sr1500/MAINTAINERS |   6 +
 board/sr1500/Makefile|   7 +
 board/sr1500/qts/iocsr_config.h  | 660 +++
 board/sr1500/qts/pinmux_config.h | 219 ++
 board/sr1500/qts/pll_config.h|  85 
 board/sr1500/qts/sdram_config.h  | 341 
 board/sr1500/socfpga.c   |  44 +++
 configs/socfpga_sr1500_defconfig |  17 +
 include/configs/socfpga_sr1500.h | 113 ++
 12 files changed, 1602 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9542fff..82d68ce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -80,7 +80,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_de0_nano_soc.dtb   \
socfpga_cyclone5_sockit.dtb \
-   socfpga_cyclone5_socrates.dtb
+   socfpga_cyclone5_socrates.dtb   \
+   socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts 
b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
new file mode 100644
index 000..3729ca0
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2015 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+   model = "SoCFPGA Cyclone V SR1500";
+   compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", 
"altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   /*
+* This allows the ethaddr uboot environmnet variable
+* contents to be added to the gmac1 device tree blob.
+*/
+   ethernet0 = 
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   speed-mode = <0>;
+};
+
+ {
+   status = "okay";
+   speed-mode = <0>;
+};
+
+ {
+   status = "okay";
+   bus-width = <8>;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+
+   flash0: n25q00@0 {
+   u-boot,dm-pre-reloc;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q00", "spi-flash";
+   reg = <0>;  /* chip select */
+   spi-max-frequency = <5000>;
+   m25p,fast-read;
+   page-size = <256>;
+   block-size = <16>; /* 2^16, 64KB */
+   read-delay = <4>;  /* delay value in read data capture register 
*/
+   tshsl-ns = <50>;
+   tsd2d-ns = <50>;
+   tchsh-ns = <4>;
+   tslch-ns = <4>;
+   };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 

Re: [U-Boot] [PULL] Please pull u-boot-nios/master

[Tom Rini]

On Wed, Nov 18, 2015 at 09:24:40PM +0800, Thomas Chou wrote:

> Hi Tom,
> 
> Please pull,
> 
> The following changes since commit fe524569d4a7eea66475d5815be75660e59b6ee4:
> 
>   Merge git://git.denx.de/u-boot-marvell (2015-11-17 17:57:32 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-nios.git master
> 
> for you to fetch changes up to f5b76de4403881940a3ef57f9b6e9fa5b3433070:
> 
>   nios2: zap ioremap (2015-11-18 21:18:30 +0800)
> 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH v2 05/13] ns16550: unify serial_ppc

[Thomas Chou]

Unify serial_ppc, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 arch/powerpc/include/asm/config.h |  4 
 drivers/serial/Kconfig|  2 +-
 drivers/serial/Makefile   |  1 -
 drivers/serial/serial_ppc.c   | 40 ---
 4 files changed, 5 insertions(+), 42 deletions(-)
 delete mode 100644 drivers/serial/serial_ppc.c

diff --git a/arch/powerpc/include/asm/config.h 
b/arch/powerpc/include/asm/config.h
index 65496d0..7391066 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -104,4 +104,8 @@
 /* All PPC boards must swap IDE bytes */
 #define CONFIG_IDE_SWAP_IO
 
+#if defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
+
 #endif /* _ASM_CONFIG_H_ */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 93faa4c..b41f508 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -198,7 +198,7 @@ config ROCKCHIP_SERIAL
 config NS16550_SERIAL
bool "NS16550 UART or compatible"
depends on DM_SERIAL
-   default y if X86
+   default y if X86 || PPC
help
  Support NS16550 UART or compatible with driver model. This can be
  enabled in the device tree with the correct input clock frequency.
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9036a8e..9f61113 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -8,7 +8,6 @@
 ifdef CONFIG_DM_SERIAL
 obj-y += serial-uclass.o
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PPC) += serial_ppc.o
 else
 obj-y += serial.o
 obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
diff --git a/drivers/serial/serial_ppc.c b/drivers/serial/serial_ppc.c
deleted file mode 100644
index 47141c6..000
--- a/drivers/serial/serial_ppc.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-static const struct udevice_id ppc_serial_ids[] = {
-   { .compatible = "ns16550" },
-   { }
-};
-
-static int ppc_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-   plat->clock = get_serial_clock();
-
-   return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
-   .name   = "serial_ppc",
-   .id = UCLASS_SERIAL,
-   .of_match = ppc_serial_ids,
-   .ofdata_to_platdata = ppc_serial_ofdata_to_platdata,
-   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-   .priv_auto_alloc_size = sizeof(struct NS16550),
-   .probe = ns16550_serial_probe,
-   .ops= _serial_ops,
-   .flags  = DM_FLAG_PRE_RELOC,
-};
-- 
2.5.0

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[U-Boot] [PATCH v2 00/13] ns16550: add generic binding to unify the drivers

[Thomas Chou]

Add generic binding to unify ns16550 drivers. There are
several drivers using almost the same code, such as serial_dw,
serial_keystone, serial_omap, serial_ppc, serial_rockchip,
serial_tegra.c, and serial_x86. But each is platform specific.

The key difference between these drivers is the way to get
input clock frequency. With this unified approach, fixed clock
frequency should be extracted from "clock-frequency" property of
device tree blob. If this property is not available, the macro
CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a
function to get clock, eg, get_serial_clock().

v2
  use default in driver Kconfig as suggested by Bin Meng.
  remove extra #ifdef CONFIG_NS16550_SERIAL.
  zap CONFIG_NS16550_SERIAL.
  move CONFIG_SYS_NS16550 to Kconfig.

Thomas Chou (13):
  debug_uart: restore ns16550 as default
  ns16550: change map_sysmem to map_physmem
  ns16550: add generic binding to unify the drivers
  ns16550: unify serial_x86
  ns16550: unify serial_ppc
  ns16550: unify serial_rockchip
  ns16550: unify serial_keystone
  ns16550: unify serial_dw
  ns16550: unify serial_tegra
  ns16550: unify serial_omap
  ns16550: zap CONFIG_NS16550_SERIAL
  ns16550: move CONFIG_SYS_NS16550 to Kconfig
  nios2: 10m50: change to ns16550 uart

 arch/arm/dts/rk3288.dtsi   |  5 ++
 arch/arm/include/asm/arch-lpc32xx/config.h |  1 -
 arch/arm/mach-rockchip/Kconfig |  3 --
 arch/arm/mach-tegra/board.c| 14 ++
 arch/nios2/dts/10m50_devboard.dts  |  2 +-
 arch/powerpc/include/asm/config.h  |  4 ++
 arch/x86/dts/serial.dtsi   |  2 +-
 board/isee/igep00x0/igep00x0.c |  2 +-
 board/lge/sniper/sniper.c  |  2 +-
 board/logicpd/omap3som/omap3logic.c|  2 +-
 board/logicpd/zoom1/zoom1.c|  2 +-
 board/overo/overo.c|  2 +-
 board/quipos/cairo/cairo.c |  2 +-
 board/ti/beagle/beagle.c   |  2 +-
 board/timll/devkit8000/devkit8000.c|  2 +-
 configs/10m50_defconfig|  2 +-
 configs/A10-OLinuXino-Lime_defconfig   |  1 +
 configs/A10s-OLinuXino-M_defconfig |  3 +-
 configs/A13-OLinuXinoM_defconfig   |  3 +-
 configs/A13-OLinuXino_defconfig|  4 +-
 configs/A20-OLinuXino-Lime2_defconfig  |  1 +
 configs/A20-OLinuXino-Lime_defconfig   |  1 +
 configs/A20-OLinuXino_MICRO_defconfig  |  1 +
 configs/A20-Olimex-SOM-EVB_defconfig   |  1 +
 configs/Ainol_AW1_defconfig|  1 +
 configs/Ampe_A76_defconfig |  1 +
 configs/Auxtek-T003_defconfig  |  3 +-
 configs/Auxtek-T004_defconfig  |  3 +-
 configs/B4420QDS_NAND_defconfig|  1 +
 configs/B4420QDS_SPIFLASH_defconfig|  1 +
 configs/B4420QDS_defconfig |  1 +
 configs/B4860QDS_NAND_defconfig|  1 +
 configs/B4860QDS_SECURE_BOOT_defconfig |  1 +
 configs/B4860QDS_SPIFLASH_defconfig|  1 +
 configs/B4860QDS_SRIO_PCIE_BOOT_defconfig  |  1 +
 configs/B4860QDS_defconfig |  1 +
 configs/BSC9131RDB_NAND_SYSCLK100_defconfig|  1 +
 configs/BSC9131RDB_NAND_defconfig  |  1 +
 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig|  1 +
 configs/BSC9131RDB_SPIFLASH_defconfig  |  1 +
 configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig |  1 +
 configs/BSC9132QDS_NAND_DDRCLK100_defconfig|  1 +
 configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig |  1 +
 configs/BSC9132QDS_NAND_DDRCLK133_defconfig|  1 +
 configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig  |  1 +
 configs/BSC9132QDS_NOR_DDRCLK100_defconfig |  1 +
 configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig  |  1 +
 configs/BSC9132QDS_NOR_DDRCLK133_defconfig |  1 +
 .../BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig   |  1 +
 configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig  |  1 +
 .../BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig   |  1 +
 configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig  |  1 +
 .../BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig |  1 +
 configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig|  1 +
 .../BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig |  1 +
 configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig|  1 +
 configs/Bananapi_defconfig |  1 +
 configs/Bananapro_defconfig|  1 +
 configs/C29XPCIE_NAND_defconfig|  1 +
 configs/C29XPCIE_NOR_SECBOOT_defconfig |  1 +
 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig|  1 +
 configs/C29XPCIE_SPIFLASH_defconfig|  1 +
 configs/C29XPCIE_defconfig | 

[U-Boot] [PATCH v2 09/13] ns16550: unify serial_tegra

[Thomas Chou]

Unify serial_tegra, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 arch/arm/mach-tegra/board.c| 14 +++
 drivers/serial/Makefile|  1 -
 drivers/serial/serial_tegra.c  | 54 --
 include/configs/tegra-common.h |  3 ++-
 4 files changed, 16 insertions(+), 56 deletions(-)
 delete mode 100644 drivers/serial/serial_tegra.c

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index b00e4b5..8c8927d 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -6,6 +6,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -212,6 +214,18 @@ void board_init_uart_f(void)
setup_uarts(uart_ids);
 }
 
+#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static struct ns16550_platdata ns16550_com1_pdata = {
+   .base = CONFIG_SYS_NS16550_COM1,
+   .reg_shift = 2,
+   .clock = CONFIG_SYS_NS16550_CLK,
+};
+
+U_BOOT_DEVICE(ns16550_com1) = {
+   "ns16550_serial", _com1_pdata
+};
+#endif
+
 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 2a83756..86ae50f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,7 +39,6 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
-obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c
deleted file mode 100644
index 0c84f0b..000
--- a/drivers/serial/serial_tegra.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id tegra_serial_ids[] = {
-   { .compatible = "nvidia,tegra20-uart" },
-   { }
-};
-
-static int tegra_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-   plat->clock = V_NS16550_CLK;
-
-   return 0;
-}
-#else
-struct ns16550_platdata tegra_serial = {
-   .base = CONFIG_SYS_NS16550_COM1,
-   .reg_shift = 2,
-   .clock = V_NS16550_CLK,
-};
-
-U_BOOT_DEVICE(ns16550_serial) = {
-   "serial_tegra20", _serial
-};
-#endif
-
-U_BOOT_DRIVER(serial_ns16550) = {
-   .name   = "serial_tegra20",
-   .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-   .of_match = tegra_serial_ids,
-   .ofdata_to_platdata = tegra_serial_ofdata_to_platdata,
-   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
-   .priv_auto_alloc_size = sizeof(struct NS16550),
-   .probe = ns16550_serial_probe,
-   .ops= _serial_ops,
-   .flags  = DM_FLAG_PRE_RELOC,
-};
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 32cc39b..ceda304 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -39,8 +39,9 @@
 /*
  * NS16550 Configuration
  */
-#define CONFIG_TEGRA_SERIAL
+#define CONFIG_NS16550_SERIAL
 #define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
 
 /*
  * Common HW configuration.
-- 
2.5.0

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Re: [U-Boot] mxs: HAB experiments

[Florian Achleitner]

On Wednesday, November 18, 2015 11:01:03 AM Marek Vasut wrote:
> > [Header]
> > Version = 4.0
> > Hash Algorithm = sha256
> > Engine Configuration = 0
> > Certificate Format = X509
> > Signature Format = CMS
> > Engine = DCP
> 
> I use "Engine = ANY" here, not sure if it matters.

Makes no difference.

> 
> > 
> >
> > [Install SRK]
> > File = "$SRK_1_2_table.bin"
> > Source index = 0
> >
> > 
> >
> > [Install CSFK]
> > File = "$CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
> >
> > 
> >
> > [Authenticate CSF]
> >
> > 
> >
> > [Install Key]
> > Verification index = 0
> > Target index = 2
> > File = "$IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
> >
> > 
> >
> > [Authenticate Data]
> > Verification index = 2
> 
> Here I use "Engine = DCP" (missing in your example)

Also no difference. 
> 
> I am using BLN_CST_MAIN_02.00.00 btw.

I think I have to try this version..

> 
> Best regards,
> Marek Vasut

Thanks!
Florian

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[U-Boot] [PULL] Please pull u-boot-nios/master

[Thomas Chou]

Hi Tom,

Please pull,

The following changes since commit fe524569d4a7eea66475d5815be75660e59b6ee4:

  Merge git://git.denx.de/u-boot-marvell (2015-11-17 17:57:32 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-nios.git master

for you to fetch changes up to f5b76de4403881940a3ef57f9b6e9fa5b3433070:

  nios2: zap ioremap (2015-11-18 21:18:30 +0800)


Thomas Chou (10):
  altera_jtag_uart: change ioremap to map_physmem
  altera_uart: change ioremap to map_physmem
  altera_timer: change ioremap to map_physmem
  altera_spi: change ioremap to map_physmem
  altera_sysid: change ioremap to map_physmem
  altera_tse: change ioremap to map_physmem
  altera_qspi: change ioremap to map_physmem
  altera_pio: change ioremap to map_physmem
  nios2: dma-mapping.h: change ioremap to map_physmem
  nios2: zap ioremap

 arch/nios2/include/asm/dma-mapping.h | 2 +-
 arch/nios2/include/asm/io.h  | 6 --
 drivers/gpio/altera_pio.c| 5 +++--
 drivers/misc/altera_sysid.c  | 5 +++--
 drivers/mtd/altera_qspi.c| 2 +-
 drivers/net/altera_tse.c | 2 +-
 drivers/serial/altera_jtag_uart.c| 5 +++--
 drivers/serial/altera_uart.c | 5 +++--
 drivers/spi/altera_spi.c | 5 +++--
 drivers/timer/altera_timer.c | 5 +++--
 10 files changed, 21 insertions(+), 21 deletions(-)
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Re: [U-Boot] [PATCH v2 01/13] debug_uart: restore ns16550 as default

[Bin Meng]

On Wed, Nov 18, 2015 at 9:44 PM, Thomas Chou  wrote:
> Since commit 220e8021af96 ("nios2: convert altera_jtag_uart to
> driver model"), the default debug uart was changed. Most people
> use ns16550 UART, so restore it as default.
>
> Signed-off-by: Thomas Chou 
> Reported-by: Ezequiel Garcia 
> Reported-by: Ariel D'Alessandro 
> Reviewed-by: Tom Rini 
> ---
>  drivers/serial/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index eba96f4..2a50771 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -53,6 +53,7 @@ config DEBUG_UART
>  choice
> prompt "Select which UART will provide the debug UART"
> depends on DEBUG_UART
> +   default DEBUG_UART_NS16550
>
>  config DEBUG_UART_ALTERA_JTAGUART
> bool "Altera JTAG UART"
> --

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Re: [U-Boot] [PATCH v2 11/13] ns16550: zap CONFIG_NS16550_SERIAL

[Bin Meng]

Hi Thomas,

On Wed, Nov 18, 2015 at 9:44 PM, Thomas Chou  wrote:
> Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers
> is completed.
>
> Signed-off-by: Thomas Chou 
> ---
>  configs/efi-x86_defconfig|  1 -
>  drivers/serial/Kconfig   | 12 
>  drivers/serial/ns16550.c |  4 
>  include/configs/am43xx_evm.h |  2 --
>  include/configs/cm_t43.h |  1 -
>  include/configs/mv-common.h  |  4 
>  include/configs/omap3_pandora.h  |  1 -
>  include/configs/sniper.h |  4 +---
>  include/configs/sunxi-common.h   |  4 +---
>  include/configs/tb100.h  |  1 -
>  include/configs/tegra-common.h   |  1 -
>  include/configs/ti_am335x_common.h   |  4 
>  include/configs/ti_armv7_keystone2.h |  2 --
>  include/configs/ti_omap3_common.h|  4 
>  include/configs/ti_omap4_common.h|  2 --
>  include/configs/ti_omap5_common.h|  2 --
>  16 files changed, 2 insertions(+), 47 deletions(-)
>
> diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
> index b1573df..904b564 100644
> --- a/configs/efi-x86_defconfig
> +++ b/configs/efi-x86_defconfig
> @@ -3,7 +3,6 @@ CONFIG_VENDOR_EFI=y
>  CONFIG_DEFAULT_DEVICE_TREE="efi"
>  CONFIG_TARGET_EFI=y
>  CONFIG_TSC_CALIBRATION_BYPASS=y
> -# CONFIG_NS16550_SERIAL is not set

This line should not be removed.

>  # CONFIG_CMD_BOOTM is not set
>  # CONFIG_CMD_NET is not set
>  CONFIG_OF_CONTROL=y
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 1239416..fe407b7 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -186,18 +186,6 @@ config ALTERA_UART
>   Select this to enable an UART for Altera devices. Please find
>   details on the "Embedded Peripherals IP User Guide" of Altera.
>
> -config NS16550_SERIAL
> -   bool "NS16550 UART or compatible"
> -   depends on DM_SERIAL
> -   default y if X86 || PPC || ARCH_ROCKCHIP
> -   help
> - Support NS16550 UART or compatible with driver model. This can be
> - enabled in the device tree with the correct input clock frequency.
> - If the input clock frequency is not defined in the device tree,
> - the macro CONFIG_SYS_NS16550_CLK defined in a legacy board header
> - file will be used. It can be a constant or a function to get clock,
> - eg, get_serial_clock().
> -
>  config SANDBOX_SERIAL
> bool "Sandbox UART support"
> depends on SANDBOX
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index f0a9aac..d5bcbc3 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -404,7 +404,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
> plat->base = addr;
> plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>  "reg-shift", 1);
> -#ifdef CONFIG_NS16550_SERIAL
> plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>  "clock-frequency",
>  CONFIG_SYS_NS16550_CLK);
> @@ -412,7 +411,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
> debug("ns16550 clock not defined\n");
> return -EINVAL;
> }
> -#endif /* CONFIG_NS16550_SERIAL */
>
> return 0;
>  }
> @@ -425,7 +423,6 @@ const struct dm_serial_ops ns16550_serial_ops = {
> .setbrg = ns16550_serial_setbrg,
>  };
>
> -#ifdef CONFIG_NS16550_SERIAL
>  #if CONFIG_IS_ENABLED(OF_CONTROL)
>  static const struct udevice_id ns16550_serial_ids[] = {
> { .compatible = "ns16550" },
> @@ -454,5 +451,4 @@ U_BOOT_DRIVER(ns16550_serial) = {
> .probe = ns16550_serial_probe,
> .ops= _serial_ops,
>  };
> -#endif /* CONFIG_NS16550_SERIAL */
>  #endif /* CONFIG_DM_SERIAL */
> diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
> index a962bf5..75b8f53 100644
> --- a/include/configs/am43xx_evm.h
> +++ b/include/configs/am43xx_evm.h
> @@ -27,8 +27,6 @@
>  #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
>  #define CONFIG_SYS_NS16550_SERIAL
>  #define CONFIG_SYS_NS16550_REG_SIZE(-4)
> -#else
> -#define CONFIG_NS16550_SERIAL
>  #endif
>
>  /* I2C Configuration */
> diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
> index e1019ff..f8c39bf 100644
> --- a/include/configs/cm_t43.h
> +++ b/include/configs/cm_t43.h
> @@ -18,7 +18,6 @@
>  #include 
>
>  /* Serial support */
> -#define CONFIG_NS16550_SERIAL
>  #define CONFIG_DM_SERIAL
>  #define CONFIG_SYS_NS16550
>  #define CONFIG_SYS_NS16550_SERIAL
> diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
> index 0e33a89..575e53e 100644
> --- a/include/configs/mv-common.h
> +++ b/include/configs/mv-common.h
> @@ -39,10 +39,6 @@
>  /*
>   * NS16550 Configuration
>   */
> -#if 

Re: [U-Boot] [PATCH v0 1/5] pci: mvebu: Fix Armada 38x support

[Dirk Eibach]

2015-11-18 14:23 GMT+01:00 Anton Schubert :
> Am 18.11.2015 um 13:48 schrieb Dirk Eibach:
>> I assume the idea is to go to the next port if the current port is
>> disabled. But adding 3 to the index does not seem to be the right
>> thing to do, since Armada XP has ports with 4 lanes, but also with
>> ports with one lane.
>> I assume that iterating over all lanes would not be a problem, but by
>> mistake the pcie->lane == 0  was left in the condition.
> Yeah you are right. The additional condition was superfluous in the
> original version.
>
>> So this should perform better:
>>
>> /* Don't read at all from pci registers if port power is down */
>> if (SELECT(soc_ctrl, pcie->port) == 0) {
>> if (pcie->lane == 0)
>> debug("%s: skipping port %d\n", __func__, pcie->port);
>> continue;
>> }
> I agree.

Fine. I will add this to the v1 series.

Cheers
Dirk
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Re: [U-Boot] [PATCH v2 04/13] ns16550: unify serial_x86

[Bin Meng]

On Wed, Nov 18, 2015 at 9:44 PM, Thomas Chou  wrote:
> Unify serial_x86, and use the generic binding.
>
> Signed-off-by: Thomas Chou 
> Reviewed-by: Tom Rini 
> ---
>  arch/x86/dts/serial.dtsi|  2 +-
>  configs/efi-x86_defconfig   |  2 +-
>  drivers/serial/Kconfig  | 11 +--
>  drivers/serial/Makefile |  1 -
>  drivers/serial/serial_x86.c | 44 
>  5 files changed, 3 insertions(+), 57 deletions(-)
>  delete mode 100644 drivers/serial/serial_x86.c
>
> diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
> index 6865eed..54c3faf 100644
> --- a/arch/x86/dts/serial.dtsi
> +++ b/arch/x86/dts/serial.dtsi
> @@ -1,6 +1,6 @@
>  / {
> serial: serial {
> -   compatible = "x86-uart";
> +   compatible = "ns16550";
> reg = <0x3f8 8>;
> reg-shift = <0>;
> clock-frequency = <1843200>;
> diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
> index 43fb0c4..b1573df 100644
> --- a/configs/efi-x86_defconfig
> +++ b/configs/efi-x86_defconfig
> @@ -3,6 +3,7 @@ CONFIG_VENDOR_EFI=y
>  CONFIG_DEFAULT_DEVICE_TREE="efi"
>  CONFIG_TARGET_EFI=y
>  CONFIG_TSC_CALIBRATION_BYPASS=y
> +# CONFIG_NS16550_SERIAL is not set
>  # CONFIG_CMD_BOOTM is not set
>  # CONFIG_CMD_NET is not set
>  CONFIG_OF_CONTROL=y
> @@ -12,5 +13,4 @@ CONFIG_DEBUG_UART=y
>  CONFIG_DEBUG_EFI_CONSOLE=y
>  CONFIG_DEBUG_UART_BASE=0
>  CONFIG_DEBUG_UART_CLOCK=0
> -# CONFIG_X86_SERIAL is not set
>  CONFIG_EFI=y
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 0f0e92d..93faa4c 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -198,6 +198,7 @@ config ROCKCHIP_SERIAL
>  config NS16550_SERIAL
> bool "NS16550 UART or compatible"
> depends on DM_SERIAL
> +   default y if X86
> help
>   Support NS16550 UART or compatible with driver model. This can be
>   enabled in the device tree with the correct input clock frequency.
> @@ -233,14 +234,4 @@ config UNIPHIER_SERIAL
>   If you have a UniPhier based board and want to use the on-chip
>   serial ports, say Y to this option. If unsure, say N.
>
> -config X86_SERIAL
> -   bool "Support for 16550 serial port on x86 machines"
> -   depends on X86
> -   default y
> -   help
> - Most x86 machines have a ns16550 UART or compatible. This can be
> - enabled in the device tree with the correct input clock frequency
> - provided (default 1843200). Enable this to obtain serial console
> - output.
> -
>  endmenu
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 1818c7c..9036a8e 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -46,7 +46,6 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
>  obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
>  obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>  obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
> -obj-$(CONFIG_X86_SERIAL) += serial_x86.o
>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>
>  ifndef CONFIG_SPL_BUILD
> diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
> deleted file mode 100644
> index 4bf6062..000
> --- a/drivers/serial/serial_x86.c
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/*
> - * Copyright (c) 2014 Google, Inc
> - *
> - * SPDX-License-Identifier:GPL-2.0+
> - */
> -
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static const struct udevice_id x86_serial_ids[] = {
> -   { .compatible = "x86-uart" },
> -   { }
> -};
> -
> -static int x86_serial_ofdata_to_platdata(struct udevice *dev)
> -{
> -   struct ns16550_platdata *plat = dev_get_platdata(dev);
> -   int ret;
> -
> -   ret = ns16550_serial_ofdata_to_platdata(dev);
> -   if (ret)
> -   return ret;
> -
> -   plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> -"clock-frequency", 1843200);
> -
> -   return 0;
> -}
> -
> -U_BOOT_DRIVER(serial_ns16550) = {
> -   .name   = "serial_x86",
> -   .id = UCLASS_SERIAL,
> -   .of_match = x86_serial_ids,
> -   .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
> -   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
> -   .priv_auto_alloc_size = sizeof(struct NS16550),
> -   .probe = ns16550_serial_probe,
> -   .ops= _serial_ops,
> -};
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] Ethernet i210 (e1000 driver) on tegra K1

[Marcel Ziswiler]

Hi Stephen

By accident I stumbled over this post and by incident now that we at
Toradex are working on an Apalis TK1 module design using the same
i210/i211 gigabit Ethernet chip as already widely deployed on Apalis
T30 we are facing this as well.

On Mon, 2015-11-09 at 10:21 -0700, Stephen Warren wrote:
> On 11/04/2015 08:49 PM, Bin Meng wrote:
> > On Thu, Nov 5, 2015 at 2:54 AM, Stephen Warren  > rg> wrote:
> > > On 10/30/2015 05:07 AM, Ivan Mercier wrote:
> > > > 
> > > > Hi,
> > > > 
> > > > I'm using a ethernet controller intel i210
> > > > (http://www.commell.com.tw/product/Surveillance/MPX-210.htm) on
> > > > my
> > > > nvidia tegra k1 jetson.
> > > 
> > > 
> > > (You didn't actually CC anyone involved with Tegra, so I only
> > > accidentally
> > > noticed this while I was looking at my mailing list folder)

Exactly. Looking through the e1000 git log one should also have seen
that me and others actually worked on it and that we are indeed
successfully using it on Tegra albeit T30 only so far.

> > > > I not an expert with pci, but the only way to make it working
> > > > in u-boot
> > > > (upstream) is with the workaround below.
> > > > 
> > > > E1000 is very common, so finding a critical bug in this driver
> > > > seems
> > > > weird...
> > > > Do you think there is a bug in e1000.c or in tegra pci layer?
> > > 
> > > 
> > > > diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
> > > 
> > > 
> > > > @@ -5186,7 +5186,7 @@ static int _e1000_transmit(struct
> > > > e1000_hw *hw,
> > > > void *txpacket, int length)
> > > >    txp = tx_base + tx_tail;
> > > >    tx_tail = (tx_tail + 1) % 8;
> > > > 
> > > > -txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev,
> > > > nv_packet));
> > > > +txp->buffer_addr = cpu_to_le64((unsigned long) nv_packet);
> > > >    txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
> > > >    txp->upper.data = 0;
> > > 
> > > 
> > > In order to work out what's going on, perhaps you could print out
> > > the values
> > > of nv_packet and virt_to_bus(hw->pdev, nv_packet).

I did exactly that which gives:

Loading: nv_packet = 0xfffecb00
pci_hose_phys_to_bus: invalid physical address
virt_to_bus(hw->pdev, nv_packet) = 0x

So that looks OK but does not yet give us much further clues.

Looking at where the actual translation happens
in drivers/pci/pci_common.c:

int __pci_hose_phys_to_bus(struct pci_controller *hose,
...

if (bus_addr >= res->bus_start &&
bus_addr < res->bus_start + res->size) {
*ba = bus_addr;
...

So I added some more prints there giving:

bus_addr = 0xfffecb00
phys_addr = 0xfffecb00
res->phys_start = 0x8000
res->bus_start = 0x8000
res->size = 0x8000

Ah, OK. That makes sense now. Just a classical overflow happening in
the address range check (e.g. 0x8000 + 0x8000 giving 0x0 in 32-
bits).

Strange that this works for others but e.g. the Realtek driver seems to
do the inverse conversion:

int __pci_hose_bus_to_phys(struct pci_controller *hose,
...

if (bus_addr >= res->bus_start &&
(bus_addr - res->bus_start) < res->size) {
*pa = (bus_addr - res->bus_start + res-
>phys_start);

Ah, they worked around it by changing the order of the addition vs.
subtraction in the range check. That will work.

I will be sending out a proper patch to fix this shortly.

But why does it work on T30?

bus_addr = 0xffee92e0
phys_addr = 0xffee92e0
res->phys_start = 0x8000
res->bus_start = 0x8000
res->size = 0x7ff0

Ah funny, ooks like we got lucky due to the size being slightly below
0x8000 (;-p).

> > > It's not terribly surprising that removing the call to
> > > virt_to_bus works,
> > > since IIRC U-Boot on Tegra uses the same address setup for the
> > > PCIe bus as
> > > for CPU physical addresses as for CPU virtual addresses.
> > > 
> > > So, the question is: what is virt_to_bus() doing, and is it the
> > > right API to
> > > call?
> > 
> > virt_to_bus() is to translate cpu virtual address to pci bus
> > physical
> > address. Basically two levels of translation.
> > 
> > > I see that virt_to_bus() is defined as:
> > > 
> > > e1000.c:
> > > 
> > > #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *)
> > > (v))
> > > 
> > > pci.h:
> > > 
> > > #define pci_virt_to_mem(dev, addr) \
> > >  pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
> > > 
> > > #define pci_virt_to_bus(dev, addr, flags) \
> > >  pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
> > >   (virt_to_phys(addr)), (flags))
> > > 
> > > I know that the RTL8169 driver works on the same board (it's
> > > soldered down
> > > and attached to the other PCIe root port on the SoC). For what
> > > looks like
> > > the same "use case", it seems to call pci_mem_to_phys() which is:
> > > 
> > > pci.h:
> > > 
> > > #define pci_mem_to_phys(dev, addr) \
> > >  

Re: [U-Boot] mxs: HAB experiments

[Florian Achleitner]

Hi,

On Wednesday, November 18, 2015 09:55:12 AM Marek Vasut wrote:
> On Tuesday, November 17, 2015 at 02:16:06 PM, Florian Achleitner wrote:
> > Hi Marek,
> 
> Hi,
> 
> > thanks for you contributions to support mxs HAB v4 in u-boot. I'm
> > currently
> > experimenting with HAB on my imx28 board. I think I put everything
> > together
> > quite well.
> >
> > 
> >
> > But examining the HAB event log I see two successful authentications for
> > the u-boot.bin and the IVT followed by a FAILURE with "unsupported
> > command" in the "CSF Context".  It is the same for both the SPL and the
> > main u-boot. Did you see something similar? It suggests a wrong command in
> > the CSF file, but I think there is not a lot that can be wrong in the CSF
> > input file for the cst tool. But probably the cst output is different
> > between versions? I use version BLN_CST_MAIN_02.03.00.
> >
> > 
> >
> > I use u-boot's mkimage, which can generate a signed boot stream, together
> > with your hand-crafted IVT generator in the Makefile.
> 
> Can you share your CSF files (make sure to blank out the private material) ?

The CSF follows. It is the same for the spl and the main u-boot. 

Anyways, I currently suspect the cst tool in its current version (2.3.1) to 
produce binaries that are incompatible with the mx28 HAB Rom. However, I 
couldn't find an older version of the cst yet, so I can't try it at the 
moment.

Thanks!
Florian

[Header]
Version = 4.0
Hash Algorithm = sha256
Engine Configuration = 0
Certificate Format = X509
Signature Format = CMS
Engine = DCP

[Install SRK]
File = "$SRK_1_2_table.bin"
Source index = 0

[Install CSFK]
File = "$CSF1_1_sha256_2048_65537_v3_usr_crt.pem"

[Authenticate CSF]

[Install Key]
Verification index = 0
Target index = 2
File = "$IMG1_1_sha256_2048_65537_v3_usr_crt.pem"

[Authenticate Data]
Verification index = 2



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[U-Boot] [PATCH] pci: fix address range check in __pci_hose_phys_to_bus()

[Marcel Ziswiler]

The address range check may overflow if the memory region is located at
the top of the 32-bit address space. This can e.g. be seen on TK1 if
using the E1000 gigabit Ethernet driver where start and size are both
0x8000 leading to the following messages:

Apalis TK1 # tftpboot $loadaddr test_file
Using e1000#0 device
TFTP from server 192.168.10.1; our IP address is 192.168.10.2
Filename 'test_file'.
Load address: 0x80408000
Loading: pci_hose_phys_to_bus: invalid physical address

This patch fixes this by changing the order of the addition vs.
subtraction in the range check just like already done in
__pci_hose_bus_to_phys().

Reported-by: Ivan Mercier 
Signed-off-by: Marcel Ziswiler 
---

 drivers/pci/pci_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index a64792f..2a14902 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -268,7 +268,7 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
bus_addr = phys_addr - res->phys_start + res->bus_start;
 
if (bus_addr >= res->bus_start &&
-   bus_addr < res->bus_start + res->size) {
+   (bus_addr - res->bus_start) < res->size) {
*ba = bus_addr;
return 0;
}
-- 
2.5.0

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Re: [U-Boot] [PATCH v2 03/13] ns16550: add generic binding to unify the drivers

[Bin Meng]

On Wed, Nov 18, 2015 at 9:44 PM, Thomas Chou  wrote:
> Add generic binding to unify ns16550 drivers. There are
> several drivers using almost the same code, such as serial_dw,
> serial_keystone, serial_omap, serial_ppc, serial_rockchip,
> serial_tegra.c, and serial_x86. But each is platform specific.
>
> The key difference between these drivers is the way to get
> input clock frequency. With this unified approach, fixed clock
> frequency should be extracted from "clock-frequency" property of
> device tree blob. If this property is not available, the macro
> CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a
> function to get clock, eg, get_serial_clock().
>
> Signed-off-by: Thomas Chou 
> Reviewed-by: Tom Rini 
> ---
>  drivers/serial/Kconfig   | 11 +++
>  drivers/serial/ns16550.c | 44 
>  2 files changed, 55 insertions(+)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 2a50771..0f0e92d 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -195,6 +195,17 @@ config ROCKCHIP_SERIAL
>   your board config header. The clock input is automatically set to
>   use the oscillator (24MHz).
>
> +config NS16550_SERIAL
> +   bool "NS16550 UART or compatible"
> +   depends on DM_SERIAL
> +   help
> + Support NS16550 UART or compatible with driver model. This can be
> + enabled in the device tree with the correct input clock frequency.
> + If the input clock frequency is not defined in the device tree,
> + the macro CONFIG_SYS_NS16550_CLK defined in a legacy board header
> + file will be used. It can be a constant or a function to get clock,
> + eg, get_serial_clock().
> +
>  config SANDBOX_SERIAL
> bool "Sandbox UART support"
> depends on SANDBOX
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 8d028de..f0a9aac 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -56,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  #ifdef CONFIG_DM_SERIAL
>
> +#ifndef CONFIG_SYS_NS16550_CLK
> +#define CONFIG_SYS_NS16550_CLK  0
> +#endif
> +
>  static inline void serial_out_shift(void *addr, int shift, int value)
>  {
>  #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> @@ -400,6 +404,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice 
> *dev)
> plat->base = addr;
> plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>  "reg-shift", 1);
> +#ifdef CONFIG_NS16550_SERIAL
> +   plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> +"clock-frequency",
> +CONFIG_SYS_NS16550_CLK);
> +   if (!plat->clock) {
> +   debug("ns16550 clock not defined\n");
> +   return -EINVAL;
> +   }
> +#endif /* CONFIG_NS16550_SERIAL */
>
> return 0;
>  }
> @@ -411,4 +424,35 @@ const struct dm_serial_ops ns16550_serial_ops = {
> .getc = ns16550_serial_getc,
> .setbrg = ns16550_serial_setbrg,
>  };
> +
> +#ifdef CONFIG_NS16550_SERIAL
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> +static const struct udevice_id ns16550_serial_ids[] = {
> +   { .compatible = "ns16550" },
> +   { .compatible = "ns16550a" },
> +   { .compatible = "nvidia,tegra20-uart" },
> +   { .compatible = "snps,dw-apb-uart" },
> +   { .compatible = "ti,omap2-uart" },
> +   { .compatible = "ti,omap3-uart" },
> +   { .compatible = "ti,omap4-uart" },
> +   { .compatible = "ti,am3352-uart" },
> +   { .compatible = "ti,am4372-uart" },
> +   { .compatible = "ti,dra742-uart" },
> +   {}
> +};
> +#endif
> +
> +U_BOOT_DRIVER(ns16550_serial) = {
> +   .name   = "ns16550_serial",
> +   .id = UCLASS_SERIAL,
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> +   .of_match = ns16550_serial_ids,
> +   .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
> +   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
> +#endif
> +   .priv_auto_alloc_size = sizeof(struct NS16550),
> +   .probe = ns16550_serial_probe,
> +   .ops= _serial_ops,
> +};
> +#endif /* CONFIG_NS16550_SERIAL */
>  #endif /* CONFIG_DM_SERIAL */
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 00/10] nios2: change ioremap to map_physmem

[Thomas Chou]

On 2015年11月14日 13:59, Thomas Chou wrote:

Change ioremap() to map_physmem(,,MAP_NOCACHE), as it is more used
in u-boot. There are no other archs use ioremap(), except nios2.

Thomas Chou (10):
   altera_jtag_uart: change ioremap to map_physmem
   altera_uart: change ioremap to map_physmem
   altera_timer: change ioremap to map_physmem
   altera_spi: change ioremap to map_physmem
   altera_sysid: change ioremap to map_physmem
   altera_tse: change ioremap to map_physmem
   altera_qspi: change ioremap to map_physmem
   altera_pio: change ioremap to map_physmem
   nios2: dma-mapping.h: change ioremap to map_physmem
   nios2: zap ioremap

  arch/nios2/include/asm/dma-mapping.h | 2 +-
  arch/nios2/include/asm/io.h  | 6 --
  drivers/gpio/altera_pio.c| 5 +++--
  drivers/misc/altera_sysid.c  | 5 +++--
  drivers/mtd/altera_qspi.c| 2 +-
  drivers/net/altera_tse.c | 2 +-
  drivers/serial/altera_jtag_uart.c| 5 +++--
  drivers/serial/altera_uart.c | 5 +++--
  drivers/spi/altera_spi.c | 5 +++--
  drivers/timer/altera_timer.c | 5 +++--
  10 files changed, 21 insertions(+), 21 deletions(-)



Applied to u-boot-nios.
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Re: [U-Boot] [PATCH v0 1/5] pci: mvebu: Fix Armada 38x support

[Anton Schubert]

Am 18.11.2015 um 13:48 schrieb Dirk Eibach:
> I assume the idea is to go to the next port if the current port is
> disabled. But adding 3 to the index does not seem to be the right
> thing to do, since Armada XP has ports with 4 lanes, but also with
> ports with one lane.
> I assume that iterating over all lanes would not be a problem, but by
> mistake the pcie->lane == 0  was left in the condition. 
Yeah you are right. The additional condition was superfluous in the
original version.

> So this should perform better:
>
> /* Don't read at all from pci registers if port power is down */
> if (SELECT(soc_ctrl, pcie->port) == 0) {
> if (pcie->lane == 0)
> debug("%s: skipping port %d\n", __func__, pcie->port);
> continue;
> }
I agree.

Regards,
Anton
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Re: [U-Boot] [PATCH v2 11/13] ns16550: zap CONFIG_NS16550_SERIAL

[Thomas Chou]

Hi Bin,

On 2015年11月18日 22:09, Bin Meng wrote:

Hi Thomas,

On Wed, Nov 18, 2015 at 9:44 PM, Thomas Chou  wrote:

Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers
is completed.

Signed-off-by: Thomas Chou 
---
  configs/efi-x86_defconfig|  1 -
  drivers/serial/Kconfig   | 12 
  drivers/serial/ns16550.c |  4 
  include/configs/am43xx_evm.h |  2 --
  include/configs/cm_t43.h |  1 -
  include/configs/mv-common.h  |  4 
  include/configs/omap3_pandora.h  |  1 -
  include/configs/sniper.h |  4 +---
  include/configs/sunxi-common.h   |  4 +---
  include/configs/tb100.h  |  1 -
  include/configs/tegra-common.h   |  1 -
  include/configs/ti_am335x_common.h   |  4 
  include/configs/ti_armv7_keystone2.h |  2 --
  include/configs/ti_omap3_common.h|  4 
  include/configs/ti_omap4_common.h|  2 --
  include/configs/ti_omap5_common.h|  2 --
  16 files changed, 2 insertions(+), 47 deletions(-)

diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index b1573df..904b564 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -3,7 +3,6 @@ CONFIG_VENDOR_EFI=y
  CONFIG_DEFAULT_DEVICE_TREE="efi"
  CONFIG_TARGET_EFI=y
  CONFIG_TSC_CALIBRATION_BYPASS=y
-# CONFIG_NS16550_SERIAL is not set


This line should not be removed.


The CONFIG_NS16550_SERIAL is used only during the transition and it is 
removed now. It does not need this for efi serial to work.


Thank you again for the review.

Best regards,
Thomas
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[U-Boot] [PATCH v2 07/13] ns16550: unify serial_keystone

[Thomas Chou]

Unify serial_keystone, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 configs/k2g_evm_defconfig|  1 -
 drivers/serial/Makefile  |  1 -
 drivers/serial/serial_keystone.c | 48 
 include/configs/ti_armv7_keystone2.h |  2 +-
 4 files changed, 1 insertion(+), 51 deletions(-)
 delete mode 100644 drivers/serial/serial_keystone.c

diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 59020af..c6efe80 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -11,4 +11,3 @@ CONFIG_SPL_DISABLE_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
-CONFIG_KEYSTONE_SERIAL=y
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index debc175..1663ca2 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
-obj-$(CONFIG_KEYSTONE_SERIAL) += serial_keystone.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
diff --git a/drivers/serial/serial_keystone.c b/drivers/serial/serial_keystone.c
deleted file mode 100644
index 7b5ab6c..000
--- a/drivers/serial/serial_keystone.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2015 Texas Instruments, 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id keystone_serial_ids[] = {
-   { .compatible = "ti,keystone-uart" },
-   { .compatible = "ns16550a" },
-   { }
-};
-
-static int keystone_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-   plat->clock = CONFIG_SYS_NS16550_CLK;
-   return 0;
-}
-#endif
-
-U_BOOT_DRIVER(serial_keystone_ns16550) = {
-   .name   = "serial_keystone",
-   .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-   .of_match = of_match_ptr(keystone_serial_ids),
-   .ofdata_to_platdata = of_match_ptr(keystone_serial_ofdata_to_platdata),
-   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
-   .priv_auto_alloc_size = sizeof(struct NS16550),
-   .probe = ns16550_serial_probe,
-   .ops= _serial_ops,
-   .flags  = DM_FLAG_PRE_RELOC,
-};
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index ed86561..5ab9b6e 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -64,7 +64,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE-4
 #else
-#define CONFIG_KEYSTONE_SERIAL
+#define CONFIG_NS16550_SERIAL
 #endif
 #define CONFIG_SYS_NS16550_COM1KS2_UART0_BASE
 #define CONFIG_SYS_NS16550_COM2KS2_UART1_BASE
-- 
2.5.0

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[U-Boot] [PATCH v2 10/13] ns16550: unify serial_omap

[Thomas Chou]

Unify serial_omap, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 board/isee/igep00x0/igep00x0.c  |  2 +-
 board/lge/sniper/sniper.c   |  2 +-
 board/logicpd/omap3som/omap3logic.c |  2 +-
 board/logicpd/zoom1/zoom1.c |  2 +-
 board/overo/overo.c |  2 +-
 board/quipos/cairo/cairo.c  |  2 +-
 board/ti/beagle/beagle.c|  2 +-
 board/timll/devkit8000/devkit8000.c |  2 +-
 drivers/serial/Makefile |  1 -
 drivers/serial/serial_omap.c| 54 -
 include/configs/am43xx_evm.h|  4 +--
 include/configs/cm_t43.h|  2 +-
 include/configs/omap3_pandora.h |  3 ++-
 include/configs/sniper.h|  4 +--
 include/configs/ti_am335x_common.h  |  2 +-
 include/configs/ti_omap3_common.h   |  4 +--
 include/configs/ti_omap4_common.h   |  4 +--
 include/configs/ti_omap5_common.h   |  4 +--
 18 files changed, 22 insertions(+), 76 deletions(-)
 delete mode 100644 drivers/serial/serial_omap.c

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 044c6d5..57b89e0 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -40,7 +40,7 @@ static const struct ns16550_platdata igep_serial = {
 };
 
 U_BOOT_DEVICE(igep_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c
index 4eff01a..c818c9d 100644
--- a/board/lge/sniper/sniper.c
+++ b/board/lge/sniper/sniper.c
@@ -35,7 +35,7 @@ static const struct ns16550_platdata serial_omap_platdata = {
 };
 
 U_BOOT_DEVICE(sniper_serial) = {
-   .name = "serial_omap",
+   .name = "ns16550_serial",
.platdata = _omap_platdata
 };
 
diff --git a/board/logicpd/omap3som/omap3logic.c 
b/board/logicpd/omap3som/omap3logic.c
index babb0dc..fb89921 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -43,7 +43,7 @@ static const struct ns16550_platdata omap3logic_serial = {
 };
 
 U_BOOT_DEVICE(omap3logic_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 0a3b55b..4040114 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -50,7 +50,7 @@ static const struct ns16550_platdata zoom1_serial = {
 };
 
 U_BOOT_DEVICE(zoom1_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 20cbec2..a38b959 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -74,7 +74,7 @@ static const struct ns16550_platdata overo_serial = {
 };
 
 U_BOOT_DEVICE(overo_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index b97a09a..21793e8 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -97,7 +97,7 @@ static const struct ns16550_platdata cairo_serial = {
 };
 
 U_BOOT_DEVICE(cairo_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 56e3cfe..ff317ef 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -79,7 +79,7 @@ static const struct ns16550_platdata beagle_serial = {
 };
 
 U_BOOT_DEVICE(beagle_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/board/timll/devkit8000/devkit8000.c 
b/board/timll/devkit8000/devkit8000.c
index a61cc14..1a447c7 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -52,7 +52,7 @@ static const struct ns16550_platdata devkit8000_serial = {
 };
 
 U_BOOT_DEVICE(devkit8000_uart) = {
-   "serial_omap",
+   "ns16550_serial",
_serial
 };
 
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 86ae50f..dd87147 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
-obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
deleted file mode 100644
index 891cd7b..000
--- a/drivers/serial/serial_omap.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEFAULT_CLK_SPEED 4800 /* 48Mhz */
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id omap_serial_ids[] = {
-   { .compatible = "ti,omap2-uart" },
-   

[U-Boot] [PATCH v2 08/13] ns16550: unify serial_dw

[Thomas Chou]

Unify serial_dw, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 drivers/serial/Makefile|  1 -
 drivers/serial/serial_dw.c | 39 ---
 include/configs/mv-common.h|  2 +-
 include/configs/sunxi-common.h |  2 +-
 include/configs/tb100.h|  2 +-
 5 files changed, 3 insertions(+), 43 deletions(-)
 delete mode 100644 drivers/serial/serial_dw.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 1663ca2..2a83756 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
-obj-$(CONFIG_DW_SERIAL) += serial_dw.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c
deleted file mode 100644
index a348f29..000
--- a/drivers/serial/serial_dw.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-static const struct udevice_id dw_serial_ids[] = {
-   { .compatible = "snps,dw-apb-uart" },
-   { }
-};
-
-static int dw_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-   plat->clock = CONFIG_SYS_NS16550_CLK;
-
-   return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
-   .name   = "serial_dw",
-   .id = UCLASS_SERIAL,
-   .of_match = dw_serial_ids,
-   .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
-   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-   .priv_auto_alloc_size = sizeof(struct NS16550),
-   .probe = ns16550_serial_probe,
-   .ops= _serial_ops,
-};
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 1ecbd35..0e33a89 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -40,7 +40,7 @@
  * NS16550 Configuration
  */
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
-#define CONFIG_DW_SERIAL
+#define CONFIG_NS16550_SERIAL
 #endif
 
 #define CONFIG_SYS_NS16550
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index f5db4d3..ab584ac 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -46,7 +46,7 @@
 /* ns16550 reg in the low bits of cpu reg */
 #define CONFIG_SYS_NS16550_CLK 2400
 #ifdef CONFIG_DM_SERIAL
-# define CONFIG_DW_SERIAL
+# define CONFIG_NS16550_SERIAL
 #else
 # define CONFIG_SYS_NS16550_REG_SIZE   -4
 # define CONFIG_SYS_NS16550_COM1   SUNXI_UART0_BASE
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index e3c41ef..44287d8 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -35,7 +35,7 @@
 /*
  * UART configuration
  */
-#define CONFIG_DW_SERIAL
+#define CONFIG_NS16550_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_CLK 1
-- 
2.5.0

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[U-Boot] [PATCH v2 13/13] nios2: 10m50: change to ns16550 uart

[Thomas Chou]

Change to ns16550 uart for 10m50 devboard based on a new
Altera release.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 arch/nios2/dts/10m50_devboard.dts | 2 +-
 configs/10m50_defconfig   | 2 +-
 include/configs/10m50_devboard.h  | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/nios2/dts/10m50_devboard.dts 
b/arch/nios2/dts/10m50_devboard.dts
index e89dbb2..05eac30 100644
--- a/arch/nios2/dts/10m50_devboard.dts
+++ b/arch/nios2/dts/10m50_devboard.dts
@@ -262,6 +262,6 @@
 
chosen {
bootargs = "debug console=ttyS0,115200";
-   stdout-path = _0;
+   stdout-path = _16550_uart_0;
};
 };
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index af2cef7..9e858bc 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -21,6 +21,6 @@ CONFIG_MTD=y
 CONFIG_ALTERA_QSPI=y
 CONFIG_DM_ETH=y
 CONFIG_ALTERA_TSE=y
-CONFIG_ALTERA_UART=y
+CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_ALTERA_TIMER=y
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index ab7dd08..715b1b4 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -20,6 +20,7 @@
  */
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* Suppress console info */
+#define CONFIG_SYS_NS16550_MEM32
 
 /*
  * Flash
-- 
2.5.0

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[U-Boot] [PATCH v2 06/13] ns16550: unify serial_rockchip

[Thomas Chou]

Unify serial_rockchip, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 arch/arm/dts/rk3288.dtsi |  5 +
 arch/arm/mach-rockchip/Kconfig   |  3 ---
 drivers/serial/Kconfig   | 11 +-
 drivers/serial/Makefile  |  1 -
 drivers/serial/serial_rockchip.c | 43 
 5 files changed, 6 insertions(+), 57 deletions(-)
 delete mode 100644 drivers/serial/serial_rockchip.c

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 0f49709..ac367f8 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -324,6 +324,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
+   clock-frequency = <2400>;
clocks = < SCLK_UART0>, < PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -337,6 +338,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
+   clock-frequency = <2400>;
clocks = < SCLK_UART1>, < PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -350,6 +352,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
+   clock-frequency = <2400>;
clocks = < SCLK_UART2>, < PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -362,6 +365,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
+   clock-frequency = <2400>;
clocks = < SCLK_UART3>, < PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -375,6 +379,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
+   clock-frequency = <2400>;
clocks = < SCLK_UART4>, < PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ab50f4e..3f7dc8e 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -33,9 +33,6 @@ config DM_I2C
 config DM_GPIO
default y
 
-config ROCKCHIP_SERIAL
-   default y
-
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 
 endif
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b41f508..1239416 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -186,19 +186,10 @@ config ALTERA_UART
  Select this to enable an UART for Altera devices. Please find
  details on the "Embedded Peripherals IP User Guide" of Altera.
 
-config ROCKCHIP_SERIAL
-   bool "Rockchip on-chip UART support"
-   depends on ARCH_ROCKCHIP && DM_SERIAL
-   help
- Select this to enable a debug UART for Rockchip devices. This uses
- the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
- your board config header. The clock input is automatically set to
- use the oscillator (24MHz).
-
 config NS16550_SERIAL
bool "NS16550 UART or compatible"
depends on DM_SERIAL
-   default y if X86 || PPC
+   default y if X86 || PPC || ARCH_ROCKCHIP
help
  Support NS16550 UART or compatible with driver model. This can be
  enabled in the device tree with the correct input clock frequency.
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9f61113..debc175 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
-obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
deleted file mode 100644
index 0e7bbfc..000
--- a/drivers/serial/serial_rockchip.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static const struct udevice_id rockchip_serial_ids[] = {
-   { .compatible = "rockchip,rk3288-uart" },
-   { }
-};
-
-static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-
-   /* Do all Rockchip parts use 24MHz? */
-   

[U-Boot] [PATCH v2 11/13] ns16550: zap CONFIG_NS16550_SERIAL

[Thomas Chou]

Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers
is completed.

Signed-off-by: Thomas Chou 
---
 configs/efi-x86_defconfig|  1 -
 drivers/serial/Kconfig   | 12 
 drivers/serial/ns16550.c |  4 
 include/configs/am43xx_evm.h |  2 --
 include/configs/cm_t43.h |  1 -
 include/configs/mv-common.h  |  4 
 include/configs/omap3_pandora.h  |  1 -
 include/configs/sniper.h |  4 +---
 include/configs/sunxi-common.h   |  4 +---
 include/configs/tb100.h  |  1 -
 include/configs/tegra-common.h   |  1 -
 include/configs/ti_am335x_common.h   |  4 
 include/configs/ti_armv7_keystone2.h |  2 --
 include/configs/ti_omap3_common.h|  4 
 include/configs/ti_omap4_common.h|  2 --
 include/configs/ti_omap5_common.h|  2 --
 16 files changed, 2 insertions(+), 47 deletions(-)

diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index b1573df..904b564 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -3,7 +3,6 @@ CONFIG_VENDOR_EFI=y
 CONFIG_DEFAULT_DEVICE_TREE="efi"
 CONFIG_TARGET_EFI=y
 CONFIG_TSC_CALIBRATION_BYPASS=y
-# CONFIG_NS16550_SERIAL is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_NET is not set
 CONFIG_OF_CONTROL=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1239416..fe407b7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -186,18 +186,6 @@ config ALTERA_UART
  Select this to enable an UART for Altera devices. Please find
  details on the "Embedded Peripherals IP User Guide" of Altera.
 
-config NS16550_SERIAL
-   bool "NS16550 UART or compatible"
-   depends on DM_SERIAL
-   default y if X86 || PPC || ARCH_ROCKCHIP
-   help
- Support NS16550 UART or compatible with driver model. This can be
- enabled in the device tree with the correct input clock frequency.
- If the input clock frequency is not defined in the device tree,
- the macro CONFIG_SYS_NS16550_CLK defined in a legacy board header
- file will be used. It can be a constant or a function to get clock,
- eg, get_serial_clock().
-
 config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f0a9aac..d5bcbc3 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -404,7 +404,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 "reg-shift", 1);
-#ifdef CONFIG_NS16550_SERIAL
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 "clock-frequency",
 CONFIG_SYS_NS16550_CLK);
@@ -412,7 +411,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
debug("ns16550 clock not defined\n");
return -EINVAL;
}
-#endif /* CONFIG_NS16550_SERIAL */
 
return 0;
 }
@@ -425,7 +423,6 @@ const struct dm_serial_ops ns16550_serial_ops = {
.setbrg = ns16550_serial_setbrg,
 };
 
-#ifdef CONFIG_NS16550_SERIAL
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ns16550" },
@@ -454,5 +451,4 @@ U_BOOT_DRIVER(ns16550_serial) = {
.probe = ns16550_serial_probe,
.ops= _serial_ops,
 };
-#endif /* CONFIG_NS16550_SERIAL */
 #endif /* CONFIG_DM_SERIAL */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a962bf5..75b8f53 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -27,8 +27,6 @@
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
-#else
-#define CONFIG_NS16550_SERIAL
 #endif
 
 /* I2C Configuration */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index e1019ff..f8c39bf 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -18,7 +18,6 @@
 #include 
 
 /* Serial support */
-#define CONFIG_NS16550_SERIAL
 #define CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 0e33a89..575e53e 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -39,10 +39,6 @@
 /*
  * NS16550 Configuration
  */
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
-#define CONFIG_NS16550_SERIAL
-#endif
-
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index c15c699..803f4b8 100644
--- a/include/configs/omap3_pandora.h
+++ 

Re: [U-Boot] [PATCH 07/12] ns16550: unify serial_rockchip

[Ariel D'Alessandro]

Hi Thomas,

El 16/11/15 a las 21:35, Thomas Chou escribió:
> Hi Ariel,
> 
> On 2015年11月16日 22:36, Thomas Chou wrote:
>> Unify serial_rockchip, and use the generic binding.
>>
>> Signed-off-by: Thomas Chou 
>> ---
>>   arch/arm/mach-rockchip/Kconfig   |  8 +++-
>>   drivers/serial/Kconfig   |  9 -
>>   drivers/serial/Makefile  |  1 -
>>   drivers/serial/serial_rockchip.c | 43
>> 
>>   4 files changed, 7 insertions(+), 54 deletions(-)
>>   delete mode 100644 drivers/serial/serial_rockchip.c
>>
> 
> Please check this series. Though I run buildman, I don't have a rockchip
> board to test. Thanks.

Successfully tested on a Firefly RK3288 board.

Tested-by: Ariel D'Alessandro 

-- 
Ariel D'Alessandro, VanguardiaSur
www.vanguardiasur.com.ar
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Re: [U-Boot] [PATCH] pci: fix address range check in __pci_hose_phys_to_bus()

[Bin Meng]

On Wed, Nov 18, 2015 at 10:05 PM, Marcel Ziswiler
 wrote:
> The address range check may overflow if the memory region is located at
> the top of the 32-bit address space. This can e.g. be seen on TK1 if
> using the E1000 gigabit Ethernet driver where start and size are both
> 0x8000 leading to the following messages:
>
> Apalis TK1 # tftpboot $loadaddr test_file
> Using e1000#0 device
> TFTP from server 192.168.10.1; our IP address is 192.168.10.2
> Filename 'test_file'.
> Load address: 0x80408000
> Loading: pci_hose_phys_to_bus: invalid physical address
>
> This patch fixes this by changing the order of the addition vs.
> subtraction in the range check just like already done in
> __pci_hose_bus_to_phys().
>
> Reported-by: Ivan Mercier 
> Signed-off-by: Marcel Ziswiler 
> ---
>
>  drivers/pci/pci_common.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
> index a64792f..2a14902 100644
> --- a/drivers/pci/pci_common.c
> +++ b/drivers/pci/pci_common.c
> @@ -268,7 +268,7 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
> bus_addr = phys_addr - res->phys_start + res->bus_start;
>
> if (bus_addr >= res->bus_start &&
> -   bus_addr < res->bus_start + res->size) {
> +   (bus_addr - res->bus_start) < res->size) {
> *ba = bus_addr;
> return 0;
> }
> --

Reviewed-by: Bin Meng 
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[U-Boot] [PATCH v2 04/13] ns16550: unify serial_x86

[Thomas Chou]

Unify serial_x86, and use the generic binding.

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 arch/x86/dts/serial.dtsi|  2 +-
 configs/efi-x86_defconfig   |  2 +-
 drivers/serial/Kconfig  | 11 +--
 drivers/serial/Makefile |  1 -
 drivers/serial/serial_x86.c | 44 
 5 files changed, 3 insertions(+), 57 deletions(-)
 delete mode 100644 drivers/serial/serial_x86.c

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 6865eed..54c3faf 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,6 +1,6 @@
 / {
serial: serial {
-   compatible = "x86-uart";
+   compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
clock-frequency = <1843200>;
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 43fb0c4..b1573df 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_EFI=y
 CONFIG_DEFAULT_DEVICE_TREE="efi"
 CONFIG_TARGET_EFI=y
 CONFIG_TSC_CALIBRATION_BYPASS=y
+# CONFIG_NS16550_SERIAL is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_NET is not set
 CONFIG_OF_CONTROL=y
@@ -12,5 +13,4 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_EFI_CONSOLE=y
 CONFIG_DEBUG_UART_BASE=0
 CONFIG_DEBUG_UART_CLOCK=0
-# CONFIG_X86_SERIAL is not set
 CONFIG_EFI=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 0f0e92d..93faa4c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -198,6 +198,7 @@ config ROCKCHIP_SERIAL
 config NS16550_SERIAL
bool "NS16550 UART or compatible"
depends on DM_SERIAL
+   default y if X86
help
  Support NS16550 UART or compatible with driver model. This can be
  enabled in the device tree with the correct input clock frequency.
@@ -233,14 +234,4 @@ config UNIPHIER_SERIAL
  If you have a UniPhier based board and want to use the on-chip
  serial ports, say Y to this option. If unsure, say N.
 
-config X86_SERIAL
-   bool "Support for 16550 serial port on x86 machines"
-   depends on X86
-   default y
-   help
- Most x86 machines have a ns16550 UART or compatible. This can be
- enabled in the device tree with the correct input clock frequency
- provided (default 1843200). Enable this to obtain serial console
- output.
-
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 1818c7c..9036a8e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_X86_SERIAL) += serial_x86.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
deleted file mode 100644
index 4bf6062..000
--- a/drivers/serial/serial_x86.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct udevice_id x86_serial_ids[] = {
-   { .compatible = "x86-uart" },
-   { }
-};
-
-static int x86_serial_ofdata_to_platdata(struct udevice *dev)
-{
-   struct ns16550_platdata *plat = dev_get_platdata(dev);
-   int ret;
-
-   ret = ns16550_serial_ofdata_to_platdata(dev);
-   if (ret)
-   return ret;
-
-   plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-"clock-frequency", 1843200);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
-   .name   = "serial_x86",
-   .id = UCLASS_SERIAL,
-   .of_match = x86_serial_ids,
-   .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
-   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-   .priv_auto_alloc_size = sizeof(struct NS16550),
-   .probe = ns16550_serial_probe,
-   .ops= _serial_ops,
-};
-- 
2.5.0

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[U-Boot] [PATCH v2 03/13] ns16550: add generic binding to unify the drivers

[Thomas Chou]

Add generic binding to unify ns16550 drivers. There are
several drivers using almost the same code, such as serial_dw,
serial_keystone, serial_omap, serial_ppc, serial_rockchip,
serial_tegra.c, and serial_x86. But each is platform specific.

The key difference between these drivers is the way to get
input clock frequency. With this unified approach, fixed clock
frequency should be extracted from "clock-frequency" property of
device tree blob. If this property is not available, the macro
CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a
function to get clock, eg, get_serial_clock().

Signed-off-by: Thomas Chou 
Reviewed-by: Tom Rini 
---
 drivers/serial/Kconfig   | 11 +++
 drivers/serial/ns16550.c | 44 
 2 files changed, 55 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2a50771..0f0e92d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -195,6 +195,17 @@ config ROCKCHIP_SERIAL
  your board config header. The clock input is automatically set to
  use the oscillator (24MHz).
 
+config NS16550_SERIAL
+   bool "NS16550 UART or compatible"
+   depends on DM_SERIAL
+   help
+ Support NS16550 UART or compatible with driver model. This can be
+ enabled in the device tree with the correct input clock frequency.
+ If the input clock frequency is not defined in the device tree,
+ the macro CONFIG_SYS_NS16550_CLK defined in a legacy board header
+ file will be used. It can be a constant or a function to get clock,
+ eg, get_serial_clock().
+
 config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8d028de..f0a9aac 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -56,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_DM_SERIAL
 
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK  0
+#endif
+
 static inline void serial_out_shift(void *addr, int shift, int value)
 {
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
@@ -400,6 +404,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 "reg-shift", 1);
+#ifdef CONFIG_NS16550_SERIAL
+   plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+"clock-frequency",
+CONFIG_SYS_NS16550_CLK);
+   if (!plat->clock) {
+   debug("ns16550 clock not defined\n");
+   return -EINVAL;
+   }
+#endif /* CONFIG_NS16550_SERIAL */
 
return 0;
 }
@@ -411,4 +424,35 @@ const struct dm_serial_ops ns16550_serial_ops = {
.getc = ns16550_serial_getc,
.setbrg = ns16550_serial_setbrg,
 };
+
+#ifdef CONFIG_NS16550_SERIAL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id ns16550_serial_ids[] = {
+   { .compatible = "ns16550" },
+   { .compatible = "ns16550a" },
+   { .compatible = "nvidia,tegra20-uart" },
+   { .compatible = "snps,dw-apb-uart" },
+   { .compatible = "ti,omap2-uart" },
+   { .compatible = "ti,omap3-uart" },
+   { .compatible = "ti,omap4-uart" },
+   { .compatible = "ti,am3352-uart" },
+   { .compatible = "ti,am4372-uart" },
+   { .compatible = "ti,dra742-uart" },
+   {}
+};
+#endif
+
+U_BOOT_DRIVER(ns16550_serial) = {
+   .name   = "ns16550_serial",
+   .id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+   .of_match = ns16550_serial_ids,
+   .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+#endif
+   .priv_auto_alloc_size = sizeof(struct NS16550),
+   .probe = ns16550_serial_probe,
+   .ops= _serial_ops,
+};
+#endif /* CONFIG_NS16550_SERIAL */
 #endif /* CONFIG_DM_SERIAL */
-- 
2.5.0

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[U-Boot] [PATCH v2 02/13] ns16550: change map_sysmem to map_physmem

[Thomas Chou]

Change map_sysmem() to map_physmem(), because sandbox is the only
arch which define map_sysmem() and it actually only calls
map_physmem(). For some arch like nios2, the flag should be
MAP_NOCACHE for port access.

Signed-off-by: Thomas Chou 
---
 drivers/serial/ns16550.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 6433844..8d028de 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -8,7 +8,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -97,7 +96,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int 
value)
unsigned char *addr;
 
offset *= 1 << plat->reg_shift;
-   addr = map_sysmem(plat->base, 0) + offset;
+   addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
/*
 * As far as we know it doesn't make sense to support selection of
 * these options at run-time, so use the existing CONFIG options.
@@ -111,7 +110,7 @@ static int ns16550_readb(NS16550_t port, int offset)
unsigned char *addr;
 
offset *= 1 << plat->reg_shift;
-   addr = map_sysmem(plat->base, 0) + offset;
+   addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
 
return serial_in_shift(addr, plat->reg_shift);
 }
-- 
2.5.0

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[U-Boot] [PATCH v2 01/13] debug_uart: restore ns16550 as default

[Thomas Chou]

Since commit 220e8021af96 ("nios2: convert altera_jtag_uart to
driver model"), the default debug uart was changed. Most people
use ns16550 UART, so restore it as default.

Signed-off-by: Thomas Chou 
Reported-by: Ezequiel Garcia 
Reported-by: Ariel D'Alessandro 
Reviewed-by: Tom Rini 
---
 drivers/serial/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index eba96f4..2a50771 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -53,6 +53,7 @@ config DEBUG_UART
 choice
prompt "Select which UART will provide the debug UART"
depends on DEBUG_UART
+   default DEBUG_UART_NS16550
 
 config DEBUG_UART_ALTERA_JTAGUART
bool "Altera JTAG UART"
-- 
2.5.0

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Re: [U-Boot] [PATCH V2 06/12] board: keymile: Move common headers to board-common directory

[Valentin Longchamp]

On 13/11/2015 06:43, Nishanth Menon wrote:
> Header files can be located in a generic location without
> needing to reference them with ../common/
> 
> Generated with the following script
> 
>  #!/bin/bash
> vendor=board/keymile
> common=$vendor/common
> 
> cfiles=`git grep "../common" $vendor|grep "#include"|cut -d '"' -f2|sort 
> -u|grep c$`
> headers=`git grep "../common" $vendor|grep "#include"|cut -d '"' -f2|sort 
> -u|grep h$`
> 
> mkdir -p $common/include/board-common
> set -x
> for header in $headers
> do
>   echo "processing $header in $common"
>   hbase=`basename $header`
>   git mv $common/$hbase $common/include/board-common
>   sed -i -e "s/\"..\/common\/$hbase\"//g" 
> $vendor/*/*.[chS]
>   sed -i -e "s/\"$hbase\"//g" $vendor/common/*.[chS]
> done
> 
> Cc: Valentin Longchamp 
> Cc: Holger Brunck 
> 
> Signed-off-by: Nishanth Menon 

This was successfully tested on several Keymile boards and it is good that the
Keymile boards also follow this new board/common include scheme.

Acked-by: Valentin Longchamp 

> ---
>  board/keymile/common/common.c| 2 +-
>  board/keymile/common/{ => include/board-common}/common.h | 0
>  board/keymile/common/ivm.c   | 2 +-
>  board/keymile/km82xx/km82xx.c| 2 +-
>  board/keymile/km83xx/km83xx.c| 2 +-
>  board/keymile/km83xx/km83xx_i2c.c| 2 +-
>  board/keymile/km_arm/km_arm.c| 2 +-
>  board/keymile/kmp204x/kmp204x.c  | 2 +-
>  board/keymile/kmp204x/qrio.c | 2 +-
>  9 files changed, 8 insertions(+), 8 deletions(-)
>  rename board/keymile/common/{ => include/board-common}/common.h (100%)
> 
> diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
> index b9aff1a84dcb..4f8b68ee5ccd 100644
> --- a/board/keymile/common/common.c
> +++ b/board/keymile/common/common.c
> @@ -21,7 +21,7 @@
>  #if defined(CONFIG_POST)
>  #include "post.h"
>  #endif
> -#include "common.h"
> +#include 
>  #include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
> diff --git a/board/keymile/common/common.h 
> b/board/keymile/common/include/board-common/common.h
> similarity index 100%
> rename from board/keymile/common/common.h
> rename to board/keymile/common/include/board-common/common.h
> diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
> index 42db54221bb3..4d2963ad5f84 100644
> --- a/board/keymile/common/ivm.c
> +++ b/board/keymile/common/ivm.c
> @@ -8,7 +8,7 @@
>  #include 
>  #include 
>  #include 
> -#include "common.h"
> +#include 
>  
>  #define MAC_STR_SZ   20
>  
> diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
> index c599b4093626..73d22dc6ac19 100644
> --- a/board/keymile/km82xx/km82xx.c
> +++ b/board/keymile/km82xx/km82xx.c
> @@ -16,7 +16,7 @@
>  #endif
>  
>  #include 
> -#include "../common/common.h"
> +#include 
>  
>  static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
>  
> diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
> index 89e9e1e57c38..83deca56aebc 100644
> --- a/board/keymile/km83xx/km83xx.c
> +++ b/board/keymile/km83xx/km83xx.c
> @@ -26,7 +26,7 @@
>  #include 
>  #include 
>  
> -#include "../common/common.h"
> +#include 
>  
>  static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
>  
> diff --git a/board/keymile/km83xx/km83xx_i2c.c 
> b/board/keymile/km83xx/km83xx_i2c.c
> index c961937530ac..e702a5cf86e2 100644
> --- a/board/keymile/km83xx/km83xx_i2c.c
> +++ b/board/keymile/km83xx/km83xx_i2c.c
> @@ -9,7 +9,7 @@
>  #include 
>  #include 
>  #include 
> -#include "../common/common.h"
> +#include 
>  
>  static void i2c_write_start_seq(void)
>  {
> diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
> index 2938861f368f..82fa31c2208d 100644
> --- a/board/keymile/km_arm/km_arm.c
> +++ b/board/keymile/km_arm/km_arm.c
> @@ -23,7 +23,7 @@
>  #include 
>  #include 
>  
> -#include "../common/common.h"
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
> index eebb47fc21f1..fbe6d98af6ce 100644
> --- a/board/keymile/kmp204x/kmp204x.c
> +++ b/board/keymile/kmp204x/kmp204x.c
> @@ -21,7 +21,7 @@
>  #include 
>  #include 
>  
> -#include "../common/common.h"
> +#include 
>  #include "kmp204x.h"
>  
>  DECLARE_GLOBAL_DATA_PTR;
> diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
> index edf3bf11a894..a4c25e084846 100644
> --- a/board/keymile/kmp204x/qrio.c
> +++ b/board/keymile/kmp204x/qrio.c
> @@ -7,7 +7,7 @@
>  
>  #include 
>  
> -#include "../common/common.h"
> +#include 
>  #include "kmp204x.h"
>  
>  /* QRIO GPIO register offsets */
> 

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Re: [U-Boot] [U-Boot, V4, 10/13] spl: add support for alternative boot device

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:51PM +0200, Nikita Kiryanov wrote:

> Introduce spl_boot_list array, which defines a list of boot devices
> that SPL will try before hanging. By default this list will consist
> of only spl_boot_device(), but board_boot_order() can be overridden
> by board code to populate the array with custom values.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

So, a problem with this patch is that we push the x600 board, which is
an 8KiB SPL target, over the line.  I feel like maybe we need a
follow-up patch that makes announcing depend not on libcommon (which
x600 needs) but something else to know that there's a reason to
announce.

-- 
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Re: [U-Boot] tools/env: allow config filename to be passed via command line argument

[Tom Rini]

On Tue, Oct 27, 2015 at 10:34:49PM +0100, Michael Heimpold wrote:

> When for example generating/manipulating SD card/eMMC images which
> contain U-Boot and its environment(s), it is handy to use a given
> configuration file instead of the compiled-in default one.
> And since the default configuration file is expected under /etc
> it's hard for an usual linux user account without special permissions
> to use fw_printenv/fw_setenv for this purpose.
> So allow to pass an optional filename via a new '-c' command
> line argument.
> 
> Example:
> 
> $ ln -s fw_printenv tools/env/fw_setenv
> $ cat fw_env.config
> test.img 0x2 0x2
> test.img 0x4 0x2
> 
> $ tools/env/fw_printenv -c ./fw_env.config fdt_file
> fdt_file=imx28-duckbill.dtb
> 
> $ tools/env/fw_setenv -c ./fw_env.config fdt_file imx28-duckbill-spi.dtb
> 
> $ tools/env/fw_printenv -c ./fw_env.config fdt_file
> fdt_file=imx28-duckbill-spi.dtb
> 
> Signed-off-by: Michael Heimpold 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, 2/2] itest: add missing break statements to evalexp()

[Tom Rini]

On Tue, Nov 17, 2015 at 10:29:08AM -0700, Stephen Warren wrote:

> From: Stephen Warren 
> 
> The commit mentioned below replaced return statements inside a switch so
> that other code could be called after the switch. However, it didn't add
> any break statements, causing the cases to run together. Fix this.
> 
> Reported-by: Coverity (CID 132282, 132283)
> Fixes: 7861204c9af7 ("itest: make memory access work under sandbox")
> Signed-off-by: Stephen Warren 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 15/15] km/powerpc: fix ft_board_setup prototype for km82xx & km83xx

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:38AM +0100, Valentin Longchamp wrote:

> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 10/15] powerpc/km8360: fix the ODT parameters for CS0

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:33AM +0100, Valentin Longchamp wrote:

> The ODT parameters for km8360 set the ODT_WR_ACS bit in u-boot KM-2011.09
> that is used in the release bootpackage for kmcoge5ne. During the
> transition from the kmeter1 to km8360 this was changed to
> ODT_RD_ONLY_CURRENT, which is uncorrect and causes faulty RAM accesses at
> low temperatures.
> 
> This is now changed to ODT_WR_ONLY_CURRENT which is the equivalent of
> ODT_WR_ACS.
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 14/15] powerpc/83xx: add support for kmtegr1 board

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:37AM +0100, Valentin Longchamp wrote:

> This board uses the same CPU (8309) as VECT1. The memory however is
> different since it has NAND Flash, the NOR Flash partitioning is
> different and of course the FPGAs as well.
> 
> Signed-off-by: Valentin Longchamp 
> Signed-off-by: Christoph Dietrich 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH] ARM: tegra: refactor common Kconfig options

[Stephen Warren]

From: Stephen Warren 

This makes it easier to select common options in a single place, rather
than having to add them separately for different SoCs or architectures.

The lists of select statements are now also sorted for easy searching.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/Kconfig | 36 +++-
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a5b7e0d22d29..d2ca376d23f6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,17 +1,26 @@
 if TEGRA
 
-config TEGRA_ARMV7_COMMON
-   bool "Tegra 32-bit"
-   select SUPPORT_SPL
-   select SPL
-   select OF_CONTROL
-   select CPU_V7
+config TEGRA_COMMON
+   bool "Tegra common options"
select DM
-   select DM_SPI_FLASH
-   select DM_SERIAL
+   select DM_GPIO
select DM_I2C
+   select DM_SERIAL
select DM_SPI
-   select DM_GPIO
+   select DM_SPI_FLASH
+   select OF_CONTROL
+
+config TEGRA_ARMV7_COMMON
+   bool "Tegra 32-bit common options"
+   select CPU_V7
+   select SPL
+   select SUPPORT_SPL
+   select TEGRA_COMMON
+
+config TEGRA_ARMV8_COMMON
+   bool "Tegra 64-bit common options"
+   select ARM64
+   select TEGRA_COMMON
 
 choice
prompt "Tegra SoC select"
@@ -35,14 +44,7 @@ config TEGRA124
 
 config TEGRA210
bool "Tegra210 family"
-   select OF_CONTROL
-   select ARM64
-   select DM
-   select DM_SPI_FLASH
-   select DM_SERIAL
-   select DM_I2C
-   select DM_SPI
-   select DM_GPIO
+   select TEGRA_ARMV8_COMMON
 
 endchoice
 
-- 
1.9.1

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Re: [U-Boot] [PATCH v5] Fix board init code to respect the C runtime environment

[Simon Glass]

Hi Albert,

On 17 November 2015 at 05:59, Albert ARIBAUD  wrote:
> Hello Simon,
>
> On Mon, 16 Nov 2015 21:11:38 -0700, Simon Glass 
> wrote:
>
>> > +++ b/arch/arm/lib/crt0.S
>> > @@ -82,9 +82,11 @@ ENTRY(_main)
>> >  #else
>> > bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
>> >  #endif
>> > +   bl  board_init_f_get_reserve_size
>> > +   sub sp, sp, r0
>> > +   mov r9, sp
>>
>> Why do you need that?
>
> To set gd in ARM architecture, as arch_setup_gd() may not work for
> ARM, see my 'Note about the ARM case' in my answer dated Sun, 15 Nov
> 2015 14:51:04 +0100 for details:
>
> https://www.mail-archive.com/u-boot@lists.denx.de/msg192494.html
>

OK I understand that now.

> I shall post a 2-patch v6 with this fix standalone as 1/2 and the rest
> of the changes as 2/2.
>
>> > +++ b/common/init/board_init.c
>> > @@ -21,39 +21,121 @@ DECLARE_GLOBAL_DATA_PTR;
>> >  #define _USE_MEMCPY
>> >  #endif
>> >
>> > -/* Unfortunately x86 can't compile this code as gd cannot be assigned */
>> > -#ifndef CONFIG_X86
>> > +/* Unfortunately x86 or ARM can't compile this code as gd cannot be 
>> > assigned */
>> > +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
>> >  __weak void arch_setup_gd(struct global_data *gd_ptr)
>> >  {
>> > gd = gd_ptr;
>> >  }
>> > -#endif /* !CONFIG_X86 */
>> > +#endif /* !CONFIG_X86 && !CONFIG_SYS_THUMB_BUILD */
>> >
>> > -ulong board_init_f_mem(ulong top)
>> > +/*
>> > + * Compute size of space to reserve on stack for use as 'globals'
>> > + * and return size request for reserved area.
>> > + *
>> > + * Notes:
>> > + *
>> > + * Actual reservation cannot be done from within this function as
>> > + * it requires altering the C stack pointer, so this will be done by
>> > + * the caller upon return from this function.
>> > + *
>> > + * IMPORTANT:
>> > + *
>> > + * The return value of this function has two uses:
>> > + * - it determines the amount of stack reserved for global data and
>> > + *   the malloc arena;
>>
>> early malloc() area
>
> "Arena", and "malloc arena", are established designations for the
> memory space used by malloc implementations; and I prefer to use this
> more specific term, as people may use it as a search keyword when
> looking for malloc related stuff.

Arena is OK, but can you please mention 'early' each time? It's
confusing otherwise. I think we should have a clear distinction
between the early malloc() and full malloc().

>
>> Another option would be to pass the address and have this function
>> return the new address. That would simplify the assembly code slightly
>> for all archs I think. It would also allow you to align the address
>> for sure, whereas at present it only works if the original address was
>> aligned, and CONFIG_SYS_MALLOC_F_LEN is aligned.
>
> Good point, with a few caveats though.
>
> Regarding alignment of CONFIG_SYS_MALLOC_F_LEN:
>
> Indeed, no attempt is made to check that it is aligned (and no attempt
> is made in the original code either) -- all the more since there is no
> strict definition of what it should be aligned to. There is, actually,
> no indication that it should be aligned, although it will probably only
> be used up until the last full 4-byte-word (or 8-byte word for 64-bit
> architectures). In fact, the alignment of CONFIG_SYS_MALLOC_F_LEN does
> not matter much, see (*) below.
>
> Regarding alignment of the original/'top' address:
>
> This top address is the SP for all architectures, and at least for ARM,
> it is aligned to an 8-byte boundary, as this is an ARM architecture
> EABI requirement. For other architectures, I cannot claim it is, but I
> suspect all initial values of SP, which generally are CONFIG_SPL_STACK
> or CONFIG_SYS_INIT_SP_ADDR, are (sufficiently) aligned.
>
> And if CONFIG_SPL_STACK and CONFIG_SYS_INIT_SP_ADDR are not
> (sufficiently) aligned in their definition, then either we can fix
> these definitions (and that of CONFIG_SYS_MALLOC_F_LEN too, while we
> are at it), or, if we can only fix this at run time, then this should be
> done where the stack pointer is altered, in the crt0.S file or whatever
> its equivalent is for any given architecture, outside the C environment.
>
> But that will have to go in another patch dealing with alignment.

If you can have it so that the stack top equals the global_data
bottom, then we should be OK.

>
> (*)
>
> Indeed board_init_f_get_reserve_size may have to respect some location
> or size alignment for each of the chunks it reserves. Right now, for
> instance, GD is aligned to a 16-byte boundary, and the malloc arena is
> aligned by virtue of the rounded value of CONFIG_SYS_MALLOC_F_LEN.
>
> And yes, should some new reservation be made beside GD and the malloc
> arena, it might require some specific alignment not dealt with so far;
> for instance, we may need to reserve some 4KB-aligned chunk for memory
> management purposes, or whatever, and there is no guarantee 

[U-Boot] [PATCH] Don't try to stat() a colon separated list of files in multi or script mode

[Nye Liu]

---
 tools/mkimage.c | 32 +++-
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 8af9d50..aa739b4 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -311,21 +311,27 @@ NXTARG:   ;
exit (retval);
}
 
-   dfd = open(params.datafile, O_RDONLY | O_BINARY);
-   if (dfd < 0) {
-   fprintf(stderr, "%s: Can't open %s: %s\n",
-   params.cmdname, params.datafile, strerror(errno));
-   exit(EXIT_FAILURE);
-   }
+   if (params.skipcpy ||
+   !(params.type == IH_TYPE_MULTI ||
+   params.type == IH_TYPE_SCRIPT)) {
+   dfd = open(params.datafile, O_RDONLY | O_BINARY);
+   if (dfd < 0) {
+   fprintf(stderr, "%s: Can't open %s: %s\n",
+   params.cmdname, params.datafile,
+   strerror(errno));
+   exit(EXIT_FAILURE);
+   }
 
-   if (fstat(dfd, ) < 0) {
-   fprintf(stderr, "%s: Can't stat %s: %s\n",
-   params.cmdname, params.datafile, strerror(errno));
-   exit(EXIT_FAILURE);
-   }
+   if (fstat(dfd, ) < 0) {
+   fprintf(stderr, "%s: Can't stat %s: %s\n",
+   params.cmdname, params.datafile,
+   strerror(errno));
+   exit(EXIT_FAILURE);
+   }
 
-   params.file_size = sbuf.st_size + tparams->header_size;
-   close(dfd);
+   params.file_size = sbuf.st_size + tparams->header_size;
+   close(dfd);
+   }
 
/*
 * In case there an header with a variable
-- 
2.6.2

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Re: [U-Boot] [PATCH] pci: fix address range check in __pci_hose_phys_to_bus()

[Bin Meng]

On Wed, Nov 18, 2015 at 10:05 PM, Marcel Ziswiler
 wrote:
> The address range check may overflow if the memory region is located at
> the top of the 32-bit address space. This can e.g. be seen on TK1 if
> using the E1000 gigabit Ethernet driver where start and size are both
> 0x8000 leading to the following messages:
>
> Apalis TK1 # tftpboot $loadaddr test_file
> Using e1000#0 device
> TFTP from server 192.168.10.1; our IP address is 192.168.10.2
> Filename 'test_file'.
> Load address: 0x80408000
> Loading: pci_hose_phys_to_bus: invalid physical address
>
> This patch fixes this by changing the order of the addition vs.
> subtraction in the range check just like already done in
> __pci_hose_bus_to_phys().
>
> Reported-by: Ivan Mercier 
> Signed-off-by: Marcel Ziswiler 
> ---
>
>  drivers/pci/pci_common.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
> index a64792f..2a14902 100644
> --- a/drivers/pci/pci_common.c
> +++ b/drivers/pci/pci_common.c
> @@ -268,7 +268,7 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
> bus_addr = phys_addr - res->phys_start + res->bus_start;
>
> if (bus_addr >= res->bus_start &&
> -   bus_addr < res->bus_start + res->size) {
> +   (bus_addr - res->bus_start) < res->size) {
> *ba = bus_addr;
> return 0;
> }
> --

For some reason, this patch did not show up on patchwork for sometime
and it lost my 'Reviewed-by' tag. Here it is:

Reviewed-by: Bin Meng 
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Re: [U-Boot] [U-Boot, V4, 07/13] spl: mmc: get rid of emmc boot code duplication

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:48PM +0200, Nikita Kiryanov wrote:

> Get rid of emmc boot code duplication in spl_mmc_load_image() using a switch
> case fallthrough into MMCSD_MODE_RAW. Since the #ifdef 
> CONFIG_SUPPORT_EMMC_BOOT
> check is not really necessary, remove it in the process.
> 
> No functional changes.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Igor Grinberg 
> Cc: Paul Kocialkowski 
> Cc: Pantelis Antoniou 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Reviewed-by: Simon Glass 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,V4,11/13] spl: announce boot devices

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:52PM +0200, Nikita Kiryanov wrote:

> Now that we support alternative boot devices, it can sometimes be
> unclear which boot devices was actually used. Provide a function to
> announce which boot devices are attempted during boot.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, V4, 08/13] spl: change return values of spl_*_load_image()

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:49PM +0200, Nikita Kiryanov wrote:

> Make spl_*_load_image() functions return a value instead of
> hanging if a problem is encountered. This enables main spl code
> to make the decision whether to hang or not, thus preparing
> it to support alternative boot devices.
> 
> Some boot devices (namely nand and spi) do not hang on error.
> Instead, they return normally and SPL proceeds to boot the
> contents of the load address. This is considered a bug and
> is rectified by hanging on error for these devices as well.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Ian Campbell 
> Cc: Hans De Goede 
> Cc: Albert Aribaud 
> Cc: Jagan Teki 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, V4, 10/13] spl: add support for alternative boot device

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:51PM +0200, Nikita Kiryanov wrote:

> Introduce spl_boot_list array, which defines a list of boot devices
> that SPL will try before hanging. By default this list will consist
> of only spl_boot_device(), but board_boot_order() can be overridden
> by board code to populate the array with custom values.
> 
> Signed-off-by: Nikita Kiryanov 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 05/15] km/powerpc: move open firmware defines to km-powerpc.h

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:28AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> We use the same settings for open firmware defines on all our powerpc
> targets, so move them from the CPU specific headers to the common
> powerpc header.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, v2, 07/15] km/powerpc82xx: remove unused function

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:30AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> commit 0a4f88b98 removed the usage of our setports function, but the
> function itself were not removed. So toss it it's dead code.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2,06/15] km/powerpc: remove unneeded defines

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:29AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> We use CONFIG_OF_LIBFDT and CONFIG_OF_BOARD_SETUP on all our powerpc
> targets, so there is no need to check these defines within our C code.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 02/15] powerpc/82xx: make set/get_pin for km82xx more flexible

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:25AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> The get_pin and set_pin funciton was only used for pins on Port D and
> therefore the value was hard coded in the function. Enhance this with a
> parameter, that we are able to use this functions for other ports too.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, v2, 04/15] km/powerpc: increase space for kernel imange and FDT blob

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:27AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> 128kByte and 3,986MB may be in the future too little for kernel the fdt
> blob respectively the kernel image. So increase the reserved areas here,
> we have the space for this.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, v2, 01/15] powerpc/83xx: add support for kmtepr2 board

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:24AM +0100, Valentin Longchamp wrote:

> From: Christoph Dietrich 
> 
> This board is similar to TUXX1, but it has differend FPGAs.
> 
> Signed-off-by: Christoph Dietrich 
> Signed-off-by: Andreas Huber 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, v2, 03/15] powerpc/82xx/km: add testpin detection for mgcoge3ne

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:26AM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> On mgcoge3ne we also want to start the test application if the testpin
> is asserted. But we don't have a full POST test support yet. So simply
> add a function to read the testpin value.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 3/4] km/scripts: load fdt_bid_kwkey.dtb when working with tftp

[Tom Rini]

On Fri, Nov 13, 2015 at 04:15:21PM +0100, Valentin Longchamp wrote:

> From: Holger Brunck 
> 
> When loading the dtb file via tftp we should load the one which matches
> boardId and hwKey and not a common one for the boardname. We have boards
> were different hwKeys are used and then we may load an incorrect dtb
> file. If no fdt_bid_kwkey.dtb file is not a fallback to boardname.dtb is used.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Tobias Müller 
> Signed-off-by: Valentin Longchamp 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 4/4] km/scripts: search for kernel/DTBs at serverip:/PRODUCTNAME via TFTP in develop mode

[Tom Rini]

On Fri, Nov 13, 2015 at 04:15:22PM +0100, Valentin Longchamp wrote:

> From: Tobias Müller 
> 
> Search for the kernel and DTBs in a folder named PRODUCTNAME (found in the 
> IVM)
> at the TFTP server instead of the u-boot boardname.
> 
> Signed-off-by: Tobias Müller 
> Signed-off-by: Valentin Longchamp 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 2/6] gpt: command: cosmetic: Replace printf with puts

[Tom Rini]

On Fri, Nov 13, 2015 at 07:42:08AM +0100, Lukasz Majewski wrote:

> This code is not processing any data to serial console output and hence
> can be replaced with puts.
> 
> Signed-off-by: Lukasz Majewski 

No, printf is fine, always.  We went over this before and it's not a win
to change things.

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Re: [U-Boot] Fix sandbox build on Ubuntu 10.04

[Tom Rini]

On Sat, Nov 14, 2015 at 11:53:49PM -0700, Stephen Warren wrote:

> gcc 4.4.3 (which is the default native compiler on x86-64 Ubuntu 10.04)
> doesn't seem to like initializers for sub-fields of anonymous unions.
> Solve this by replacing the initialization with an assignment. This
> fixes:
> 
> lib/lz4_wrapper.c: In function ‘ulz4fn’:
> lib/lz4_wrapper.c:97: error: unknown field ‘raw’ specified in initializer
> 
> Signed-off-by: Stephen Warren 
> Reviewed-by: Tom Rini 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 2/4] km: update the boot script to check for a DTB

[Tom Rini]

On Fri, Nov 13, 2015 at 04:15:20PM +0100, Valentin Longchamp wrote:

> If a DTB is found with cramfsls, the bootscript continues as expected.
> If none is found, the cramfsloadfdt and boot subbootcmds are updated to
> not load the DTB from cramfs and not pass it to the kernel. The kernel
> thus must have an appended DTB otherwise the boot will fail.
> 
> This is required for the km_kirkwood boards that must support .esw where
> the DTB sometimes is appended (for backwards compatibility) and sometimes
> is passed correctly (as we do now for all newer boards).
> 
> Signed-off-by: Valentin Longchamp 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 4/4] arm/km_kirkwood: fix the #ifdef for KM_COGE5UN dip switch

[Tom Rini]

On Fri, Nov 13, 2015 at 03:01:17PM +0100, Valentin Longchamp wrote:

> There was a small typo for KM_COGE5UN that resulted in the dip switch
> not to behave as expected.
> 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, 2/4] arm/km: Fix LED configuration for 88E1118R PHY (PIGGY3)

[Tom Rini]

On Fri, Nov 13, 2015 at 03:01:15PM +0100, Valentin Longchamp wrote:

> From: Tobias Müller 
> 
> Configure PHY LED register for Marvell 88E1118R PHY used on PIGGY3 to
> match with printed descriptions on PCB
> 
> Signed-off-by: Tobias Müller 
> Signed-off-by: Valentin Longchamp 

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Re: [U-Boot] [U-Boot, v2, 08/15] powerpc/km8321: define CONFIG_SYS_DDRCDR

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:31AM +0100, Valentin Longchamp wrote:

> On the km8321 boards is CONFIG_SYS_DDRCDR not defined, which leads to
> the DDRCDR not being configured at startup and still containing the
> reset value.
> 
> The required settings for our km8321 hardware designs are different than
> the reset value and must be set with CONFIG_SYS_DDRCDR, that is used
> by mpc83xx's cpu_init_f function at early CPU initialization.
> 
> The important settings are the DDR2 internal voltage level and the
> half-strength "drivers".
> 
> In our case where the DRAM chips are soldered on board and the routing
> for these signals under control, half-strength is sufficient as a few
> measurements done in the lasts have shown. Since all the hardware
> qualification tests have been performed with half strength, the nominal
> strength settings are removed in favor of the default reset half
> strength settings.
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 09/15] powerpc/km8309: define CONFIG_SYS_DDRCDR

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:32AM +0100, Valentin Longchamp wrote:

> For consistency with all the other km83xx plaforms, this should also be
> defined for km8309. The same settings as for km8321 are taken.
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 11/15] board/keymile/km82xx: setting dip_switch 3 and 4 will run bootloader

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:34AM +0100, Valentin Longchamp wrote:

> From: Bagavathiannan Palanisamy 
> 
> Setting dip_switch 3 and 4 also will run bootloader in COGE3 and COGE6
> It is required remove local mgmt IP address, when DIP Switch PIN3 is
> enabled. DIP Switch 4 also enabled to avoid u-boot update in future
> for DIP switch enhancements.
> 
> Signed-off-by: Bagavathiannan Palanisamy 
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 13/15] km8309: change the default QE_FW address

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:36AM +0100, Valentin Longchamp wrote:

> It should be after the u-boot reserved sectors and before the env
> sectors, since the solution used for kmvect1 (tell the linker to put the
> firmware into the u-boot produced binary, at the end of the area) should
> be the exception.
> 
> The #define is only "conditional" so that we can still support kmvect1.
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 12/15] km83xx: use CONFIG_ENV_ADDR for the newenv env command

[Tom Rini]

On Tue, Nov 17, 2015 at 10:53:35AM +0100, Valentin Longchamp wrote:

> The hardcoded value are bad, since the address could change between
> different boards.
> 
> Furthermore, the relevant #defines are set only if #undefined here, so
> that they can be changed by some boards if required.
> 
> Signed-off-by: Valentin Longchamp 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 14/25] dm: tegra: net: Convert tegra boards to driver model for Ethernet

[Stephen Warren]

On 11/18/2015 03:14 PM, Simon Glass wrote:

Hi Stephen,

On 18 November 2015 at 14:35, Stephen Warren  wrote:

On 11/16/2015 08:53 PM, Simon Glass wrote:


Adjust all Tegra boards to use driver model for Ethernet, now that the
required drivers are converted.




diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig




@@ -14,6 +14,7 @@ config TEGRA_ARMV7_COMMON
 select DM_GPIO
 select DM_PCI
 select DM_PCI_COMPAT
+   select DM_ETH



This should be set for Tegra210 too. I suggest creating a "config
TEGRA_COMMON" to contain all the shared settings, and making
TEGRA_ARMV7_COMMON and TEGRA_ARMV8_COMMON (also new) select that.


Would you mind doing a patch for that? It seems like it should be a
separate patch.


OK, I've sent it. I will point out that what with the merge conflicts 
you'll now have to resolve, it probably would have been quicker for you 
if you had written it yourself...

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Re: [U-Boot] board/ti/am335x: add support for BeagleBone Green

[Tom Rini]

On Wed, Nov 11, 2015 at 09:10:52AM -0600, robertcnel...@gmail.com wrote:

> SeeedStudio BeagleBone Green (BBG) is clone of the BeagleBone Black (BBB) 
> minus
> the HDMI port and addition of two Grove connectors (i2c2 and usart2).
> 
> This board can be identified by the 1A value after A335BNLT (BBB) in the at24 
> eeprom:
> 1A: [aa 55 33 ee 41 33 33 35  42 4e 4c 54 1a 00 00 00 |.U3.A335BNLT|]
> 
> http://beagleboard.org/green
> http://www.seeedstudio.com/wiki/Beaglebone_green
> 
> In Mainline Kernel as of:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=79a4e64c679d8a0b1037da174e4aea578c80c4e6
> 
> Patch tested on BeagleBone Black (rev C) and BeagleBone Green (production 
> model)
> 
> Signed-off-by: Robert Nelson 
> CC: Tom Rini 
> CC: Jason Kridner 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, V4, 13/13] spl: mmc: add support for BOOT_DEVICE_MMC2

[Tom Rini]

On Sun, Nov 08, 2015 at 05:11:54PM +0200, Nikita Kiryanov wrote:

> Currently the mmc device that SPL looks at is always mmc0, regardless
> of the BOOT_DEVICE_MMCx value. This forces some boards to
> implement hacks in order to boot from other mmc devices.
> 
> Make SPL take into account the correct mmc device.
> 
> Signed-off-by: Nikita Kiryanov 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 1/6] gpt: command: Remove duplicated check for empty partition description

[Tom Rini]

On Fri, Nov 13, 2015 at 07:42:07AM +0100, Lukasz Majewski wrote:

> Exactly the same check is performed in set_gpt_info() function executed
> just after this check.
> 
> Signed-off-by: Lukasz Majewski 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 3/6] gpt: doc: README: Update README entry for gpt verify extension

[Tom Rini]

On Fri, Nov 13, 2015 at 07:42:09AM +0100, Lukasz Majewski wrote:

> ./doc/README.gpt entry has been updated to explain usage of "gpt verify"
> command.
> 
> Signed-off-by: Lukasz Majewski 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 4/6] gpt: doc: Update gpt command's help description

[Tom Rini]

On Fri, Nov 13, 2015 at 07:42:10AM +0100, Lukasz Majewski wrote:

> Signed-off-by: Lukasz Majewski 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 14/25] dm: tegra: net: Convert tegra boards to driver model for Ethernet

[Simon Glass]

Hi Stephen,

On 18 November 2015 at 14:35, Stephen Warren  wrote:
> On 11/16/2015 08:53 PM, Simon Glass wrote:
>>
>> Adjust all Tegra boards to use driver model for Ethernet, now that the
>> required drivers are converted.
>
>
>> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
>
>
>> @@ -14,6 +14,7 @@ config TEGRA_ARMV7_COMMON
>> select DM_GPIO
>> select DM_PCI
>> select DM_PCI_COMPAT
>> +   select DM_ETH
>
>
> This should be set for Tegra210 too. I suggest creating a "config
> TEGRA_COMMON" to contain all the shared settings, and making
> TEGRA_ARMV7_COMMON and TEGRA_ARMV8_COMMON (also new) select that.

Would you mind doing a patch for that? It seems like it should be a
separate patch.

>
>> diff --git a/board/compulab/trimslice/trimslice.c
>> b/board/compulab/trimslice/trimslice.c
>
>
>> -#ifdef CONFIG_PCI
>> -int board_eth_init(bd_t *bis)
>> -{
>> -   return pci_eth_init(bis);
>> -}
>> -#endif
>
>
> Has the need to call this function already been removed by this point in the
> series. In other words, does each commit in this series compile and support
> using Ethernet? If not, anyone running "git bisect" is going to be very sad.

It's connected with CONFIG_DM_ETH, so we should be OK.

Regards,
Simon
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