[U-Boot] [RFC PATCH] kbuild: turn of dtc unit address warnings by default

2017-02-26 Thread Masahiro Yamada
DTC 1.4.2 or later checks DT unit-address without reg property and
vice-versa, and generates lots of warnings.  Fixing DT files will
take for a while.  Until then, let's turn off the check unless
building with W=*.

Introduce a new helper dtc-option to check if the option is supported
in order to suppress warnings on older versions.

Signed-off-by: Masahiro Yamada 
---

This is one possible answer to Tom's:
https://www.mail-archive.com/u-boot@lists.denx.de/msg240328.html

He fixed the problem on travis-ci by commit a0f3e3d, but it is still
annoying during the regular development.
Perhaps we may want to hide the warnings (at least hidden in Linux
Kernel by default).
Or, is it better to keep it noisy
to motivate people to fix their DT files?
I am not quite sure...

Now I am sending this as RFC patch in case people may want to start discussion.

BTW, this is a counter-part of the patch I sent to the Kbuild sub-system
(https://patchwork.kernel.org/patch/9592747/)
because I want the U-Boot build system with Linux as much as possible.
Let's see if I will get possible opinions in the Kbuild review.


 Makefile   | 2 +-
 scripts/Kbuild.include | 5 +
 scripts/Makefile.extrawarn | 6 ++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 38b42da..b258de8 100644
--- a/Makefile
+++ b/Makefile
@@ -371,7 +371,7 @@ export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
 export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
+export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 30e6e31..1b62aed 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -172,6 +172,11 @@ ld-version = $(shell $(LD) --version | 
$(srctree)/scripts/ld-version.sh)
 # Usage:  $(call ld-ifversion, -ge, 22252, y)
 ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4))
 
+# dtc-option
+# Usage:  DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+dtc-option = $(call try-run,\
+   echo '/dts-v1/; / {};' | $(DTC) $(1),$(1),$(2))
+
 ##
 
 ###
diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn
index 6547e57..7b2cffc 100644
--- a/scripts/Makefile.extrawarn
+++ b/scripts/Makefile.extrawarn
@@ -57,4 +57,10 @@ ifeq ("$(strip $(warning))","")
 endif
 
 KBUILD_CFLAGS += $(warning)
+
+else
+
+# Disable noisy checks by default
+DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+
 endif
-- 
2.7.4

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[U-Boot] [PATCH 2/2] ARM: dts: uniphier: fix no unit name warnings

2017-02-26 Thread Masahiro Yamada
Fix warnings reported when built by DTC 1.4.2 or later:
  Node /memory has a reg or ranges property, but no unit name

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld11-ref.dts  | 2 +-
 arch/arm/dts/uniphier-ld11.dtsi | 2 +-
 arch/arm/dts/uniphier-ld20-ref.dts  | 2 +-
 arch/arm/dts/uniphier-ld20.dtsi | 2 +-
 arch/arm/dts/uniphier-ld4-ref.dts   | 2 +-
 arch/arm/dts/uniphier-ld6b-ref.dts  | 2 +-
 arch/arm/dts/uniphier-pro4-ace.dts  | 2 +-
 arch/arm/dts/uniphier-pro4-ref.dts  | 2 +-
 arch/arm/dts/uniphier-pro4-sanji.dts| 2 +-
 arch/arm/dts/uniphier-pxs2-gentil.dts   | 2 +-
 arch/arm/dts/uniphier-pxs2-vodka.dts| 2 +-
 arch/arm/dts/uniphier-sld3-ref.dts  | 2 +-
 arch/arm/dts/uniphier-sld8-ref.dts  | 2 +-
 arch/arm/dts/uniphier-support-card.dtsi | 2 +-
 14 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld11-ref.dts 
b/arch/arm/dts/uniphier-ld11-ref.dts
index 7693bf2..b4ef804 100644
--- a/arch/arm/dts/uniphier-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ld11-ref.dts
@@ -29,7 +29,7 @@
i2c5 = 
};
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0 0x8000 0 0x4000>;
};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 38dc1ec..8488984 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -104,7 +104,7 @@
 <1 10 4>;
};
 
-   soc {
+   soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/uniphier-ld20-ref.dts 
b/arch/arm/dts/uniphier-ld20-ref.dts
index 41ee07e..61bce42 100644
--- a/arch/arm/dts/uniphier-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -29,7 +29,7 @@
i2c5 = 
};
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0 0x8000 0 0xc000>;
};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 7176757..d853526 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -173,7 +173,7 @@
 <1 10 4>;
};
 
-   soc {
+   soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/uniphier-ld4-ref.dts 
b/arch/arm/dts/uniphier-ld4-ref.dts
index 0f4bd9b..95fe90c 100644
--- a/arch/arm/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -16,7 +16,7 @@
model = "UniPhier LD4 Reference Board";
compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0x8000 0x2000>;
};
diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts 
b/arch/arm/dts/uniphier-ld6b-ref.dts
index 4da3c63..e9ab1e9 100644
--- a/arch/arm/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ld6b-ref.dts
@@ -16,7 +16,7 @@
model = "UniPhier LD6b Reference Board";
compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0x8000 0x8000>;
};
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts 
b/arch/arm/dts/uniphier-pro4-ace.dts
index f70bc82..4f81d3c 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -14,7 +14,7 @@
model = "UniPhier Pro4 Ace Board";
compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0x8000 0x4000>;
};
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts 
b/arch/arm/dts/uniphier-pro4-ref.dts
index 9714fb0..6431912 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -16,7 +16,7 @@
model = "UniPhier Pro4 Reference Board";
compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0x8000 0x4000>;
};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts 
b/arch/arm/dts/uniphier-pro4-sanji.dts
index d43f725..33380a0 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -14,7 +14,7 @@
model = "UniPhier Pro4 Sanji Board";
compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
 
-   memory {
+   memory@8000 {
device_type = "memory";
reg = <0x8000 0x8000>;
};
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts 

[U-Boot] [PATCH 1/2] ARM: dts: uniphier: remove skeleton.dtsi inclusion

2017-02-26 Thread Masahiro Yamada
Linux Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated") declared that skeleton.dtsi was deprecated.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld4.dtsi  | 4 ++--
 arch/arm/dts/uniphier-pro4.dtsi | 4 ++--
 arch/arm/dts/uniphier-pro5.dtsi | 4 ++--
 arch/arm/dts/uniphier-pxs2.dtsi | 4 ++--
 arch/arm/dts/uniphier-sld3.dtsi | 4 ++--
 arch/arm/dts/uniphier-sld8.dtsi | 4 ++--
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index bbfa164..0d3d963 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-ld4";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 9b881f6..210ac27 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-pro4";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 68866e1..de98697 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-pro5";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index da62070..904320c 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-pxs2";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
index 919cbff..7578920 100644
--- a/arch/arm/dts/uniphier-sld3.dtsi
+++ b/arch/arm/dts/uniphier-sld3.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-sld3";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index 5550bb8..4117132 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -7,10 +7,10 @@
  * SPDX-License-Identifier:GPL-2.0+X11
  */
 
-/include/ "skeleton.dtsi"
-
 / {
compatible = "socionext,uniphier-sld8";
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
-- 
2.7.4

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Re: [U-Boot] [PATCH] travis-ci: Temporarily disable using a newer device tree compiler

2017-02-26 Thread Robert Nelson
On Sun, Feb 26, 2017 at 11:29 PM, Heiko Schocher  wrote:
> Hello Robert,
>
> Am 27.02.2017 um 05:34 schrieb Robert Nelson:
>>
>> On Sun, Feb 26, 2017 at 7:37 PM, Tom Rini  wrote:
>>>
>>> On Sun, Feb 26, 2017 at 08:01:19PM -0500, Tom Rini wrote:
>>>
 For a long while dtc has warned about various constructs.  This is now
 leading to log file size being exceeded in travis, and as the majority
 of these errors need to be fixed in the kernel, switch to using the
 stock device-tree-compiler package.

 Signed-off-by: Tom Rini 
>>>
>>>
>>> Applied to u-boot/master, thanks!
>>>
>>> But I'm not happy to have to apply it, either.  I do not wish to break
>>> travis-ci, but sun7i is now exceeding the allowed stdout size.  And
>>> these are problems that need to be fixed in the kernel first, rather
>>> than here first.  The patches to fix u-boot local issues (such as x86
>>> never got picked up either, but likely need to be respun.  I expect that
>>> once the new DTC version is tagged and populated upstream in the kernel
>>> as well, we will be able to re-enable the changes we had here.
>>
>>
>> This was fixed (aka a hidden bandaid) in the linux kernel via:
>>
>>
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/Makefile.lib?id=bc553986a2f7c56d0de811485d5312ea29692d5d
>
>
> Heh... IIRC, I tried to fix a lot of this messages (in U-Boot), around
> a year ago, and we decided to not apply them in u-boot, instead they
> should go away via kernel resyncs, when the warnings are fixed in the
> kernel!
>
> Also I think, I tried a similiar approach as the commit you mentioned...
> Ah, yes, here:
> http://lists.denx.de/pipermail/u-boot/2016-April/252408.html
>
> We decided (for u-boot) it would be better to fix the problems and
> not supress the warning, but it seems, the problems get not really fixed
> in the kernel ...
>
> I wasn;t aware of the above patch in the kernel... thanks for pointing!

and i think by moving the kernel to disable that patch, it's slowed
down the number of register fix patches..

ps, this just came in on kbuild list just a few minutes ago:

https://marc.info/?l=linux-kbuild=148817429929267=2

one of the issues with bc553986a2f7c56d0de811485d5312ea29692d5d is
that it breaks the build with older version of dtc that don't know
what to do with the -Wno-unit_address_vs_reg flag..

Regards,

-- 
Robert Nelson
https://rcn-ee.com/
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Re: [U-Boot] [PATCH 14/20] arm: socfpga: add SPL support for Arria 10

2017-02-26 Thread Chee, Tien Fong
On Sab, 2017-02-25 at 22:43 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> > 
> > Add SPL support for Arria 10.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Signed-off-by: Ley Foon Tan 
> > ---
> >  arch/arm/mach-socfpga/spl.c | 92
> > -
> >  1 file changed, 90 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..1299e67 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -19,37 +19,55 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include 
> > +#endif
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#define BOOTINFO_BSEL_SHIFT0
> Wasn't this defined in the misc support patch already ?
> 
> > 
> >  static struct pl310_regs *const pl310 =
> >     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> >  static struct scu_registers *scu_regs =
> >     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> >  static struct nic301_registers *nic301_regs =
> >     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define BOOTINFO_BSEL_SHIFT12
> > +#endif
> > +
> > +static const struct socfpga_system_manager *sysmgr_regs =
> >     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >  
> >  u32 spl_boot_device(void)
> >  {
> >     const u32 bsel = readl(_regs->bootinfo);
> >  
> > -   switch (bsel & 0x7) {
> > +   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
> >     case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> >     return BOOT_DEVICE_RAM;
> >     case 0x2:   /* NAND Flash (1.8V) */
> >     case 0x3:   /* NAND Flash (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
> > +#endif
> >     return BOOT_DEVICE_NAND;
> >     case 0x4:   /* SD/MMC External Transceiver (1.8V) */
> >     case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
> >     socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
> > +#endif
> >     return BOOT_DEVICE_MMC1;
> >     case 0x6:   /* QSPI Flash (1.8V) */
> >     case 0x7:   /* QSPI Flash (3.0V) */
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
> > +#endif
> This looks awful, you might want to split this function into
> A10-specific and Gen5 specific one(s) .
> 
#if defined(CONFIG_TARGET_SOCFPGA_GEN5) can be removed, Arria10 would
use the same implementation as gen5.
> > 
> >     return BOOT_DEVICE_SPI;
> >     default:
> >     printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > @@ -68,6 +86,7 @@ u32 spl_boot_mode(const u32 boot_device)
> >  }
> >  #endif
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static void socfpga_nic301_slave_ns(void)
> >  {
> >     writel(0x1, _regs->lwhps2fpgaregs);
> > @@ -182,3 +201,72 @@ void board_init_f(ulong dummy)
> >     /* Configure simple malloc base pointer into RAM. */
> >     gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
> >  }
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#ifdef CONFIG_SPL_BOARD_INIT
> > +void spl_board_init(void)
> > +{
> > +   /* configuring the clock based on handoff */
> > +   cm_basic_init(gd->fdt_blob);
> > +   WATCHDOG_RESET();
> > +
> > +   config_dedicated_pins(gd->fdt_blob);
> > +   WATCHDOG_RESET();
> > +
> > +   /* Release UART from reset */
> > +   reset_deassert_uart();
> > +
> > +   /* enable console uart printing */
> > +   preloader_console_init();
> > +}
> > +#endif
> > +
> > +void board_init_f(ulong dummy)
> > +{
> > +   memset(__bss_start, 0, __bss_end - __bss_start);
> Is this really needed ? Should be done by common code already ...
> 
> > 
> > +   /*
> > +    * Configure Clock Manager to use intosc clock instead
> > external osc to
> > +    * ensure success watchdog operation. We do it as early as
> > possible.
> > +    */
> > +   cm_use_intosc();
> > +
> > +   watchdog_disable();
> > +
> > +   arch_early_init_r();
> > +
> > +#ifdef CONFIG_HW_WATCHDOG
> > +   /* release osc1 watchdog timer 0 from reset */
> > +   reset_deassert_osc1wd0();
> > +
> > +   /* reconfigure and enable the watchdog */
> > +   hw_watchdog_init();
> > +   WATCHDOG_RESET();
> > +#endif /* CONFIG_HW_WATCHDOG */
> > +
> > +#ifdef CONFIG_OF_CONTROL
> > +   /* We need to access to FDT as this stage */
> > +   /* FDT is at end of image */
> > +   gd->fdt_blob = (void *)(__bss_end);
> This looks like common code too ?
> 
> > 
> > +   /* Check whether we have a valid FDT or not. */
> > +   if (fdtdec_prepare_fdt()) {
> > + 

Re: [U-Boot] [PATCH] travis-ci: Temporarily disable using a newer device tree compiler

2017-02-26 Thread Heiko Schocher

Hello Robert,

Am 27.02.2017 um 05:34 schrieb Robert Nelson:

On Sun, Feb 26, 2017 at 7:37 PM, Tom Rini  wrote:

On Sun, Feb 26, 2017 at 08:01:19PM -0500, Tom Rini wrote:


For a long while dtc has warned about various constructs.  This is now
leading to log file size being exceeded in travis, and as the majority
of these errors need to be fixed in the kernel, switch to using the
stock device-tree-compiler package.

Signed-off-by: Tom Rini 


Applied to u-boot/master, thanks!

But I'm not happy to have to apply it, either.  I do not wish to break
travis-ci, but sun7i is now exceeding the allowed stdout size.  And
these are problems that need to be fixed in the kernel first, rather
than here first.  The patches to fix u-boot local issues (such as x86
never got picked up either, but likely need to be respun.  I expect that
once the new DTC version is tagged and populated upstream in the kernel
as well, we will be able to re-enable the changes we had here.


This was fixed (aka a hidden bandaid) in the linux kernel via:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/Makefile.lib?id=bc553986a2f7c56d0de811485d5312ea29692d5d


Heh... IIRC, I tried to fix a lot of this messages (in U-Boot), around
a year ago, and we decided to not apply them in u-boot, instead they
should go away via kernel resyncs, when the warnings are fixed in the
kernel!

Also I think, I tried a similiar approach as the commit you mentioned...
Ah, yes, here:
http://lists.denx.de/pipermail/u-boot/2016-April/252408.html

We decided (for u-boot) it would be better to fix the problems and
not supress the warning, but it seems, the problems get not really fixed
in the kernel ...

I wasn;t aware of the above patch in the kernel... thanks for pointing!

@Tom:
So, I feel, the problems get not fixed fast in the kernel (if ever),
may we want to cherry-pick this patch from the kernel (or make a
similiar patch for U-Boot)?

bye,
Heiko
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[U-Boot] [PATCH 3/3] board: at91sam9263ek: clean up code

2017-02-26 Thread Wenyou Yang
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
---

 board/atmel/at91sam9263ek/at91sam9263ek.c | 58 ---
 1 file changed, 58 deletions(-)

diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c 
b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 04e5812db3..0c64db9559 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -19,11 +19,6 @@
 #include 
 #include 
 #include 
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include 
-#endif
-#include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,34 +72,6 @@ static void at91sam9263ek_nand_hw_init(void)
 }
 #endif
 
-#ifdef CONFIG_MACB
-static void at91sam9263ek_macb_hw_init(void)
-{
-   at91_pio_t  *pio= (at91_pio_t *) ATMEL_BASE_PIO;
-
-   at91_periph_clk_enable(ATMEL_ID_EMAC);
-
-   /*
-* Disable pull-up on:
-*  RXDV (PC25) => PHY normal mode (not Test mode)
-*  ERX0 (PE25) => PHY ADDR0
-*  ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
-*
-* PHY has internal pull-down
-*/
-   writel(1 << 25, >pioc.pudr);
-   writel((1 << 25) | (1 <<26), >pioe.pudr);
-
-   at91_phy_reset();
-
-   /* Re-enable pull-up */
-   writel(1 << 25, >pioc.puer);
-   writel((1 << 25) | (1 <<26), >pioe.puer);
-
-   at91_macb_hw_init();
-}
-#endif
-
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
.vl_col =   240,
@@ -209,21 +176,8 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bd)
-{
-   at91_mci_hw_init();
-
-   return atmel_mci_init((void *)ATMEL_BASE_MCI1);
-}
-#endif
-
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-
at91_seriald_hw_init();
return 0;
 }
@@ -242,9 +196,6 @@ int board_init(void)
at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
at91_spi0_hw_init(1 << 0);
 #endif
-#ifdef CONFIG_MACB
-   at91sam9263ek_macb_hw_init();
-#endif
 #ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init();
 #endif
@@ -267,12 +218,3 @@ void reset_phy(void)
 {
 }
 #endif
-
-int board_eth_init(bd_t *bis)
-{
-   int rc = 0;
-#ifdef CONFIG_MACB
-   rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
-#endif
-   return rc;
-}
-- 
2.11.0

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[U-Boot] [PATCH 2/3] configs: at91sam9263ek: update for DT and DM support

2017-02-26 Thread Wenyou Yang
Support the device tree and enable CONFIG_CLK and CONFIG_PINCTRL
to support the at91 clock driver and the at91 pinctrl driver.

Enable DM_GPIO, DM_MMC and DM_ETH support, move CONFIG_AT91_GPIO,
CONFIG_GENERIC_ATMEL_MCI and CONFIG_MACB config option to the
default config files.

Signed-off-by: Wenyou Yang 
---

 configs/at91sam9263ek_dataflash_cs0_defconfig | 16 +++-
 configs/at91sam9263ek_dataflash_defconfig | 16 +++-
 configs/at91sam9263ek_nandflash_defconfig | 16 +++-
 configs/at91sam9263ek_norflash_boot_defconfig | 16 +++-
 configs/at91sam9263ek_norflash_defconfig  | 16 +++-
 include/configs/at91sam9263ek.h   | 10 --
 6 files changed, 75 insertions(+), 15 deletions(-)

diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig 
b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 6605a0ea58..6df678a85e 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,7 +23,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig 
b/configs/at91sam9263ek_dataflash_defconfig
index 6605a0ea58..6df678a85e 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,7 +23,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig 
b/configs/at91sam9263ek_nandflash_defconfig
index 9c6bab9a37..0d6d506ff6 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,7 +23,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig 
b/configs/at91sam9263ek_norflash_boot_defconfig
index 59c4f9b72f..91e23e13b8 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,7 +23,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_defconfig 
b/configs/at91sam9263ek_norflash_defconfig
index b588871371..14aea05bb4 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,7 +23,19 @@ CONFIG_CMD_USB=y
 

[U-Boot] [PATCH 0/3] board: at91sam9263ek: convert to support DM and DT

2017-02-26 Thread Wenyou Yang
The purpose of the patch set is to convert the board to support
the Driver Model and the Device Tree.


Wenyou Yang (3):
  ARM: dts: at91: add dts files for at91sam9263ek
  configs: at91sam9263ek: update for DT and DM support
  board: at91sam9263ek: clean up code

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/at91sam9263.dtsi | 185 +++--
 arch/arm/dts/at91sam9263ek.dts| 227 ++
 board/atmel/at91sam9263ek/at91sam9263ek.c |  58 ---
 configs/at91sam9263ek_dataflash_cs0_defconfig |  16 +-
 configs/at91sam9263ek_dataflash_defconfig |  16 +-
 configs/at91sam9263ek_nandflash_defconfig |  16 +-
 configs/at91sam9263ek_norflash_boot_defconfig |  16 +-
 configs/at91sam9263ek_norflash_defconfig  |  16 +-
 include/configs/at91sam9263ek.h   |  10 --
 10 files changed, 400 insertions(+), 162 deletions(-)
 create mode 100644 arch/arm/dts/at91sam9263ek.dts

-- 
2.11.0

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[U-Boot] [PATCH 1/3] ARM: dts: at91: add dts files for at91sam9263ek

2017-02-26 Thread Wenyou Yang
The device tree source files of at91sam9263ek boards are copied
from the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang 
---

 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/at91sam9263.dtsi  | 185 +
 arch/arm/dts/at91sam9263ek.dts | 227 +
 3 files changed, 325 insertions(+), 89 deletions(-)
 create mode 100644 arch/arm/dts/at91sam9263ek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 76dc6562ed..4511b14376 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -330,6 +330,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
at91sam9g20ek.dtb   \
at91sam9g20ek_2mmc.dtb
 
+dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
at91sam9g15ek.dtb   \
at91sam9g25ek.dtb   \
diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi
index 93446420af..433d8554b2 100644
--- a/arch/arm/dts/at91sam9263.dtsi
+++ b/arch/arm/dts/at91sam9263.dtsi
@@ -114,7 +114,7 @@
clocks = <_osc>;
};
 
-   plla: pllack {
+   plla: pllack@0 {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = < 
AT91_PMC_LOCKA>;
@@ -126,7 +126,7 @@
<19000 
24000 2 1>;
};
 
-   pllb: pllbck {
+   pllb: pllbck@1 {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = < 
AT91_PMC_LOCKB>;
@@ -161,25 +161,25 @@
interrupt-parent = <>;
clocks = <_xtal>, <>, 
<>, <>;
 
-   prog0: prog0 {
+   prog0: prog@0 {
#clock-cells = <0>;
reg = <0>;
interrupts = 
;
};
 
-   prog1: prog1 {
+   prog1: prog@1 {
#clock-cells = <0>;
reg = <1>;
interrupts = 
;
};
 
-   prog2: prog2 {
+   prog2: prog@2 {
#clock-cells = <0>;
reg = <2>;
interrupts = 
;
};
 
-   prog3: prog3 {
+   prog3: prog@3 {
#clock-cells = <0>;
reg = <3>;
interrupts = 
;
@@ -191,37 +191,37 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   uhpck: uhpck {
+   uhpck: uhpck@6 {
#clock-cells = <0>;
reg = <6>;
clocks = <>;
};
 
-   udpck: udpck {
+   udpck: udpck@7 {
#clock-cells = <0>;
reg = <7>;
clocks = <>;
};
 
-   pck0: pck0 {
+   pck0: pck0@8 {
#clock-cells = <0>;
reg = <8>;
clocks = <>;
};
 
-   pck1: pck1 

Re: [U-Boot] [PATCH] travis-ci: Temporarily disable using a newer device tree compiler

2017-02-26 Thread Robert Nelson
On Sun, Feb 26, 2017 at 7:37 PM, Tom Rini  wrote:
> On Sun, Feb 26, 2017 at 08:01:19PM -0500, Tom Rini wrote:
>
>> For a long while dtc has warned about various constructs.  This is now
>> leading to log file size being exceeded in travis, and as the majority
>> of these errors need to be fixed in the kernel, switch to using the
>> stock device-tree-compiler package.
>>
>> Signed-off-by: Tom Rini 
>
> Applied to u-boot/master, thanks!
>
> But I'm not happy to have to apply it, either.  I do not wish to break
> travis-ci, but sun7i is now exceeding the allowed stdout size.  And
> these are problems that need to be fixed in the kernel first, rather
> than here first.  The patches to fix u-boot local issues (such as x86
> never got picked up either, but likely need to be respun.  I expect that
> once the new DTC version is tagged and populated upstream in the kernel
> as well, we will be able to re-enable the changes we had here.

This was fixed (aka a hidden bandaid) in the linux kernel via:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/Makefile.lib?id=bc553986a2f7c56d0de811485d5312ea29692d5d

Regards,

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Re: [U-Boot] [linux-sunxi] [PATCH v2 4/6] sunxi: fix an error when setting DLDO on AXP818

2017-02-26 Thread Chen-Yu Tsai
On Sun, Feb 26, 2017 at 7:52 AM, Icenowy Zheng  wrote:
> The driver of AXP818 PMIC have a serious bug when setting DLDOs' voltage
> -- the register offset of ELDO is wrongly used instead of DLDO.
>
> Fix this problem.
>
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Chen-Yu Tsai 
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[U-Boot] [PATCH 2/2] board: at91sam9261ek: update for DT and DM support

2017-02-26 Thread Wenyou Yang
Support the device tree and enable CONFIG_CLK and CONFIG_PINCTRL
to support the at91 clock driver and the at91 pinctrl driver.

Enable DM_GPIO support, move CONFIG_AT91_GPIO config option to
the default config files.

Signed-off-by: Wenyou Yang 
---

 configs/at91sam9261ek_dataflash_cs0_defconfig | 13 +++--
 configs/at91sam9261ek_dataflash_cs3_defconfig | 13 +++--
 configs/at91sam9261ek_nandflash_defconfig | 13 +++--
 configs/at91sam9g10ek_dataflash_cs0_defconfig | 13 +++--
 configs/at91sam9g10ek_dataflash_cs3_defconfig | 13 +++--
 configs/at91sam9g10ek_nandflash_defconfig | 13 +++--
 include/configs/at91sam9261ek.h   |  4 
 7 files changed, 66 insertions(+), 16 deletions(-)

diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig 
b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 6b26c78368..5bd0e8659a 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -19,7 +20,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig 
b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 293009d663..90a2357d92 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -19,7 +20,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig 
b/configs/at91sam9261ek_nandflash_defconfig
index 4760c4e07b..7e47940b7b 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -19,7 +20,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig 
b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 02cd5fa6a5..b7f27e2768 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -19,7 +20,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig 
b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 453a75ddf2..ee7020920f 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -1,7 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -19,7 +20,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y

[U-Boot] [PATCH 1/2] ARM: dts: at91: add dts files for at91sam9261ek

2017-02-26 Thread Wenyou Yang
The device tree source files of at91sam9261ek boards are copied
from the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC) nodes as the pinctrl's slibling
   nodes, instead of the child nodes.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang 
---

 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/at91sam9261.dtsi  | 136 +-
 arch/arm/dts/at91sam9261ek.dts | 211 +
 3 files changed, 283 insertions(+), 66 deletions(-)
 create mode 100644 arch/arm/dts/at91sam9261ek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1444261a07..cc7f63254e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -330,6 +330,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
at91sam9g20ek.dtb   \
at91sam9g20ek_2mmc.dtb
 
+dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
 
 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi
index 5e09de4eb9..f1f2fe804c 100644
--- a/arch/arm/dts/at91sam9261.dtsi
+++ b/arch/arm/dts/at91sam9261.dtsi
@@ -291,6 +291,10 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", 
"simple-bus";
ranges = <0xf400 0xf400 0x600>;
+   reg = <0xf400 0x200
+  0xf600 0x200
+  0xf800 0x200
+ >;
 
atmel,mux-mask =
  /*A B */
@@ -302,8 +306,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
-   ,
-   ;
+   ,
+   ;
};
};
 
@@ -532,39 +536,39 @@
;
};
};
+   };
 
-   pioA: gpio@f400 {
-   compatible = "atmel,at91rm9200-gpio";
-   reg = <0xf400 0x200>;
-   interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-   #gpio-cells = <2>;
-   gpio-controller;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   clocks = <_clk>;
-   };
+   pioA: gpio@f400 {
+   compatible = "atmel,at91rm9200-gpio";
+   reg = <0xf400 0x200>;
+   interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+   #gpio-cells = <2>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   clocks = <_clk>;
+   };
 
-   pioB: gpio@f600 {
-   compatible = "atmel,at91rm9200-gpio";
-   reg = <0xf600 0x200>;
-   interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-   #gpio-cells = <2>;
-   gpio-controller;
-   interrupt-controller;
-   #interrupt-cells = <2>;
-   clocks = <_clk>;
-   };
+   pioB: gpio@f600 {
+   compatible = "atmel,at91rm9200-gpio";
+   reg = <0xf600 0x200>;
+   interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+   #gpio-cells = <2>;
+   gpio-controller;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   clocks = <_clk>;
+   };
 
-   pioC: gpio@f800 {
-   compatible = "atmel,at91rm9200-gpio";
-   reg = 

Re: [U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

2017-02-26 Thread Chen-Yu Tsai
On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara  wrote:
> Instead of hard-coding GPIO pins used for a certain peripheral, we
> should just use the pinctrl information from the DT.
> The sun8i-emac driver has some simple implementation of that, so
> let's just generalize this and move the code into a more common
> location.
> On the way we add support for the new, generic pinctrl binding now
> used by all Allwinner SoCs.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
>  arch/arm/mach-sunxi/pinmux.c   | 77 
> ++
>  2 files changed, 81 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 85a4ec3..ba8c661 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -239,4 +239,8 @@ int axp_gpio_init(void);
>  static inline int axp_gpio_init(void) { return 0; }
>  #endif
>
> +int sunxi_gpio_parse_pin_name(const char *pin_name);
> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
> +const char * mux_name, int mux_sel);
> +
>  #endif /* _SUNXI_GPIO_H */
> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
> index b026f78..f1e1e8f 100644
> --- a/arch/arm/mach-sunxi/pinmux.c
> +++ b/arch/arm/mach-sunxi/pinmux.c
> @@ -9,6 +9,9 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
>
>  void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
>  {
> @@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
>
> return 0;
>  }
> +
> +int sunxi_gpio_parse_pin_name(const char *pin_name)
> +{
> +   int pin;
> +
> +   if (pin_name[0] != 'P')
> +   return -1;
> +
> +   if (pin_name[1] < 'A' || pin_name[1] > 'Z')
> +   return -1;
> +
> +   pin = (pin_name[1] - 'A') << 5;
> +   pin += simple_strtol(_name[2], NULL, 10);
> +
> +   return pin;
> +}
> +
> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
> +const char * mux_name, int mux_sel)
> +{
> +   int drive, pull, pin, i;
> +   const char *pin_name;
> +   int offset;
> +
> +   offset = fdtdec_lookup_phandle(fdt_blob, node, "pinctrl-0");
> +   if (offset < 0)
> +   return offset;
> +
> +   drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +"drive-strength", 0);
> +   if (drive) {
> +   if (drive <= 10)
> +   drive = SUN4I_PINCTRL_10_MA;
> +   else if (drive <= 20)
> +   drive = SUN4I_PINCTRL_20_MA;
> +   else if (drive <= 30)
> +   drive = SUN4I_PINCTRL_30_MA;
> +   else
> +   drive = SUN4I_PINCTRL_40_MA;
> +   } else {
> +   drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +"allwinner,drive", 4);

You should use a different default, something invalid.


> +   }
> +
> +   if (fdt_get_property(fdt_blob, offset, "bias-pull-up", NULL))
> +   pull = SUN4I_PINCTRL_PULL_UP;
> +   else if (fdt_get_property(fdt_blob, offset, "bias-disable", NULL))
> +   pull = SUN4I_PINCTRL_NO_PULL;
> +   else if (fdt_get_property(fdt_blob, offset, "bias-pull-down", NULL))
> +   pull = SUN4I_PINCTRL_PULL_DOWN;
> +   else
> +   pull = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +   "allwinner,pull", 0);

Same here.

> +
> +   for (i = 0; ; i++) {
> +   pin_name = fdt_stringlist_get(fdt_blob, offset,
> + "allwinner,pins", i, NULL);
> +   if (!pin_name) {
> +   pin_name = fdt_stringlist_get(fdt_blob, offset,
> + "pins", i, NULL);
> +   if (!pin_name)
> +   break;
> +   }
> +   pin = sunxi_gpio_parse_pin_name(pin_name);
> +   if (pin < 0)
> +   continue;
> +
> +   sunxi_gpio_set_cfgpin(pin, mux_sel);
> +   sunxi_gpio_set_drv(pin, drive);
> +   sunxi_gpio_set_pull(pin, pull);

As the defaults implied by the bindings are to not touch the settings
if they aren't specified, as in "whatever the hardware was set to".
This applies to both drive strength and bias/pull.

Regards
ChenYu

> +   }
> +
> +   return i;
> +}
> --
> 2.8.2
>
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[U-Boot] [PATCH 0/2] board: at91sam9261ek: convert to support DM and DT

2017-02-26 Thread Wenyou Yang
The purpose of the patch set is to convert the board to support
the Driver Model and the Device Tree.


Wenyou Yang (2):
  ARM: dts: at91: add dts files for at91sam9261ek
  board: at91sam9261ek: update for DT and DM support

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/at91sam9261.dtsi | 136 +
 arch/arm/dts/at91sam9261ek.dts| 211 ++
 configs/at91sam9261ek_dataflash_cs0_defconfig |  13 +-
 configs/at91sam9261ek_dataflash_cs3_defconfig |  13 +-
 configs/at91sam9261ek_nandflash_defconfig |  13 +-
 configs/at91sam9g10ek_dataflash_cs0_defconfig |  13 +-
 configs/at91sam9g10ek_dataflash_cs3_defconfig |  13 +-
 configs/at91sam9g10ek_nandflash_defconfig |  13 +-
 include/configs/at91sam9261ek.h   |   4 -
 10 files changed, 349 insertions(+), 82 deletions(-)
 create mode 100644 arch/arm/dts/at91sam9261ek.dts

-- 
2.11.0

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Re: [U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

2017-02-26 Thread Chen-Yu Tsai
On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara  wrote:
> Hi,
>
> in the wake of the sunxi DM enablement series it became apparent that
> the current device tree files for the A64 SoC and its board are outdated.
>
> Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
> A64 SoC and the Pine64 boards in the mainline kernel.
> Linux v4.11-rc1 added MMC and USB support.
> Because our preliminary device trees used in U-Boot differ significantly,
> let's update our copy with what's in the current Linus' master tree.
> Since in contrast to U-Boot the kernel still lacks support for Ethernet,
> we keep our preliminary nodes for that IP, but adjust it slightly to
> match the new clocks and reset bindings.
>
> As the sun8i-emac driver is actually using the DT for the pinmux setup,
> we teach it how to cope with the new pinctrl bindings in the first two
> patches. This is probably becoming somewhat obsolete very soon (with
> DM GPIO support on the list already), however I consider these two
> patches as merely fixes for the existing driver to maintain bisectability.
> It would make sense to merge the new DTs before the DM patches, so we
> need to have something in place which works meanwhile.
>
> Let me know what you think.
>
> Cheers,
> Andre.
>
> Andre Przywara (6):
>   sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
>   net: sun8i-emac: use new, generic GPIO setup routine
>   sunxi: dts: update sun50i-a64.dtsi from Linux
>   sunxi: dts: update Pine64 .dts
>   sunxi: dts: remove now obsolete pine64-common.dtsi
>   sunxi: dts: add Bananapi M64 .dts

Could we keep this simple, and just do a "sync with the kernel" commit for
sun50i, which also keeps the sun8i-emac specific bits. And also explicitly
mention the git commit or tag you are syncing to.

ChenYu

>
>  arch/arm/dts/Makefile  |   3 +-
>  arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++
>  arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -
>  arch/arm/dts/sun50i-a64-pine64-plus.dts|  16 +-
>  arch/arm/dts/sun50i-a64-pine64.dts |  72 +++-
>  arch/arm/dts/sun50i-a64.dtsi   | 615 
> +
>  arch/arm/include/asm/arch-sunxi/gpio.h |   4 +
>  arch/arm/mach-sunxi/pinmux.c   |  77 
>  drivers/net/sun8i_emac.c   |  38 +-
>  include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++
>  include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +
>  11 files changed, 706 insertions(+), 579 deletions(-)
>  create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
>  delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
>  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>
> --
> 2.8.2
>
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Re: [U-Boot] [PATCH 1/2 RFT] sunxi: power: Add AXP806 and AXP808 support

2017-02-26 Thread Chen-Yu Tsai
On Mon, Feb 27, 2017 at 3:01 AM, Rask Ingemann Lambertsen
 wrote:
> An X-Powers AXP806 or AXP808 PMIC is usually found on boards using the
> Allwinner A80 ARM SoC. This patch adds support for the PMIC's regulators
> and sets up the runtime address and master/slave mode in pmic_bus_init().
>
> AXP806/AXP808 support is enabled by default on all MACH_SUN9I boards.
>
> Because there are boards with both an AXP806 and an AXP809,
> drivers/power/Kconfig and arch/arm/mach-sunxi/pmic_bus.c are changed to
> make it possible to have more than one PMIC enabled at a time.
>
> Signed-off-by: Rask Ingemann Lambertsen 
> ---
> This patch needs to be tested on the following boards which I don't have:
> Cubietech Cubieboard4
> Merrii A80 Optimus
>
>  arch/arm/include/asm/arch-sunxi/pmic_bus.h |   4 +
>  arch/arm/mach-sunxi/Makefile   |   1 +
>  arch/arm/mach-sunxi/pmic_bus.c | 107 ++---
>  board/sunxi/board.c|  20 +++
>  drivers/power/Kconfig  | 226 +++-
>  drivers/power/Makefile |   1 +
>  drivers/power/axp806.c | 231 
> +
>  include/axp806.h   |  50 +++
>  include/axp_pmic.h |  13 ++
>  9 files changed, 623 insertions(+), 30 deletions(-)
>  create mode 100644 drivers/power/axp806.c
>  create mode 100644 include/axp806.h
>
> diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h 
> b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
> index 9c4372a..d143d54 100644
> --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h
> +++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
> @@ -14,5 +14,9 @@ int pmic_bus_read(u8 reg, u8 *data);
>  int pmic_bus_write(u8 reg, u8 data);
>  int pmic_bus_setbits(u8 reg, u8 bits);
>  int pmic_bus_clrbits(u8 reg, u8 bits);
> +int pmic2_bus_read(u8 reg, u8 *data);
> +int pmic2_bus_write(u8 reg, u8 data);
> +int pmic2_bus_setbits(u8 reg, u8 bits);
> +int pmic2_bus_clrbits(u8 reg, u8 bits);
>
>  #endif
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 7daba11..410fb49 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I)  += clock_sun9i.o gtbus_sun9i.o
>  obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
>  obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
>  obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
> +obj-$(CONFIG_AXP806_POWER) += pmic_bus.o
>  obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
>  obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
>
> diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
> index 7c57f02..a2da40c 100644
> --- a/arch/arm/mach-sunxi/pmic_bus.c
> +++ b/arch/arm/mach-sunxi/pmic_bus.c
> @@ -27,6 +27,15 @@
>  #define AXP223_DEVICE_ADDR 0x3a3
>  #define AXP223_RUNTIME_ADDR0x2d
>
> +/* AXP806 and AXP808 use the same addresses. */
> +#define AXP806_DEVICE_ADDR 0x745
> +#define AXP806_RUNTIME_ADDR0x3a
> +
> +/* AXP806 and AXP808 address space extension. */
> +#define AXP806_REG_ADDR_EXT0xff
> +#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE   0
> +#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODEBIT(4)
> +
>  int pmic_bus_init(void)
>  {
> /* This cannot be 0 because it is used in SPL before BSS is ready */
> @@ -36,7 +45,8 @@ int pmic_bus_init(void)
> if (!needs_init)
> return 0;
>
> -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
> CONFIG_AXP818_POWER
> +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP806_POWER || \
> +   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
>  # ifdef CONFIG_MACH_SUN6I
> p2wi_init();
> ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
> @@ -46,16 +56,70 @@ int pmic_bus_init(void)
> if (ret)
> return ret;
>
> +#  if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
> +   defined CONFIG_AXP818_POWER
> ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
> -# endif
> if (ret)
> return ret;
> +#  endif
> +#  ifdef CONFIG_AXP806_POWER
> +   ret = rsb_set_device_address(AXP806_DEVICE_ADDR, AXP806_RUNTIME_ADDR);
> +   if (ret)
> +   return ret;
> +#  endif
> +# endif
> +
> +# ifdef CONFIG_AXP806_POWER
> +   /*
> +* An AXP806 or AXP808 can be wired for either master mode or slave
> +* mode. The AXP806_REG_ADDR_EXT register must be set accordingly for
> +* the chip to repond to access to its other registers.
> +*/
> +#  ifdef CONFIG_AXP806_POWER_SLAVE_MODE
> +   ret = pmic2_bus_write(AXP806_REG_ADDR_EXT,
> + AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
> +#  else
> +   ret = pmic2_bus_write(AXP806_REG_ADDR_EXT,
> + 

Re: [U-Boot] [PATCH 2/2] sunxi: defconfig: Sunchip CX-A99: Raise CPU voltage and clock frequency

2017-02-26 Thread Chen-Yu Tsai
On Mon, Feb 27, 2017 at 3:02 AM, Rask Ingemann Lambertsen
 wrote:
> This patch uses the AXP808 support to raise the Cortex-A7 core voltage
> from the power-on default of 0.9 V to 1.02 V and increases the clock
> frequency from the default 1008 MHz to 1200 MHz. This is the maximum clock
> frequency listed in the vendor's sys_config.fex file.

This should really be left to a proper cpufreq/DVFS system. The bootloader
should bring up the system in a safe, usable state.

1008 MHz is the default across all Allwinner SoCs, aside from a few boards
that cannot reach it without overvoltage. It's even the default in BSP
bootloaders.


ChenYu

>
> Signed-off-by: Rask Ingemann Lambertsen 
> ---
> This patch goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99".
>
> FWIW, I seem to get away with
>
> CONFIG_SYS_CLK_FREQ=129600
> CONFIG_AXP_DCDCA_VOLT=1100
>
> but neither "Allwinner UltraOcta A80 Datasheet" (revision 1.3) nor
> "Allwinner A80 User Manual" (revision 1.3.1) say anything about the
> supported clock frequencies.
>
>  configs/Sunchip_CX-A99_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/configs/Sunchip_CX-A99_defconfig 
> b/configs/Sunchip_CX-A99_defconfig
> index 7530d7d..3b760d8 100644
> --- a/configs/Sunchip_CX-A99_defconfig
> +++ b/configs/Sunchip_CX-A99_defconfig
> @@ -4,6 +4,7 @@ CONFIG_MACH_SUN9I=y
>  CONFIG_DRAM_CLK=600
>  CONFIG_DRAM_ZQ=3881915
>  CONFIG_DRAM_ODT_EN=y
> +CONFIG_SYS_CLK_FREQ=12
>  CONFIG_MMC0_CD_PIN="PH17"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB0_VBUS_PIN="PH15"
> @@ -17,6 +18,7 @@ CONFIG_SPL=y
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
>  # CONFIG_CMD_FPGA is not set
> +CONFIG_AXP_DCDCA_VOLT=1020
>  # CONFIG_SPL_DOS_PARTITION is not set
>  # CONFIG_SPL_ISO_PARTITION is not set
>  # CONFIG_SPL_EFI_PARTITION is not set
> --
> 2.10.2
>
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[U-Boot] [PATCH 3/3] board: at91sam9rlek: clean up code

2017-02-26 Thread Wenyou Yang
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
---

 board/atmel/at91sam9rlek/at91sam9rlek.c | 18 --
 1 file changed, 18 deletions(-)

diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c 
b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 994f246078..24eb763750 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -18,10 +18,6 @@
 
 #include 
 #include 
-#include 
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -159,22 +155,8 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-   at91_mci_hw_init();
-
-   return atmel_mci_init((void *)ATMEL_BASE_MCI);
-}
-#endif
-
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-
return 0;
 }
 
-- 
2.11.0

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[U-Boot] [PATCH 2/3] configs: at91sam9rlek: update for DT and DM support

2017-02-26 Thread Wenyou Yang
Support the device tree and enable CONFIG_CLK and CONFIG_PINCTRL
to support at91 clock driver and at91 pinctrl driver.

Enable DM_GPIO, DM_MMC support, move CONFIG_AT91_GPIO and
CONFIG_GENERIC_ATMEL_MCI config option to the default config files.

Signed-off-by: Wenyou Yang 
---

 configs/at91sam9rlek_dataflash_defconfig | 14 +-
 configs/at91sam9rlek_mmc_defconfig   | 14 +-
 configs/at91sam9rlek_nandflash_defconfig | 14 +-
 include/configs/at91sam9rlek.h   |  8 
 4 files changed, 39 insertions(+), 11 deletions(-)

diff --git a/configs/at91sam9rlek_dataflash_defconfig 
b/configs/at91sam9rlek_dataflash_defconfig
index 49e1353b7d..1d52a3f9ab 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -20,5 +22,15 @@ CONFIG_CMD_MMC=y
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_mmc_defconfig 
b/configs/at91sam9rlek_mmc_defconfig
index 483d9b68ec..944cc88acc 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -20,5 +22,15 @@ CONFIG_CMD_MMC=y
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig 
b/configs/at91sam9rlek_nandflash_defconfig
index d7f2d7f1b3..f1406cc4fa 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -20,5 +22,15 @@ CONFIG_CMD_MMC=y
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 4d0e7b48f1..3799706c0a 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -29,8 +29,6 @@
 #define CONFIG_INITRD_TAG  1
 
 #define CONFIG_ATMEL_LEGACY
-#define CONFIG_AT91_GPIO   1
-#define CONFIG_AT91_GPIO_PULLUP1
 
 /*
  * Hardware drivers
@@ -102,12 +100,6 @@
 
 #endif
 
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#endif
-
 /* Ethernet - not present */
 
 /* USB - not supported */
-- 
2.11.0

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[U-Boot] [PATCH 1/3] ARM: dts: at91: add dts files for at91sam9rlek

2017-02-26 Thread Wenyou Yang
The device tree source files of at91sam9rlek boards are copied
from the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang 
---

 arch/arm/dts/Makefile |2 +
 arch/arm/dts/at91sam9rl.dtsi  | 1124 +
 arch/arm/dts/at91sam9rlek.dts |  237 +
 3 files changed, 1363 insertions(+)
 create mode 100644 arch/arm/dts/at91sam9rl.dtsi
 create mode 100644 arch/arm/dts/at91sam9rlek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0403a389a9..5d4cb236c1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -330,6 +330,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
at91sam9g20ek.dtb   \
at91sam9g20ek_2mmc.dtb
 
+dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
 
 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi
new file mode 100644
index 00..c6f5443488
--- /dev/null
+++ b/arch/arm/dts/at91sam9rl.dtsi
@@ -0,0 +1,1124 @@
+/*
+ * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
+ *
+ *  Copyright (C) 2014 Alexandre Belloni 
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Atmel AT91SAM9RL family SoC";
+   compatible = "atmel,at91sam9rl", "atmel,at91sam9";
+   interrupt-parent = <>;
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   tcb0 = 
+   i2c0 = 
+   i2c1 = 
+   ssc0 = 
+   ssc1 = 
+   pwm0 = 
+   };
+
+   cpus {
+   #address-cells = <0>;
+   #size-cells = <0>;
+
+   cpu {
+   compatible = "arm,arm926ej-s";
+   device_type = "cpu";
+   };
+   };
+
+   memory {
+   reg = <0x2000 0x0400>;
+   };
+
+   clocks {
+   slow_xtal: slow_xtal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   main_xtal: main_xtal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   adc_op_clk: adc_op_clk{
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <100>;
+   };
+   };
+
+   sram: sram@0030 {
+   compatible = "mmio-sram";
+   reg = <0x0030 0x1>;
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   fb0: fb@0050 {
+   compatible = "atmel,at91sam9rl-lcdc";
+   reg = <0x0050 0x1000>;
+   interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_fb>;
+   clocks = <_clk>, <_clk>;
+   clock-names = "hclk", "lcdc_clk";
+   status = "disabled";
+   };
+
+   nand0: nand@4000 {
+   compatible = "atmel,at91rm9200-nand";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x4000 0x1000>,
+ <0xe800 0x200>;
+   atmel,nand-addr-offset = <21>;
+   atmel,nand-cmd-offset = <22>;
+   atmel,nand-has-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <_nand>;
+   gpios = < 17 GPIO_ACTIVE_HIGH>,
+   < 6 GPIO_ACTIVE_HIGH>,
+   <0>;
+   status = "disabled";
+   };
+
+   apb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   tcb0: timer@fffa {
+   compatible = "atmel,at91rm9200-tcb";
+   reg = <0xfffa 0x100>;
+ 

[U-Boot] [PATCH 0/3] board: at91sam9rlek: convert to support DM and DT

2017-02-26 Thread Wenyou Yang
The purpose of the patch set is to convert the board to support
the Driver Model and the Device Tree.


Wenyou Yang (3):
  ARM: dts: at91: add dts files for at91sam9rlek
  configs: at91sam9rlek: update for DT and DM support
  board: at91sam9rlek: clean up code

 arch/arm/dts/Makefile|2 +
 arch/arm/dts/at91sam9rl.dtsi | 1124 ++
 arch/arm/dts/at91sam9rlek.dts|  237 +++
 board/atmel/at91sam9rlek/at91sam9rlek.c  |   18 -
 configs/at91sam9rlek_dataflash_defconfig |   14 +-
 configs/at91sam9rlek_mmc_defconfig   |   14 +-
 configs/at91sam9rlek_nandflash_defconfig |   14 +-
 include/configs/at91sam9rlek.h   |8 -
 8 files changed, 1402 insertions(+), 29 deletions(-)
 create mode 100644 arch/arm/dts/at91sam9rl.dtsi
 create mode 100644 arch/arm/dts/at91sam9rlek.dts

-- 
2.11.0

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Re: [U-Boot] [PULL] u-boot-usb/master

2017-02-26 Thread Tom Rini
On Sun, Feb 26, 2017 at 05:51:19PM +0100, Marek Vasut wrote:

> Hi,
> 
> mostly DFU fixes for current release .
> 
> The following changes since commit b24cf8540a85a9bf97975aadd6a7542f166c78a3:
> 
>   video: mxsfb: Fix reset hang when videomode variable is not present
> (2017-02-22 21:47:59 +0100)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 9bf9e813584c23b677e92d8dca742ae9ef27fc94:
> 
>   usb: gadget: f_dfu: set serial number if serial# is valid (2017-02-26
> 13:24:30 +0100)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] Please pull u-boot-rockchip

2017-02-26 Thread Tom Rini
On Thu, Feb 23, 2017 at 09:42:57AM -0700, Simon Glass wrote:

> Hi Tom,
> 
> This includes support for two SoCs that have been in the works for a while:
> rk3188 from Heiko Stübner and and SPL for rk3399 from Kever Yang. For the
> former there are a few more patches to come but I'll apply them in a few
> days once I've had time to test. In addition this includes rk3328 also from
> Kever which is based on the rk3399 work. I've decided to bring this in also
> as the impact is minimal.
> 
> There are a few bugs in mainline affecting rockchip which I'd like to fix
> for the release also. But I want to take a bit more time to really
> understand the problem before applying anything. Hopefully I will have
> those early next week. I'm sending this pull request now as I feel
> uncomfortable having so many pending patches.
> 
> 
> The following changes since commit b24cf8540a85a9bf97975aadd6a7542f166c78a3:
> 
>   video: mxsfb: Fix reset hang when videomode variable is not present
> (2017-02-22 21:47:59 +0100)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-rockchip.git
> 
> for you to fetch changes up to 984fe3b08c8fcc61253965c88f882411ad8c78ec:
> 
>   rockchip: rk3288: add defconfig for evb-rk3328 (2017-02-23 09:17:59 -0700)
> 
> 
> Eddie Cai (1):
>   rockchip: tinker: configs: use correct mmc instance as boot target
> device
> 
> Heiko Stübner (18):
>   dm: allow limiting pre-reloc markings to spl or tpl
>   rockchip: clk: rk3288: limit gpll and cpll init to SPL build
>   rockchip: rk3288: sdram: use constants in ddrconf table
>   rockchip: rk3288: sdram: style fixes from rk3188 sdram review
>   rockchip: Move bootrom helper compilation to a hidden option
>   rockchip: Move bootrom-related declarations to a header
>   rockchip: mkimage: Allow encoding of loader code in spl images
>   rockchip: mkimage: Add support rk3188 serial
>   rockchip: serial: Adapt rockchip of-platdata driver for rk3188
>   rockchip: rk3188: Add header files for PMU and GRF
>   rockchip: rk3188: Add pinctrl driver
>   rockchip: rk3188: Add sysreset driver
>   rockchip: rk3188: Add rk3066/rk3188 clock bindings
>   rockchip: rk3188: Add clock driver
>   rockchip: rk3188: Add core devicetree files
>   rockchip: rk3188: Add core support
>   rockchip: rk3188: Add sdram driver
>   rockchip: rk3188: Add main, spl and tpl boards
> 
> Jacob Chen (1):
>   rockchip: firefly: configs: remove config_spl_of_platdata
> 
> Kever Yang (16):
>   rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h
>   rockchip: clk: rk3399: update driver for spl
>   rockchip: sdhci: rk3399: update driver to support of-platdata
>   rockchip: pinctrl: rk3399: add the of-platdata support
>   rockchip: arm64: rk3399: syscon addition for rk3399
>   rockchip: arm64: rk3399: add ddr controller driver
>   rockchip: dts: rk3399: update for spl require driver
>   rockchip: arm64: rk3399: add SPL support
>   rockchip: config: rk3399: enable SPL config for evb-rk3399
>   rockchip: rk3328: add device tree file
>   rockchip: rk3328: add soc basic support
>   rockchip: rk3328: add clock driver
>   rockchip: rk3328: add pinctrl driver
>   rockchip: rk3328: add sysreset driver
>   rockchip: rk3328: add evb-rk3328 support
>   rockchip: rk3288: add defconfig for evb-rk3328
> 
>  arch/arm/dts/Makefile  |1 +
>  arch/arm/dts/rk3188.dtsi   |  601
> ++
>  arch/arm/dts/rk3328-evb.dts|   45 +
>  arch/arm/dts/rk3328.dtsi   | 1477
> +
>  arch/arm/dts/rk3399-evb.dts|2 +
>  arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 1536
> +++
>  arch/arm/dts/rk3399.dtsi   |   44 +
>  arch/arm/dts/rk3xxx.dtsi   |  417 ++
>  arch/arm/include/asm/arch-rockchip/bootrom.h   |   22 +
>  arch/arm/include/asm/arch-rockchip/clock.h |9 +
>  arch/arm/include/asm/arch-rockchip/cru_rk3188.h|  191 +
>  arch/arm/include/asm/arch-rockchip/cru_rk3328.h|   70 ++
>  arch/arm/include/asm/arch-rockchip/cru_rk3399.h|5 +
>  arch/arm/include/asm/arch-rockchip/ddr_rk3188.h|   25 +
>  arch/arm/include/asm/arch-rockchip/ddr_rk3288.h|8 +
>  arch/arm/include/asm/arch-rockchip/grf_rk3188.h|  589
> ++
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h|  134 +++
>  arch/arm/include/asm/arch-rockchip/grf_rk3399.h|  118 +++
>  arch/arm/include/asm/arch-rockchip/pmu_rk3188.h|   36 +
>  arch/arm/include/asm/arch-rockchip/sdram_rk3399.h  |  119 +++
>  arch/arm/mach-rockchip/Kconfig  

Re: [U-Boot] [PATCH] travis-ci: Temporarily disable using a newer device tree compiler

2017-02-26 Thread Tom Rini
On Sun, Feb 26, 2017 at 08:01:19PM -0500, Tom Rini wrote:

> For a long while dtc has warned about various constructs.  This is now
> leading to log file size being exceeded in travis, and as the majority
> of these errors need to be fixed in the kernel, switch to using the
> stock device-tree-compiler package.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

But I'm not happy to have to apply it, either.  I do not wish to break
travis-ci, but sun7i is now exceeding the allowed stdout size.  And
these are problems that need to be fixed in the kernel first, rather
than here first.  The patches to fix u-boot local issues (such as x86
never got picked up either, but likely need to be respun.  I expect that
once the new DTC version is tagged and populated upstream in the kernel
as well, we will be able to re-enable the changes we had here.

-- 
Tom


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Re: [U-Boot] pull request: u-boot-uniphier/master

2017-02-26 Thread Tom Rini
On Thu, Feb 23, 2017 at 11:03:24AM +0900, Masahiro Yamada wrote:

> Hi Tom,
> 
> Please pull the 4th round of UniPhier updates for v2017.03:
> 
>   - Fix regressions caused by the previous reworks
>   - Add pin configuration support
>   - Re-work SPL code
>   - Update DRAM and PLL setup code
>   - Enable needed configs, disable unneeded configs
> 
> 
> The following changes since commit b24cf8540a85a9bf97975aadd6a7542f166c78a3:
> 
>   video: mxsfb: Fix reset hang when videomode variable is not present
> (2017-02-22 21:47:59 +0100)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-uniphier.git master
> 
> for you to fetch changes up to bc647958047cd03193e19cd8c08a6771fea828b7:
> 
>   ARM: uniphier: set up charge pump current for MPLL of LD11 SoC
> (2017-02-23 09:00:16 +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] openrd: disable private arch memset, memcpy and libgcc

2017-02-26 Thread Tom Rini
On Sun, Feb 26, 2017 at 04:29:32PM +0100, Albert ARIBAUD wrote:

> The switch to private LIBGCC causes 'undefined instruction'
> exception in at least the Open-RD Ultimate and Client, and
> quite probably the Open-RD Base as well.
> 
> While debugging this issue, it appeared the switch to
> architecture-optimized memset and memcpy also causes the
> same exceptions.
> 
> Until a fix to private libgcc and architecture-optimized
> memcpy and memset is mainlined, disable their use in all
> openrd configurations.
> 
> Signed-off-by: Albert ARIBAUD 

Implementation wise, there's two big problems here.  First, all of the
code we're talking about is a direct drop-in from the kernel.  So
whatever is wrong here is a problem that the kernel itself can trigger,
so needs sorting out and fixing.  Second, do you have more details on
how to recreate (or not recreate) these problems?

> ---
> 
>  configs/openrd_base_defconfig | 4 
>  configs/openrd_client_defconfig   | 4 
>  configs/openrd_ultimate_defconfig | 4 
>  3 files changed, 12 insertions(+)
> 
> diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
> index 067ddbc5cc..4b8c51a771 100644
> --- a/configs/openrd_base_defconfig
> +++ b/configs/openrd_base_defconfig
> @@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
>  CONFIG_USB=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_OF_LIBFDT=y
> +# Private memcpy, memset and libgcc cause undefined instruction exceptions
> +CONFIG_USE_ARCH_MEMSET=n
> +CONFIG_USE_ARCH_MEMCPY=n
> +CONFIG_USE_PRIVATE_LIBGCC=n
> diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
> index b90ead158f..04f243a57b 100644
> --- a/configs/openrd_client_defconfig
> +++ b/configs/openrd_client_defconfig
> @@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
>  CONFIG_USB=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_OF_LIBFDT=y
> +# Private memcpy, memset and libgcc cause undefined instruction exceptions
> +CONFIG_USE_ARCH_MEMSET=n
> +CONFIG_USE_ARCH_MEMCPY=n
> +CONFIG_USE_PRIVATE_LIBGCC=n
> diff --git a/configs/openrd_ultimate_defconfig 
> b/configs/openrd_ultimate_defconfig
> index 2bc8ace8d0..c8d4c3176f 100644
> --- a/configs/openrd_ultimate_defconfig
> +++ b/configs/openrd_ultimate_defconfig
> @@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
>  CONFIG_USB=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_OF_LIBFDT=y
> +# Private memcpy, memset and libgcc cause undefined instruction exceptions
> +CONFIG_USE_ARCH_MEMSET=n
> +CONFIG_USE_ARCH_MEMCPY=n
> +CONFIG_USE_PRIVATE_LIBGCC=n

Content-wise, this is wrong.  Please run them past 'savedefconfig'.
Thanks!

-- 
Tom


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[U-Boot] [PATCH] travis-ci: Temporarily disable using a newer device tree compiler

2017-02-26 Thread Tom Rini
For a long while dtc has warned about various constructs.  This is now
leading to log file size being exceeded in travis, and as the majority
of these errors need to be fixed in the kernel, switch to using the
stock device-tree-compiler package.

Signed-off-by: Tom Rini 
---
 .travis.yml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 48b7b101f1c6..8333fae9b333 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,11 +28,12 @@ addons:
 - grub-efi-ia32-bin
 - rpm2cpio
 - wget
+- device-tree-compiler
 
 install:
  # install latest device tree compiler
- - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- - make -j4 -C /tmp/dtc
+ #- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ #- make -j4 -C /tmp/dtc
  # Clone uboot-test-hooks
  - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git 
/tmp/uboot-test-hooks
  - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
-- 
1.9.1

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[U-Boot] [PATCH 3/6] sunxi: dts: update sun50i-a64.dtsi from Linux

2017-02-26 Thread Andre Przywara
Now with USB and MMC for the A64 supported in mainline Linux, let's
sync our DT with what's in the official Linux repository.
This completely changes the clock representation, but U-Boot doesn't
use this anyway.
Also it switches to a new pinctrl binding, which uses generic property
names.
The only user of that was the sun8i-emac, which has just learned
how to deal with this. Since mainline Linux does not support this
Ethernet IP yet, let's copy over our previous DT nodes for that,
adjusting them to match the new clock and pinctrl bindings.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi |   2 +-
 arch/arm/dts/sun50i-a64.dtsi   | 615 +
 include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++
 include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +
 4 files changed, 411 insertions(+), 438 deletions(-)
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index 9ec81c6..a42b0fa 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -61,7 +61,7 @@
 
  {
pinctrl-names = "default";
-   pinctrl-0 = <_pins>, <_default_cd_pin>;
+   pinctrl-0 = <_pins>;
vmmc-supply = <_vcc3v3>;
cd-gpios = < 5 6 0>;
cd-inverted;
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index bef0d00..3a5515f 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -42,8 +42,9 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
-#include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -54,28 +55,28 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   cpu@0 {
+   cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
 
-   cpu@1 {
+   cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
 
-   cpu@2 {
+   cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
 
-   cpu@3 {
+   cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
@@ -83,28 +84,23 @@
};
};
 
-   psci {
-   compatible = "arm,psci-0.2";
-   method = "smc";
+   osc24M: osc24M_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
};
 
-   memory {
-   device_type = "memory";
-   reg = <0x4000 0>;
+   osc32k: osc32k_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
};
 
-   gic: interrupt-controller@1c81000 {
-   compatible = "arm,gic-400";
-   interrupt-controller;
-   #interrupt-cells = <3>;
-   #address-cells = <0>;
-
-   reg = <0x01c81000 0x1000>,
- <0x01c82000 0x2000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
-   interrupts = ;
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
};
 
timer {
@@ -119,199 +115,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
 
-   clocks {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges;
-
-   osc24M: osc24M_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   clock-output-names = "osc24M";
-   };
-
-   osc32k: osc32k_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32768>;
-   clock-output-names = "osc32k";
-   };
-
-   pll1: pll1_clk@1c2 {
-   #clock-cells = <0>;
-   compatible = 

[U-Boot] [PATCH 6/6] sunxi: dts: add Bananapi M64 .dts

2017-02-26 Thread Andre Przywara
Since mainline Linux gained support for the BananaPi-M64, let's just
copy this DT to prepare the U-Boot support for that board.
Again add the required DT nodes for the Ethernet IP.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/sun50i-a64-bananapi-m64.dts | 135 +++
 2 files changed, 137 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eeaa9e0..ffe1a9e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -299,7 +299,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
-   sun50i-a64-pine64.dtb
+   sun50i-a64-pine64.dtb \
+   sun50i-a64-bananapi-m64.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts 
b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
new file mode 100644
index 000..943b303
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include 
+
+/ {
+   model = "BananaPi-M64";
+   compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   ethernet0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   reg_vcc3v3: vcc3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+};
+
+_pins {
+   bias-pull-up;
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
+   cd-inverted;
+   disable-wp;
+   bus-width = <4>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   non-removable;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <8>;
+   non-removable;
+   cap-mmc-hw-reset;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>, <_rts_cts_pins>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   phy-handle = <>;
+   phy-mode = "rgmii";
+
+   allwinner,leds-active-low;
+   status = "okay";
+
+   

[U-Boot] [PATCH 4/6] sunxi: dts: update Pine64 .dts

2017-02-26 Thread Andre Przywara
Update the two .dts files for the Pine64 boards with those used in the
kernel. This switches from using a -common.dtsi to including the .dts
for the non-plus model in the -plus file.
Again we keep our EMAC driver nodes in, which are not yet in mainline
Linux.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/sun50i-a64-pine64-plus.dts | 16 ++--
 arch/arm/dts/sun50i-a64-pine64.dts  | 72 +++--
 2 files changed, 72 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts 
b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index 389c609..65c698c 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -40,22 +40,13 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/dts-v1/;
-
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64-pine64.dts"
 
 / {
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
 
-   chosen {
-   stdout-path = "serial0:115200n8";
-   };
-
-   /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
-   memory {
-   reg = <0x4000 0x4000>;
-   };
+   /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
 };
 
  {
@@ -66,7 +57,6 @@
status = "okay";
 
phy1: ethernet-phy@1 {
-   reg = <1>;
+   reg = <1>;
};
 };
-
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts 
b/arch/arm/dts/sun50i-a64-pine64.dts
index ebe029e..006aa04 100644
--- a/arch/arm/dts/sun50i-a64-pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -42,17 +42,83 @@
 
 /dts-v1/;
 
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64.dtsi"
+
+#include 
 
 / {
model = "Pine64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
 
+   aliases {
+   serial0 = 
+   ethernet0 = 
+   };
+
chosen {
stdout-path = "serial0:115200n8";
};
 
-   memory {
-   reg = <0x4000 0x2000>;
+   reg_vcc3v3: vcc3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   phy-mode = "rmii";
+   phy = <>;
+   status = "okay";
+
+   phy1: ethernet-phy@1 {
+   reg = <1>;
};
 };
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+};
+
+_pins {
+   bias-pull-up;
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
+   cd-inverted;
+   disable-wp;
+   bus-width = <4>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
+
+_otg {
+   dr_mode = "host";
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.8.2

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[U-Boot] [PATCH 5/6] sunxi: dts: remove now obsolete pine64-common.dtsi

2017-02-26 Thread Andre Przywara
Now since the common DT nodes between the two Pine64 boards have been
moved into the .dts for the non-plus model, we no longer need the
extra -common.dtsi.
Let's just remove it.

Signed-off-by: Andre Przywara 
---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi | 93 --
 1 file changed, 93 deletions(-)
 delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
deleted file mode 100644
index a42b0fa..000
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "sun50i-a64.dtsi"
-
-/ {
-
-   aliases {
-   serial0 = 
-   ethernet0 = 
-   };
-
-   soc {
-   reg_vcc3v3: vcc3v3 {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc3v3";
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   };
-   };
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins>;
-   vmmc-supply = <_vcc3v3>;
-   cd-gpios = < 5 6 0>;
-   cd-inverted;
-   status = "okay";
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins_a>;
-   status = "okay";
-};
-
- {
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins>;
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-};
-- 
2.8.2

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[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

2017-02-26 Thread Andre Przywara
Hi,

in the wake of the sunxi DM enablement series it became apparent that
the current device tree files for the A64 SoC and its board are outdated.

Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
A64 SoC and the Pine64 boards in the mainline kernel.
Linux v4.11-rc1 added MMC and USB support.
Because our preliminary device trees used in U-Boot differ significantly,
let's update our copy with what's in the current Linus' master tree.
Since in contrast to U-Boot the kernel still lacks support for Ethernet,
we keep our preliminary nodes for that IP, but adjust it slightly to
match the new clocks and reset bindings.

As the sun8i-emac driver is actually using the DT for the pinmux setup,
we teach it how to cope with the new pinctrl bindings in the first two
patches. This is probably becoming somewhat obsolete very soon (with
DM GPIO support on the list already), however I consider these two
patches as merely fixes for the existing driver to maintain bisectability.
It would make sense to merge the new DTs before the DM patches, so we
need to have something in place which works meanwhile.

Let me know what you think.

Cheers,
Andre.

Andre Przywara (6):
  sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
  net: sun8i-emac: use new, generic GPIO setup routine
  sunxi: dts: update sun50i-a64.dtsi from Linux
  sunxi: dts: update Pine64 .dts
  sunxi: dts: remove now obsolete pine64-common.dtsi
  sunxi: dts: add Bananapi M64 .dts

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++
 arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -
 arch/arm/dts/sun50i-a64-pine64-plus.dts|  16 +-
 arch/arm/dts/sun50i-a64-pine64.dts |  72 +++-
 arch/arm/dts/sun50i-a64.dtsi   | 615 +
 arch/arm/include/asm/arch-sunxi/gpio.h |   4 +
 arch/arm/mach-sunxi/pinmux.c   |  77 
 drivers/net/sun8i_emac.c   |  38 +-
 include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++
 include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +
 11 files changed, 706 insertions(+), 579 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
 delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

-- 
2.8.2

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[U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

2017-02-26 Thread Andre Przywara
Instead of hard-coding GPIO pins used for a certain peripheral, we
should just use the pinctrl information from the DT.
The sun8i-emac driver has some simple implementation of that, so
let's just generalize this and move the code into a more common
location.
On the way we add support for the new, generic pinctrl binding now
used by all Allwinner SoCs.

Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
 arch/arm/mach-sunxi/pinmux.c   | 77 ++
 2 files changed, 81 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 85a4ec3..ba8c661 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -239,4 +239,8 @@ int axp_gpio_init(void);
 static inline int axp_gpio_init(void) { return 0; }
 #endif
 
+int sunxi_gpio_parse_pin_name(const char *pin_name);
+int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
+const char * mux_name, int mux_sel);
+
 #endif /* _SUNXI_GPIO_H */
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index b026f78..f1e1e8f 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
@@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
 
return 0;
 }
+
+int sunxi_gpio_parse_pin_name(const char *pin_name)
+{
+   int pin;
+
+   if (pin_name[0] != 'P')
+   return -1;
+
+   if (pin_name[1] < 'A' || pin_name[1] > 'Z')
+   return -1;
+
+   pin = (pin_name[1] - 'A') << 5;
+   pin += simple_strtol(_name[2], NULL, 10);
+
+   return pin;
+}
+
+int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
+const char * mux_name, int mux_sel)
+{
+   int drive, pull, pin, i;
+   const char *pin_name;
+   int offset;
+
+   offset = fdtdec_lookup_phandle(fdt_blob, node, "pinctrl-0");
+   if (offset < 0)
+   return offset;
+
+   drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+"drive-strength", 0);
+   if (drive) {
+   if (drive <= 10)
+   drive = SUN4I_PINCTRL_10_MA;
+   else if (drive <= 20)
+   drive = SUN4I_PINCTRL_20_MA;
+   else if (drive <= 30)
+   drive = SUN4I_PINCTRL_30_MA;
+   else
+   drive = SUN4I_PINCTRL_40_MA;
+   } else {
+   drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+"allwinner,drive", 4);
+   }
+
+   if (fdt_get_property(fdt_blob, offset, "bias-pull-up", NULL))
+   pull = SUN4I_PINCTRL_PULL_UP;
+   else if (fdt_get_property(fdt_blob, offset, "bias-disable", NULL))
+   pull = SUN4I_PINCTRL_NO_PULL;
+   else if (fdt_get_property(fdt_blob, offset, "bias-pull-down", NULL))
+   pull = SUN4I_PINCTRL_PULL_DOWN;
+   else
+   pull = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+   "allwinner,pull", 0);
+
+   for (i = 0; ; i++) {
+   pin_name = fdt_stringlist_get(fdt_blob, offset,
+ "allwinner,pins", i, NULL);
+   if (!pin_name) {
+   pin_name = fdt_stringlist_get(fdt_blob, offset,
+ "pins", i, NULL);
+   if (!pin_name)
+   break;
+   }
+   pin = sunxi_gpio_parse_pin_name(pin_name);
+   if (pin < 0)
+   continue;
+
+   sunxi_gpio_set_cfgpin(pin, mux_sel);
+   sunxi_gpio_set_drv(pin, drive);
+   sunxi_gpio_set_pull(pin, pull);
+   }
+
+   return i;
+}
-- 
2.8.2

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[U-Boot] [PATCH 2/6] net: sun8i-emac: use new, generic GPIO setup routine

2017-02-26 Thread Andre Przywara
Instead of open-coding the fairly generic pinmux setup in the sun8i-emac
driver, let's just use the new common implementation of that.
This has also the advantage of supporting the newpinctrl bindings, so
the driver can cope with the upstream Linux DTs.

Signed-off-by: Andre Przywara 
---
 drivers/net/sun8i_emac.c | 38 ++
 1 file changed, 6 insertions(+), 32 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index abdfada..8a1ea55 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -438,42 +438,16 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev 
*priv, u8 *enetaddr)
 
 static int parse_phy_pins(struct udevice *dev)
 {
-   int offset;
-   const char *pin_name;
-   int drive, pull, i;
+   int ret = sunxi_gpio_setup_dt_pins(gd->fdt_blob, dev->of_offset,
+  "emac", SUN8I_GPD8_GMAC);
 
-   offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-  "pinctrl-0");
-   if (offset < 0) {
+   if (ret < 0) {
printf("WARNING: emac: cannot find pinctrl-0 node\n");
-   return offset;
+   return ret;
}
 
-   drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-"allwinner,drive", 4);
-   pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-   "allwinner,pull", 0);
-   for (i = 0; ; i++) {
-   int pin;
-
-   pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
- "allwinner,pins", i, NULL);
-   if (!pin_name)
-   break;
-   if (pin_name[0] != 'P')
-   continue;
-   pin = (pin_name[1] - 'A') << 5;
-   if (pin >= 26 << 5)
-   continue;
-   pin += simple_strtol(_name[2], NULL, 10);
-
-   sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
-   sunxi_gpio_set_drv(pin, drive);
-   sunxi_gpio_set_pull(pin, pull);
-   }
-
-   if (!i) {
-   printf("WARNING: emac: cannot find allwinner,pins property\n");
+   if (!ret) {
+   printf("WARNING: emac: cannot find pins property\n");
return -2;
}
 
-- 
2.8.2

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Re: [U-Boot] [PATCH 2/2] arm64: booti: allow to place kernel image anywhere in physical memory

2017-02-26 Thread Tom Rini
On Thu, Feb 23, 2017 at 10:31:17AM -0500, Tom Rini wrote:
> On Thu, Feb 23, 2017 at 06:17:38PM +0900, Masahiro Yamada wrote:
> > Hi Tom,
> > 
> > 
> > 2017-02-23 1:19 GMT+09:00 Tom Rini :
> > > On Wed, Feb 22, 2017 at 11:34:26AM +0900, Masahiro Yamada wrote:
> > >
> > >> At first, the ARM64 Linux booting requirement recommended that the
> > >> kernel image be placed text_offset bytes from 2MB aligned base near
> > >> the start of usable system RAM because memory below that base address
> > >> was unusable at that time.
> > >>
> > >> This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
> > >> allow kernel Image to be loaded anywhere in physical memory").
> > >> Since then, the bit 3 of the flags field indicates the tolerance
> > >> of the kernel physical placement.  If this bit is set, the 2MB
> > >> aligned base may be anywhere in physical memory.  For details, see
> > >> Documentation/arm64/booting.txt of Linux.
> > >>
> > >> The booti command should be also relaxed to not expect the kernel
> > >> image at the start of the system RAM.  Even when booting older
> > >> kernel versions, it still makes sense to have some space below the
> > >> kernel.  For example, some firmware may sit at the start of the
> > >> system RAM.
> > >>
> > >> After all, the most flexible way for booting the kernel is to respect
> > >> the original images->ep instead of gd->bd->bi_dram[0].start.  If
> > >> image->ep (which is the address given to the booti command) already
> > >> meets the address requirement, just use it.  If not, relocate the
> > >> kernel to the next 2MB aligned address.
> > >>
> > >> Signed-off-by: Masahiro Yamada 
> > >> ---
> > >>
> > >>  cmd/booti.c | 6 +-
> > >>  1 file changed, 5 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/cmd/booti.c b/cmd/booti.c
> > >> index f65f0e7..9408c34 100644
> > >> --- a/cmd/booti.c
> > >> +++ b/cmd/booti.c
> > >> @@ -11,6 +11,8 @@
> > >>  #include 
> > >>  #include 
> > >>  #include 
> > >> +#include 
> > >> +#include 
> > >>
> > >>  DECLARE_GLOBAL_DATA_PTR;
> > >>
> > >> @@ -54,7 +56,9 @@ static int booti_setup(bootm_headers_t *images)
> > >>* If we are not at the correct run-time location, set the new
> > >>* correct location and then move the image there.
> > >>*/
> > >> - dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
> > >> + dst = images->ep - ih->text_offset;
> > >> + dst = ALIGN(dst, SZ_2M);
> > >> + dst += ih->text_offset;
> > >
> > > I think the code will be slightly more complex here but I would rather
> > > see us check for the presence of the flag which allows for us to
> > > relocate things rather than assume that we can always use the address
> > > provided, or round it up.  The 'contract' wwith the kernel previously
> > > said it must be from start of memory and I'd rather not change that.
> > 
> > 
> > At first, I tried this approach.
> > 
> > The problem (at least for me) is
> > commit a7f8de168ace is quite new; this is only included in Linux 4.5 and 
> > later.
> > Linux 4.4 LTS will be used on Socionext's products for a while.
> > However, I need to avoid the relocation of the kernel image.
> > 
> > The gd->bd->bi_dram[0].start points to the start of the DRAM.
> > Here, some firmware is sitting at the start of the DRAM.
> > To hide the head of the memory from Linux,
> > the memory node in the device tree is carved out.
> > 
> > If CONFIG_ARCH_FIXUP_FDT_MEMORY is not set,
> > U-Boot passes the memory node as-is to Linux.
> > As a result, the Image is placed out of the available memory region
> > specified by DT,
> > then Linux fails to boot.
> > 
> > 
> > Somehow I want to achieve,
> > "Even when booting older kernel versions, it still makes sense to have
> > some space below the
> > kernel.  For example, some firmware may sit at the start of the system RAM."
> > 
> > 
> > Perhaps, can we introduce a CONFIG
> > to enable/disable the relocation?
> > Or, any other good idea?
> 
> I guess the answer is that I need to find some time to re-read the
> history on Documentation/arm64/booting.txt to see when various
> restrictions changed / were introduced.  I'm also willing to say that
> perhaps my initial implementation (or the follow up when text_offset was
> introduced) was incorrectly too strict.

So, I re-read what the changes to the document were, before and after.
Prior to the change, the kernel will not be able to use any memory below
the 2MiB aligned address.  After the change, the memory must be excluded
using normal mechanisms (and is outside of this problem here).  So,
conceptually, I'm OK with changing our logic here a bit, what I did at
first wrt text_offset was too literal.  But:
a) We need to re-work the comment in question now to explain a little
better what is going on.
b) we should continue to use le64_to_cpu() on text_offset (for
consistency).
c) I'm not convinced your math above is correct.  images->ep is where 

[U-Boot] [PATCH 2/2] sunxi: defconfig: Sunchip CX-A99: Raise CPU voltage and clock frequency

2017-02-26 Thread Rask Ingemann Lambertsen
This patch uses the AXP808 support to raise the Cortex-A7 core voltage
from the power-on default of 0.9 V to 1.02 V and increases the clock
frequency from the default 1008 MHz to 1200 MHz. This is the maximum clock
frequency listed in the vendor's sys_config.fex file.

Signed-off-by: Rask Ingemann Lambertsen 
---
This patch goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99".

FWIW, I seem to get away with

CONFIG_SYS_CLK_FREQ=129600
CONFIG_AXP_DCDCA_VOLT=1100

but neither "Allwinner UltraOcta A80 Datasheet" (revision 1.3) nor 
"Allwinner A80 User Manual" (revision 1.3.1) say anything about the
supported clock frequencies.

 configs/Sunchip_CX-A99_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index 7530d7d..3b760d8 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN9I=y
 CONFIG_DRAM_CLK=600
 CONFIG_DRAM_ZQ=3881915
 CONFIG_DRAM_ODT_EN=y
+CONFIG_SYS_CLK_FREQ=12
 CONFIG_MMC0_CD_PIN="PH17"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="PH15"
@@ -17,6 +18,7 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DCDCA_VOLT=1020
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-- 
2.10.2

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[U-Boot] [PATCH 1/2 RFT] sunxi: power: Add AXP806 and AXP808 support

2017-02-26 Thread Rask Ingemann Lambertsen
An X-Powers AXP806 or AXP808 PMIC is usually found on boards using the
Allwinner A80 ARM SoC. This patch adds support for the PMIC's regulators
and sets up the runtime address and master/slave mode in pmic_bus_init().

AXP806/AXP808 support is enabled by default on all MACH_SUN9I boards.

Because there are boards with both an AXP806 and an AXP809,
drivers/power/Kconfig and arch/arm/mach-sunxi/pmic_bus.c are changed to
make it possible to have more than one PMIC enabled at a time.

Signed-off-by: Rask Ingemann Lambertsen 
---
This patch needs to be tested on the following boards which I don't have:
Cubietech Cubieboard4
Merrii A80 Optimus

 arch/arm/include/asm/arch-sunxi/pmic_bus.h |   4 +
 arch/arm/mach-sunxi/Makefile   |   1 +
 arch/arm/mach-sunxi/pmic_bus.c | 107 ++---
 board/sunxi/board.c|  20 +++
 drivers/power/Kconfig  | 226 +++-
 drivers/power/Makefile |   1 +
 drivers/power/axp806.c | 231 +
 include/axp806.h   |  50 +++
 include/axp_pmic.h |  13 ++
 9 files changed, 623 insertions(+), 30 deletions(-)
 create mode 100644 drivers/power/axp806.c
 create mode 100644 include/axp806.h

diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h 
b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
index 9c4372a..d143d54 100644
--- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h
+++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
@@ -14,5 +14,9 @@ int pmic_bus_read(u8 reg, u8 *data);
 int pmic_bus_write(u8 reg, u8 data);
 int pmic_bus_setbits(u8 reg, u8 bits);
 int pmic_bus_clrbits(u8 reg, u8 bits);
+int pmic2_bus_read(u8 reg, u8 *data);
+int pmic2_bus_write(u8 reg, u8 data);
+int pmic2_bus_setbits(u8 reg, u8 bits);
+int pmic2_bus_clrbits(u8 reg, u8 bits);
 
 #endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba11..410fb49 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I)  += clock_sun9i.o gtbus_sun9i.o
 obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP806_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
 
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 7c57f02..a2da40c 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -27,6 +27,15 @@
 #define AXP223_DEVICE_ADDR 0x3a3
 #define AXP223_RUNTIME_ADDR0x2d
 
+/* AXP806 and AXP808 use the same addresses. */
+#define AXP806_DEVICE_ADDR 0x745
+#define AXP806_RUNTIME_ADDR0x3a
+
+/* AXP806 and AXP808 address space extension. */
+#define AXP806_REG_ADDR_EXT0xff
+#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE   0
+#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODEBIT(4)
+
 int pmic_bus_init(void)
 {
/* This cannot be 0 because it is used in SPL before BSS is ready */
@@ -36,7 +45,8 @@ int pmic_bus_init(void)
if (!needs_init)
return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP806_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -46,16 +56,70 @@ int pmic_bus_init(void)
if (ret)
return ret;
 
+#  if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+   defined CONFIG_AXP818_POWER
ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-# endif
if (ret)
return ret;
+#  endif
+#  ifdef CONFIG_AXP806_POWER
+   ret = rsb_set_device_address(AXP806_DEVICE_ADDR, AXP806_RUNTIME_ADDR);
+   if (ret)
+   return ret;
+#  endif
+# endif
+
+# ifdef CONFIG_AXP806_POWER
+   /*
+* An AXP806 or AXP808 can be wired for either master mode or slave
+* mode. The AXP806_REG_ADDR_EXT register must be set accordingly for
+* the chip to repond to access to its other registers.
+*/
+#  ifdef CONFIG_AXP806_POWER_SLAVE_MODE
+   ret = pmic2_bus_write(AXP806_REG_ADDR_EXT,
+ AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
+#  else
+   ret = pmic2_bus_write(AXP806_REG_ADDR_EXT,
+ AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
+#  endif
+   if (ret)
+   return ret;
+# endif
 #endif
 
needs_init = 0;
return 0;
 }
 
+#define PMIC_BUS_SETBITS(pmic_bus_read, pmic_bus_write, reg, bits) \
+{  \
+   int ret;

[U-Boot] [PATCH 0/2] sunxi: power: Add AXP806 and AXP808 support

2017-02-26 Thread Rask Ingemann Lambertsen
The X-Powers AXP806 and AXP808 PMICs are usually found on boards featuring
the Allwinner A80 ARM SoC. The so far supported features are the same on the
two chips. A lack of data sheets to compare makes it impossible to know for
sure what the differences are, but at least two of the power-up voltages
(bldo2 and dcdce) differ.

Patch 1 adds support for the regulators and also sets up the master/slave
mode addressing to match the way it is wired on the board. This is necessary
for the PMIC to respond to register accesses and hopefully solves the AXP806
problems for the Linux 4.9 and 4.10 kernels on Cubieboard4 and A80 Optimus
boards, where the AXP806 is wired for slave mode addressing.

Patch 2 goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99". It
updates the defconfig for the Sunchip CX-A99 board. Now that the CPU core
voltage can be controlled, the board is configured for 1200 MHz at 1020 mV,
which is the maximum according to the vendor's sys_config.fex file, instead
of the previous 1008 MHz at 900 mV.

Rask Ingemann Lambertsen (2):
  sunxi: power: Add AXP806 and AXP808 support
  sunxi: defconfig: Sunchip CX-A99: Raise CPU voltage and clock frequency

 arch/arm/include/asm/arch-sunxi/pmic_bus.h |   4 +
 arch/arm/mach-sunxi/Makefile   |   1 +
 arch/arm/mach-sunxi/pmic_bus.c | 107 ++---
 board/sunxi/board.c|  20 +++
 configs/Sunchip_CX-A99_defconfig   |   2 +
 drivers/power/Kconfig  | 226 +++-
 drivers/power/Makefile |   1 +
 drivers/power/axp806.c | 231 +
 include/axp806.h   |  50 +++
 include/axp_pmic.h |  13 ++
 10 files changed, 625 insertions(+), 30 deletions(-)
 create mode 100644 drivers/power/axp806.c
 create mode 100644 include/axp806.h

-- 
2.10.2
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[U-Boot] [PULL] u-boot-usb/master

2017-02-26 Thread Marek Vasut
Hi,

mostly DFU fixes for current release .

The following changes since commit b24cf8540a85a9bf97975aadd6a7542f166c78a3:

  video: mxsfb: Fix reset hang when videomode variable is not present
(2017-02-22 21:47:59 +0100)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to 9bf9e813584c23b677e92d8dca742ae9ef27fc94:

  usb: gadget: f_dfu: set serial number if serial# is valid (2017-02-26
13:24:30 +0100)


Felipe Balbi (3):
  usb: gadget: f_dfu: write req->actual bytes
  usb: gadget: g_dnl: fix g_dnl_set_serialnumber()
  usb: gadget: f_dfu: set serial number if serial# is valid

Patrick Delaunay (3):
  usb: gadget: dfu: add functional descriptor in descriptor set
  usb: gadget: dfu: correct size for USB_REQ_DFU_GETSTATE result
  usb: gadget: dfu: add result for handle_getstatus()

Vincent Tinelli (1):
  usb: dwc3: gadget: Remove unused header inclusion

 drivers/usb/dwc3/gadget.c  |  1 -
 drivers/usb/gadget/f_dfu.c | 73
+++--
 drivers/usb/gadget/f_dfu.h |  1 -
 drivers/usb/gadget/g_dnl.c |  3 +--
 4 files changed, 40 insertions(+), 38 deletions(-)
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[U-Boot] [PATCHV2] tools: plbimage support generate rcw file

2017-02-26 Thread yuan linyu
From: yuan linyu 

some system will not generate pbl format u-boot, but require rcw.

Signed-off-by: yuan linyu 
---
 tools/pblimage.c | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/tools/pblimage.c b/tools/pblimage.c
index 16d94c98c6..30055a9463 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -194,17 +194,20 @@ void pbl_load_uboot(int ifd, struct image_tool_params 
*params)
pbl_parser(params->imagename);
 
/* parse the pbi.cfg file. */
-   pbl_parser(params->imagename2);
+   if (params->imagename2[0] != '\0')
+   pbl_parser(params->imagename2);
+
+   if (params->datafile) {
+   fp_uboot = fopen(params->datafile, "r");
+   if (fp_uboot == NULL) {
+   printf("Error: %s open failed\n", params->datafile);
+   exit(EXIT_FAILURE);
+   }
 
-   fp_uboot = fopen(params->datafile, "r");
-   if (fp_uboot == NULL) {
-   printf("Error: %s open failed\n", params->datafile);
-   exit(EXIT_FAILURE);
+   load_uboot(fp_uboot);
+   fclose(fp_uboot);
}
-
-   load_uboot(fp_uboot);
add_end_cmd();
-   fclose(fp_uboot);
lseek(ifd, 0, SEEK_SET);
 
size = pbl_size;
@@ -265,21 +268,24 @@ int pblimage_check_params(struct image_tool_params 
*params)
if (!params)
return EXIT_FAILURE;
 
-   fp_uboot = fopen(params->datafile, "r");
-   if (fp_uboot == NULL) {
-   printf("Error: %s open failed\n", params->datafile);
-   exit(EXIT_FAILURE);
-   }
-   fd = fileno(fp_uboot);
+   if (params->datafile) {
+   fp_uboot = fopen(params->datafile, "r");
+   if (fp_uboot == NULL) {
+   printf("Error: %s open failed\n", params->datafile);
+   exit(EXIT_FAILURE);
+   }
+   fd = fileno(fp_uboot);
 
-   if (fstat(fd, ) == -1) {
-   printf("Error: Could not determine u-boot image size. %s\n",
-  strerror(errno));
-   exit(EXIT_FAILURE);
-   }
+   if (fstat(fd, ) == -1) {
+   printf("Error: Could not determine u-boot image size. 
%s\n",
+  strerror(errno));
+   exit(EXIT_FAILURE);
+   }
 
-   /* For the variable size, we need to pad it to 64 byte boundary */
-   uboot_size = roundup(st.st_size, 64);
+   /* For the variable size, we need to pad it to 64 byte boundary 
*/
+   uboot_size = roundup(st.st_size, 64);
+   fclose(fp_uboot);
+   }
 
if (params->arch == IH_ARCH_ARM) {
arch_flag = IH_ARCH_ARM;
-- 
2.11.1


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[U-Boot] [PATCH] tools: plbimage support generate rcw file

2017-02-26 Thread yuan linyu
From: yuan linyu 

some system will not generate pbl format u-boot, but require rcw.

Signed-off-by: yuan linyu 
---
 tools/pblimage.c | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/tools/pblimage.c b/tools/pblimage.c
index 16d94c98c6..30055a9463 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -194,17 +194,20 @@ void pbl_load_uboot(int ifd, struct image_tool_params 
*params)
pbl_parser(params->imagename);
 
/* parse the pbi.cfg file. */
-   pbl_parser(params->imagename2);
+   if (params->imagename2[0] != '\0')
+   pbl_parser(params->imagename2);
+
+   if (params->datafile) {
+   fp_uboot = fopen(params->datafile, "r");
+   if (fp_uboot == NULL) {
+   printf("Error: %s open failed\n", params->datafile);
+   exit(EXIT_FAILURE);
+   }
 
-   fp_uboot = fopen(params->datafile, "r");
-   if (fp_uboot == NULL) {
-   printf("Error: %s open failed\n", params->datafile);
-   exit(EXIT_FAILURE);
+   load_uboot(fp_uboot);
+   fclose(fp_uboot);
}
-
-   load_uboot(fp_uboot);
add_end_cmd();
-   fclose(fp_uboot);
lseek(ifd, 0, SEEK_SET);
 
size = pbl_size;
@@ -265,21 +268,24 @@ int pblimage_check_params(struct image_tool_params 
*params)
if (!params)
return EXIT_FAILURE;
 
-   fp_uboot = fopen(params->datafile, "r");
-   if (fp_uboot == NULL) {
-   printf("Error: %s open failed\n", params->datafile);
-   exit(EXIT_FAILURE);
-   }
-   fd = fileno(fp_uboot);
+   if (params->datafile) {
+   fp_uboot = fopen(params->datafile, "r");
+   if (fp_uboot == NULL) {
+   printf("Error: %s open failed\n", params->datafile);
+   exit(EXIT_FAILURE);
+   }
+   fd = fileno(fp_uboot);
 
-   if (fstat(fd, ) == -1) {
-   printf("Error: Could not determine u-boot image size. %s\n",
-  strerror(errno));
-   exit(EXIT_FAILURE);
-   }
+   if (fstat(fd, ) == -1) {
+   printf("Error: Could not determine u-boot image size. 
%s\n",
+  strerror(errno));
+   exit(EXIT_FAILURE);
+   }
 
-   /* For the variable size, we need to pad it to 64 byte boundary */
-   uboot_size = roundup(st.st_size, 64);
+   /* For the variable size, we need to pad it to 64 byte boundary 
*/
+   uboot_size = roundup(st.st_size, 64);
+   fclose(fp_uboot);
+   }
 
if (params->arch == IH_ARCH_ARM) {
arch_flag = IH_ARCH_ARM;
-- 
2.11.1


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[U-Boot] [PATCH] openrd: disable private arch memset, memcpy and libgcc

2017-02-26 Thread Albert ARIBAUD
The switch to private LIBGCC causes 'undefined instruction'
exception in at least the Open-RD Ultimate and Client, and
quite probably the Open-RD Base as well.

While debugging this issue, it appeared the switch to
architecture-optimized memset and memcpy also causes the
same exceptions.

Until a fix to private libgcc and architecture-optimized
memcpy and memset is mainlined, disable their use in all
openrd configurations.

Signed-off-by: Albert ARIBAUD 
---

 configs/openrd_base_defconfig | 4 
 configs/openrd_client_defconfig   | 4 
 configs/openrd_ultimate_defconfig | 4 
 3 files changed, 12 insertions(+)

diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 067ddbc5cc..4b8c51a771 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+# Private memcpy, memset and libgcc cause undefined instruction exceptions
+CONFIG_USE_ARCH_MEMSET=n
+CONFIG_USE_ARCH_MEMCPY=n
+CONFIG_USE_PRIVATE_LIBGCC=n
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index b90ead158f..04f243a57b 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+# Private memcpy, memset and libgcc cause undefined instruction exceptions
+CONFIG_USE_ARCH_MEMSET=n
+CONFIG_USE_ARCH_MEMCPY=n
+CONFIG_USE_PRIVATE_LIBGCC=n
diff --git a/configs/openrd_ultimate_defconfig 
b/configs/openrd_ultimate_defconfig
index 2bc8ace8d0..c8d4c3176f 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -21,3 +21,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+# Private memcpy, memset and libgcc cause undefined instruction exceptions
+CONFIG_USE_ARCH_MEMSET=n
+CONFIG_USE_ARCH_MEMCPY=n
+CONFIG_USE_PRIVATE_LIBGCC=n
-- 
2.11.0

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Re: [U-Boot] [PATCH v4 2/7] arm: usb: dra7xx: xHCI registers based on USB port index

2017-02-26 Thread Tom Rini
On Thu, Feb 23, 2017 at 03:39:36PM +0200, Uri Mashiach wrote:

> Modify the determination of the base address of xHCI registers of DRA7XX
> targets.
> Before the commit: by the target.
> After the commit: by the USB port index.
> 
> Cc: Lokesh Vutla 
> Cc: Marek Vasut 
> Cc: Roger Quadros 
> Signed-off-by: Uri Mashiach 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v4 1/7] arm: dra7xx: move CONFIG_DRA7XX to Kconfig

2017-02-26 Thread Tom Rini
On Thu, Feb 23, 2017 at 03:39:35PM +0200, Uri Mashiach wrote:

> The symbol CONFIG_DRA7XX is needed for Kconfig conditions.
> 
> Cc: Lokesh Vutla 
> Signed-off-by: Uri Mashiach 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [GIT] Pull request: u-boot-dfu

2017-02-26 Thread Marek Vasut
On 02/22/2017 01:36 PM, Lukasz Majewski wrote:
> Dear Marek,

Pulled, thanks.

> Please find pull request for dfu repository:
> 
> The following changes since commit cc84f46800752edefb45a8a2de59ab6650dc4840:
> 
>   usb: dwc3: gadget: Remove unused header inclusion (2017-02-14 17:19:20 
> +0100)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-dfu.git 
> 
> for you to fetch changes up to 97786cc0ee07dabfbbd471ee686be1df82d3db64:
> 
>   usb: gadget: f_dfu: set serial number if serial# is valid (2017-02-22 
> 13:22:05 +0100)
> 
> 
> Felipe Balbi (3):
>   usb: gadget: f_dfu: write req->actual bytes
>   usb: gadget: g_dnl: fix g_dnl_set_serialnumber()
>   usb: gadget: f_dfu: set serial number if serial# is valid
> 
> Patrick Delaunay (3):
>   usb: gadget: dfu: add functional descriptor in descriptor set
>   usb: gadget: dfu: correct size for USB_REQ_DFU_GETSTATE result
>   usb: gadget: dfu: add result for handle_getstatus()
> 
>  drivers/usb/gadget/f_dfu.c | 73 
> +++--
>  drivers/usb/gadget/f_dfu.h |  1 -
>  drivers/usb/gadget/g_dnl.c |  3 +--
>  3 files changed, 40 insertions(+), 37 deletions(-)
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
> 


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Re: [U-Boot] [PATCH v4 3/7] usb: host: xhci-omap: fix double weak board_usb_init functions

2017-02-26 Thread Marek Vasut
On 02/26/2017 01:25 PM, Igor Grinberg wrote:
> Cc Marex...

This came just in time to answer my concern /wrt patch 4/7, thanks.

> On 02/23/17 15:39, Uri Mashiach wrote:
>> A weak version of the function board_usb_init is implemented in:
>> common/usb.c
>> drivers/usb/host/xhci-omap.c
>>
>> To fix the double implementations:
>> * Convert the board_usb_init function in drivers/usb/host/xhci-omap.c
>>   normal (not weak).
>> * The function board_usb_init in drivers/usb/host/xhci-omap.c calls to
>>   the weak function omap_xhci_board_usb_init.
>> * Rename board version of the function board_usb_init to
>>   omap_xhci_board_usb_init.
>>   Done only for boards that defines CONFIG_USB_XHCI_OMAP.
>>
>> To achieve the same flexibility with the function board_usb_cleanup:
>> * Add a normal (not weak) implementation of the function
>>   board_usb_cleanup in drivers/usb/host/xhci-omap.c
>> * The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls
>>   to the weak function omap_xhci_board_usb_cleanup.
>> * Rename board version of the function board_usb_cleanup to
>>   omap_xhci_board_usb_cleanup.
>>   Done only for boards that defines CONFIG_USB_XHCI_OMAP.
>>
>> Cc: Lokesh Vutla 
>> Signed-off-by: Uri Mashiach 
>> Acked-by: Marek Vasut 
>> Reviewed-by: Tom Rini 

Would be great to get a review from someone from TI, but I'm fine with this.

>> ---
>> V1 -> V2: Use __weak instead of attribute block
>> V2 -> V4: none
>>
>>  board/compulab/cl-som-am57x/cl-som-am57x.c |  2 +-
>>  board/ti/am43xx/board.c|  4 ++--
>>  board/ti/am57xx/board.c|  4 ++--
>>  board/ti/dra7xx/evm.c  |  4 ++--
>>  drivers/usb/host/xhci-omap.c   | 17 +++--
>>  5 files changed, 22 insertions(+), 9 deletions(-)
>>
>> diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c 
>> b/board/compulab/cl-som-am57x/cl-som-am57x.c
>> index bdd0a2b..fe1468f 100644
>> --- a/board/compulab/cl-som-am57x/cl-som-am57x.c
>> +++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
>> @@ -54,7 +54,7 @@ int board_mmc_init(bd_t *bis)
>>  #endif /* CONFIG_GENERIC_MMC */
>>  
>>  #ifdef CONFIG_USB_XHCI_OMAP
>> -int board_usb_init(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>>  {
>>  setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
>>   OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
>> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
>> index 390cc16..2572029 100644
>> --- a/board/ti/am43xx/board.c
>> +++ b/board/ti/am43xx/board.c
>> @@ -694,7 +694,7 @@ int usb_gadget_handle_interrupts(int index)
>>  #endif /* CONFIG_USB_DWC3 */
>>  
>>  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
>> -int board_usb_init(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>>  {
>>  enable_usb_clocks(index);
>>  #ifdef CONFIG_USB_DWC3
>> @@ -725,7 +725,7 @@ int board_usb_init(int index, enum usb_init_type init)
>>  return 0;
>>  }
>>  
>> -int board_usb_cleanup(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>>  {
>>  #ifdef CONFIG_USB_DWC3
>>  switch (index) {
>> diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
>> index 1611514..4afa914 100644
>> --- a/board/ti/am57xx/board.c
>> +++ b/board/ti/am57xx/board.c
>> @@ -618,7 +618,7 @@ int usb_gadget_handle_interrupts(int index)
>>  #endif /* CONFIG_USB_DWC3 */
>>  
>>  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
>> -int board_usb_init(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>>  {
>>  enable_usb_clocks(index);
>>  switch (index) {
>> @@ -652,7 +652,7 @@ int board_usb_init(int index, enum usb_init_type init)
>>  return 0;
>>  }
>>  
>> -int board_usb_cleanup(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>>  {
>>  #ifdef CONFIG_USB_DWC3
>>  switch (index) {
>> diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
>> index bd1c809..65bce93 100644
>> --- a/board/ti/dra7xx/evm.c
>> +++ b/board/ti/dra7xx/evm.c
>> @@ -727,7 +727,7 @@ static struct ti_usb_phy_device usb_phy2_device = {
>>  .index = 1,
>>  };
>>  
>> -int board_usb_init(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>>  {
>>  enable_usb_clocks(index);
>>  switch (index) {
>> @@ -764,7 +764,7 @@ int board_usb_init(int index, enum usb_init_type init)
>>  return 0;
>>  }
>>  
>> -int board_usb_cleanup(int index, enum usb_init_type init)
>> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>>  {
>>  switch (index) {
>>  case 0:
>> diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c

Re: [U-Boot] [PATCH v4 2/7] arm: usb: dra7xx: xHCI registers based on USB port index

2017-02-26 Thread Marek Vasut
On 02/23/2017 02:39 PM, Uri Mashiach wrote:
> Modify the determination of the base address of xHCI registers of DRA7XX
> targets.
> Before the commit: by the target.
> After the commit: by the USB port index.
> 
> Cc: Lokesh Vutla 
> Cc: Marek Vasut 
> Cc: Roger Quadros 
> Signed-off-by: Uri Mashiach 

It still sucks and I'm not impressed, but
Reviewed-by: Marek Vasut 

I'd still like a review from one of the TI guys, this will go into next
release anyway, so there's still some time .

> ---
> V1 -> V2: Replace the commit "fix XHCI registers base address".
> V2 -> V3: Replace the commit "reintroduce the CONFIG_AM57XX symbol"
> V3 -> V4: Replace boolean symbols USB_XHCI_DRA7XX_INDEX0 and 
> USB_XHCI_DRA7XX_INDEX1 with
> integer symbol USB_XHCI_DRA7XX_INDEX.
> 
>  configs/dra7xx_evm_defconfig| 1 +
>  configs/dra7xx_hs_evm_defconfig | 1 +
>  drivers/usb/host/Kconfig| 9 +
>  include/linux/usb/xhci-omap.h   | 6 --
>  4 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
> index 26b26cc..05f7778 100644
> --- a/configs/dra7xx_evm_defconfig
> +++ b/configs/dra7xx_evm_defconfig
> @@ -86,6 +86,7 @@ CONFIG_OMAP_TIMER=y
>  CONFIG_USB=y
>  CONFIG_USB_XHCI_HCD=y
>  CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_XHCI_DRA7XX_INDEX=1
>  CONFIG_USB_DWC3=y
>  CONFIG_USB_DWC3_GADGET=y
>  CONFIG_USB_DWC3_OMAP=y
> diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
> index 244940c..23ae2c7 100644
> --- a/configs/dra7xx_hs_evm_defconfig
> +++ b/configs/dra7xx_hs_evm_defconfig
> @@ -91,6 +91,7 @@ CONFIG_OMAP_TIMER=y
>  CONFIG_USB=y
>  CONFIG_USB_XHCI_HCD=y
>  CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_XHCI_DRA7XX_INDEX=1
>  CONFIG_USB_DWC3=y
>  CONFIG_USB_DWC3_GADGET=y
>  CONFIG_USB_DWC3_OMAP=y
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 5129a57..3ff79fc 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -43,6 +43,15 @@ config USB_XHCI_ZYNQMP
>   help
> Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
>  
> +config USB_XHCI_DRA7XX_INDEX
> + int "DRA7XX xHCI USB index"
> + range 0 1
> + default 0
> + depends on DRA7XX
> + help
> +   Select the DRA7XX xHCI USB index.
> +   Current supported values: 0, 1.
> +
>  endif # USB_XHCI_HCD
>  
>  config USB_EHCI_HCD
> diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
> index 9de80d7..f038ddb 100644
> --- a/include/linux/usb/xhci-omap.h
> +++ b/include/linux/usb/xhci-omap.h
> @@ -10,14 +10,16 @@
>  #ifndef _ASM_ARCH_XHCI_OMAP_H_
>  #define _ASM_ARCH_XHCI_OMAP_H_
>  
> -#ifdef CONFIG_TARGET_DRA7XX_EVM
> +#ifdef CONFIG_DRA7XX
> +#if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
>  #define OMAP_XHCI_BASE 0x488d
>  #define OMAP_OCP1_SCP_BASE 0x4A081000
>  #define OMAP_OTG_WRAPPER_BASE 0x488c
> -#elif defined CONFIG_TARGET_AM57XX_EVM
> +#elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
>  #define OMAP_XHCI_BASE 0x4889
>  #define OMAP_OCP1_SCP_BASE 0x4A084c00
>  #define OMAP_OTG_WRAPPER_BASE 0x4888
> +#endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
>  #elif defined CONFIG_AM43XX
>  #define OMAP_XHCI_BASE 0x483d
>  #define OMAP_OCP1_SCP_BASE 0x483E8000
> 


-- 
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Re: [U-Boot] [PATCH v4 4/7] arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks

2017-02-26 Thread Marek Vasut
On 02/23/2017 02:39 PM, Uri Mashiach wrote:
> Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
> during board_usb_exit to enable and disable clocks respectively.
> 
> Modifications:
> * Enable USB clocks in the OMAP version of the function
>   board_usb_init.
> * Disable USB clocks in the OMAP version of the function
>   board_usb_cleanup.
> 
> Cc: Marek Vasut 
> Signed-off-by: Uri Mashiach 
> Reviewed-by: Marek Vasut 
> Reviewed-by: Tom Rini 
> ---
> V1 -> V4: none
> 
>  board/compulab/cl-som-am57x/cl-som-am57x.c | 10 --
>  drivers/usb/host/xhci-omap.c   |  2 ++
>  2 files changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c 
> b/board/compulab/cl-som-am57x/cl-som-am57x.c
> index fe1468f..4701b71 100644
> --- a/board/compulab/cl-som-am57x/cl-som-am57x.c
> +++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
> @@ -53,16 +53,6 @@ int board_mmc_init(bd_t *bis)
>  }
>  #endif /* CONFIG_GENERIC_MMC */
>  
> -#ifdef CONFIG_USB_XHCI_OMAP
> -int omap_xhci_board_usb_init(int index, enum usb_init_type init)
> -{
> - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
> -  OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
> -
> - return 0;
> -}
> -#endif /* CONFIG_USB_XHCI_OMAP */
> -
>  int misc_init_r(void)
>  {
>   cl_print_pcb_info();
> diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
> index a1b4f2f..d6c5744 100644
> --- a/drivers/usb/host/xhci-omap.c
> +++ b/drivers/usb/host/xhci-omap.c
> @@ -29,6 +29,7 @@ static struct omap_xhci omap;
>  
>  __weak int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>  {
> + enable_usb_clocks(index);

How many OMAP boards will this break btw ? :)

>   return 0;
>  }
>  
> @@ -39,6 +40,7 @@ int board_usb_init(int index, enum usb_init_type init)
>  
>  __weak int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>  {
> + disable_usb_clocks(index);
>   return 0;
>  }
>  
> 


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Re: [U-Boot] [PATCH v4 3/7] usb: host: xhci-omap: fix double weak board_usb_init functions

2017-02-26 Thread Igor Grinberg
Cc Marex...

On 02/23/17 15:39, Uri Mashiach wrote:
> A weak version of the function board_usb_init is implemented in:
> common/usb.c
> drivers/usb/host/xhci-omap.c
> 
> To fix the double implementations:
> * Convert the board_usb_init function in drivers/usb/host/xhci-omap.c
>   normal (not weak).
> * The function board_usb_init in drivers/usb/host/xhci-omap.c calls to
>   the weak function omap_xhci_board_usb_init.
> * Rename board version of the function board_usb_init to
>   omap_xhci_board_usb_init.
>   Done only for boards that defines CONFIG_USB_XHCI_OMAP.
> 
> To achieve the same flexibility with the function board_usb_cleanup:
> * Add a normal (not weak) implementation of the function
>   board_usb_cleanup in drivers/usb/host/xhci-omap.c
> * The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls
>   to the weak function omap_xhci_board_usb_cleanup.
> * Rename board version of the function board_usb_cleanup to
>   omap_xhci_board_usb_cleanup.
>   Done only for boards that defines CONFIG_USB_XHCI_OMAP.
> 
> Cc: Lokesh Vutla 
> Signed-off-by: Uri Mashiach 
> Acked-by: Marek Vasut 
> Reviewed-by: Tom Rini 
> ---
> V1 -> V2: Use __weak instead of attribute block
> V2 -> V4: none
> 
>  board/compulab/cl-som-am57x/cl-som-am57x.c |  2 +-
>  board/ti/am43xx/board.c|  4 ++--
>  board/ti/am57xx/board.c|  4 ++--
>  board/ti/dra7xx/evm.c  |  4 ++--
>  drivers/usb/host/xhci-omap.c   | 17 +++--
>  5 files changed, 22 insertions(+), 9 deletions(-)
> 
> diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c 
> b/board/compulab/cl-som-am57x/cl-som-am57x.c
> index bdd0a2b..fe1468f 100644
> --- a/board/compulab/cl-som-am57x/cl-som-am57x.c
> +++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
> @@ -54,7 +54,7 @@ int board_mmc_init(bd_t *bis)
>  #endif /* CONFIG_GENERIC_MMC */
>  
>  #ifdef CONFIG_USB_XHCI_OMAP
> -int board_usb_init(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>  {
>   setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
>OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
> index 390cc16..2572029 100644
> --- a/board/ti/am43xx/board.c
> +++ b/board/ti/am43xx/board.c
> @@ -694,7 +694,7 @@ int usb_gadget_handle_interrupts(int index)
>  #endif /* CONFIG_USB_DWC3 */
>  
>  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
> -int board_usb_init(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>  {
>   enable_usb_clocks(index);
>  #ifdef CONFIG_USB_DWC3
> @@ -725,7 +725,7 @@ int board_usb_init(int index, enum usb_init_type init)
>   return 0;
>  }
>  
> -int board_usb_cleanup(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>  {
>  #ifdef CONFIG_USB_DWC3
>   switch (index) {
> diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
> index 1611514..4afa914 100644
> --- a/board/ti/am57xx/board.c
> +++ b/board/ti/am57xx/board.c
> @@ -618,7 +618,7 @@ int usb_gadget_handle_interrupts(int index)
>  #endif /* CONFIG_USB_DWC3 */
>  
>  #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
> -int board_usb_init(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>  {
>   enable_usb_clocks(index);
>   switch (index) {
> @@ -652,7 +652,7 @@ int board_usb_init(int index, enum usb_init_type init)
>   return 0;
>  }
>  
> -int board_usb_cleanup(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>  {
>  #ifdef CONFIG_USB_DWC3
>   switch (index) {
> diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
> index bd1c809..65bce93 100644
> --- a/board/ti/dra7xx/evm.c
> +++ b/board/ti/dra7xx/evm.c
> @@ -727,7 +727,7 @@ static struct ti_usb_phy_device usb_phy2_device = {
>   .index = 1,
>  };
>  
> -int board_usb_init(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_init(int index, enum usb_init_type init)
>  {
>   enable_usb_clocks(index);
>   switch (index) {
> @@ -764,7 +764,7 @@ int board_usb_init(int index, enum usb_init_type init)
>   return 0;
>  }
>  
> -int board_usb_cleanup(int index, enum usb_init_type init)
> +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
>  {
>   switch (index) {
>   case 0:
> diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
> index b881b19..a1b4f2f 100644
> --- a/drivers/usb/host/xhci-omap.c
> +++ b/drivers/usb/host/xhci-omap.c
> @@ -27,12 +27,25 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  static struct omap_xhci omap;
>  
> -__weak int __board_usb_init(int index, enum usb_init_type init)
> +__weak int 

Re: [U-Boot] [PATCH 0/5] mx6: tqma6: series of small fixes

2017-02-26 Thread Stefano Babic
On 03/02/2017 16:24, Markus Niebel wrote:
> From: Markus Niebel 
> 
> Markus Niebel (5):
>   imx6: tqma6: implement power_init_board
>   imx6: tqma6: use lower driver stength for I2C pins
>   imx6: tqma6: disable spi CS unused in U-Boot
>   imx6: tqma6: adjust ethernet phy reset delay
>   mx6: tqma6: clear enet clk sel for mba6
> 
>  board/tqc/tqma6/tqma6.c  | 24 +---
>  board/tqc/tqma6/tqma6_mba6.c | 33 -
>  2 files changed, 21 insertions(+), 36 deletions(-)
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano

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Re: [U-Boot] [PATCH 0/2] Support additional Variant for TQMa6 SOM

2017-02-26 Thread Stefano Babic
On 03/02/2017 15:20, Markus Niebel wrote:
> From: Markus Niebel 
> 
> Add support for the SOM variant featuring i.MX6DL. This needs a new
> DCD config. The first patch is a small preparation.
> 
> Markus Niebel (2):
>   arm: imx6: tqma6: use CONFIG_TQM6x for SOM specific settings
>   arm: imx6: tqma6: add support for TQMa6DL variant
> 
>  board/tqc/tqma6/Kconfig|   7 +++
>  board/tqc/tqma6/README |   3 +
>  board/tqc/tqma6/tqma6.c|   7 +++
>  board/tqc/tqma6/tqma6_mba6.c   |  14 +++--
>  board/tqc/tqma6/tqma6dl.cfg| 125 
> +
>  configs/tqma6dl_mba6_mmc_defconfig |  36 +++
>  configs/tqma6dl_mba6_spi_defconfig |  37 +++
>  include/configs/tqma6.h|  16 ++---
>  include/configs/tqma6_mba6.h   |   5 +-
>  9 files changed, 235 insertions(+), 15 deletions(-)
>  create mode 100644 board/tqc/tqma6/tqma6dl.cfg
>  create mode 100644 configs/tqma6dl_mba6_mmc_defconfig
>  create mode 100644 configs/tqma6dl_mba6_spi_defconfig
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano

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Re: [U-Boot] [PATCH v6 00/10] imx6ul: Add Engicam Is.IoT MX6UL support

2017-02-26 Thread Stefano Babic
On 24/02/2017 11:02, Jagan Teki wrote:
> From: Jagan Teki 
> 
> This patch set support Engicam Is.IoT MX6UL board support.
> 
> Changes for v6:
> - Remove 'arm: dts: Add MAINTAINERS file' patch
> - Rebase to master
> 
> Changes for v5:
> - Update ccgr_init so-that it can enable required clocks
> - Add new patch for dts files include under board MAINTAINERS
> - Add new patch for arch/arm/dts/MAINTAINERS file
> - Update 'Reviewed-by: Stefano Babic ' tag
> 
> Changes for v4:
> - Rebase to master
> 
> Changes for v3:
> - Rebase to master
> 
> Changes for v2:
> - Skiped eMMC node patch
> - Rebase to master
> 
> Jagan Teki (10):
>   configs: imx6: Don't define USDHC2_BASE_ADDR
>   arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support
>   arm: dts: imx6ul-isiot: Add I2C nodes
>   imx6: isiotmx6ul: Add I2C support
>   arm: dts: imx6ul-isiot: Add FEC node
>   imx6: isiotmx6ul: Add FEC support
>   imx6: isiotmx6ul: Add NAND support
>   imx6: isiotmx6ul: Add nandboot env support
>   imx6ul: isiotmx6ul: Enable I2C support
>   i.MX6: engicam: Include dts files under MAINTAINERS
> 
>  arch/arm/cpu/armv7/mx6/Kconfig|  12 ++
>  arch/arm/dts/Makefile |   4 +-
>  arch/arm/dts/imx6ul-isiot-mmc.dts |  50 ++
>  arch/arm/dts/imx6ul-isiot-nand.dts|  50 ++
>  arch/arm/dts/imx6ul-isiot.dtsi| 142 +++
>  board/engicam/geam6ul/MAINTAINERS |   1 +
>  board/engicam/icorem6/MAINTAINERS |   3 +
>  board/engicam/icorem6_rqs/MAINTAINERS |   3 +
>  board/engicam/isiotmx6ul/Kconfig  |  12 ++
>  board/engicam/isiotmx6ul/MAINTAINERS  |  10 ++
>  board/engicam/isiotmx6ul/Makefile |   6 +
>  board/engicam/isiotmx6ul/README   |  28 +++
>  board/engicam/isiotmx6ul/isiotmx6ul.c | 315 
> ++
>  configs/imx6ul_isiot_mmc_defconfig|  41 +
>  configs/imx6ul_isiot_nand_defconfig   |  42 +
>  include/configs/imx6qdl_icore.h   |   2 +-
>  include/configs/imx6ul_geam.h |   2 +-
>  include/configs/imx6ul_isiot.h| 205 ++
>  18 files changed, 925 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/dts/imx6ul-isiot-mmc.dts
>  create mode 100644 arch/arm/dts/imx6ul-isiot-nand.dts
>  create mode 100644 arch/arm/dts/imx6ul-isiot.dtsi
>  create mode 100644 board/engicam/isiotmx6ul/Kconfig
>  create mode 100644 board/engicam/isiotmx6ul/MAINTAINERS
>  create mode 100644 board/engicam/isiotmx6ul/Makefile
>  create mode 100644 board/engicam/isiotmx6ul/README
>  create mode 100644 board/engicam/isiotmx6ul/isiotmx6ul.c
>  create mode 100644 configs/imx6ul_isiot_mmc_defconfig
>  create mode 100644 configs/imx6ul_isiot_nand_defconfig
>  create mode 100644 include/configs/imx6ul_isiot.h
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano

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Re: [U-Boot] [PATCH v4 00/15] i.MX6: Engicam i.CoreM6/Is.IoT eMMC boot support

2017-02-26 Thread Stefano Babic
On 24/02/2017 11:15, Jagan Teki wrote:
> From: Jagan Teki 
> 
> Changes for v3:
> - Rebase on master
> - Fix checkpatch.pl Warnings
> - Add IMX6_BMODE_UART macro for uart bootmode
> - Remove value assignment in enum, since all enum list is order
> 
> Changes for v3:
> - Update IMX6_BMODE_* shift macros with real number instead of bitops
> - %s/IMX6_BMODE_SERIAL/IMX6_BMODE_SERIAL_ROM
> - Assign enums with numbers so-that it can easy to see same in RM
> - Update board MAINTAINERS file with imx6ul-isiot-emmc.dts file
> 
> Changes for v2:
> - Rebase on master
> - Add Is.IoT eMMC boot patches
> - Add few mmc env patches on board
> 
> Jagan Teki (15):
>   imx6: Add imx6_src_get_boot_mode
>   imx: spl: Update NAND bootmode detection bit
>   imx: Use IMX6_BMODE_* macros instead of numericals
>   imx6: Add src_base structure define macro
>   imx6: isiotmx6ul: Update SPL board boot order for eMMC
>   i.MX6UL: isiot: Add eMMC boot support
>   i.MX6UL: isiot: Add modeboot env via board_late_init
>   i.MX6UL: isiot: Add mmc_late_init
>   i.MX6UL: isiot: Switch the mmc env based on devno
>   arm: dts: imx6qdl-icore-rqs: Add eMMC node
>   imx6: icorem6_rqs: Update SPL board boot order for eMMC
>   imx6: icorem6_rqs: Add eMMC boot support
>   i.MX6Q: icorem6_rqs: Add modeboot env via board_late_init
>   i.MX6Q: icorem6_rqs: Add mmc_late_init
>   i.MX6Q: isiot: Switch the mmc env based on devno
> 
>  arch/arm/dts/Makefile   |   1 +
>  arch/arm/dts/imx6qdl-icore-rqs.dtsi |  22 ++
>  arch/arm/dts/imx6ul-isiot-emmc.dts  |  77 +
>  arch/arm/imx-common/init.c  |  10 +++
>  arch/arm/imx-common/spl.c   |  49 --
>  arch/arm/include/asm/arch-mx6/imx-regs.h|   2 +
>  arch/arm/include/asm/imx-common/sys_proto.h |  47 +
>  board/engicam/icorem6_rqs/icorem6_rqs.c |  96 +-
>  board/engicam/isiotmx6ul/MAINTAINERS|   2 +
>  board/engicam/isiotmx6ul/isiotmx6ul.c   | 101 
> +++-
>  configs/imx6dl_icore_rqs_mmc_defconfig  |   1 +
>  configs/imx6q_icore_rqs_mmc_defconfig   |   1 +
>  configs/imx6ul_isiot_emmc_defconfig |  40 +++
>  configs/imx6ul_isiot_mmc_defconfig  |   1 +
>  configs/imx6ul_isiot_nand_defconfig |   1 +
>  include/configs/imx6qdl_icore_rqs.h |  36 +-
>  include/configs/imx6ul_isiot.h  |  40 +--
>  17 files changed, 462 insertions(+), 65 deletions(-)
>  create mode 100644 arch/arm/dts/imx6ul-isiot-emmc.dts
>  create mode 100644 configs/imx6ul_isiot_emmc_defconfig
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano

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Re: [U-Boot] [PATCH v4 01/15] imx6: Add imx6_src_get_boot_mode

2017-02-26 Thread Stefano Babic
On 24/02/2017 11:15, Jagan Teki wrote:
> For i.MX6, the bootmode determine code is part of spl_boot_device,
> but there is might be a possibility for other part the code need to
> check the desired boot mode for adding new functionalities like
> modeboot env variable, or changing boot order etc.
> 
> So introduced imx6_src_get_boot_mode which actually reading the
> boot mode register for desired modes.
> 
> More cleanup will be add in future patches.
> 
> Cc: Stefano Babic 
> Cc: Tim Harvey 
> Cc: Matteo Lisi 
> Cc: Michael Trimarchi 
> Signed-off-by: Jagan Teki 
> ---
>  arch/arm/imx-common/init.c  | 12 
>  arch/arm/imx-common/spl.c   |  4 ++--
>  arch/arm/include/asm/imx-common/sys_proto.h | 14 ++
>  3 files changed, 28 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
> index e5dbd93..036ebb2 100644
> --- a/arch/arm/imx-common/init.c
> +++ b/arch/arm/imx-common/init.c
> @@ -115,3 +115,15 @@ void boot_mode_apply(unsigned cfg_val)
>   writel(reg, >gpr10);
>  }
>  #endif
> +
> +#if defined(CONFIG_MX6)
> +u32 imx6_src_get_boot_mode(void)
> +{
> + struct src *psrc = (struct src *)SRC_BASE_ADDR;
> +
> + if (imx6_is_bmode_from_gpr9())
> + return readl(>gpr9);
> + else
> + return readl(>sbmr1);
> +}
> +#endif
> diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
> index 46325ec..6c20f28 100644
> --- a/arch/arm/imx-common/spl.c
> +++ b/arch/arm/imx-common/spl.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -19,9 +20,8 @@
>  u32 spl_boot_device(void)
>  {
>   struct src *psrc = (struct src *)SRC_BASE_ADDR;
> - unsigned int gpr10_boot = readl(>gpr10) & (1 << 28);
> - unsigned reg = gpr10_boot ? readl(>gpr9) : readl(>sbmr1);
>   unsigned int bmode = readl(>sbmr2);
> + u32 reg = imx6_src_get_boot_mode();
>  
>   /*
>* Check for BMODE if serial downloader is enabled
> diff --git a/arch/arm/include/asm/imx-common/sys_proto.h 
> b/arch/arm/include/asm/imx-common/sys_proto.h
> index 539d34b..99e3869 100644
> --- a/arch/arm/include/asm/imx-common/sys_proto.h
> +++ b/arch/arm/include/asm/imx-common/sys_proto.h
> @@ -8,6 +8,7 @@
>  #ifndef _SYS_PROTO_H_
>  #define _SYS_PROTO_H_
>  
> +#include 
>  #include 
>  #include 
>  #include "../arch-imx/cpu.h"
> @@ -38,6 +39,19 @@
>  #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
>  #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
>  
> +#ifdef CONFIG_MX6
> +#define IMX6_SRC_GPR10_BMODE BIT(28)
> +
> +static inline u8 imx6_is_bmode_from_gpr9(void)
> +{
> + struct src *psrc = (struct src *)SRC_BASE_ADDR;
> +
> + return readl(>gpr10) & IMX6_SRC_GPR10_BMODE;
> +}
> +
> +u32 imx6_src_get_boot_mode(void);
> +#endif /* CONFIG_MX6 */
> +
>  u32 get_nr_cpus(void);
>  u32 get_cpu_rev(void);
>  u32 get_cpu_speed_grade_hz(void);
> 

Thanks !

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH V4 12/19] i2c: lpi2c: add lpi2c driver for i.MX7ULP

2017-02-26 Thread Stefano Babic
On 24/02/2017 04:56, Peng Fan wrote:
> Add lpi2c driver for i.MX7ULP.
> Need to enable the two options to use this driver:
> CONFIG_DM_I2C=y
> CONFIG_SYS_I2C_IMX_LPI2C=y
> 
> Signed-off-by: Peng Fan 
> Acked-by: Heiko Schocher 
> Cc: Stefano Babic 
> ---
> 

Fine with me - I have integrate your patches in my own tree (not yet
pushed). I will check Jagan's before sending my PR to Tom.

Regards,
Stefano


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Re: [U-Boot] [PATCH v3 2/7] arm: usb: dra7xx: xHCI registers based on USB port index

2017-02-26 Thread Marek Vasut
On 02/22/2017 01:58 PM, Uri Mashiach wrote:

[...]

>> Someone would have to put that effort in.
>>
>> I wonder if instead of defining INDEX0, INDEX1 ... this could be turned
>> into integer ...
>>
> 
> Something like the following?
> 
> #ifdef CONFIG_DRA7XX
> #if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
> ...
> #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
> ...
> #endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
> #elif defined CONFIG_AM43XX
> ...

Yes


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Re: [U-Boot] [PATCH 07/20] arm: socfpga: add clock driver for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add clock driver support for Arria 10 and update Gen5 clock driver.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile |3 +-
>  arch/arm/mach-socfpga/clock_manager.c  |   36 +-
>  arch/arm/mach-socfpga/clock_manager_arria10.c  | 1104 
> 
>  arch/arm/mach-socfpga/clock_manager_gen5.c |  132 ++-
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |8 +-
>  .../include/mach/clock_manager_arria10.h   |  231 
>  6 files changed, 1455 insertions(+), 59 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
>  mode change 100755 => 100644 arch/arm/mach-socfpga/clock_manager_gen5.c
>  create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index d81f003..c494930 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -10,7 +10,8 @@
>  obj-y+= misc.o timer.o reset_manager.o clock_manager.o \
>  fpga_manager.o board.o
>  
> -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
> + reset_manager_arria10.o
>  
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>  
> diff --git a/arch/arm/mach-socfpga/clock_manager.c 
> b/arch/arm/mach-socfpga/clock_manager.c
> index d675973..7f48193 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -18,7 +19,12 @@ void cm_wait_for_lock(u32 mask)
>   register u32 inter_val;
>   u32 retry = 0;
>   do {
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

A10 should be below Gen5 to keep this sorted chronologically IMO.

> + inter_val = readl(_manager_base->stat) & mask;
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   inter_val = readl(_manager_base->inter) & mask;
> +#endif
> + /* Wait for stable lock */
>   if (inter_val == mask)
>   retry++;
>   else
> @@ -31,22 +37,39 @@ void cm_wait_for_lock(u32 mask)
>  /* function to poll in the fsm busy bit */
>  void cm_wait_for_fsm(void)
>  {
> - while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
> + while (readl(_manager_base->stat) &
> +CLKMGR_CLKMGR_STAT_BUSY_SET_MSK)
>   ;
>  }
>  
>  static void cm_print_clock_quick_summary(void)
>  {
>   printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
> + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
> + printf("QSPI%8d kHz\n",
> +cm_get_qspi_controller_clk_hz() / 1000);
> + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> + printf("EOSC1   %8d kHz\n", eosc1_hz / 1000);
> + printf("cb_intosc   %8d kHz\n", cb_intosc_hz / 1000);
> + printf("f2s_free%8d kHz\n", f2s_free_hz / 1000);
> + printf("Main VCO%8d kHz\n", cm_get_main_vco_clk_hz()/1000);
> + printf("NOC %8d kHz\n", cm_get_noc_clk_hz()/1000);
> + printf("L4 Main %8d kHz\n",
> +cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB)/1000);
> + printf("L4 MP   %8d kHz\n",
> +cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB)/1000);
> + printf("L4 SP   %8d kHz\n",
> +cm_get_l4_sp_clk_hz()/1000);
> + printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz/1000);
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   printf("DDR   %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
>   printf("EOSC1   %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
>   printf("EOSC2   %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
>   printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
>   printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
> - printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
> - printf("QSPI%8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
>   printf("UART%8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
> - printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
> +#endif
>  }
>  
>  int set_cpu_clk_info(void)
> @@ -57,7 +80,12 @@ int set_cpu_clk_info(void)
>  
>   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
>   gd->bd->bi_dsp_freq = 0;
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> + gd->bd->bi_ddr_freq = 0;
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
> +#endif
>  
>   return 0;
>  }
> diff --git 

Re: [U-Boot] [PATCH 08/20] arm: socfpga: add system manager for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add system manager support for Arria 10.

But these are just headers, there's no system manager code here ?

> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  .../arm/mach-socfpga/include/mach/system_manager.h | 54 ++-
>  .../include/mach/system_manager_arria10.h  | 81 
> ++
>  .../include/mach/system_manager_gen5.h |  1 +
>  3 files changed, 135 insertions(+), 1 deletion(-)
>  create mode 100755 
> arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
> b/arch/arm/mach-socfpga/include/mach/system_manager.h
> index 53ced81..324d13f 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> @@ -31,7 +31,59 @@
>  #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB  2
>  #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK  0x3
>  
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +/* For dedicated IO configuration */
> +/* Voltage select enums */
> +#define VOLTAGE_SEL_3V   0x0
> +#define VOLTAGE_SEL_1P8V 0x1
> +#define VOLTAGE_SEL_2P5V 0x2
> +
> +/* Input buffer enable */
> +#define INPUT_BUF_DISABLE0
> +#define INPUT_BUF_1P8V   1
> +#define INPUT_BUF_2P5V3V 2
> +
> +/* Weak pull up enable */
> +#define WK_PU_DISABLE0
> +#define WK_PU_ENABLE 1
> +
> +/* Pull up slew rate control */
> +#define PU_SLW_RT_SLOW   0
> +#define PU_SLW_RT_FAST   1
> +#define PU_SLW_RT_DEFAULTPU_SLW_RT_SLOW
> +
> +/* Pull down slew rate control */
> +#define PD_SLW_RT_SLOW   0
> +#define PD_SLW_RT_FAST   1
> +#define PD_SLW_RT_DEFAULTPD_SLW_RT_SLOW
> +
> +/* Drive strength control */
> +#define PU_DRV_STRG_DEFAULT  0x10
> +#define PD_DRV_STRG_DEFAULT  0x10
> +
> +/* bit position */
> +#define PD_DRV_STRG_LSB  0
> +#define PD_SLW_RT_LSB5
> +#define PU_DRV_STRG_LSB  8
> +#define PU_SLW_RT_LSB13
> +#define WK_PU_LSB16
> +#define INPUT_BUF_LSB17
> +#define BIAS_TRIM_LSB19
> +#define VOLTAGE_SEL_LSB  0
> +
> +#define ALT_SYSMGR_NOC_H2F_SET_MSK   0x0001
> +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x0010
> +#define ALT_SYSMGR_NOC_F2H_SET_MSK   0x0100
> +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK0x0001
> +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK0x0010
> +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK0x0100
> +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK0x0001
> +
> +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK0x0002
> +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK0x0002
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #include 
>  #endif
>  
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h 
> b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> new file mode 100755
> index 000..78432ec
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> @@ -0,0 +1,81 @@
> +/*
> + * Copyright (C) 2013-2017 Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef _SYSTEM_MANAGER_ARRIA10_H_
> +#define _SYSTEM_MANAGER_ARRIA10_H_
> +
> +struct socfpga_system_manager {
> + u32  siliconid1;
> + u32  siliconid2;
> + u32  wddbg;
> + u32  bootinfo;
> + u32  mpu_ctrl_l2_ecc;
> + u32  _pad_0x14_0x1f[3];
> + u32  dma;
> + u32  dma_periph;
> + u32  sdmmcgrp_ctrl;
> + u32  sdmmc_l3master;
> + u32  nand_bootstrap;
> + u32  nand_l3master;
> + u32  usb0_l3master;
> + u32  usb1_l3master;
> + u32  emac_global;
> + u32  emac[3];
> + u32  _pad_0x50_0x5f[4];
> + u32  fpgaintf_en_global;
> + u32  fpgaintf_en_0;
> + u32  fpgaintf_en_1;
> + u32  fpgaintf_en_2;
> + u32  fpgaintf_en_3;
> + u32  _pad_0x74_0x7f[3];
> + u32  noc_addr_remap_value;
> + u32  noc_addr_remap_set;
> + u32  noc_addr_remap_clear;
> + u32  _pad_0x8c_0x8f;
> + u32  ecc_intmask_value;
> + u32  ecc_intmask_set;
> + u32  ecc_intmask_clr;
> + u32  ecc_intstatus_serr;
> + u32  ecc_intstatus_derr;
> + u32  mpu_status_l2_ecc;
> + u32  mpu_clear_l2_ecc;
> + u32  mpu_status_l1_parity;
> + u32  mpu_clear_l1_parity;
> + u32  mpu_set_l1_parity;
> + u32  _pad_0xb8_0xbf[2];
> + u32  noc_timeout;
> + u32  noc_idlereq_set;
> + u32  noc_idlereq_clr;
> + u32  noc_idlereq_value;
> + u32  noc_idleack;
> + u32  noc_idlestatus;
> + u32  fpga2soc_ctrl;
> + u32  _pad_0xdc_0xff[9];
> + u32  tsmc_tsel_0;
> + u32  tsmc_tsel_1;
> + u32  tsmc_tsel_2;
> + u32  tsmc_tsel_3;
> 

Re: [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add reset driver support for Arria 10.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile |   2 +
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   4 +-
>  .../include/mach/reset_manager_arria10.h   | 144 
>  arch/arm/mach-socfpga/reset_manager_arria10.c  | 406 
> +
>  include/dt-bindings/reset/altr,rst-mgr-a10.h   | 103 ++
>  5 files changed, 658 insertions(+), 1 deletion(-)
>  create mode 100755 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
>  create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index e83da2e..d81f003 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -10,6 +10,8 @@
>  obj-y+= misc.o timer.o reset_manager.o clock_manager.o \
>  fpga_manager.o board.o
>  
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> +
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>  
>  # QTS-generated config file wrappers
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 9e253bf..64526b6 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -43,7 +43,9 @@ void socfpga_per_reset_all(void);
>  /* Create a human-readable reference to SoCFPGA reset. */
>  #define SOCFPGA_RESET(_name) RSTMGR_##_name
>  
> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)

You can use #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) instead to keep
this list sorted.

>  #include 
>  #endif
>  
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> new file mode 100755
> index 000..2668a86
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -0,0 +1,144 @@
> +/*
> + *  Copyright (C) 2012-2017 Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef  _RESET_MANAGER_ARRIA10_H_
> +#define  _RESET_MANAGER_ARRIA10_H_

Use #ifdef[space]FOO and #define[space]FOO

> +void watchdog_disable(void);
> +void reset_deassert_noc_ddr_scheduler(void);
> +int is_wdt_in_reset(void);
> +void emac_manage_reset(ulong emacbase, uint state);
> +int reset_deassert_bridges_handoff(void);
> +void reset_assert_fpga_connected_peripherals(void);
> +void reset_deassert_osc1wd0(void);
> +void reset_assert_uart(void);
> +void reset_deassert_uart(void);

[...]

> +#endif /* _RESET_MANAGER_ARRIA10_H_ */
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
> b/arch/arm/mach-socfpga/reset_manager_arria10.c
> new file mode 100644
> index 000..01156de
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -0,0 +1,406 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_reset_manager *reset_manager_base =
> + (void *)SOCFPGA_RSTMGR_ADDRESS;
> +static const struct socfpga_system_manager *sysmgr_regs =
> + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

Use the tabs consistently, one or two, but pick one.

> +static int get_bridge_init_val(const void *blob, int compat_id);
> +
> +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK|\
> + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)

MSK | \

Keep the spacing please.

> +void reset_assert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = uart_com_port(gd->fdt_blob);

What's this function , is it defined later in the patchset ?

> + if (SOCFPGA_UART1_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART1_SET_MSK;
> + else if (SOCFPGA_UART0_ADDRESS == com_port)
> + mask |= ALT_RSTMGR_PER1MODRST_UART0_SET_MSK;

Use if (foo == VALUE) please, not the other way around. Fix globally.

> + setbits_le32(_manager_base->per1modrst, mask);

You can combine this with the deassert_uart() function and use
clrsetbits instead to avoid duplication of the if () else () logic above.

> +}
> +
> +void reset_deassert_uart(void)
> +{
> + u32 mask = 0;
> + unsigned int com_port;
> +
> + com_port = 

Re: [U-Boot] [PATCH 05/20] arm: socfpga: add A10 defines

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> add i2c, timer and other A10 defines.

Start with capital letter please.

> Signed-off-by: Dinh Nguyen 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index a7056d4..d3dea0b 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2014 Altera Corporation 
> + * Copyright (C) 2014-2017 Altera Corporation 
>   *
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
> @@ -29,14 +29,20 @@
>  #define SOCFPGA_MPUL2_ADDRESS0xf000
>  #define SOCFPGA_I2C0_ADDRESS 0xffc02200
>  #define SOCFPGA_I2C1_ADDRESS 0xffc02300
> +#define SOCFPGA_I2C2_ADDRESS 0xffc02400
> +#define SOCFPGA_I2C3_ADDRESS 0xffc02500
> +#define SOCFPGA_I2C4_ADDRESS 0xffc02600

Shouldn't all this come from DT already ? What's the point of having
those macros at all ?

>  #define SOCFPGA_ECC_OCRAM_ADDRESS0xff8c3000
>  #define SOCFPGA_UART0_ADDRESS0xffc02000
>  #define SOCFPGA_OSC1TIMER0_ADDRESS   0xffd0
> +#define SOCFPGA_OSC1TIMER1_ADDRESS   0xffd00100
>  #define SOCFPGA_CLKMGR_ADDRESS   0xffd04000
>  #define SOCFPGA_RSTMGR_ADDRESS   0xffd05000
>  
>  #define SOCFPGA_SDR_ADDRESS  0xffcfb000
> +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
> +#define SOCFPGA_NOC_FW_H2F_SCR_OFST  0xffd13500
>  #define SOCFPGA_SDR_SCHEDULER_ADDRESS0xffd12400
>  #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS   0xffd13200
>  #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS0xffd13300
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] splash: Prevent splash_load_fs from writing to 0x0

2017-02-26 Thread Igor Grinberg
Hi Jonathan,

On 02/24/17 18:46, Jonathan Golder wrote:
> Passing NULL to fs_read() for actread value results in hanging U-Boot
> at least on our ARM plattform (TI AM335x). Since fs_read() and
> following functions do not catch nullpointers, writing to 0x0 occurs.
> 
> Passing a local dummy var instead of NULL solves this issue.

I haven't looked at fs_read() yet, but from the above it seems
that a better approach would be to fix the fs_read()?
Might there be use cases when it is legitimate to pass NULL?

> 
> Signed-off-by: Jonathan Golder 
> Cc: Anatolij Gustschin 
> ---
>  common/splash_source.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/common/splash_source.c b/common/splash_source.c
> index a5eeb3f..d1647c8 100644
> --- a/common/splash_source.c
> +++ b/common/splash_source.c
> @@ -216,6 +216,7 @@ static int splash_load_fs(struct splash_location 
> *location, u32 bmp_load_addr)
>  {
>   int res = 0;
>   loff_t bmp_size;
> + loff_t actread;
>   char *splash_file;
>  
>   splash_file = getenv("splashfile");
> @@ -251,7 +252,7 @@ static int splash_load_fs(struct splash_location 
> *location, u32 bmp_load_addr)
>   }
>  
>   splash_select_fs_dev(location);
> - res = fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
> + res = fs_read(splash_file, bmp_load_addr, 0, 0, );
>  
>  out:
>   if (location->ubivol != NULL)
> 

-- 
Regards,
Igor.
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[U-Boot] [U-boot] Question about bootp structure pack

2017-02-26 Thread Eric BOUXIROT
Hi everyone,



I’m using u-boot-2015.07 in one of my project based on vpac270 soc module.

u-boot is well configured and build is fine without error.

Gcc is v3.4.5 and glibc v2.3.6 built by crosstool 0.43 for
arm-softfloat-linux-gnu



My problem is when i use DHCP command to retrieve a file from my TFTP
server, i can’t get any IP from the DHCP server.

After analysing ethernet frames on server side i found that frame do not
arrive at all on server.

After checking debug détails on U-boot, it seem bootp frame is not good
because of some 0x00 paddings Inside the frame. (at end of header for
example)



If i add the attribute packed to the bootp header struct and ethernet
header, now all is working fine !



In net/bootp.h :

struct bootp_hdr {

u8   bp_op; /*
Operation */

# define OP_BOOTREQUEST   1

# define OP_BOOTREPLY 2

u8   bp_htype;  /* Hardware
type   */

# define HWT_ETHER 1

u8   bp_hlen; /*
Hardware address length   */

# define HWL_ETHER 6

u8   bp_hops;/* Hop
count (gateway thing)*/

u32bp_id;  /*
Transaction ID */

u16bp_secs; /* Seconds
since boot   */

u16bp_spare1;/*
Alignment */

struct in_addr   bp_ciaddr;  /* Client IP
address*/

struct in_addr   bp_yiaddr; /* Your (client) IP
address   */

struct in_addr   bp_siaddr;  /* Server IP
address   */

struct in_addr   bp_giaddr; /* Gateway IP
address  */

u8   bp_chaddr[16]; /* Client
hardware address */

char   bp_sname[64]; /* Server host
name  */

char   bp_file[128]; /* Boot file
name*/

char   bp_vend[OPT_FIELD_SIZE]; /*
Vendor information */

} __attribute__((packed));



#define BOOTP_HDR_SIZE  sizeof(struct bootp_hdr)



And in include/net.h

struct ethernet_hdr {

u8   et_dest[6];/*
Destination node   */

u8   et_src[6];/*
Source node*/

u16et_protlen;/* Protocol
or length */

} __attribute__((packed));



I think the uboot src should work as is, because I have checked uboot
source modification since 2015.07, but no changes on the struct definition
and header_size still made with sizeof(struct).

So i think, the problem come from my side and perhaps from gcc itself.



But i don’t understand why gcc should pack these structs.. i think normal
use is to not pack.. except if makefile include some build option to do
that, my gcc toolchain do not understand..



Someone can help me to understand what i made wrong ? and help me to
resolve this problem without patching  ?
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Re: [U-Boot] [PATCH 11/20] arm: socfpga: add pinmux for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add pinmux support for Arria 10.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile  |  1 +
>  arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
>  arch/arm/mach-socfpga/pinmux_arria10.c  | 98 
> +
>  3 files changed, 114 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
>  create mode 100644 arch/arm/mach-socfpga/pinmux_arria10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 9c4617f..68d55e4 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -12,6 +12,7 @@ obj-y   += misc.o timer.o reset_manager.o 
> clock_manager.o \
>  
>  obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
>   misc_arria10.o  \
> + pinmux_arria10.o\
>   reset_manager_arria10.o
>  
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
> b/arch/arm/mach-socfpga/include/mach/pinmux.h
> new file mode 100644
> index 000..c5d5dd6
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
> @@ -0,0 +1,15 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#ifndef  _PINMUX_H_
> +#define  _PINMUX_H_

Use [space] instead of [tab] after #ifdef/#define

> +#ifndef __ASSEMBLY__
> +int config_dedicated_pins(const void *blob);
> +int config_pins(const void *blob, const char *pin_grp);
> +#endif
> +
> +#endif /* _PINMUX_H_ */
> diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c 
> b/arch/arm/mach-socfpga/pinmux_arria10.c
> new file mode 100644
> index 000..04acaa2
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/pinmux_arria10.c
> @@ -0,0 +1,98 @@
> +/*
> + *  Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static int do_pinctr_pin(const void *blob, int child, const char *node_name)
> +{
> + int len;
> + fdt_addr_t base_addr;
> + fdt_size_t size;
> + const u32 *cell;
> + u32 offset, value;
> +
> + base_addr = fdtdec_get_addr_size(blob, child, "reg", );
> + if (base_addr != FDT_ADDR_T_NONE) {
> + cell = fdt_getprop(blob, child, "pinctrl-single,pins",
> + );
> + if (cell != NULL) {
> + debug("%p %d\n", cell, len);
> + for (; len > 0; len -= (2*sizeof(u32))) {

2 * sizeof(u32) , spacing

What about len == 0 , not used ?

> + offset = fdt32_to_cpu(*cell++);
> + value = fdt32_to_cpu(*cell++);
> + debug("<0x%x 0x%x>\n", offset, value);
> + writel(value, base_addr + offset);
> + }
> + return 0;
> + }
> + }
> + return -EFAULT;
> +}
> +
> +static int do_pinctrl_pins(const void *blob, int node, const char 
> *child_name)
> +{
> + int child, len;
> + const char *node_name;
> +
> + child = fdt_first_subnode(blob, node);
> +
> + if (child < 0)
> + return -EINVAL;
> +
> + node_name = fdt_get_name(blob, child, );
> +
> + while (node_name) {
> + if (!strcmp(child_name, node_name))
> + return do_pinctr_pin(blob, child, node_name);
> +
> + child = fdt_next_subnode(blob, child);
> +
> + if (child < 0)
> + break;
> +
> + node_name = fdt_get_name(blob, child, );
> + }
> +
> + return -EFAULT;
> +}
> +
> +int config_dedicated_pins(const void *blob)
> +{
> + int node;
> +
> + node = fdtdec_next_compatible(blob, 0,
> + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> + return -EINVAL;
> +
> + if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
> + return -EFAULT;
> +
> + if (do_pinctrl_pins(blob, node, "dedicated"))
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +int config_pins(const void *blob, const char *pin_grp)
> +{
> + int node;
> +
> + node = fdtdec_next_compatible(blob, 0,
> + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> + return -EINVAL;
> +
> + if (do_pinctrl_pins(blob, node, pin_grp))
> + return -EFAULT;
> +
> + return 0;
> +}
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 14/20] arm: socfpga: add SPL support for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add SPL support for Arria 10.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/spl.c | 92 
> -
>  1 file changed, 90 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> index fec4c7a..1299e67 100644
> --- a/arch/arm/mach-socfpga/spl.c
> +++ b/arch/arm/mach-socfpga/spl.c
> @@ -19,37 +19,55 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include 
> +#endif
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#define BOOTINFO_BSEL_SHIFT  0

Wasn't this defined in the misc support patch already ?

>  static struct pl310_regs *const pl310 =
>   (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>  static struct scu_registers *scu_regs =
>   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>  static struct nic301_registers *nic301_regs =
>   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define BOOTINFO_BSEL_SHIFT  12
> +#endif
> +
> +static const struct socfpga_system_manager *sysmgr_regs =
>   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  
>  u32 spl_boot_device(void)
>  {
>   const u32 bsel = readl(_regs->bootinfo);
>  
> - switch (bsel & 0x7) {
> + switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) {
>   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
>   return BOOT_DEVICE_RAM;
>   case 0x2:   /* NAND Flash (1.8V) */
>   case 0x3:   /* NAND Flash (3.0V) */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
> +#endif
>   return BOOT_DEVICE_NAND;
>   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
>   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
>   socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
> +#endif
>   return BOOT_DEVICE_MMC1;
>   case 0x6:   /* QSPI Flash (1.8V) */
>   case 0x7:   /* QSPI Flash (3.0V) */
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
> +#endif

This looks awful, you might want to split this function into
A10-specific and Gen5 specific one(s) .

>   return BOOT_DEVICE_SPI;
>   default:
>   printf("Invalid boot device (bsel=%08x)!\n", bsel);
> @@ -68,6 +86,7 @@ u32 spl_boot_mode(const u32 boot_device)
>  }
>  #endif
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static void socfpga_nic301_slave_ns(void)
>  {
>   writel(0x1, _regs->lwhps2fpgaregs);
> @@ -182,3 +201,72 @@ void board_init_f(ulong dummy)
>   /* Configure simple malloc base pointer into RAM. */
>   gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
>  }
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#ifdef CONFIG_SPL_BOARD_INIT
> +void spl_board_init(void)
> +{
> + /* configuring the clock based on handoff */
> + cm_basic_init(gd->fdt_blob);
> + WATCHDOG_RESET();
> +
> + config_dedicated_pins(gd->fdt_blob);
> + WATCHDOG_RESET();
> +
> + /* Release UART from reset */
> + reset_deassert_uart();
> +
> + /* enable console uart printing */
> + preloader_console_init();
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> + memset(__bss_start, 0, __bss_end - __bss_start);

Is this really needed ? Should be done by common code already ...

> + /*
> +  * Configure Clock Manager to use intosc clock instead external osc to
> +  * ensure success watchdog operation. We do it as early as possible.
> +  */
> + cm_use_intosc();
> +
> + watchdog_disable();
> +
> + arch_early_init_r();
> +
> +#ifdef CONFIG_HW_WATCHDOG
> + /* release osc1 watchdog timer 0 from reset */
> + reset_deassert_osc1wd0();
> +
> + /* reconfigure and enable the watchdog */
> + hw_watchdog_init();
> + WATCHDOG_RESET();
> +#endif /* CONFIG_HW_WATCHDOG */
> +
> +#ifdef CONFIG_OF_CONTROL
> + /* We need to access to FDT as this stage */
> + /* FDT is at end of image */
> + gd->fdt_blob = (void *)(__bss_end);

This looks like common code too ?

> + /* Check whether we have a valid FDT or not. */
> + if (fdtdec_prepare_fdt()) {
> + panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
> + "doc/README.fdt-control");
> + }
> +#endif /* CONFIG_OF_CONTROL */
> +
> + /* Initialize the timer */
> + timer_init();
> +
> + /* configuring the clock based on handoff */
> + cm_basic_init(gd->fdt_blob);
> + WATCHDOG_RESET();
> +
> + 

Re: [U-Boot] [PATCH 10/20] arm: socfpga: add misc support for Arria 10

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add misc support for Arria 10 and minor fix on misc Gen5.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/mach-socfpga/Makefile|   1 +
>  arch/arm/mach-socfpga/include/mach/misc.h |   6 +
>  arch/arm/mach-socfpga/misc_arria10.c  | 262 
> ++
>  arch/arm/mach-socfpga/misc_gen5.c |   3 +-
>  4 files changed, 271 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

[...]

> +/*
> + * This function looking the 1st encounter UART peripheral,
> + * and then return its offset of the dedicated/shared IO pin
> + * mux. offset value (zero and above).
> + */
> +static int find_peripheral_uart(const void *blob,
> + int child, const char *node_name)
> +{
> + int len;
> + fdt_addr_t base_addr = 0;
> + fdt_size_t size;
> + const u32 *cell;
> + u32 value, offset = 0;
> +
> + base_addr = fdtdec_get_addr_size(blob, child, "reg", );
> + if (base_addr != FDT_ADDR_T_NONE) {
> + cell = fdt_getprop(blob, child, "pinctrl-single,pins",
> + );
> + if (cell != NULL) {
> + for (; len > 0; len -= (2 * sizeof(u32))) {

len == 0 is not handled ?

> + offset = fdt32_to_cpu(*cell++);
> + value = fdt32_to_cpu(*cell++);
> + /* Found UART peripheral */
> + if (0x0D == value)
> + return offset;
> + }
> + }
> + }
> + return -1;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART peripheral,

s/looking/looks up/ ?

> + * and then return its offset of the dedicated/shared IO pin
> + * mux. UART peripheral is found if the offset is not in negative
> + * value.
> + */
> +static int is_peripheral_uart_true(const void *blob,
> + int node, const char *child_name)
> +{
> + int child, len;
> + const char *node_name;
> +
> + child = fdt_first_subnode(blob, node);
> +
> + if (child < 0)
> + return -1;

errno.h

> + node_name = fdt_get_name(blob, child, );
> +
> + while (node_name) {
> + if (!strcmp(child_name, node_name))
> + return find_peripheral_uart(blob, child, node_name);
> +
> + child = fdt_next_subnode(blob, child);
> +
> + if (child < 0)
> + break;
> +
> + node_name = fdt_get_name(blob, child, );
> + }
> +
> + return -1;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART dedicated IO peripheral,
> + * and then return based address of the 1st encounter UART dedicated
> + * IO peripheral.
> + */
> +unsigned int dedicated_uart_com_port(const void *blob)
> +{
> + int node;
> +
> + node = fdtdec_next_compatible(blob, 0,
> +  COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> + return 0;
> +
> + if (0 <= is_peripheral_uart_true(blob, node, "dedicated"))
> + return SOCFPGA_UART1_ADDRESS;
> + else
> + return 0;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART shared IO peripheral, and 
> then
> + * return based address of the 1st encounter UART shared IO peripheral.
> + */
> +unsigned int shared_uart_com_port(const void *blob)
> +{
> + int node, ret;
> +
> + node = fdtdec_next_compatible(blob, 0,
> +  COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> + if (node < 0)
> + return 0;
> +
> + ret = is_peripheral_uart_true(blob, node, "shared");
> +
> + if (PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 == ret ||
> + PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 == ret ||
> + PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 == ret)
> + return SOCFPGA_UART0_ADDRESS;
> + else if (PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 == ret ||
> + PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 == ret ||
> + PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 == ret)
> + return SOCFPGA_UART1_ADDRESS;
> + else
> + return 0;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART peripheral, and then return
> + * base address of the 1st encounter UART peripheral.
> + */
> +unsigned int uart_com_port(const void *blob)

This is referenced earlier in the patchset , it should be added earlier
if possible.

> +{
> + unsigned int ret;
> +
> + ret = dedicated_uart_com_port(blob);
> +
> + if (ret)
> + return ret;
> +
> + return shared_uart_com_port(blob);
> +}
> +
> +/*
> + * Print CPU information
> + */
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> + const u32 bsel = (readl(_regs->bootinfo) >>
> +   SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
> +
> + puts("CPU:   Altera SoCFPGA 

Re: [U-Boot] [PATCH 15/20] drivers: Makefile: include fpga build in SPL

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Arria 10 SPL needs the drivers/fpga.
> 
> Signed-off-by: Tien Fong Chee 
> Signed-off-by: Ley Foon Tan 
> ---
>  drivers/Makefile | 1 +

+CC Michal and Moritz, they did some FPGA/SPL work too.

>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 34c55bf..6e7a2c3 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
>  obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
>  obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
>  obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> +obj-$(CONFIG_FPGA) += fpga/
>  endif
>  
>  ifdef CONFIG_TPL_BUILD
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 01/20] arm: socfpga: restructure clock manager driver

2017-02-26 Thread Marek Vasut
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Restructure clock manager driver in the preparation to support A10.
> Move the Gen5 specific code to _gen5 files. No functional change.
> 
> Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
> 
> Signed-off-by: Ley Foon Tan 

[...]

> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -1,5 +1,5 @@
>  /*
> - *  Copyright (C) 2013 Altera Corporation 
> + *  Copyright (C) 2013-2017 Altera Corporation 
>   *
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
> @@ -13,10 +13,10 @@ DECLARE_GLOBAL_DATA_PTR;
>  static const struct socfpga_clock_manager *clock_manager_base =
>   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>  
> -static void cm_wait_for_lock(uint32_t mask)
> +void cm_wait_for_lock(u32 mask)
>  {
> - register uint32_t inter_val;

We should probably drop this "register" altogether.

> - uint32_t retry = 0;
> + register u32 inter_val;
> + u32 retry = 0;
>   do {
>   inter_val = readl(_manager_base->inter) & mask;
>   if (inter_val == mask)

[...]

>  static void cm_print_clock_quick_summary(void)
>  {
>   printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
> diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c 
> b/arch/arm/mach-socfpga/clock_manager_gen5.c
> new file mode 100755
> index 000..1df2ed4
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
> @@ -0,0 +1,495 @@
> +/*
> + *  Copyright (C) 2013-2017 Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_clock_manager *clock_manager_base =
> + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void cm_write_bypass(u32 val)
> +{
> + writel(val, _manager_base->bypass);
> + cm_wait_for_fsm();
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit 
> */
> +static void cm_write_ctrl(u32 val)
> +{
> + writel(val, _manager_base->ctrl);
> + cm_wait_for_fsm();
> +}
> +
> +/* function to write a clock register that has phase information */
> +static void cm_write_with_phase(u32 value,
> + u32 reg_address, u32 mask)
> +{
> + /* poll until phase is zero */
> + while (readl(reg_address) & mask)
> + ;

This polling should be bounded, in fact, wait_for_bit() might be what
you want .

> + writel(value, reg_address);
> +
> + while (readl(reg_address) & mask)
> + ;

DTTO

> +}
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the 
> clocks.

[...]

-- 
Best regards,
Marek Vasut
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